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192.168.1.100 / T800_MD / 1eb8f53f94c145708b5ea2c6b9b96ea3d613f607 / . / mcu / service / sst / include / us_excep_hdlr.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * us_excep_hdlr.h
41 *
42 * Project:
43 * --------
44 * UMOLYA
45 *
46 * Description:
47 * ------------
48 * This file provides typedefs and definiton for PS index trace.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 *------------------------------------------------------------------------------
59 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
60 *============================================================================
61 ****************************************************************************/
62
63#ifndef __US_EXCEP_HDLR_H__
64#define __US_EXCEP_HDLR_H__
65
66#include "usip_ex_common_def.h"
67#include "scq16_ex_common_def.h"
68#include "us_excep_hdlr_format.h"
69
70#include "kal_general_types.h"
71#include "ex_public.h"
72/*******************************************************************************
73 * Definition
74 *******************************************************************************/
75#define USIP_SCQ16_EX_SYNC_TIMEOUT 2000000 /* 2s, only for VRF. USIP,SCQ16: Please use EX_US_SYNC_TIME in cc_ex_item.h */
76#define USIP_SCQ16_EX_INIT_PATTERN 0x62935566
77#define USIP_SCQ16_SECTION_BUFFER_SIZE 256
78#if defined(MT6763) || defined(MT6739) || defined(MT6771) || defined(MT6765)
79 #define USIP0_APB_BASE 0xA0084000
80 #define USIP1_APB_BASE 0xA0085000
81 #define USIP_APB_DBG_EN_OFFSET 0x0
82 #define USIP_APB_MODE_SEL_OFFSET 0x4
83 #define USIP_APB_DBG_INST_OFFSET 0x10
84 #define USIP_APB_DBG_EXECUTE_OFFSET 0x14
85 #define USIP_APB_DBG_WRITE_ADDR_OFFSET 0x18
86 #define USIP_APB_DBG_WRITE_OFFSET 0x1c
87 #define USIP_APB_DBG_STATUS_OFFSET 0x20
88
89 #define USIP_APB_DBG_ATTACH_INST 0x900
90 #define USIP_APB_DBG_REQ_INST 0x811
91 #define USIP_APB_DBG_STATUS_INST 0x803
92 #define USIP_APB_DBG_ADDR_INST 0x801
93 #define USIP_APB_DBG_PM_LOAD_INST 0x840
94 #define USIP_APB_DBG_INSTR_INST 0x802
95 #define USIP_APB_DBG_RESUME_INST 0x812
96
97 #define USIP_CACHE_ALIGN 0x20
98
99#endif
100
101typedef enum
102{
103 EX_STATUS_USIP0_0,
104 EX_STATUS_USIP0_1,
105 EX_STATUS_USIP1_0,
106 EX_STATUS_USIP1_1,
107 EX_STATUS_SCQ16_0,
108 EX_STATUS_SCQ16_1,
109#if !defined(__MD97_IS_2CORES__)
110/* H3 FPGA doesn't have scq16_2 and scq16_3 */
111 EX_STATUS_SCQ16_2,
112 EX_STATUS_SCQ16_3,
113#endif
114 EX_STATUS_USIP_SCQ16_CORE_NUM,
115 EX_STATUS_USIP_SCQ16_CORE_END = 0x6293beef
116} USIP_SCQ16_EX_STATUS_CORE_TYPE;
117
118
119typedef enum
120{
121 USIP0_0_FAIL_BIT_MASK = (1<<0),
122 USIP0_1_FAIL_BIT_MASK = (1<<1),
123 USIP1_0_FAIL_BIT_MASK = (1<<2),
124 USIP1_1_FAIL_BIT_MASK = (1<<3),
125 SCQ0_FAIL_BIT_MASK = (1<<4),
126 SCQ1_FAIL_BIT_MASK = (1<<5),
127 SCQ2_FAIL_BIT_MASK = (1<<6),
128 SCQ3_FAIL_BIT_MASK = (1<<7),
129} USIP_SCQ16_EX_CORE_BIT_MASK_TYPE;
130
131// ----------------- function declaration -------------------
132
133extern kal_bool INT_SyncUsipScqExceptionInfo(void);
134
135extern void INT_GetUsipScqExceptionRecord(USIP_SCQ_EXCEPTION_RECORD_T *record);
136
137extern kal_uint32 INT_GetUsipScqFailCore(void); //0~3: Usip, 4~5: Scq
138
139extern void INT_DumpUsipScqExceptionInfo(EX_TRACE_TYPE trace_type/*0=cadefa*/, kal_char* sys_info_str, kal_uint32 len);
140
141extern kal_char* INT_GetUsipScqCoreName(kal_uint32 core_index); //0~3: Usip, 4~5: Scq
142
143extern kal_uint32 INT_GetUsipScqFailCoreIndex(void);
144
145extern void INT_GetUsipScq16ExceptionHandshakeInit(void);
146
147extern void INT_GetUsipScq16BBMemoryInfo(void);
148
149extern void INT_GetUsip0DumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
150extern void INT_GetUsip1DumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
151extern void INT_GetScq160DumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
152extern void INT_GetScq161DumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
153extern void INT_GetScq162DumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
154extern void INT_GetScq163DumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
155extern void INT_GetVrfDumpMemoryInfo(kal_uint32 **info, kal_uint32 *count, kal_uint8* region_config);
156
157#endif /* __US_EXCEP_HDLR_H__ */