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192.168.1.100 / T800_MD / 6c1fd8fba87d5723e0e5614ae30b4258b603cb70 / . / mcu / custom / modem / common / custom_port.c
blob: 42587d716d60454259171b212d77f8cd62ae5c22 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame^]1#include "custom_port.h"
2
3#include "kal_public_defs.h"
4#include "kal_general_types.h"
5#include "kal_public_api.h"
6#include "fs_general_types.h"
7#include "fs_general_api.h"
8
9#if defined(__MTK_TARGET__) && defined(__HIF_PCIE_SUPPORT__)
10extern kal_uint32 pcie_get_link_state(void);
11#else
12#define pcie_get_link_state(...) (-1)
13#define index(...) (NULL)
14#endif
15
16// 76543210 76543210 76543210 76543210
17// XXX YY AZ
18//
19// XXX (MODE) ==> PORT_MODE_NONE or PORT_MODE_USB or PORT_MODE_PCIE or PORT_MODE_USB_AND_PCIE or PORT_MODE_AP
20// YY (DIPC configuration) ==> PORT_DIPC_MODE_NOT_SUPPORT or PORT_DIPC_MODE_PCIE_ONLY or PORT_DIPC_MODE_PCIE_ADVANCE or PORT_DIPC_MODE_DUAL_IPC
21// A (port enable/disable on PCIE) ==> PORT_PCIE_DISABLE or PORT_PCIE_ENABLE
22// Z (pcie link status) ==> PORT_PCIE_STATUS_LINK_DOWN or PORT_PCIE_STATUS_LINK_UP
23
24#if !defined(__DHL_TRACE_ENABLED__)
25 #define kal_prompt_trace(...)
26#endif
27
28#define FILEPATH_SIZE (128)
29#define BUFFER_SIZE (1024)
30kal_uint32 custom_port(custom_port_user_enum port)
31{
32 kal_uint32 ret = 0;
33#if defined(__HIF_USB_SUPPORT__) && defined(__HIF_PCIE_SUPPORT__)
34 //DUAL IPC load
35 static kal_bool first = KAL_TRUE;
36 FS_HANDLE file_handle;
37 static kal_uint32 config_dual_ipc_mode = PORT_DIPC_MODE_NOT_SUPPORT;
38 static kal_uint32 config_md_logging_interface = PORT_MODE_NONE;
39 static kal_uint32 config_md_at_interface = PORT_MODE_PCIE;
40 static kal_uint32 config_md_pcie_port = 0xffffffff;
41 kal_uint32 pcie_link_ready = (pcie_get_link_state() == 0) ? 1 : 0;
42
43 if (first) {
44 kal_wchar *filepath = NULL;
45 kal_uint8 *buffer = NULL;
46 do {
47 filepath = (kal_wchar *)get_ctrl_buffer(FILEPATH_SIZE);
48 buffer = (kal_uint8 *)get_ctrl_buffer(BUFFER_SIZE);
49
50 if (filepath == NULL || buffer == NULL) {
51 //cannot allocate memory for operation
52 break;
53 }
54
55 kal_wsprintf(filepath, "%s", DIPC_CONFIG_PATH);
56 if ((file_handle = FS_Open(filepath, FS_READ_ONLY | FS_OPEN_NO_DIR)) >= FS_NO_ERROR) {
57 kal_uint32 read_size;
58 memset(buffer, 0, BUFFER_SIZE);
59 if (FS_Read(file_handle, buffer, BUFFER_SIZE - 1, &read_size) >= FS_NO_ERROR) {
60 kal_prompt_trace(MOD_NIL, "XXXX %s:%d read_size=%d", __FILE__, __LINE__, read_size);
61 kal_uint8 *cur_ptr = &buffer[0];
62 kal_uint8 *tail_ptr = &buffer[read_size];
63 while (cur_ptr < tail_ptr) {
64 kal_uint8 key[32];
65 kal_uint32 val;
66 kal_uint8 *next_ptr = (kal_uint8 *)index((char *)cur_ptr, '\n');
67 kal_uint8 *delim_ptr;
68 if (next_ptr == NULL) {
69 break;
70 }
71 *next_ptr = '\0';
72 delim_ptr = (kal_uint8 *)index((char *)cur_ptr, ':');
73 if (delim_ptr == NULL) {
74 break;
75 }
76 *delim_ptr++ = '\0';
77
78 sscanf((char *)cur_ptr, "%s\n", (char *)key);
79 sscanf((char *)delim_ptr, "%u\n", &val);
80
81 cur_ptr = next_ptr + 1;
82 kal_prompt_trace(MOD_NIL, "[%s][%x]", key, val);
83 if (strcmp(KEY_DUAL_IPC_MODE, (char *)key) == 0) {
84 switch(val) {
85 case DIPC_MODE_NOT_CONFIG:
86 config_dual_ipc_mode = PORT_DIPC_MODE_NOT_SUPPORT;
87 break;
88 case DIPC_MODE_PCIE_ADV:
89 config_dual_ipc_mode = PORT_DIPC_MODE_PCIE_ADVANCE;
90 break;
91 case DIPC_MODE_PCIE_ONLY:
92 config_dual_ipc_mode = PORT_DIPC_MODE_PCIE_ONLY;
93 break;
94 case DIPC_MODE_DUAL_IPC:
95 config_dual_ipc_mode = PORT_DIPC_MODE_DUAL_IPC;
96 break;
97 case DIPC_MODE_USB_ONLY:
98 config_dual_ipc_mode = PORT_DIPC_MODE_USB_ONLY;
99 break;
100 }
101 } else if (strcmp(KEY_MD_LOGGING_INTERFACE, (char *)key) == 0) {
102 switch(val) {
103 case DIPC_INTF_USB:
104 config_md_logging_interface = PORT_MODE_USB;
105 break;
106 case DIPC_INTF_PCIE:
107 config_md_logging_interface = PORT_MODE_PCIE;
108 break;
109#if 0
110/* under construction !*/
111/* under construction !*/
112/* under construction !*/
113#endif
114 default:
115 config_md_logging_interface = PORT_MODE_NONE;
116 break;
117 }
118 } else if (strcmp(KEY_MD_AT_INTERFACE, (char *)key) == 0) {
119 switch(val) {
120 case DIPC_INTF_USB:
121 config_md_at_interface = PORT_MODE_USB;
122 break;
123 case DIPC_INTF_PCIE:
124 config_md_at_interface = PORT_MODE_PCIE;
125 break;
126 default:
127 config_md_at_interface = PORT_MODE_PCIE;
128 break;
129 }
130 } else if (strcmp(KEY_MD_PCIE_PORT_CONFIG, (char *)key) == 0) {
131 if ((val & DIPC_CONFIG_MD_PORT_LOGGING) == 0) {
132 config_md_pcie_port &= ~(1 << CUSTOM_PORT_USER_LOG);
133 }
134 if ((val & DIPC_CONFIG_MD_PORT_META) == 0) {
135 config_md_pcie_port &= ~(1 << CUSTOM_PORT_USER_META);
136 }
137 if ((val & DIPC_CONFIG_MD_PORT_BINARY_TOOL) == 0) {
138 config_md_pcie_port &= ~(1 << CUSTOM_PORT_USER_BINARY_TOOL);
139 config_md_pcie_port &= ~(1 << CUSTOM_PORT_USER_MIPC);
140 }
141 if ((val & DIPC_CONFIG_MD_PORT_AT) == 0) {
142 config_md_pcie_port &= ~(1 << CUSTOM_PORT_USER_AT);
143 }
144 }
145 }
146 }
147 FS_Close(file_handle);
148 }
149 first = KAL_FALSE;
150 } while(0);
151
152 if (filepath) {
153 free_ctrl_buffer(filepath);
154 filepath = NULL;
155 }
156 if (buffer) {
157 free_ctrl_buffer(buffer);
158 buffer = NULL;
159 }
160 }
161
162 if (config_md_pcie_port & (1 << port)) {
163 ret |= (1 << PORT_PCIE_ENABLE_SHIFT);
164 }
165
166 switch (config_dual_ipc_mode) {
167 case PORT_DIPC_MODE_PCIE_ADVANCE:
168 if (pcie_link_ready) {
169 if (config_md_pcie_port & (1 << port)) {
170 ret |= (PORT_MODE_PCIE << PORT_MODE_SHIFT);
171 } else {
172 ret |= (PORT_MODE_NONE << PORT_MODE_SHIFT);
173 }
174 } else {
175 ret |= (PORT_MODE_USB << PORT_MODE_SHIFT);
176 }
177 ret |= (config_dual_ipc_mode << PORT_DIPC_MODE_SHIFT);
178 ret |= (pcie_link_ready << PORT_PCIE_STATUS_SHIFT);
179 return ret;
180 case PORT_DIPC_MODE_PCIE_ONLY:
181 if (config_md_pcie_port & (1 << port)) {
182 ret |= (PORT_MODE_PCIE << PORT_MODE_SHIFT);
183 } else {
184 ret |= (PORT_MODE_NONE << PORT_MODE_SHIFT);
185 }
186 ret |= (config_dual_ipc_mode << PORT_DIPC_MODE_SHIFT);
187 ret |= (pcie_link_ready << PORT_PCIE_STATUS_SHIFT);
188 return ret;
189 case PORT_DIPC_MODE_DUAL_IPC:
190 if (pcie_link_ready) {
191 switch (port) {
192 case CUSTOM_PORT_USER_AT:
193 ret |= (config_md_at_interface << PORT_MODE_SHIFT);
194 break;
195 case CUSTOM_PORT_USER_LOG:
196 if (config_md_logging_interface == PORT_MODE_USB) {
197 ret |= (PORT_MODE_USB << PORT_MODE_SHIFT);
198 } else if ((config_md_logging_interface == PORT_MODE_PCIE) && (config_md_pcie_port & (1 << port))) {
199 ret |= (PORT_MODE_PCIE << PORT_MODE_SHIFT);
200 } else {
201 ret |= (PORT_MODE_NONE << PORT_MODE_SHIFT);
202 }
203 break;
204 case CUSTOM_PORT_USER_META:
205 ret |= (PORT_MODE_USB << PORT_MODE_SHIFT);
206 break;
207 default:
208 ret |= (PORT_MODE_PCIE << PORT_MODE_SHIFT);
209 break;
210 }
211 } else {
212 ret |= (PORT_MODE_USB << PORT_MODE_SHIFT);
213 }
214 ret |= (config_dual_ipc_mode << PORT_DIPC_MODE_SHIFT);
215 ret |= (pcie_link_ready << PORT_PCIE_STATUS_SHIFT);
216 return ret;
217 case PORT_DIPC_MODE_USB_ONLY:
218 ret |= (PORT_MODE_USB << PORT_MODE_SHIFT);
219 ret |= (config_dual_ipc_mode << PORT_DIPC_MODE_SHIFT);
220 ret |= (pcie_link_ready << PORT_PCIE_STATUS_SHIFT);
221 return ret;
222 case PORT_DIPC_MODE_NOT_SUPPORT:
223 if (port == CUSTOM_PORT_USER_LOG) {
224#if defined(__ELT_SET_PORT_TO_USB__)
225 ret |= (PORT_MODE_USB << PORT_MODE_SHIFT);
226#elif defined(__ELT_SET_PORT_TO_PCIE__)
227 ret |= (PORT_MODE_PCIE << PORT_MODE_SHIFT);
228#elif defined(__ELT_SET_PORT_TO_DUAL_IPC__)
229 ret |= (PORT_MODE_NONE << PORT_MODE_SHIFT);
230#else
231 ret |= (PORT_MODE_NONE << PORT_MODE_SHIFT);
232#endif
233 } else if (port == CUSTOM_PORT_USER_META) {
234#if defined(__META_SET_PORT_TO_USB__)
235 ret |= (PORT_MODE_USB << PORT_MODE_SHIFT);
236#elif defined(__META_SET_PORT_TO_PCIE__)
237 ret |= (PORT_MODE_PCIE << PORT_MODE_SHIFT);
238#elif defined(__META_SET_PORT_TO_DUAL_IPC__)
239 ret |= (PORT_MODE_NONE << PORT_MODE_SHIFT);
240#else
241 ret |= (PORT_MODE_NONE << PORT_MODE_SHIFT);
242#endif
243 } else {
244 ret |= (PORT_MODE_NONE << PORT_MODE_SHIFT);
245 }
246 ret |= (config_dual_ipc_mode << PORT_DIPC_MODE_SHIFT);
247 ret |= (1 << PORT_PCIE_ENABLE_SHIFT);
248 ret |= (pcie_link_ready << PORT_PCIE_STATUS_SHIFT);
249 return ret;
250 default:
251 ret |= (PORT_MODE_PCIE << PORT_MODE_SHIFT);
252 ret |= (config_dual_ipc_mode << PORT_DIPC_MODE_SHIFT);
253 ret |= (1 << PORT_PCIE_ENABLE_SHIFT);
254 ret |= (pcie_link_ready << PORT_PCIE_STATUS_SHIFT);
255 return ret;
256 }
257#elif defined(__HIF_USB_SUPPORT__)
258 //support USB only
259 ret |= (PORT_MODE_USB << PORT_MODE_SHIFT);
260 return ret;
261#elif defined(__HIF_PCIE_SUPPORT__)
262 //support PCIE only
263 ret |= (PORT_MODE_PCIE << PORT_MODE_SHIFT);
264 return ret;
265#else
266#if defined(__ANDROID_MODEM__)
267 //SP
268 ret |= (PORT_MODE_AP << PORT_MODE_SHIFT);
269 return ret;
270#else
271 ret |= (PORT_MODE_NONE << PORT_MODE_SHIFT);
272 return ret;
273#endif
274#endif
275}