| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame^] | 1 | #ifndef __DRV_CUIF_H__ |
| 2 | #define __DRV_CUIF_H__ |
| 3 | |
| 4 | |
| 5 | #include "cuif_l1core_public.h" |
| 6 | |
| 7 | #include "intrCtrl.h" |
| 8 | #include "kal_public_api.h" |
| 9 | #include "kal_general_types.h" |
| 10 | |
| 11 | #include "sync_data.h" |
| 12 | #include "drv_comm.h" |
| 13 | #include "reg_base.h" |
| 14 | |
| 15 | #define __CUIF_DEBUG__ |
| 16 | |
| 17 | /******************************************************************************* |
| 18 | * CUIF Memory Definition |
| 19 | *******************************************************************************/ |
| 20 | |
| 21 | /* Control Register Offset */ |
| 22 | #define CUIF_INTERRUPT_STATUS_OFFSET (0x00) |
| 23 | #define CUIF_INTERRUPT_SET_OFFSET (0x04) |
| 24 | #define CUIF_INTERRUPT_CLEAR_OFFSET (0x08) |
| 25 | #define CUIF_INTERRUPT_EN_OFFSET (0x0C) |
| 26 | #define CUIF_INTERRUPT_EN_SET_OFFSET (0x10) |
| 27 | #define CUIF_INTERRUPT_EN_CLR_OFFSET (0x14) |
| 28 | |
| 29 | #define CUIF_INTERRUPT_STA_EN_OFFSET (CUIF_INTERRUPT_EN_OFFSET - CUIF_INTERRUPT_STATUS_OFFSET) |
| 30 | #define CUIF_INTERRUPT_NEXT_INT_OFFSET (0x18) |
| 31 | |
| 32 | |
| 33 | /* C2U Core Offset*/ |
| 34 | #define CUIF_C2U_INNER (0x00 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 35 | #define CUIF_C2U_OUTER (0x18 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 36 | |
| 37 | #if defined(__MD97__) || defined(__MD98__) |
| 38 | |
| 39 | #if defined(__SSDVT_CUIF_TEST__) |
| 40 | |
| 41 | #define CUIF_C2U_FEC (0x30 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 42 | #define CUIF_C2U_SPEECH (0x48 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 43 | |
| 44 | #else |
| 45 | |
| 46 | #define CUIF_C2U_SPEECH (0x30 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 47 | #define CUIF_C2U_FEC (0x48 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 48 | |
| 49 | #endif |
| 50 | |
| 51 | #else |
| 52 | |
| 53 | #define CUIF_C2U_FEC (0x30 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 54 | #define CUIF_C2U_SPEECH (0x48 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 55 | |
| 56 | #endif |
| 57 | |
| 58 | /* C2U INNER */ |
| 59 | #define CUIF_C2U_INNER_INTERRUPT_STATUS_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_STATUS_OFFSET) |
| 60 | #define CUIF_C2U_INNER_INTERRUPT_SET_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_SET_OFFSET) |
| 61 | #define CUIF_C2U_INNER_INTERRUPT_CLEAR_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 62 | #define CUIF_C2U_INNER_INTERRUPT_EN_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_EN_OFFSET) |
| 63 | #define CUIF_C2U_INNER_INTERRUPT_EN_SET_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 64 | #define CUIF_C2U_INNER_INTERRUPT_EN_CLR_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 65 | |
| 66 | |
| 67 | /* C2U OUTER */ |
| 68 | #define CUIF_C2U_OUTER_INTERRUPT_STATUS_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_STATUS_OFFSET) |
| 69 | #define CUIF_C2U_OUTER_INTERRUPT_SET_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_SET_OFFSET) |
| 70 | #define CUIF_C2U_OUTER_INTERRUPT_CLEAR_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 71 | #define CUIF_C2U_OUTER_INTERRUPT_EN_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_EN_OFFSET) |
| 72 | #define CUIF_C2U_OUTER_INTERRUPT_EN_SET_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 73 | #define CUIF_C2U_OUTER_INTERRUPT_EN_CLR_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 74 | |
| 75 | /* C2U FEC */ |
| 76 | #define CUIF_C2U_FEC_INTERRUPT_STATUS_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_STATUS_OFFSET) |
| 77 | #define CUIF_C2U_FEC_INTERRUPT_SET_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_SET_OFFSET) |
| 78 | #define CUIF_C2U_FEC_INTERRUPT_CLEAR_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 79 | #define CUIF_C2U_FEC_INTERRUPT_EN_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_EN_OFFSET) |
| 80 | #define CUIF_C2U_FEC_INTERRUPT_EN_SET_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 81 | #define CUIF_C2U_FEC_INTERRUPT_EN_CLR_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 82 | |
| 83 | /* C2U SPEECH */ |
| 84 | #define CUIF_C2U_SPEECH_INTERRUPT_STATUS_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_STATUS_OFFSET) |
| 85 | #define CUIF_C2U_SPEECH_INTERRUPT_SET_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_SET_OFFSET) |
| 86 | #define CUIF_C2U_SPEECH_INTERRUPT_CLEAR_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 87 | #define CUIF_C2U_SPEECH_INTERRUPT_EN_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_EN_OFFSET) |
| 88 | #define CUIF_C2U_SPEECH_INTERRUPT_EN_SET_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 89 | #define CUIF_C2U_SPEECH_INTERRUPT_EN_CLR_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 90 | |
| 91 | /* U2C Core Offset*/ |
| 92 | |
| 93 | #if defined(__MD93__) |
| 94 | |
| 95 | /* U2C Core Offset*/ |
| 96 | /* to iA core0 VPE0 */ |
| 97 | #define CUIF_U2C_N0 (0x60 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 98 | /* to iA core0 VPE1 */ |
| 99 | #define CUIF_U2C_N1 (0x78 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 100 | #define CUIF_U2C_N2 (0x90 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 101 | #define CUIF_U2C_N3 (0xa8 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 102 | /* to iA core1 VPE1 */ |
| 103 | #define CUIF_U2C_N4 (0xc0 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 104 | |
| 105 | #define CUIF_U2C_WAKEUP (0xd8 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 106 | |
| 107 | #elif defined(__MD95__) |
| 108 | |
| 109 | /* to iA core0 VPE0 */ |
| 110 | #define CUIF_U2C_N0 (0x90 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 111 | /* to iA core0 VPE1 */ |
| 112 | #define CUIF_U2C_N1 (0xa8 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 113 | #define CUIF_U2C_N2 (0xc0 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 114 | #define CUIF_U2C_N3 (0xd8 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 115 | /* to iA core1 VPE0/1 */ |
| 116 | #define CUIF_U2C_N4 (0xf0 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 117 | #define CUIF_U2C_N5 (0x108 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 118 | #define CUIF_U2C_N6 (0x120 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 119 | |
| 120 | #define CUIF_U2C_WAKEUP (0x138 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 121 | |
| 122 | #elif defined(__MD97__) || defined(__MD97P__) |
| 123 | |
| 124 | #define CUIF_U2C_N0 (0xA00 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 125 | #define CUIF_U2C_N1 (0xA18 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 126 | #define CUIF_U2C_N2 (0xA30 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 127 | #define CUIF_U2C_N3 (0xA48 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 128 | #define CUIF_U2C_N4 (0xA60 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 129 | #define CUIF_U2C_N5 (0xA78 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 130 | #define CUIF_U2C_N6 (0xA90 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 131 | #define CUIF_U2C_N7 (0xAA8 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 132 | #define CUIF_U2C_N8 (0xAC0 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 133 | #define CUIF_U2C_N9 (0xAD8 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 134 | #define CUIF_U2C_N10 (0xAF0 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 135 | #define CUIF_U2C_N11 (0xB08 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 136 | #define CUIF_U2C_N12 (0xB20 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 137 | #define CUIF_U2C_N13 (0xB38 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 138 | |
| 139 | #define CUIF_U2C_WAKEUP (0x120 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| 140 | |
| 141 | #else |
| 142 | #error "not support this arch!!!!" |
| 143 | #endif |
| 144 | |
| 145 | /* U2C N0 */ |
| 146 | #define CUIF_U2C_N0_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 147 | #define CUIF_U2C_N0_INTERRUPT_SET_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_SET_OFFSET) |
| 148 | #define CUIF_U2C_N0_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 149 | #define CUIF_U2C_N0_INTERRUPT_EN_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_EN_OFFSET) |
| 150 | #define CUIF_U2C_N0_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 151 | #define CUIF_U2C_N0_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 152 | |
| 153 | /* U2C N1 */ |
| 154 | #define CUIF_U2C_N1_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 155 | #define CUIF_U2C_N1_INTERRUPT_SET_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_SET_OFFSET) |
| 156 | #define CUIF_U2C_N1_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 157 | #define CUIF_U2C_N1_INTERRUPT_EN_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_EN_OFFSET) |
| 158 | #define CUIF_U2C_N1_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 159 | #define CUIF_U2C_N1_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 160 | |
| 161 | /* U2C N2 */ |
| 162 | #define CUIF_U2C_N2_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 163 | #define CUIF_U2C_N2_INTERRUPT_SET_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_SET_OFFSET) |
| 164 | #define CUIF_U2C_N2_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 165 | #define CUIF_U2C_N2_INTERRUPT_EN_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_EN_OFFSET) |
| 166 | #define CUIF_U2C_N2_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 167 | #define CUIF_U2C_N2_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 168 | |
| 169 | /* U2C N3 */ |
| 170 | #define CUIF_U2C_N3_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 171 | #define CUIF_U2C_N3_INTERRUPT_SET_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_SET_OFFSET) |
| 172 | #define CUIF_U2C_N3_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 173 | #define CUIF_U2C_N3_INTERRUPT_EN_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_EN_OFFSET) |
| 174 | #define CUIF_U2C_N3_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 175 | #define CUIF_U2C_N3_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 176 | |
| 177 | /* U2C N4 */ |
| 178 | #define CUIF_U2C_N4_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 179 | #define CUIF_U2C_N4_INTERRUPT_SET_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_SET_OFFSET) |
| 180 | #define CUIF_U2C_N4_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 181 | #define CUIF_U2C_N4_INTERRUPT_EN_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_EN_OFFSET) |
| 182 | #define CUIF_U2C_N4_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 183 | #define CUIF_U2C_N4_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 184 | |
| 185 | #if defined(__MD95__) |
| 186 | |
| 187 | /* U2C N5 */ |
| 188 | #define CUIF_U2C_N5_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 189 | #define CUIF_U2C_N5_INTERRUPT_SET_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_SET_OFFSET) |
| 190 | #define CUIF_U2C_N5_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 191 | #define CUIF_U2C_N5_INTERRUPT_EN_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_OFFSET) |
| 192 | #define CUIF_U2C_N5_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 193 | #define CUIF_U2C_N5_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 194 | |
| 195 | /* U2C N6 */ |
| 196 | #define CUIF_U2C_N6_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 197 | #define CUIF_U2C_N6_INTERRUPT_SET_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_SET_OFFSET) |
| 198 | #define CUIF_U2C_N6_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 199 | #define CUIF_U2C_N6_INTERRUPT_EN_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_OFFSET) |
| 200 | #define CUIF_U2C_N6_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 201 | #define CUIF_U2C_N6_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 202 | |
| 203 | #elif defined(__MD97__) || defined(__MD97P__) |
| 204 | |
| 205 | /* U2C N5 */ |
| 206 | #define CUIF_U2C_N5_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 207 | #define CUIF_U2C_N5_INTERRUPT_SET_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_SET_OFFSET) |
| 208 | #define CUIF_U2C_N5_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 209 | #define CUIF_U2C_N5_INTERRUPT_EN_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_OFFSET) |
| 210 | #define CUIF_U2C_N5_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 211 | #define CUIF_U2C_N5_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 212 | |
| 213 | /* U2C N6 */ |
| 214 | #define CUIF_U2C_N6_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 215 | #define CUIF_U2C_N6_INTERRUPT_SET_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_SET_OFFSET) |
| 216 | #define CUIF_U2C_N6_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 217 | #define CUIF_U2C_N6_INTERRUPT_EN_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_OFFSET) |
| 218 | #define CUIF_U2C_N6_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 219 | #define CUIF_U2C_N6_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 220 | |
| 221 | /* U2C N7 */ |
| 222 | #define CUIF_U2C_N7_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 223 | #define CUIF_U2C_N7_INTERRUPT_SET_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_SET_OFFSET) |
| 224 | #define CUIF_U2C_N7_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 225 | #define CUIF_U2C_N7_INTERRUPT_EN_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_EN_OFFSET) |
| 226 | #define CUIF_U2C_N7_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 227 | #define CUIF_U2C_N7_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 228 | |
| 229 | /* U2C N8 */ |
| 230 | #define CUIF_U2C_N8_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 231 | #define CUIF_U2C_N8_INTERRUPT_SET_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_SET_OFFSET) |
| 232 | #define CUIF_U2C_N8_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 233 | #define CUIF_U2C_N8_INTERRUPT_EN_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_EN_OFFSET) |
| 234 | #define CUIF_U2C_N8_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 235 | #define CUIF_U2C_N8_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 236 | |
| 237 | /* U2C N9 */ |
| 238 | #define CUIF_U2C_N9_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 239 | #define CUIF_U2C_N9_INTERRUPT_SET_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_SET_OFFSET) |
| 240 | #define CUIF_U2C_N9_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 241 | #define CUIF_U2C_N9_INTERRUPT_EN_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_EN_OFFSET) |
| 242 | #define CUIF_U2C_N9_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 243 | #define CUIF_U2C_N9_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 244 | |
| 245 | /* U2C N10 */ |
| 246 | #define CUIF_U2C_N10_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 247 | #define CUIF_U2C_N10_INTERRUPT_SET_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_SET_OFFSET) |
| 248 | #define CUIF_U2C_N10_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 249 | #define CUIF_U2C_N10_INTERRUPT_EN_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_EN_OFFSET) |
| 250 | #define CUIF_U2C_N10_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 251 | #define CUIF_U2C_N10_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 252 | |
| 253 | /* U2C N11 */ |
| 254 | #define CUIF_U2C_N11_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 255 | #define CUIF_U2C_N11_INTERRUPT_SET_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_SET_OFFSET) |
| 256 | #define CUIF_U2C_N11_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 257 | #define CUIF_U2C_N11_INTERRUPT_EN_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_EN_OFFSET) |
| 258 | #define CUIF_U2C_N11_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 259 | #define CUIF_U2C_N11_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 260 | |
| 261 | /* U2C N12 */ |
| 262 | #define CUIF_U2C_N12_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 263 | #define CUIF_U2C_N12_INTERRUPT_SET_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_SET_OFFSET) |
| 264 | #define CUIF_U2C_N12_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 265 | #define CUIF_U2C_N12_INTERRUPT_EN_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_EN_OFFSET) |
| 266 | #define CUIF_U2C_N12_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 267 | #define CUIF_U2C_N12_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 268 | |
| 269 | /* U2C N13 */ |
| 270 | #define CUIF_U2C_N13_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_STATUS_OFFSET) |
| 271 | #define CUIF_U2C_N13_INTERRUPT_SET_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_SET_OFFSET) |
| 272 | #define CUIF_U2C_N13_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 273 | #define CUIF_U2C_N13_INTERRUPT_EN_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_EN_OFFSET) |
| 274 | #define CUIF_U2C_N13_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 275 | #define CUIF_U2C_N13_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 276 | |
| 277 | /* U2C WAKEUP */ |
| 278 | #define CUIF_U2C_WAKEUP_INTERRUPT_STATUS_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_STATUS_OFFSET) |
| 279 | #define CUIF_U2C_WAKEUP_INTERRUPT_SET_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_SET_OFFSET) |
| 280 | #define CUIF_U2C_WAKEUP_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_CLEAR_OFFSET) |
| 281 | #define CUIF_U2C_WAKEUP_INTERRUPT_EN_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_EN_OFFSET) |
| 282 | #define CUIF_U2C_WAKEUP_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_EN_SET_OFFSET) |
| 283 | #define CUIF_U2C_WAKEUP_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| 284 | |
| 285 | #endif |
| 286 | /******************************************************************************* |
| 287 | * Macros |
| 288 | *******************************************************************************/ |
| 289 | |
| 290 | /* C2U */ |
| 291 | #define CUIF_C2U_STATUS_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_STATUS_OFFSET)) |
| 292 | #define CUIF_C2U_SET_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_SET_OFFSET)) |
| 293 | #define CUIF_C2U_CLEAR_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_CLEAR_OFFSET)) |
| 294 | #define CUIF_C2U_EN_STATUS_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_EN_OFFSET)) |
| 295 | #define CUIF_C2U_EN_SET_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_EN_SET_OFFSET)) |
| 296 | #define CUIF_C2U_EN_CLR_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_EN_CLR_OFFSET)) |
| 297 | |
| 298 | |
| 299 | /* U2C */ |
| 300 | #define CUIF_U2C_STATUS_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_STATUS_OFFSET)) |
| 301 | #define CUIF_U2C_SET_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_SET_OFFSET)) |
| 302 | #define CUIF_U2C_CLEAR_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_CLEAR_OFFSET)) |
| 303 | #define CUIF_U2C_EN_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_EN_OFFSET)) |
| 304 | #define CUIF_U2C_EN_SET_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_EN_SET_OFFSET)) |
| 305 | #define CUIF_U2C_EN_CLR_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_EN_CLR_OFFSET)) |
| 306 | |
| 307 | |
| 308 | #if defined(__MD97__) || defined(__MD97P__) |
| 309 | /* U2C WAKEUP*/ |
| 310 | #define CUIF_U2C_WAKEUP_STATUS_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_STATUS_OFFSET)) |
| 311 | #define CUIF_U2C_WAKEUP_SET_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_SET_OFFSET)) |
| 312 | #define CUIF_U2C_WAKEUP_CLEAR_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_CLEAR_OFFSET)) |
| 313 | #define CUIF_U2C_WAKEUP_EN_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_EN_OFFSET)) |
| 314 | #define CUIF_U2C_WAKEUP_EN_SET_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_EN_SET_OFFSET)) |
| 315 | #define CUIF_U2C_WAKEUP_EN_CLR_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_EN_CLR_OFFSET)) |
| 316 | #endif |
| 317 | |
| 318 | #define CUIF_TRUE KAL_TRUE |
| 319 | #define CUIF_FALSE KAL_FALSE |
| 320 | |
| 321 | |
| 322 | /* Read/Write macros */ |
| 323 | #define CUIF_REG_READ(addr) *(volatile cuif_uint32*)(addr) |
| 324 | #define CUIF_REG_WRITE(addr, value) do{DRV_WriteReg32(addr, value); MO_Sync();}while(0); |
| 325 | |
| 326 | |
| 327 | #define CUIF_NULL NULL |
| 328 | #define CUIF_ASSERT(expr, c1, c2, c3) EXT_ASSERT(expr, c1, c2, c3) |
| 329 | #define CUIF_GET_RETURN_ADDRESS(a) GET_RETURN_ADDRESS(a) |
| 330 | |
| 331 | #define CUIF_CLZ(z) __builtin_clz((z)) |
| 332 | #define CUIF_GET_LSB(b) (31 - CUIF_CLZ((b) & -(b))) |
| 333 | |
| 334 | #if defined(__MD93__) || defined(__MD95__) |
| 335 | |
| 336 | #define IRQID_CUIF_U2C_IRQ_N0 IRQ_USIP0_0_CODE |
| 337 | #define IRQID_CUIF_U2C_IRQ_N1 IRQ_USIP1_0_CODE |
| 338 | #define IRQID_CUIF_U2C_IRQ_N2 IRQ_USIP2_0_CODE |
| 339 | #define IRQID_CUIF_U2C_IRQ_N3 IRQ_USIP3_0_CODE |
| 340 | #define IRQID_CUIF_U2C_IRQ_N4 IRQ_USIP0_1_CODE |
| 341 | |
| 342 | #if defined(__MD95__) |
| 343 | #define IRQID_CUIF_U2C_IRQ_N5 IRQ_USIP1_1_CODE |
| 344 | #define IRQID_CUIF_U2C_IRQ_N6 IRQ_USIP2_1_CODE |
| 345 | #endif |
| 346 | |
| 347 | #elif defined(__MD97__) || defined(__MD97P__) |
| 348 | |
| 349 | #define IRQID_CUIF_U2C_IRQ_N0 IRQ_USIP0_CODE |
| 350 | #define IRQID_CUIF_U2C_IRQ_N1 IRQ_USIP1_CODE |
| 351 | #define IRQID_CUIF_U2C_IRQ_N2 IRQ_USIP2_CODE |
| 352 | #define IRQID_CUIF_U2C_IRQ_N3 IRQ_USIP3_CODE |
| 353 | #define IRQID_CUIF_U2C_IRQ_N4 IRQ_USIP4_CODE |
| 354 | #define IRQID_CUIF_U2C_IRQ_N5 IRQ_USIP5_CODE |
| 355 | #define IRQID_CUIF_U2C_IRQ_N6 IRQ_USIP6_CODE |
| 356 | #define IRQID_CUIF_U2C_IRQ_N7 IRQ_USIP7_CODE |
| 357 | #define IRQID_CUIF_U2C_IRQ_N8 IRQ_USIP8_CODE |
| 358 | #define IRQID_CUIF_U2C_IRQ_N9 IRQ_USIP9_CODE |
| 359 | #define IRQID_CUIF_U2C_IRQ_N10 IRQ_USIP10_CODE |
| 360 | #define IRQID_CUIF_U2C_IRQ_N11 IRQ_USIP11_CODE |
| 361 | #define IRQID_CUIF_U2C_IRQ_N12 IRQ_USIP12_CODE |
| 362 | #define IRQID_CUIF_U2C_IRQ_N13 IRQ_USIP13_CODE |
| 363 | |
| 364 | #endif |
| 365 | |
| 366 | |
| 367 | #if defined(__MD93__) |
| 368 | #define CUIF_VPE_NUM (4) |
| 369 | #elif defined(__MD95__) |
| 370 | #define CUIF_VPE_NUM (6) |
| 371 | #elif defined(__MD97__) || defined(__MD97P__) |
| 372 | #define CUIF_VPE_NUM (12) |
| 373 | #endif |
| 374 | /* because reg is type of int, reg + 1 = addr + 4 */ |
| 375 | #define REG_OFFSET(mID) (mID * 6) |
| 376 | |
| 377 | #define ARRAY_OFFSET(mID) (mID) |
| 378 | |
| 379 | |
| 380 | /* cuif handler*/ |
| 381 | #if !defined(__CUIF_DEBUG__) |
| 382 | #define CUIF_HANDLER(nID) \ |
| 383 | cuif_InterruptHandlerInternal( \ |
| 384 | CUIF_U2C_STATUS_BASE + REG_OFFSET(nID), \ |
| 385 | CUIF_U2C_EN_BASE + REG_OFFSET(nID), \ |
| 386 | CUIF_U2C_CLEAR_BASE + REG_OFFSET(nID), \ |
| 387 | cuif_isr_handler[ARRAY_OFFSET(nID)], \ |
| 388 | cuif_isr_eoi[ARRAY_OFFSET(nID)]) |
| 389 | #else /* __CUIF_DEBUG__ */ |
| 390 | #define CUIF_HANDLER(nID) \ |
| 391 | cuif_InterruptHandlerInternal( \ |
| 392 | CUIF_U2C_STATUS_BASE + REG_OFFSET(nID), \ |
| 393 | CUIF_U2C_EN_BASE + REG_OFFSET(nID), \ |
| 394 | CUIF_U2C_CLEAR_BASE + REG_OFFSET(nID), \ |
| 395 | cuif_isr_handler[ARRAY_OFFSET(nID)], \ |
| 396 | cuif_isr_eoi[ARRAY_OFFSET(nID)], \ |
| 397 | nID) |
| 398 | #endif /* __CUIF_DEBUG__ */ |
| 399 | |
| 400 | |
| 401 | |
| 402 | /* cuif overflow debug info */ |
| 403 | typedef struct{ |
| 404 | cuif_uint32 receiver; /**< The mcu receiver: 0~4 means n0~n4 */ |
| 405 | cuif_uint32 interrupt_bit; /**< The overflow bit */ |
| 406 | cuif_uint32 status_addr; /**< The addr of the status register */ |
| 407 | cuif_uint32 current_status;/**< The current value of the status register */ |
| 408 | cuif_uint32 caller; /**< The caller address */ |
| 409 | cuif_uint32 time; |
| 410 | }CUIF_OverFlowRecord; |
| 411 | |
| 412 | /** |
| 413 | * CUIF Init function |
| 414 | */ |
| 415 | extern void CUIF_Init(); |
| 416 | |
| 417 | |
| 418 | /******************************************************************************* |
| 419 | * Debug feature |
| 420 | *******************************************************************************/ |
| 421 | #if defined(__CUIF_DEBUG__) |
| 422 | |
| 423 | #if __CUIF_MD32S_CORE__ |
| 424 | /* MD32 side */ |
| 425 | #define CUIF_DEBUG_API_RECORD_SIZE 8 |
| 426 | #define CUIF_DEBUG_ISR_HANDLE_CODE_SIZE 8 |
| 427 | |
| 428 | #else /* __CUIF_MD32S_CORE__ */ |
| 429 | |
| 430 | #define CUIF_DEBUG_API_RECORD_SIZE 16 |
| 431 | #define CUIF_DEBUG_ISR_HANDLE_CODE_SIZE 16 |
| 432 | |
| 433 | #endif /* __CUIF_MD32S_CORE__ */ |
| 434 | |
| 435 | typedef struct{ |
| 436 | cuif_uint32 time; |
| 437 | cuif_uint32 code; |
| 438 | }CUIF_DebugISRRecord; |
| 439 | |
| 440 | /** The Ring Buffer */ |
| 441 | typedef struct{ |
| 442 | CUIF_DebugISRRecord records[CUIF_DEBUG_ISR_HANDLE_CODE_SIZE]; |
| 443 | cuif_uint32 top_index; |
| 444 | }CUIF_DebugISRCodeList; |
| 445 | |
| 446 | typedef struct{ |
| 447 | cuif_uint32 time; |
| 448 | cuif_uint32 status; |
| 449 | cuif_uint32 set_addr; /**< The control register address */ |
| 450 | cuif_uint32 set_value; /**< The writing value for the control regsiters */ |
| 451 | cuif_uint32 caller; /**< The caller address */ |
| 452 | }CUIF_DebugRecord; |
| 453 | |
| 454 | /** The Ring Buffer */ |
| 455 | typedef struct{ |
| 456 | CUIF_DebugRecord records[CUIF_DEBUG_API_RECORD_SIZE]; |
| 457 | kal_atomic_uint32 top_index; |
| 458 | }CUIF_DebugRecordList; |
| 459 | |
| 460 | void cuif_DebugAddRecord(cuif_uint32 status, |
| 461 | volatile cuif_uint32* set_addr, |
| 462 | cuif_uint32 set_value, |
| 463 | cuif_uint32 caller); |
| 464 | |
| 465 | void cuif_DebugAddISRHandleCode(cuif_uint32 code, CUIF_MCU_INT nID); |
| 466 | |
| 467 | #endif /* __CUIF_DEBUG__ */ |
| 468 | |
| 469 | |
| 470 | |
| 471 | #if defined(__CUIF_DRV_TEST__) |
| 472 | |
| 473 | |
| 474 | //#include "dsp_header_define_cuif_inner_brp.h" |
| 475 | #define CUIF_INNER_BRP_BASE ((kal_uint32)(0xA0840000)) // Bank A: L1 normal access. |
| 476 | #define CUIF_SYNC_ADDR_USIP0 ((CUIF_INNER_BRP_BASE) + 0x2000) |
| 477 | |
| 478 | #if defined(__MD97__) || defined(__MD97P__) |
| 479 | //#include "dsp_header_define_cuif_speech.h" |
| 480 | #define CUIF_SPEECH_BASE ((kal_uint32)(0xA0944700)) |
| 481 | #define CUIF_SYNC_ADDR_USIP1 ((CUIF_SPEECH_BASE) + 0x2000) |
| 482 | #else |
| 483 | #include "dsp_header_define_cuif_fec_wbrp.h" |
| 484 | #define CUIF_SYNC_ADDR_USIP1 ((CUIF_FEC_WBRP_BASE) + 0x2000) |
| 485 | #endif |
| 486 | |
| 487 | #define INT INVALID_INT |
| 488 | #define UINT INVALID_UINT |
| 489 | #define INT32 INVALID_INT32 |
| 490 | #define UINT32 INVALID_UINT32 |
| 491 | |
| 492 | #define CUIF_DRV_TEST_ASSERT_EQ(a, b) \ |
| 493 | do{ \ |
| 494 | if((a) != (b)){ \ |
| 495 | dbg_print("Error: %s: %d - %d != %d\n", __FILE__, __LINE__, (a), (b)); \ |
| 496 | while(1); \ |
| 497 | } \ |
| 498 | }while(0) |
| 499 | |
| 500 | extern cuif_uint32 cuif_c2u_int_source_num[CUIF_ENUM_ALL_USIP_INT_NUM]; |
| 501 | extern cuif_uint32 cuif_u2c_int_source_num[CUIF_ENUM_ALL_MCU_INT_NUM - 1]; |
| 502 | |
| 503 | extern void CUIF_DriverTestISR_N0(CUIF_Mask_t* mask); |
| 504 | extern void CUIF_DriverTestISR_N1(CUIF_Mask_t* mask); |
| 505 | extern void CUIF_DriverTestISR_N2(CUIF_Mask_t* mask); |
| 506 | extern void CUIF_DriverTestISR_N3(CUIF_Mask_t* mask); |
| 507 | extern void CUIF_DriverTestISR_N4(CUIF_Mask_t* mask); |
| 508 | #if defined(__MD97__) || defined(__MD97P__) |
| 509 | extern void CUIF_DriverTestISR_N5(CUIF_Mask_t* mask); |
| 510 | extern void CUIF_DriverTestISR_N6(CUIF_Mask_t* mask); |
| 511 | extern void CUIF_DriverTestISR_N7(CUIF_Mask_t* mask); |
| 512 | extern void CUIF_DriverTestISR_N8(CUIF_Mask_t* mask); |
| 513 | extern void CUIF_DriverTestISR_N9(CUIF_Mask_t* mask); |
| 514 | extern void CUIF_DriverTestISR_N10(CUIF_Mask_t* mask); |
| 515 | extern void CUIF_DriverTestISR_N11(CUIF_Mask_t* mask); |
| 516 | extern void CUIF_DriverTestISR_N12(CUIF_Mask_t* mask); |
| 517 | extern void CUIF_DriverTestISR_N13(CUIF_Mask_t* mask); |
| 518 | #endif |
| 519 | |
| 520 | #endif /* __CUIF_DRV_TEST__ */ |
| 521 | |
| 522 | |
| 523 | #endif /* __DRV_CUIF_H__ */ |