| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame^] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * idc_reg.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * MOLY_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This file is intends for UART driver. |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
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| 168 | *------------------------------------------------------------------------------ |
| 169 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 170 | *============================================================================ |
| 171 | ****************************************************************************/ |
| 172 | #ifndef __IDC_REG_H__ |
| 173 | #define __IDC_REG_H__ |
| 174 | |
| 175 | |
| 176 | #define IDC_CTRL_BASE (L1_BASE_NADDR_IDC_CTRL) |
| 177 | #define IDC_CTRL_BASE_D ((L1_BASE_MADDR_IDC_CTRL & ~MDSYS_PERI_ACC_TYPE_MASK) | MDSYS_PERI_DEVICE_TYPE) |
| 178 | #define IDC_UART_BASE (L1_BASE_NADDR_IDC_UART) |
| 179 | |
| 180 | // Clock Gating Reg |
| 181 | #define PDN_LTE_TMR_MASK (0x00000200) |
| 182 | |
| 183 | #if defined(__MD97__) || (defined(__MD97P__)) |
| 184 | #define MODEML1_AO_CONFIG_BASE (0xB8020000) |
| 185 | #define IDC_FRC_READY (1 << 31) |
| 186 | #define IDC_FRC_OFFSET 0x3FFFFFFF |
| 187 | #define IDC_FRC_WRAP 0x40000000 |
| 188 | #else |
| 189 | #define MODEML1_AO_CONFIG_BASE (0xB6020000) |
| 190 | #endif |
| 191 | #define MDL1AO_CLK_STA (MODEML1_AO_CONFIG_BASE + 0x18) |
| 192 | #define MDL1AO_PDN_STA (MODEML1_AO_CONFIG_BASE + 0x50) |
| 193 | #define MDL1AO_PDN_CLR (MODEML1_AO_CONFIG_BASE + 0x58) |
| 194 | #define PDN_IDC_CTRL_MASK (0x00000800) |
| 195 | #define PDN_IDC_UART_MASK (0x00004000) |
| 196 | |
| 197 | //GPS_B13_B14 |
| 198 | #define GPS_B13_B14_REG (0xC0003328) |
| 199 | #define GPS_LTE_MASK (0xFFFC) |
| 200 | #define GPS_NR_MASK (0xFFFB) |
| 201 | #define GPS_LTE_OFS (0x3) |
| 202 | #define GPS_NR_OFS (0x4) |
| 203 | |
| 204 | //GEN97_PETRUS |
| 205 | // IDC_CTRL |
| 206 | #define IDC_CTRL_WRAP_REG (IDC_CTRL_BASE + 0x2C) //set SRAM wrap start_idx |
| 207 | // IDC_UART |
| 208 | #define IDC_STATUS_1 (IDC_UART_BASE + 0x134) // show NEW_PM ERR status |
| 209 | #define IDC_TX_AUTO_DIS (IDC_UART_BASE + 0x138) |
| 210 | #define IDC_HW_TX_FORCFE_ON_MASK (IDC_UART_BASE + 0x13C) |
| 211 | #define IDC_HW_TX_FORCE_ON (IDC_UART_BASE + 0x140) |
| 212 | #define IDC_CAL_WINDOW_CFG (IDC_UART_BASE + 0x144) |
| 213 | #define IDC_TX_SUSP_QUOTA_CFG (IDC_UART_BASE + 0x148) |
| 214 | #define IDC_TX_FORCFE_ON_INT_MASK (IDC_UART_BASE + 0x14C) |
| 215 | #define IDC_HW_IDC_FORCFE_ON_CLR (IDC_UART_BASE + 0x150) |
| 216 | |
| 217 | #define CAL_WINDOW_RF0 (IDC_UART_BASE + 0x20C) |
| 218 | #define TX_SUSP_QUOTA_RF0 (IDC_UART_BASE + 0x210) |
| 219 | #define CAL_WINDOW_RF1 (IDC_UART_BASE + 0x214) |
| 220 | #define TX_SUSP_QUOTA_RF1 (IDC_UART_BASE + 0x218) |
| 221 | |
| 222 | // IDC_CTRL (Strongly Order) |
| 223 | #define IDC_CTRL_SCH_STOP (IDC_CTRL_BASE + 0x04) |
| 224 | #define IDC_CTRL_SCH_STATUS (IDC_CTRL_BASE + 0x08) |
| 225 | #define IDC_CTRL_DATA_CNT_CTRL (IDC_CTRL_BASE + 0x0C) |
| 226 | #define IDC_CTRL_DATA_CNT (IDC_CTRL_BASE + 0x10) |
| 227 | #define IDC_CTRL_FRC_REG (IDC_CTRL_BASE + 0x24) |
| 228 | #define IDC_CTRL_SCH_STATUS2 (IDC_CTRL_BASE + 0x28) |
| 229 | |
| 230 | #define IDC_CTRL_EVT_DATA0 (IDC_CTRL_BASE + 0x100) |
| 231 | #define IDC_CTRL_EVT_DATA(_n) (IDC_CTRL_EVT_DATA0 + ((_n) << 2)) |
| 232 | |
| 233 | #define IDC_CTRL_EVENT_SETETING0 (IDC_CTRL_BASE + 0x200) |
| 234 | #define IDC_CTRL_EVENT_SETETING(_n) (IDC_CTRL_EVENT_SETETING0 + ((_n) << 2)) |
| 235 | |
| 236 | #if defined(__MD95__) || defined(__MD97__) || defined(__MD97P__) |
| 237 | #define IDC_CTRL_EVENT_MEM_POS0 (IDC_CTRL_BASE + 0x300) |
| 238 | #define IDC_CTRL_EVENT_MEM_POS(_n) (IDC_CTRL_EVENT_MEM_POS0 + ((_n) << 2)) |
| 239 | #endif |
| 240 | |
| 241 | #if defined(__MD93__) |
| 242 | #define IDC_CTRL_GPS_EVENT_BASE (IDC_CTRL_BASE + 0x300) |
| 243 | #elif defined(__MD95__) || defined(__MD97__) || defined(__MD97P__) |
| 244 | #define IDC_CTRL_GPS_EVENT_BASE (IDC_CTRL_BASE + 0x400) |
| 245 | #endif |
| 246 | |
| 247 | #define IDC_CTRL_GPS_EVENT_OFF (IDC_CTRL_GPS_EVENT_BASE) |
| 248 | #define IDC_CTRL_GPS_EVENT_ON (IDC_CTRL_GPS_EVENT_BASE + 0x04) |
| 249 | #define IDC_CTRL_GPS_EVENT_STATUS (IDC_CTRL_GPS_EVENT_BASE + 0x08) |
| 250 | #define IDC_CTRL_GPS_EVENT_STOP (IDC_CTRL_GPS_EVENT_BASE + 0x0C) |
| 251 | #define IDC_CTRL_GPS_EVENT_L5_OFF (IDC_CTRL_GPS_EVENT_BASE + 0x10) |
| 252 | #define IDC_CTRL_GPS_EVENT_L5_ON (IDC_CTRL_GPS_EVENT_BASE + 0x14) |
| 253 | #define IDC_CTRL_GPS_EVENT_L5_STATUS (IDC_CTRL_GPS_EVENT_BASE + 0x18) |
| 254 | #define IDC_CTRL_GPS_EVENT_L5_STOP (IDC_CTRL_GPS_EVENT_BASE + 0x1C) |
| 255 | |
| 256 | |
| 257 | |
| 258 | #define IDC_CTRL_DUMMY (IDC_CTRL_BASE + 0x14) |
| 259 | #define IDC_CTRL_RSV0 (IDC_CTRL_BASE + 0x18) |
| 260 | #define IDC_CTRL_RSV1 (IDC_CTRL_BASE + 0x1C) |
| 261 | #define IDC_CTRL_DBG_FLAG (IDC_CTRL_BASE + 0x20) |
| 262 | |
| 263 | |
| 264 | // IDC_CTRL (Device Type) |
| 265 | #define IDC_CTRL_SCH_STOP_D (IDC_CTRL_BASE_D + 0x04) |
| 266 | #define IDC_CTRL_SCH_STATUS_D (IDC_CTRL_BASE_D + 0x08) |
| 267 | #define IDC_CTRL_DATA_CNT_CTRL_D (IDC_CTRL_BASE_D + 0x0C) |
| 268 | #define IDC_CTRL_DATA_CNT_D (IDC_CTRL_BASE_D + 0x10) |
| 269 | #define IDC_CTRL_EVT_DATA0_D (IDC_CTRL_BASE_D + 0x100) |
| 270 | #define IDC_CTRL_EVT_DATA_D(_n) (IDC_CTRL_EVT_DATA0_D + ((_n) << 2)) |
| 271 | #define IDC_CTRL_EVENT_SETETING0_D (IDC_CTRL_BASE_D + 0x200) |
| 272 | #define IDC_CTRL_EVENT_SETETING_D(_n) (IDC_CTRL_EVENT_SETETING0_D + ((_n) << 2)) |
| 273 | |
| 274 | #define IDC_CTRL_GPS_EVENT_BASE_D (IDC_CTRL_BASE_D + 0x300) |
| 275 | #define IDC_CTRL_GPS_EVENT_OFF_D (IDC_CTRL_GPS_EVENT_BASE_D) |
| 276 | #define IDC_CTRL_GPS_EVENT_ON_D (IDC_CTRL_GPS_EVENT_BASE_D + 0x04) |
| 277 | #define IDC_CTRL_GPS_EVENT_STATUS_D (IDC_CTRL_GPS_EVENT_BASE_D + 0x08) |
| 278 | |
| 279 | #define IDC_CTRL_DUMMY_D (IDC_CTRL_BASE_D + 0x14) |
| 280 | #define IDC_CTRL_RSV0_D (IDC_CTRL_BASE_D + 0x18) |
| 281 | #define IDC_CTRL_RSV1_D (IDC_CTRL_BASE_D + 0x1C) |
| 282 | #define IDC_CTRL_DBG_FLAG_D (IDC_CTRL_BASE_D + 0x20) |
| 283 | |
| 284 | |
| 285 | // IDC_UART |
| 286 | #define IDC_UART_RBR (IDC_UART_BASE + 0x00) |
| 287 | #define IDC_UART_THR (IDC_UART_BASE + 0x00) |
| 288 | #define IDC_UART_DLL (IDC_UART_BASE + 0x00) |
| 289 | #define IDC_UART_DLM (IDC_UART_BASE + 0x04) |
| 290 | #define IDC_UART_IER (IDC_UART_BASE + 0x04) |
| 291 | #define IDC_UART_IIR (IDC_UART_BASE + 0x08) |
| 292 | #define IDC_UART_FCR (IDC_UART_BASE + 0x08) |
| 293 | #define IDC_UART_LCR (IDC_UART_BASE + 0x0C) |
| 294 | #define IDC_UART_MCR (IDC_UART_BASE + 0x10) |
| 295 | #define IDC_UART_LSR (IDC_UART_BASE + 0x14) |
| 296 | #define IDC_UART_MSR (IDC_UART_BASE + 0x18) |
| 297 | #define IDC_UART_HIGHSPEED (IDC_UART_BASE + 0x24) |
| 298 | #define IDC_UART_SAMPLE_COUNT (IDC_UART_BASE + 0x28) |
| 299 | #define IDC_UART_SAMPLE_POINT (IDC_UART_BASE + 0x2C) |
| 300 | #define IDC_UART_RXTRIG (IDC_UART_BASE + 0x50) |
| 301 | #define IDC_UART_FRACDIV_L_TX (IDC_UART_BASE + 0x54) |
| 302 | #define IDC_UART_FRACDIV_M_TX (IDC_UART_BASE + 0x58) |
| 303 | #define IDC_UART_FRACDIV_L_RX (IDC_UART_BASE + 0x84) |
| 304 | #define IDC_UART_FRACDIV_M_RX (IDC_UART_BASE + 0x88) |
| 305 | #define IDC_UART_FCR_RD (IDC_UART_BASE + 0x5C) |
| 306 | #define IDC_PM_STATUS (IDC_UART_BASE + 0xBC) |
| 307 | #define IDC_PRI0 (IDC_UART_BASE + 0xC0) |
| 308 | #define IDC_PRI0_BITEN (IDC_UART_BASE + 0xC4) |
| 309 | #define IDC_PAT0 (IDC_UART_BASE + 0xC8) |
| 310 | #define IDC_PAT0_BITEN (IDC_UART_BASE + 0xCC) |
| 311 | #define IDC_PRI(_n) (IDC_PRI0 + ((_n) << 4)) |
| 312 | #define IDC_PRI_BITEN(_n) (IDC_PRI0_BITEN + ((_n) << 4)) |
| 313 | #define IDC_PAT(_n) (IDC_PAT0 + ((_n) << 4)) |
| 314 | #define IDC_PAT_BITEN(_n) (IDC_PAT0_BITEN + ((_n) << 4)) |
| 315 | |
| 316 | #define IDC_NEW_PM_ERR_RX_BUFF (IDC_UART_BASE + 0x100) |
| 317 | #define IDC_CC_STATUS (IDC_UART_BASE + 0x104) |
| 318 | #define IDC_NEW_PAT0 (IDC_UART_BASE + 0x108) |
| 319 | #define IDC_NEW_PAT1 (IDC_UART_BASE + 0x10C) |
| 320 | #define IDC_INT_MASK_STATUS (IDC_UART_BASE + 0x110) |
| 321 | #define IDC_INT_MASK_SET (IDC_UART_BASE + 0x114) |
| 322 | #define IDC_INT_MASK_CLR (IDC_UART_BASE + 0x118) |
| 323 | #define IDC_FORCE_TRIGGER_RF (IDC_UART_BASE + 0x11C) |
| 324 | #define IDC_NEW_PM_DEBUG (IDC_UART_BASE + 0x120) |
| 325 | #define IDC_REMAPPING_CFG (IDC_UART_BASE + 0x124) |
| 326 | #define IDC_REMAPPING_EN (IDC_UART_BASE + 0x128) |
| 327 | #define IDC_CC4_STATUS (IDC_UART_BASE + 0x130) // show cc4~cc5 status |
| 328 | |
| 329 | //DEBUG |
| 330 | #define IDC_UART_SCR (IDC_UART_BASE + 0x1C) |
| 331 | #define IDC_TX_WOFFSET (IDC_UART_BASE + 0x70) |
| 332 | #define IDC_OP_RX_REQ (IDC_UART_BASE + 0x74) |
| 333 | #define IDC_RX_ROFFSET (IDC_UART_BASE + 0x78) |
| 334 | #define IDC_RX_WOFFSET (IDC_UART_BASE + 0x7C) |
| 335 | #define IDC_UART_GUARD (IDC_UART_BASE + 0x3C) |
| 336 | #define IDC_UART_ESCAPE_EN (IDC_UART_BASE + 0x44) |
| 337 | #define IDC_UART_SLEEP_EN (IDC_UART_BASE + 0x48) |
| 338 | #define IDC_UART_DEBUG_1 (IDC_UART_BASE + 0x64) |
| 339 | #define IDC_UART_DEBUG_8 (IDC_UART_BASE + 0x80) |
| 340 | #define IDC_UART_DEBUG_10 (IDC_UART_BASE + 0x204) |
| 341 | #define IDC_UART_SLEEP_CTRL (IDC_UART_BASE + 0xB0) |
| 342 | #define IDC_UART_MISC_CTRL (IDC_UART_BASE + 0xB4) |
| 343 | #define IDC_UART_DLL_backup (IDC_UART_BASE + 0x90) |
| 344 | #define IDC_UART_DLM_backup (IDC_UART_BASE + 0x94) |
| 345 | #define IDC_UART_EFR_backup (IDC_UART_BASE + 0x98) |
| 346 | #define IDC_UART_FEATURE_SEL (IDC_UART_BASE + 0x9C) |
| 347 | |
| 348 | //M2C Bridge |
| 349 | #define M2C_IDC2PTA_BRIDGE_BASE 0xC0211000 |
| 350 | #define M2C_IDC2PTA_BRIDGE_SPM_ACK (M2C_IDC2PTA_BRIDGE_BASE + 0xF00) |
| 351 | #define M2C_IDC2PTA_BRIDGE_M2C_EN (M2C_IDC2PTA_BRIDGE_BASE + 0x500) |
| 352 | #define M2C_IDC2PTA_BRIDGE_M2C_TIME (M2C_IDC2PTA_BRIDGE_BASE + 0x504) |
| 353 | #define M2C_IDC2PTA_BRIDGE_M2C_DBG1 (M2C_IDC2PTA_BRIDGE_BASE + 0x800) |
| 354 | #define M2C_IDC2PTA_BRIDGE_M2C_DBG2 (M2C_IDC2PTA_BRIDGE_BASE + 0x900) |
| 355 | |
| 356 | #define M2C_SPM_ACK (0x7 << 2) |
| 357 | #define M2C_EN 0x7ff |
| 358 | #define M2C_TIME 0x040404 |
| 359 | |
| 360 | //IER |
| 361 | #define IDC_UART_IER_ALLOFF 0x0000 |
| 362 | #define IDC_UART_IER_ERBFI 0x0001 |
| 363 | #define IDC_UART_IER_ETBEI 0x0002 |
| 364 | #define IDC_UART_IER_INT_MASK 0x00ef |
| 365 | |
| 366 | //HIGHSPEED |
| 367 | #define IDC_UART_HIGHSPEED_X 0x0003 // baud = clock/UART_RATE_STEP_COUNT |
| 368 | |
| 369 | //FCR |
| 370 | #define IDC_UART_FCR_FIFOEN 0x0001 |
| 371 | #define IDC_UART_FCR_CLRR 0x0002 |
| 372 | #define IDC_UART_FCR_CLRT 0x0004 |
| 373 | #define IDC_UART_FCR_FIFOINI 0x0007 |
| 374 | #define IDC_UART_FCR_RXTRIG 0x00c0 |
| 375 | |
| 376 | #define IDC_UART_TxFIFO_DEPTH 32 |
| 377 | #define IDC_UART_RxFIFO_DEPTH 32 |
| 378 | |
| 379 | //IIR (RO) |
| 380 | #define IDC_UART_IIR_INT_INVALID 0x0001 |
| 381 | #define IDC_UART_IIR_THR_EMPTY 0x0002 // TX Empty |
| 382 | #define IDC_UART_IIR_RDA 0x0004 // Receive Data Available |
| 383 | #define IDC_UART_IIR_RDT 0x000c // Receive Data Timeout |
| 384 | #define IDC_UART_IIR_INT_MASK 0x003f |
| 385 | |
| 386 | //===============================LCR================================ |
| 387 | //WLS |
| 388 | #define IDC_UART_WLS_8 0x0003 |
| 389 | #define IDC_UART_WLS_7 0x0002 |
| 390 | #define IDC_UART_WLS_6 0x0001 |
| 391 | #define IDC_UART_WLS_5 0x0000 |
| 392 | #define IDC_UART_DATA_MASK 0x0003 |
| 393 | |
| 394 | //Parity |
| 395 | #define IDC_UART_NONE_PARITY 0x0000 |
| 396 | #define IDC_UART_ODD_PARITY 0x0008 |
| 397 | #define IDC_UART_EVEN_PARITY 0x0018 |
| 398 | #define IDC_UART_ONE_PARITY 0x0028 |
| 399 | #define IDC_UART_ZERO_PARITY 0x0038 |
| 400 | #define IDC_UART_PARITY_MASK 0x0038 |
| 401 | |
| 402 | //Stop bits |
| 403 | #define IDC_UART_1_STOP 0x0000 |
| 404 | #define IDC_UART_1_5_STOP 0x0004 // Only valid for 5 data bits |
| 405 | #define IDC_UART_2_STOP 0x0004 |
| 406 | #define IDC_UART_STOP_MASK 0x0004 |
| 407 | |
| 408 | #define IDC_UART_LCR_DLAB 0x0080 |
| 409 | //===============================LCR================================ |
| 410 | |
| 411 | //LSR |
| 412 | #define IDC_UART_LSR_DR 0x0001 |
| 413 | #define IDC_UART_LSR_TEMT 0x0040 |
| 414 | |
| 415 | #endif // __IDC_REG_H__ |