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192.168.1.100 / T800_MD / 6c1fd8fba87d5723e0e5614ae30b4258b603cb70 / . / mcu / driver / devdrv / spmi / src / spmi_dbg.c
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame^]1/* Copyright Statement:
2 *
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein is
5 * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
6 * the prior written permission of MediaTek inc. and/or its licensors, any
7 * reproduction, modification, use or disclosure of MediaTek Software, and
8 * information contained herein, in whole or in part, shall be strictly
9 * prohibited.
10 *
11 * MediaTek Inc. (C) 2019. All rights reserved.
12 *
13 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
14 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
15 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
16 * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
17 * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
19 * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
20 * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
21 * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
22 * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
23 * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
24 * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
25 * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
26 * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
27 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
28 * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
29 * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
30 * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
31 * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
32 *
33 * The following software/firmware and/or related documentation ("MediaTek
34 * Software") have been modified by MediaTek Inc. All revisions are subject to
35 * any receiver's applicable license agreements with MediaTek Inc.
36 */
37/*
38 * MTK SPMI Driver
39 *
40 * Copyright 2018 MediaTek Co.,Ltd.
41 *
42 * DESCRIPTION:
43 * This file provides API for other drivers to access PMIC registers
44 *
45 */
46#include <pmif.h>
47#include <spmi.h>
48#include <spmi_sw.h>
49#include <pmif_sw.h>
50#include <mt6315_upmu_hw.h>
51
52#if !SPMI_NO_PMIC
53
54#if (SPMI_CTP)
55#define sprintf FormatString
56#endif
57
58enum pmif_dbg_regs {
59 PMIF_INIT_DONE,
60 PMIF_INF_BUSY_STA,
61 PMIF_OTHER_BUSY_STA_0,
62 PMIF_OTHER_BUSY_STA_1,
63 PMIF_IRQ_EVENT_EN_0,
64 PMIF_IRQ_FLAG_0,
65 PMIF_IRQ_CLR_0,
66 PMIF_IRQ_EVENT_EN_1,
67 PMIF_IRQ_FLAG_1,
68 PMIF_IRQ_CLR_1,
69 PMIF_IRQ_EVENT_EN_2,
70 PMIF_IRQ_FLAG_2,
71 PMIF_IRQ_CLR_2,
72 PMIF_IRQ_EVENT_EN_3,
73 PMIF_IRQ_FLAG_3,
74 PMIF_IRQ_CLR_3,
75 PMIF_IRQ_EVENT_EN_4,
76 PMIF_IRQ_FLAG_4,
77 PMIF_IRQ_CLR_4,
78 PMIF_WDT_EVENT_EN_0,
79 PMIF_WDT_FLAG_0,
80 PMIF_WDT_EVENT_EN_1,
81 PMIF_WDT_FLAG_1,
82 PMIF_MONITOR_CTRL,
83 PMIF_MONITOR_TARGET_CHAN_0,
84 PMIF_MONITOR_TARGET_CHAN_1,
85 PMIF_MONITOR_TARGET_CHAN_2,
86 PMIF_MONITOR_TARGET_CHAN_3,
87 PMIF_MONITOR_TARGET_CHAN_4,
88 PMIF_MONITOR_TARGET_CHAN_5,
89 PMIF_MONITOR_TARGET_CHAN_6,
90 PMIF_MONITOR_TARGET_CHAN_7,
91 PMIF_MONITOR_TARGET_WRITE,
92 PMIF_MONITOR_TARGET_ADDR_0,
93 PMIF_MONITOR_TARGET_ADDR_1,
94 PMIF_MONITOR_TARGET_ADDR_2,
95 PMIF_MONITOR_TARGET_ADDR_3,
96 PMIF_MONITOR_TARGET_ADDR_4,
97 PMIF_MONITOR_TARGET_ADDR_5,
98 PMIF_MONITOR_TARGET_ADDR_6,
99 PMIF_MONITOR_TARGET_ADDR_7,
100 PMIF_MONITOR_TARGET_WDATA_0,
101 PMIF_MONITOR_TARGET_WDATA_1,
102 PMIF_MONITOR_TARGET_WDATA_2,
103 PMIF_MONITOR_TARGET_WDATA_3,
104 PMIF_MONITOR_TARGET_WDATA_4,
105 PMIF_MONITOR_TARGET_WDATA_5,
106 PMIF_MONITOR_TARGET_WDATA_6,
107 PMIF_MONITOR_TARGET_WDATA_7,
108 PMIF_MONITOR_STA,
109 PMIF_MONITOR_RECORD_0_0,
110 PMIF_MONITOR_RECORD_0_1,
111 PMIF_MONITOR_RECORD_0_2,
112 PMIF_MONITOR_RECORD_0_3,
113 PMIF_MONITOR_RECORD_0_4,
114 PMIF_MONITOR_RECORD_1_0,
115 PMIF_MONITOR_RECORD_1_1,
116 PMIF_MONITOR_RECORD_1_2,
117 PMIF_MONITOR_RECORD_1_3,
118 PMIF_MONITOR_RECORD_1_4,
119 PMIF_MONITOR_RECORD_2_0,
120 PMIF_MONITOR_RECORD_2_1,
121 PMIF_MONITOR_RECORD_2_2,
122 PMIF_MONITOR_RECORD_2_3,
123 PMIF_MONITOR_RECORD_2_4,
124 PMIF_MONITOR_RECORD_3_0,
125 PMIF_MONITOR_RECORD_3_1,
126 PMIF_MONITOR_RECORD_3_2,
127 PMIF_MONITOR_RECORD_3_3,
128 PMIF_MONITOR_RECORD_3_4,
129 PMIF_MONITOR_RECORD_4_0,
130 PMIF_MONITOR_RECORD_4_1,
131 PMIF_MONITOR_RECORD_4_2,
132 PMIF_MONITOR_RECORD_4_3,
133 PMIF_MONITOR_RECORD_4_4,
134 PMIF_MONITOR_RECORD_5_0,
135 PMIF_MONITOR_RECORD_5_1,
136 PMIF_MONITOR_RECORD_5_2,
137 PMIF_MONITOR_RECORD_5_3,
138 PMIF_MONITOR_RECORD_5_4,
139 PMIF_MONITOR_RECORD_6_0,
140 PMIF_MONITOR_RECORD_6_1,
141 PMIF_MONITOR_RECORD_6_2,
142 PMIF_MONITOR_RECORD_6_3,
143 PMIF_MONITOR_RECORD_6_4,
144 PMIF_MONITOR_RECORD_7_0,
145 PMIF_MONITOR_RECORD_7_1,
146 PMIF_MONITOR_RECORD_7_2,
147 PMIF_MONITOR_RECORD_7_3,
148 PMIF_MONITOR_RECORD_7_4,
149 PMIF_MONITOR_RECORD_8_0,
150 PMIF_MONITOR_RECORD_8_1,
151 PMIF_MONITOR_RECORD_8_2,
152 PMIF_MONITOR_RECORD_8_3,
153 PMIF_MONITOR_RECORD_8_4,
154 PMIF_MONITOR_RECORD_9_0,
155 PMIF_MONITOR_RECORD_9_1,
156 PMIF_MONITOR_RECORD_9_2,
157 PMIF_MONITOR_RECORD_9_3,
158 PMIF_MONITOR_RECORD_9_4,
159 PMIF_MONITOR_RECORD_10_0,
160 PMIF_MONITOR_RECORD_10_1,
161 PMIF_MONITOR_RECORD_10_2,
162 PMIF_MONITOR_RECORD_10_3,
163 PMIF_MONITOR_RECORD_10_4,
164 PMIF_MONITOR_RECORD_11_0,
165 PMIF_MONITOR_RECORD_11_1,
166 PMIF_MONITOR_RECORD_11_2,
167 PMIF_MONITOR_RECORD_11_3,
168 PMIF_MONITOR_RECORD_11_4,
169 PMIF_MONITOR_RECORD_12_0,
170 PMIF_MONITOR_RECORD_12_1,
171 PMIF_MONITOR_RECORD_12_2,
172 PMIF_MONITOR_RECORD_12_3,
173 PMIF_MONITOR_RECORD_12_4,
174 PMIF_MONITOR_RECORD_13_0,
175 PMIF_MONITOR_RECORD_13_1,
176 PMIF_MONITOR_RECORD_13_2,
177 PMIF_MONITOR_RECORD_13_3,
178 PMIF_MONITOR_RECORD_13_4,
179 PMIF_MONITOR_RECORD_14_0,
180 PMIF_MONITOR_RECORD_14_1,
181 PMIF_MONITOR_RECORD_14_2,
182 PMIF_MONITOR_RECORD_14_3,
183 PMIF_MONITOR_RECORD_14_4,
184 PMIF_MONITOR_RECORD_15_0,
185 PMIF_MONITOR_RECORD_15_1,
186 PMIF_MONITOR_RECORD_15_2,
187 PMIF_MONITOR_RECORD_15_3,
188 PMIF_MONITOR_RECORD_15_4,
189 PMIF_MONITOR_RECORD_16_0,
190 PMIF_MONITOR_RECORD_16_1,
191 PMIF_MONITOR_RECORD_16_2,
192 PMIF_MONITOR_RECORD_16_3,
193 PMIF_MONITOR_RECORD_16_4,
194 PMIF_MONITOR_RECORD_17_0,
195 PMIF_MONITOR_RECORD_17_1,
196 PMIF_MONITOR_RECORD_17_2,
197 PMIF_MONITOR_RECORD_17_3,
198 PMIF_MONITOR_RECORD_17_4,
199 PMIF_MONITOR_RECORD_18_0,
200 PMIF_MONITOR_RECORD_18_1,
201 PMIF_MONITOR_RECORD_18_2,
202 PMIF_MONITOR_RECORD_18_3,
203 PMIF_MONITOR_RECORD_18_4,
204 PMIF_MONITOR_RECORD_19_0,
205 PMIF_MONITOR_RECORD_19_1,
206 PMIF_MONITOR_RECORD_19_2,
207 PMIF_MONITOR_RECORD_19_3,
208 PMIF_MONITOR_RECORD_19_4,
209 PMIF_MONITOR_RECORD_20_0,
210 PMIF_MONITOR_RECORD_20_1,
211 PMIF_MONITOR_RECORD_20_2,
212 PMIF_MONITOR_RECORD_20_3,
213 PMIF_MONITOR_RECORD_20_4,
214 PMIF_MONITOR_RECORD_21_0,
215 PMIF_MONITOR_RECORD_21_1,
216 PMIF_MONITOR_RECORD_21_2,
217 PMIF_MONITOR_RECORD_21_3,
218 PMIF_MONITOR_RECORD_21_4,
219 PMIF_MONITOR_RECORD_22_0,
220 PMIF_MONITOR_RECORD_22_1,
221 PMIF_MONITOR_RECORD_22_2,
222 PMIF_MONITOR_RECORD_22_3,
223 PMIF_MONITOR_RECORD_22_4,
224 PMIF_MONITOR_RECORD_23_0,
225 PMIF_MONITOR_RECORD_23_1,
226 PMIF_MONITOR_RECORD_23_2,
227 PMIF_MONITOR_RECORD_23_3,
228 PMIF_MONITOR_RECORD_23_4,
229 PMIF_MONITOR_RECORD_24_0,
230 PMIF_MONITOR_RECORD_24_1,
231 PMIF_MONITOR_RECORD_24_2,
232 PMIF_MONITOR_RECORD_24_3,
233 PMIF_MONITOR_RECORD_24_4,
234 PMIF_MONITOR_RECORD_25_0,
235 PMIF_MONITOR_RECORD_25_1,
236 PMIF_MONITOR_RECORD_25_2,
237 PMIF_MONITOR_RECORD_25_3,
238 PMIF_MONITOR_RECORD_25_4,
239 PMIF_MONITOR_RECORD_26_0,
240 PMIF_MONITOR_RECORD_26_1,
241 PMIF_MONITOR_RECORD_26_2,
242 PMIF_MONITOR_RECORD_26_3,
243 PMIF_MONITOR_RECORD_26_4,
244 PMIF_MONITOR_RECORD_27_0,
245 PMIF_MONITOR_RECORD_27_1,
246 PMIF_MONITOR_RECORD_27_2,
247 PMIF_MONITOR_RECORD_27_3,
248 PMIF_MONITOR_RECORD_27_4,
249 PMIF_MONITOR_RECORD_28_0,
250 PMIF_MONITOR_RECORD_28_1,
251 PMIF_MONITOR_RECORD_28_2,
252 PMIF_MONITOR_RECORD_28_3,
253 PMIF_MONITOR_RECORD_28_4,
254 PMIF_MONITOR_RECORD_29_0,
255 PMIF_MONITOR_RECORD_29_1,
256 PMIF_MONITOR_RECORD_29_2,
257 PMIF_MONITOR_RECORD_29_3,
258 PMIF_MONITOR_RECORD_29_4,
259 PMIF_MONITOR_RECORD_30_0,
260 PMIF_MONITOR_RECORD_30_1,
261 PMIF_MONITOR_RECORD_30_2,
262 PMIF_MONITOR_RECORD_30_3,
263 PMIF_MONITOR_RECORD_30_4,
264 PMIF_MONITOR_RECORD_31_0,
265 PMIF_MONITOR_RECORD_31_1,
266 PMIF_MONITOR_RECORD_31_2,
267 PMIF_MONITOR_RECORD_31_3,
268 PMIF_MONITOR_RECORD_31_4,
269 PMIF_DEBUG_CTRL,
270 PMIF_RESERVED_0,
271 PMIF_SWINF_0_ACC,
272 PMIF_SWINF_0_WDATA_31_0,
273 PMIF_SWINF_0_WDATA_63_32,
274 PMIF_SWINF_0_RDATA_31_0,
275 PMIF_SWINF_0_RDATA_63_32,
276 PMIF_SWINF_0_VLD_CLR,
277 PMIF_SWINF_0_STA,
278 PMIF_SWINF_1_ACC,
279 PMIF_SWINF_1_WDATA_31_0,
280 PMIF_SWINF_1_WDATA_63_32,
281 PMIF_SWINF_1_RDATA_31_0,
282 PMIF_SWINF_1_RDATA_63_32,
283 PMIF_SWINF_1_VLD_CLR,
284 PMIF_SWINF_1_STA,
285 PMIF_SWINF_2_ACC,
286 PMIF_SWINF_2_WDATA_31_0,
287 PMIF_SWINF_2_WDATA_63_32,
288 PMIF_SWINF_2_RDATA_31_0,
289 PMIF_SWINF_2_RDATA_63_32,
290 PMIF_SWINF_2_VLD_CLR,
291 PMIF_SWINF_2_STA,
292 PMIF_SWINF_3_ACC,
293 PMIF_SWINF_3_WDATA_31_0,
294 PMIF_SWINF_3_WDATA_63_32,
295 PMIF_SWINF_3_RDATA_31_0,
296 PMIF_SWINF_3_RDATA_63_32,
297 PMIF_SWINF_3_VLD_CLR,
298 PMIF_SWINF_3_STA,
299};
300
301static int mt6xxx_pmif_dbg_regs[] = {
302 [PMIF_INIT_DONE] = 0x0000,
303 [PMIF_INF_BUSY_STA] = 0x0018,
304 [PMIF_OTHER_BUSY_STA_0] = 0x001C,
305 [PMIF_OTHER_BUSY_STA_1] = 0x0020,
306 [PMIF_IRQ_EVENT_EN_0] = 0x0418,
307 [PMIF_IRQ_FLAG_0] = 0x0420,
308 [PMIF_IRQ_CLR_0] = 0x0424,
309 [PMIF_IRQ_EVENT_EN_1] = 0x0428,
310 [PMIF_IRQ_FLAG_1] = 0x0430,
311 [PMIF_IRQ_CLR_1] = 0x0434,
312 [PMIF_IRQ_EVENT_EN_2] = 0x0438,
313 [PMIF_IRQ_FLAG_2] = 0x0440,
314 [PMIF_IRQ_CLR_2] = 0x0444,
315 [PMIF_IRQ_EVENT_EN_3] = 0x0448,
316 [PMIF_IRQ_FLAG_3] = 0x0450,
317 [PMIF_IRQ_CLR_3] = 0x0454,
318 [PMIF_IRQ_EVENT_EN_4] = 0x0458,
319 [PMIF_IRQ_FLAG_4] = 0x0460,
320 [PMIF_IRQ_CLR_4] = 0x0464,
321 [PMIF_WDT_EVENT_EN_0] = 0x046C,
322 [PMIF_WDT_FLAG_0] = 0x0470,
323 [PMIF_WDT_EVENT_EN_1] = 0x0474,
324 [PMIF_WDT_FLAG_1] = 0x0478,
325 [PMIF_MONITOR_CTRL] = 0x047C,
326 [PMIF_MONITOR_TARGET_CHAN_0] = 0x0480,
327 [PMIF_MONITOR_TARGET_CHAN_1] = 0x0484,
328 [PMIF_MONITOR_TARGET_CHAN_2] = 0x0488,
329 [PMIF_MONITOR_TARGET_CHAN_3] = 0x048C,
330 [PMIF_MONITOR_TARGET_CHAN_4] = 0x0490,
331 [PMIF_MONITOR_TARGET_CHAN_5] = 0x0494,
332 [PMIF_MONITOR_TARGET_CHAN_6] = 0x0498,
333 [PMIF_MONITOR_TARGET_CHAN_7] = 0x049C,
334 [PMIF_MONITOR_TARGET_WRITE] = 0x04A0,
335 [PMIF_MONITOR_TARGET_ADDR_0] = 0x04A4,
336 [PMIF_MONITOR_TARGET_ADDR_1] = 0x04A8,
337 [PMIF_MONITOR_TARGET_ADDR_2] = 0x04AC,
338 [PMIF_MONITOR_TARGET_ADDR_3] = 0x04B0,
339 [PMIF_MONITOR_TARGET_ADDR_4] = 0x04B4,
340 [PMIF_MONITOR_TARGET_ADDR_5] = 0x04B8,
341 [PMIF_MONITOR_TARGET_ADDR_6] = 0x04BC,
342 [PMIF_MONITOR_TARGET_ADDR_7] = 0x04C0,
343 [PMIF_MONITOR_TARGET_WDATA_0] = 0x04C4,
344 [PMIF_MONITOR_TARGET_WDATA_1] = 0x04C8,
345 [PMIF_MONITOR_TARGET_WDATA_2] = 0x04CC,
346 [PMIF_MONITOR_TARGET_WDATA_3] = 0x04D0,
347 [PMIF_MONITOR_TARGET_WDATA_4] = 0x04D4,
348 [PMIF_MONITOR_TARGET_WDATA_5] = 0x04D8,
349 [PMIF_MONITOR_TARGET_WDATA_6] = 0x04DC,
350 [PMIF_MONITOR_TARGET_WDATA_7] = 0x04E0,
351 [PMIF_MONITOR_STA] = 0x04E4,
352 [PMIF_MONITOR_RECORD_0_0] = 0x04E8,
353 [PMIF_MONITOR_RECORD_0_1] = 0x04EC,
354 [PMIF_MONITOR_RECORD_0_2] = 0x04F0,
355 [PMIF_MONITOR_RECORD_0_3] = 0x04F4,
356 [PMIF_MONITOR_RECORD_0_4] = 0x04F8,
357 [PMIF_MONITOR_RECORD_1_0] = 0x04FC,
358 [PMIF_MONITOR_RECORD_1_1] = 0x0500,
359 [PMIF_MONITOR_RECORD_1_2] = 0x0504,
360 [PMIF_MONITOR_RECORD_1_3] = 0x0508,
361 [PMIF_MONITOR_RECORD_1_4] = 0x050C,
362 [PMIF_MONITOR_RECORD_2_0] = 0x0510,
363 [PMIF_MONITOR_RECORD_2_1] = 0x0514,
364 [PMIF_MONITOR_RECORD_2_2] = 0x0518,
365 [PMIF_MONITOR_RECORD_2_3] = 0x051C,
366 [PMIF_MONITOR_RECORD_2_4] = 0x0520,
367 [PMIF_MONITOR_RECORD_3_0] = 0x0524,
368 [PMIF_MONITOR_RECORD_3_1] = 0x0528,
369 [PMIF_MONITOR_RECORD_3_2] = 0x052C,
370 [PMIF_MONITOR_RECORD_3_3] = 0x0530,
371 [PMIF_MONITOR_RECORD_3_4] = 0x0534,
372 [PMIF_MONITOR_RECORD_4_0] = 0x0538,
373 [PMIF_MONITOR_RECORD_4_1] = 0x053C,
374 [PMIF_MONITOR_RECORD_4_2] = 0x0540,
375 [PMIF_MONITOR_RECORD_4_3] = 0x0544,
376 [PMIF_MONITOR_RECORD_4_4] = 0x0548,
377 [PMIF_MONITOR_RECORD_5_0] = 0x054C,
378 [PMIF_MONITOR_RECORD_5_1] = 0x0550,
379 [PMIF_MONITOR_RECORD_5_2] = 0x0554,
380 [PMIF_MONITOR_RECORD_5_3] = 0x0558,
381 [PMIF_MONITOR_RECORD_5_4] = 0x055C,
382 [PMIF_MONITOR_RECORD_6_0] = 0x0560,
383 [PMIF_MONITOR_RECORD_6_1] = 0x0564,
384 [PMIF_MONITOR_RECORD_6_2] = 0x0568,
385 [PMIF_MONITOR_RECORD_6_3] = 0x056C,
386 [PMIF_MONITOR_RECORD_6_4] = 0x0570,
387 [PMIF_MONITOR_RECORD_7_0] = 0x0574,
388 [PMIF_MONITOR_RECORD_7_1] = 0x0578,
389 [PMIF_MONITOR_RECORD_7_2] = 0x057C,
390 [PMIF_MONITOR_RECORD_7_3] = 0x0580,
391 [PMIF_MONITOR_RECORD_7_4] = 0x0584,
392 [PMIF_MONITOR_RECORD_8_0] = 0x0588,
393 [PMIF_MONITOR_RECORD_8_1] = 0x058C,
394 [PMIF_MONITOR_RECORD_8_2] = 0x0590,
395 [PMIF_MONITOR_RECORD_8_3] = 0x0594,
396 [PMIF_MONITOR_RECORD_8_4] = 0x0598,
397 [PMIF_MONITOR_RECORD_9_0] = 0x059C,
398 [PMIF_MONITOR_RECORD_9_1] = 0x05A0,
399 [PMIF_MONITOR_RECORD_9_2] = 0x05A4,
400 [PMIF_MONITOR_RECORD_9_3] = 0x05A8,
401 [PMIF_MONITOR_RECORD_9_4] = 0x05AC,
402 [PMIF_MONITOR_RECORD_10_0] = 0x05B0,
403 [PMIF_MONITOR_RECORD_10_1] = 0x05B4,
404 [PMIF_MONITOR_RECORD_10_2] = 0x05B8,
405 [PMIF_MONITOR_RECORD_10_3] = 0x05BC,
406 [PMIF_MONITOR_RECORD_10_4] = 0x05C0,
407 [PMIF_MONITOR_RECORD_11_0] = 0x05C4,
408 [PMIF_MONITOR_RECORD_11_1] = 0x05C8,
409 [PMIF_MONITOR_RECORD_11_2] = 0x05CC,
410 [PMIF_MONITOR_RECORD_11_3] = 0x05D0,
411 [PMIF_MONITOR_RECORD_11_4] = 0x05D4,
412 [PMIF_MONITOR_RECORD_12_0] = 0x05D8,
413 [PMIF_MONITOR_RECORD_12_1] = 0x05DC,
414 [PMIF_MONITOR_RECORD_12_2] = 0x05E0,
415 [PMIF_MONITOR_RECORD_12_3] = 0x05E4,
416 [PMIF_MONITOR_RECORD_12_4] = 0x05E8,
417 [PMIF_MONITOR_RECORD_13_0] = 0x05EC,
418 [PMIF_MONITOR_RECORD_13_1] = 0x05F0,
419 [PMIF_MONITOR_RECORD_13_2] = 0x05F4,
420 [PMIF_MONITOR_RECORD_13_3] = 0x05F8,
421 [PMIF_MONITOR_RECORD_13_4] = 0x05FC,
422 [PMIF_MONITOR_RECORD_14_0] = 0x0600,
423 [PMIF_MONITOR_RECORD_14_1] = 0x0604,
424 [PMIF_MONITOR_RECORD_14_2] = 0x0608,
425 [PMIF_MONITOR_RECORD_14_3] = 0x060C,
426 [PMIF_MONITOR_RECORD_14_4] = 0x0610,
427 [PMIF_MONITOR_RECORD_15_0] = 0x0614,
428 [PMIF_MONITOR_RECORD_15_1] = 0x0618,
429 [PMIF_MONITOR_RECORD_15_2] = 0x061C,
430 [PMIF_MONITOR_RECORD_15_3] = 0x0620,
431 [PMIF_MONITOR_RECORD_15_4] = 0x0624,
432 [PMIF_MONITOR_RECORD_16_0] = 0x0628,
433 [PMIF_MONITOR_RECORD_16_1] = 0x062C,
434 [PMIF_MONITOR_RECORD_16_2] = 0x0630,
435 [PMIF_MONITOR_RECORD_16_3] = 0x0634,
436 [PMIF_MONITOR_RECORD_16_4] = 0x0638,
437 [PMIF_MONITOR_RECORD_17_0] = 0x063C,
438 [PMIF_MONITOR_RECORD_17_1] = 0x0640,
439 [PMIF_MONITOR_RECORD_17_2] = 0x0644,
440 [PMIF_MONITOR_RECORD_17_3] = 0x0648,
441 [PMIF_MONITOR_RECORD_17_4] = 0x064C,
442 [PMIF_MONITOR_RECORD_18_0] = 0x0650,
443 [PMIF_MONITOR_RECORD_18_1] = 0x0654,
444 [PMIF_MONITOR_RECORD_18_2] = 0x0658,
445 [PMIF_MONITOR_RECORD_18_3] = 0x065C,
446 [PMIF_MONITOR_RECORD_18_4] = 0x0660,
447 [PMIF_MONITOR_RECORD_19_0] = 0x0664,
448 [PMIF_MONITOR_RECORD_19_1] = 0x0668,
449 [PMIF_MONITOR_RECORD_19_2] = 0x066C,
450 [PMIF_MONITOR_RECORD_19_3] = 0x0670,
451 [PMIF_MONITOR_RECORD_19_4] = 0x0674,
452 [PMIF_MONITOR_RECORD_20_0] = 0x0678,
453 [PMIF_MONITOR_RECORD_20_1] = 0x067C,
454 [PMIF_MONITOR_RECORD_20_2] = 0x0680,
455 [PMIF_MONITOR_RECORD_20_3] = 0x0684,
456 [PMIF_MONITOR_RECORD_20_4] = 0x0688,
457 [PMIF_MONITOR_RECORD_21_0] = 0x068C,
458 [PMIF_MONITOR_RECORD_21_1] = 0x0690,
459 [PMIF_MONITOR_RECORD_21_2] = 0x0694,
460 [PMIF_MONITOR_RECORD_21_3] = 0x0698,
461 [PMIF_MONITOR_RECORD_21_4] = 0x069C,
462 [PMIF_MONITOR_RECORD_22_0] = 0x06A0,
463 [PMIF_MONITOR_RECORD_22_1] = 0x06A4,
464 [PMIF_MONITOR_RECORD_22_2] = 0x06A8,
465 [PMIF_MONITOR_RECORD_22_3] = 0x06AC,
466 [PMIF_MONITOR_RECORD_22_4] = 0x06B0,
467 [PMIF_MONITOR_RECORD_23_0] = 0x06B4,
468 [PMIF_MONITOR_RECORD_23_1] = 0x06B8,
469 [PMIF_MONITOR_RECORD_23_2] = 0x06BC,
470 [PMIF_MONITOR_RECORD_23_3] = 0x06C0,
471 [PMIF_MONITOR_RECORD_23_4] = 0x06C4,
472 [PMIF_MONITOR_RECORD_24_0] = 0x06C8,
473 [PMIF_MONITOR_RECORD_24_1] = 0x06CC,
474 [PMIF_MONITOR_RECORD_24_2] = 0x06D0,
475 [PMIF_MONITOR_RECORD_24_3] = 0x06D4,
476 [PMIF_MONITOR_RECORD_24_4] = 0x06D8,
477 [PMIF_MONITOR_RECORD_25_0] = 0x06DC,
478 [PMIF_MONITOR_RECORD_25_1] = 0x06E0,
479 [PMIF_MONITOR_RECORD_25_2] = 0x06E4,
480 [PMIF_MONITOR_RECORD_25_3] = 0x06E8,
481 [PMIF_MONITOR_RECORD_25_4] = 0x06EC,
482 [PMIF_MONITOR_RECORD_26_0] = 0x06F0,
483 [PMIF_MONITOR_RECORD_26_1] = 0x06F4,
484 [PMIF_MONITOR_RECORD_26_2] = 0x06F8,
485 [PMIF_MONITOR_RECORD_26_3] = 0x06FC,
486 [PMIF_MONITOR_RECORD_26_4] = 0x0700,
487 [PMIF_MONITOR_RECORD_27_0] = 0x0704,
488 [PMIF_MONITOR_RECORD_27_1] = 0x0708,
489 [PMIF_MONITOR_RECORD_27_2] = 0x070C,
490 [PMIF_MONITOR_RECORD_27_3] = 0x0710,
491 [PMIF_MONITOR_RECORD_27_4] = 0x0714,
492 [PMIF_MONITOR_RECORD_28_0] = 0x0718,
493 [PMIF_MONITOR_RECORD_28_1] = 0x071C,
494 [PMIF_MONITOR_RECORD_28_2] = 0x0720,
495 [PMIF_MONITOR_RECORD_28_3] = 0x0724,
496 [PMIF_MONITOR_RECORD_28_4] = 0x0728,
497 [PMIF_MONITOR_RECORD_29_0] = 0x072C,
498 [PMIF_MONITOR_RECORD_29_1] = 0x0730,
499 [PMIF_MONITOR_RECORD_29_2] = 0x0734,
500 [PMIF_MONITOR_RECORD_29_3] = 0x0738,
501 [PMIF_MONITOR_RECORD_29_4] = 0x073C,
502 [PMIF_MONITOR_RECORD_30_0] = 0x0740,
503 [PMIF_MONITOR_RECORD_30_1] = 0x0744,
504 [PMIF_MONITOR_RECORD_30_2] = 0x0748,
505 [PMIF_MONITOR_RECORD_30_3] = 0x074C,
506 [PMIF_MONITOR_RECORD_30_4] = 0x0750,
507 [PMIF_MONITOR_RECORD_31_0] = 0x0754,
508 [PMIF_MONITOR_RECORD_31_1] = 0x0758,
509 [PMIF_MONITOR_RECORD_31_2] = 0x075C,
510 [PMIF_MONITOR_RECORD_31_3] = 0x0760,
511 [PMIF_MONITOR_RECORD_31_4] = 0x0764,
512 [PMIF_DEBUG_CTRL] = 0x0768,
513 [PMIF_RESERVED_0] = 0x0770,
514 [PMIF_SWINF_0_ACC] = 0x0C00,
515 [PMIF_SWINF_0_WDATA_31_0] = 0x0C04,
516 [PMIF_SWINF_0_WDATA_63_32] = 0x0C08,
517 [PMIF_SWINF_0_RDATA_31_0] = 0x0C14,
518 [PMIF_SWINF_0_RDATA_63_32] = 0x0C18,
519 [PMIF_SWINF_0_VLD_CLR] = 0x0C24,
520 [PMIF_SWINF_0_STA] = 0x0C28,
521 [PMIF_SWINF_1_ACC] = 0x0C40,
522 [PMIF_SWINF_1_WDATA_31_0] = 0x0C44,
523 [PMIF_SWINF_1_WDATA_63_32] = 0x0C48,
524 [PMIF_SWINF_1_RDATA_31_0] = 0x0C54,
525 [PMIF_SWINF_1_RDATA_63_32] = 0x0C58,
526 [PMIF_SWINF_1_VLD_CLR] = 0x0C64,
527 [PMIF_SWINF_1_STA] = 0x0C68,
528 [PMIF_SWINF_2_ACC] = 0x0C80,
529 [PMIF_SWINF_2_WDATA_31_0] = 0x0C84,
530 [PMIF_SWINF_2_WDATA_63_32] = 0x0C88,
531 [PMIF_SWINF_2_RDATA_31_0] = 0x0C94,
532 [PMIF_SWINF_2_RDATA_63_32] = 0x0C98,
533 [PMIF_SWINF_2_VLD_CLR] = 0x0CA4,
534 [PMIF_SWINF_2_STA] = 0x0CA8,
535 [PMIF_SWINF_3_ACC] = 0x0CC0,
536 [PMIF_SWINF_3_WDATA_31_0] = 0x0CC4,
537 [PMIF_SWINF_3_WDATA_63_32] = 0x0CC8,
538 [PMIF_SWINF_3_RDATA_31_0] = 0x0CD4,
539 [PMIF_SWINF_3_RDATA_63_32] = 0x0CD8,
540 [PMIF_SWINF_3_VLD_CLR] = 0x0CE4,
541 [PMIF_SWINF_3_STA] = 0x0CE8,
542};
543#if SPMI_KERNEL
544static unsigned char spmi_pmif_log_buf[1280];
545#endif
546
547/* spmi & pmif debug mechanism */
548void spmi_dump_pmif_busy_reg(int mstid)
549{
550 struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
551 unsigned int i = 0, offset = 0, tmp_dat = 0;
552 unsigned int start = 0, end = 0;
553
554 start = arb->dbgregs[PMIF_INF_BUSY_STA]/4;
555 end = arb->dbgregs[PMIF_OTHER_BUSY_STA_1]/4;
556
557 PMIF_CRI("");
558 for (i = start; i <= end; i++) {
559 offset = arb->dbgregs[PMIF_INF_BUSY_STA] + (i * 4);
560 tmp_dat = DRV_Reg32(arb->base + offset);
561 PMIF_CRIL("(0x%x)=0x%x ", offset, tmp_dat);
562
563 if (i == 0)
564 continue;
565 }
566 PMIF_CRIL("\r\n");
567 spmi_dump_pmif_swinf_reg(mstid);
568
569}
570void spmi_dump_pmif_swinf_reg(int mstid)
571{
572 struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
573 unsigned int i = 0, offset = 0, j = 0, tmp_dat = 0;
574 unsigned int swinf[4] = {0}, cmd[4] = {0}, rw[4] = {0};
575 unsigned int slvid[4] = {0}, bytecnt[4] = {0}, adr[4] = {0};
576#if 0
577/* under construction !*/
578/* under construction !*/
579#endif
580 unsigned int wd_31_0[4] = {0}, rd_31_0[4] = {0};
581 unsigned int err[4] = {0}, sbusy[4] = {0}, done[4] = {0};
582 unsigned int qfillcnt[4] = {0}, qfreecnt[4] = {0}, qempty[4] = {0};
583 unsigned int qfull[4] = {0}, req[4] = {0}, fsm[4] = {0}, en[4] = {0};
584
585 for (i = 0; i < 4; i++) {
586 offset = arb->dbgregs[PMIF_SWINF_0_ACC] + (i * 0x40);
587 tmp_dat = DRV_Reg32(arb->base + offset);
588 swinf[j] = i;
589 cmd[j] = (tmp_dat & (0x3 << 30)) >> 30;
590 rw[j] = (tmp_dat & (0x1 << 29)) >> 29;
591 slvid[j] = (tmp_dat & (0xf << 24)) >> 24;
592 bytecnt[j] = (tmp_dat & (0xf << 16)) >> 16;
593 adr[j] = (tmp_dat & (0xffff << 0)) >> 0;
594 j += 1;
595 }
596 j = 0;
597 for (i = 0; i < 4; i++) {
598 offset = arb->dbgregs[PMIF_SWINF_0_WDATA_31_0] + (i * 0x40);
599 tmp_dat = DRV_Reg32(arb->base + offset);
600 wd_31_0[j] = tmp_dat;
601 j += 1;
602 }
603 j = 0;
604 for (i = 0; i < 4; i++) {
605 offset = arb->dbgregs[PMIF_SWINF_0_RDATA_31_0] + (i * 0x40);
606 tmp_dat = DRV_Reg32(arb->base + offset);
607 rd_31_0[j] = tmp_dat;
608 j += 1;
609 }
610 j = 0;
611 for (i = 0; i < 4; i++) {
612 offset = arb->dbgregs[PMIF_SWINF_0_STA] + (i * 0x40);
613 tmp_dat = DRV_Reg32(arb->base + offset);
614 err[j] = (tmp_dat & (0x1 << 18)) >> 18;
615 sbusy[j] = (tmp_dat & (0x1 << 17)) >> 17;
616 done[j] = (tmp_dat & (0x1 << 15)) >> 15;
617 qfillcnt[j] = (tmp_dat & (0xf << 11)) >> 11;
618 qfreecnt[j] = (tmp_dat & (0xf << 7)) >> 7;
619 qempty[j] = (tmp_dat & (0x1 << 6)) >> 6;
620 qfull[j] = (tmp_dat & (0x1 << 5)) >> 5;
621 req[j] = (tmp_dat & (0x1 << 4)) >> 4;
622 fsm[j] = (tmp_dat & (0x7 << 1)) >> 1;
623 en[j] = (tmp_dat & (0x1 << 0)) >> 0;
624 j += 1;
625 }
626 for (i = 0; i < 4; i++) {
627 if (rw[i] == 0) {
628 PMIF_CRI("[swinf:%d, cmd:0x%x, rw:0x%x, slvid:%d ",
629 swinf[i], cmd[i], rw[i], slvid[i]);
630 PMIF_CRIL("bytecnt:%d (read adr 0x%04x=0x%x)]\r\n",
631 bytecnt[i], adr[i], rd_31_0[i]);
632 PMIF_CRI("[err:%d, sbusy:%d, done:%d, qfillcnt:%d ",
633 err[i], sbusy[i], done[i], qfillcnt[i]);
634 PMIF_CRIL("qfreecnt:%d, qempty:%d, qfull:%d, req:%d ",
635 qfreecnt[i], qempty[i], qfull[i], req[i]);
636 PMIF_CRIL("fsm:%d, en:%d]\r\n", fsm[i], en[i]);
637 } else {
638 PMIF_CRI("[swinf:%d, cmd:0x%x, rw:0x%x, slvid:%d ",
639 swinf[i], cmd[i], rw[i], slvid[i]);
640 PMIF_CRIL("bytecnt:%d (write adr 0x%04x=0x%x)]\r\n",
641 bytecnt[i], adr[i], wd_31_0[i]);
642 PMIF_CRI("[err:%d, sbusy:%d, done:%d, qfillcnt:%d ",
643 err[i], sbusy[i], done[i], qfillcnt[i]);
644 PMIF_CRIL("qfreecnt:%d, qempty:%d, qfull:%d, req:%d ",
645 qfreecnt[i], qempty[i], qfull[i], req[i]);
646 PMIF_CRIL("fsm:%d, en:%d]\r\n", fsm[i], en[i]);
647 }
648 }
649}
650
651void spmi_dump_pmif_reg(int mstid)
652{
653 struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
654 unsigned int i = 0, offset = 0, tmp_dat = 0;
655 unsigned int start = 0, end = 0;
656
657 start = arb->dbgregs[PMIF_INIT_DONE]/4;
658 end = arb->dbgregs[PMIF_RESERVED_0]/4;
659
660 PMIF_CRI("");
661 for (i = start; i <= end; i++) {
662 offset = arb->dbgregs[PMIF_INIT_DONE] + (i * 4);
663 tmp_dat = DRV_Reg32(arb->base + offset);
664 PMIF_CRIL("(0x%x)=0x%x ", offset, tmp_dat);
665
666 if (i == 0)
667 continue;
668 if (i % 8 == 0) {
669 PMIF_CRIL("\r\n[PMIF] ");
670 }
671 }
672 PMIF_CRIL("\r\n");
673 spmi_dump_pmif_swinf_reg(mstid);
674}
675
676void spmi_dump_pmif_record_reg(int mstid)
677{
678 struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
679 unsigned int i = 0, offset = 0, j = 0, tmp_dat = 0;
680 unsigned int chan[32] = {0}, cmd[32] = {0}, rw[32] = {0};
681 unsigned int slvid[32] = {0}, bytecnt[32] = {0}, adr[32] = {0};
682#if 0
683/* under construction !*/
684#endif
685 unsigned int wd_31_0[32] = {0};
686
687 for (i = 0; i < 32; i++) {
688 offset = arb->dbgregs[PMIF_MONITOR_RECORD_0_0] + (i * 0x14);
689 tmp_dat = DRV_Reg32(arb->base + offset);
690 chan[j] = (tmp_dat & (0xf8000000)) >> 27;
691 cmd[j] = (tmp_dat & (0x3 << 25)) >> 25;
692 rw[j] = (tmp_dat & (0x1 << 24)) >> 24;
693 slvid[j] = (tmp_dat & (0xf << 20)) >> 20;
694 bytecnt[j] = (tmp_dat & (0xf << 16)) >> 16;
695 adr[j] = (tmp_dat & (0xffff << 0)) >> 0;
696 j += 1;
697 }
698 j = 0;
699 for (i = 0; i < 32; i++) {
700 offset = arb->dbgregs[PMIF_MONITOR_RECORD_0_1] + (i * 0x14);
701 tmp_dat = DRV_Reg32(arb->base + offset);
702 wd_31_0[j] = tmp_dat;
703 j += 1;
704 }
705
706 for (i = 0; i < 32; i++) {
707 SPMI_CRI("[swinf:%d, cmd:0x%x, rw:0x%x, slvid:%d ",
708 chan[i], cmd[i], rw[i], slvid[i]);
709 SPMI_CRIL("bytecnt:%d (adr 0x%04x=0x%x)]\r\n",
710 bytecnt[i], adr[i], wd_31_0[i]);
711 }
712 spmi_dump_pmif_swinf_reg(mstid);
713
714 /* clear record data and re-enable */
715 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_CTRL], 0x800);
716 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_CTRL], 0x5);
717}
718#if 0
719/* under construction !*/
720/* under construction !*/
721/* under construction !*/
722/* under construction !*/
723/* under construction !*/
724/* under construction !*/
725/* under construction !*/
726/* under construction !*/
727/* under construction !*/
728/* under construction !*/
729/* under construction !*/
730/* under construction !*/
731/* under construction !*/
732/* under construction !*/
733/* under construction !*/
734/* under construction !*/
735/* under construction !*/
736/* under construction !*/
737/* under construction !*/
738/* under construction !*/
739/* under construction !*/
740/* under construction !*/
741/* under construction !*/
742/* under construction !*/
743/* under construction !*/
744/* under construction !*/
745/* under construction !*/
746/* under construction !*/
747/* under construction !*/
748/* under construction !*/
749/* under construction !*/
750/* under construction !*/
751/* under construction !*/
752/* under construction !*/
753/* under construction !*/
754/* under construction !*/
755/* under construction !*/
756/* under construction !*/
757/* under construction !*/
758/* under construction !*/
759/* under construction !*/
760/* under construction !*/
761/* under construction !*/
762/* under construction !*/
763/* under construction !*/
764/* under construction !*/
765/* under construction !*/
766/* under construction !*/
767/* under construction !*/
768#if 0
769/* under construction !*/
770/* under construction !*/
771/* under construction !*/
772/* under construction !*/
773/* under construction !*/
774/* under construction !*/
775/* under construction !*/
776/* under construction !*/
777/* under construction !*/
778/* under construction !*/
779/* under construction !*/
780/* under construction !*/
781/* under construction !*/
782/* under construction !*/
783/* under construction !*/
784#endif
785/* under construction !*/
786#endif
787void spmi_dump_spmimst_reg(int mstid)
788{
789 struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
790 unsigned int i = 0, offset = 0, tmp_dat = 0;
791 unsigned int start = 0, end = 0;
792
793 start = arb->spmimst_regs[SPMI_OP_ST_CTRL]/4;
794 end = arb->spmimst_regs[SPMI_REC4]/4;
795
796 SPMI_CRI("");
797 for (i = start; i <= end; i++) {
798 offset = arb->spmimst_regs[SPMI_OP_ST_CTRL] + (i * 4);
799 tmp_dat = DRV_Reg32(arb->spmimst_base + offset);
800 SPMI_CRIL("(0x%x)=0x%x ", offset, tmp_dat);
801
802 if (i == 0)
803 continue;
804 if (i % 8 == 0) {
805 SPMI_CRIL("\r\n[SPMI] ");
806 }
807 }
808#if SPMI_RCS_SUPPORT
809 offset = arb->spmimst_regs[SPMI_DEC_DBG];
810 tmp_dat = DRV_Reg32(arb->spmimst_base + offset);
811 SPMI_CRIL("(0x%x)=0x%x ", offset, tmp_dat);
812#endif
813 offset = arb->spmimst_regs[SPMI_MST_DBG];
814 tmp_dat = DRV_Reg32(arb->spmimst_base + offset);
815 SPMI_CRIL("(0x%x)=0x%x ", offset, tmp_dat);
816 SPMI_CRIL("\r\n");
817}
818
819void spmi_dump_slv_record_reg(struct spmi_device *dev)
820{
821 unsigned char rdata1 = 0, rdata2 = 0, rdata3 = 0, rdata4 = 0;
822 unsigned int offset, i, j = 0;
823
824 /* log sequence, idx 0->1->2->3->0 */
825 for (offset = 0x34; offset < 0x50; offset += 4)
826 {
827 spmi_ext_register_readl(dev,
828 (MT6315_PLT0_ID_ANA_ID + offset), &rdata1, 1);
829 spmi_ext_register_readl(dev,
830 (MT6315_PLT0_ID_ANA_ID + offset + 1), &rdata2, 1);
831 spmi_ext_register_readl(dev,
832 (MT6315_PLT0_ID_ANA_ID + offset + 2), &rdata3, 1);
833 spmi_ext_register_readl(dev,
834 (MT6315_PLT0_ID_ANA_ID + offset + 3), &rdata4, 1);
835 if ((offset + 3) == 0x37) {
836 i = (rdata4 & 0xc) >> 2;
837 if (i == 0)
838 SPMI_CRI("slvid:%d DBG. Last cmd idx:0x3\r\n",
839 dev->slvid);
840 else {
841 SPMI_CRI("slvid:%d DBG. Last cmd idx:0x%x\r\n",
842 dev->slvid, ((rdata4 & 0xc) >> 2) - 1);
843 }
844
845 }
846 /*
847 *SPMI_CRI("[0x%x]=0x%x [0x%x]=0x%x [0x%x]=0x%x [0x%x]=0x%x ",
848 * offset, rdata1, (offset + 1), rdata2,
849 * (offset + 2), rdata3, (offset + 3), rdata4);
850 */
851
852 SPMI_CRI("Idx:%d slvid:%d Type:0x%x, [0x%x]=0x%x\r\n", j,
853 dev->slvid, (rdata4 & 0x3),
854 (rdata2 << 0x8) | rdata1, rdata3);
855 if (j <= 3)
856 j++;
857
858 }
859}
860
861int spmi_pmif_dbg_init(struct pmif *arb)
862{
863#if PMIF_MATCH_SUPPORT
864 unsigned int int_en = 0;
865#endif
866 arb->dbgregs = mt6xxx_pmif_dbg_regs;
867#if PMIF_MATCH_SUPPORT
868 /* enable matching mode */
869 PMIF_CRI("PMIF Matching Mode\n");
870
871 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_IRQ_CLR_0], 0xffffffff);
872 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_IRQ_CLR_1], 0xffffffff);
873 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_IRQ_CLR_2], 0xffffffff);
874 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_IRQ_CLR_3], 0xffffffff);
875
876 int_en = DRV_Reg32(arb->base + arb->dbgregs[PMIF_IRQ_EVENT_EN_3]);
877 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_IRQ_EVENT_EN_3],
878 int_en | (0x1 << 7));
879
880 /* set monitor channel, should same as ARB_EN */
881 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_CHAN_0],
882 0x2f5);
883 /* [31:16] addr mask, ffff mean all bit check
884 * [15:0] addr, which addr been checked
885 */
886 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_ADDR_0],
887 0xffff03a5);
888 /* [31:16] wdata mask, ffff mean all bit check
889 * [15:0] data, which data been checked
890 */
891 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_WDATA_0],
892 0xffff005a);
893 /*
894 * BIT[0] MONITOR_TARGET_WRITE_0
895 * BIT[1] MONITOR_TARGET_WRITE_0_MASK: 0, rw all check, 1, check
896 * BIT[0] if BIT[0] = 0, only check read;otherwise only check write.
897 */
898 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_WRITE],
899 0x3);
900 /* reset then enable */
901 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_CTRL], 0x800);
902 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_CTRL], 0x405);
903#else
904 /* init pmif debug mechanism, hw matching mode or sw logging mode */
905 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_CHAN_0],
906 0x2f5);
907 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_ADDR_0],
908 0x0);
909 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_WDATA_0],
910 0x0);
911 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_TARGET_WRITE],
912 0x001);
913 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_CTRL], 0x800);
914 DRV_WriteReg32(arb->base + arb->dbgregs[PMIF_MONITOR_CTRL], 0x5);
915#endif /* end of PMIF_MATCH_SUPPORT */
916 return 0;
917}
918#endif /* endif SPMI_NO_PMIC */