| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame^] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2012 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * dcl_pmic6323_hw.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * Maui_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This file is for PMIC 6323 |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
| 58 | * removed! |
| 59 | * removed! |
| 60 | * removed! |
| 61 | * |
| 62 | * removed! |
| 63 | * removed! |
| 64 | * removed! |
| 65 | * |
| 66 | * removed! |
| 67 | * removed! |
| 68 | * removed! |
| 69 | * |
| 70 | * removed! |
| 71 | * removed! |
| 72 | * removed! |
| 73 | * |
| 74 | * removed! |
| 75 | * removed! |
| 76 | * removed! |
| 77 | * |
| 78 | * removed! |
| 79 | * removed! |
| 80 | * removed! |
| 81 | *------------------------------------------------------------------------------ |
| 82 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 83 | *============================================================================ |
| 84 | ****************************************************************************/ |
| 85 | |
| 86 | #ifndef __DCL_PMIC6323_HW_H_STRUCT__ |
| 87 | #define __DCL_PMIC6323_HW_H_STRUCT__ |
| 88 | |
| 89 | |
| 90 | #include "dcl_pmic_features.h" |
| 91 | |
| 92 | #if defined(PMIC_6323_REG_API) |
| 93 | |
| 94 | #define PMIC_BASE (0x0000) |
| 95 | #define GPIO_BASE (0xC000) |
| 96 | #define MT6323_E1_CID 0x1023 |
| 97 | |
| 98 | //register number |
| 99 | #define CHR_CON0 0x0000 |
| 100 | #define CHR_CON1 0x0002 |
| 101 | #define CHR_CON2 0x0004 |
| 102 | #define CHR_CON3 0x0006 |
| 103 | #define CHR_CON4 0x0008 |
| 104 | #define CHR_CON5 0x000A |
| 105 | #define CHR_CON6 0x000C |
| 106 | #define CHR_CON7 0x000E |
| 107 | #define CHR_CON8 0x0010 |
| 108 | #define CHR_CON9 0x0012 |
| 109 | #define CHR_CON10 0x0014 |
| 110 | #define CHR_CON11 0x0016 |
| 111 | #define CHR_CON12 0x0018 |
| 112 | #define CHR_CON13 0x001A |
| 113 | #define CHR_CON14 0x001C |
| 114 | #define CHR_CON15 0x001E |
| 115 | #define CHR_CON16 0x0020 |
| 116 | #define CHR_CON17 0x0022 |
| 117 | #define CHR_CON18 0x0024 |
| 118 | #define CHR_CON19 0x0026 |
| 119 | #define CHR_CON20 0x0028 |
| 120 | #define CHR_CON21 0x002A |
| 121 | #define CHR_CON22 0x002C |
| 122 | #define CHR_CON23 0x002E |
| 123 | #define CHR_CON24 0x0030 |
| 124 | #define CHR_CON25 0x0032 |
| 125 | #define CHR_CON26 0x0034 |
| 126 | #define CHR_CON27 0x0036 |
| 127 | #define CHR_CON28 0x0038 |
| 128 | #define CHR_CON29 0x003A |
| 129 | #define STRUP_CON0 0x003C |
| 130 | #define STRUP_CON2 0x003E |
| 131 | #define STRUP_CON3 0x0040 |
| 132 | #define STRUP_CON4 0x0042 |
| 133 | #define STRUP_CON5 0x0044 |
| 134 | #define STRUP_CON6 0x0046 |
| 135 | #define STRUP_CON7 0x0048 |
| 136 | #define STRUP_CON8 0x004A |
| 137 | #define STRUP_CON9 0x004C |
| 138 | #define STRUP_CON10 0x004E |
| 139 | #define STRUP_CON11 0x0050 |
| 140 | #define SPK_CON0 0x0052 |
| 141 | #define SPK_CON1 0x0054 |
| 142 | #define SPK_CON2 0x0056 |
| 143 | #define SPK_CON6 0x005E |
| 144 | #define SPK_CON7 0x0060 |
| 145 | #define SPK_CON8 0x0062 |
| 146 | #define SPK_CON9 0x0064 |
| 147 | #define SPK_CON10 0x0066 |
| 148 | #define SPK_CON11 0x0068 |
| 149 | #define SPK_CON12 0x006A |
| 150 | #define CID 0x0100 |
| 151 | #define TOP_CKPDN0 0x0102 |
| 152 | #define TOP_CKPDN1 0x0108 |
| 153 | #define TOP_CKPDN1_SET 0x010A |
| 154 | #define TOP_CKPDN1_CLR 0x010C |
| 155 | #define TOP_CKPDN2 0x010E |
| 156 | #define TOP_RST_CON 0x0114 |
| 157 | #define TOP_RST_MISC 0x011A |
| 158 | #define TOP_CKCON0 0x0120 |
| 159 | #define TOP_CKCON1 0x0126 |
| 160 | #define TOP_CKCON1_CLR 0x012A |
| 161 | #define TOP_CKTST0 0x012C |
| 162 | #define TOP_CKTST1 0x012E |
| 163 | #define TOP_CKTST2 0x0130 |
| 164 | #define TEST_OUT 0x0132 |
| 165 | #define TEST_CON0 0x0134 |
| 166 | #define TEST_CON1 0x0136 |
| 167 | #define EN_STATUS0 0x0138 |
| 168 | #define EN_STATUS1 0x013A |
| 169 | #define OCSTATUS0 0x013C |
| 170 | #define OCSTATUS1 0x013E |
| 171 | #define PGSTATUS 0x0140 |
| 172 | #define CHRSTATUS 0x0142 |
| 173 | #define TDSEL_CON 0x0144 |
| 174 | #define RDSEL_CON 0x0146 |
| 175 | #define SMT_CON0 0x0148 |
| 176 | #define SMT_CON1 0x014A |
| 177 | #define SMT_CON2 0x014C |
| 178 | #define SMT_CON3 0x014E |
| 179 | #define SMT_CON4 0x0150 |
| 180 | #define DRV_CON0 0x0152 |
| 181 | #define DRV_CON1 0x0154 |
| 182 | #define DRV_CON2 0x0156 |
| 183 | #define DRV_CON3 0x0158 |
| 184 | #define DRV_CON4 0x015A |
| 185 | #define SIMLS1_CON 0x015C |
| 186 | #define SIMLS2_CON 0x015E |
| 187 | #define INT_CON0 0x0160 |
| 188 | #define INT_CON1 0x0166 |
| 189 | #define INT_MISC_CON 0x016C |
| 190 | #define INT_STATUS0 0x0172 |
| 191 | #define INT_STATUS1 0x0174 |
| 192 | #define OC_GEAR_0 0x0176 |
| 193 | #define OC_GEAR_1 0x0178 |
| 194 | #define OC_GEAR_2 0x017A |
| 195 | #define OC_CTL_VPROC 0x017C |
| 196 | #define OC_CTL_VSYS 0x017E |
| 197 | #define OC_CTL_VPA 0x0180 |
| 198 | #define FQMTR_CON0 0x0182 |
| 199 | #define FQMTR_CON1 0x0184 |
| 200 | #define FQMTR_CON2 0x0186 |
| 201 | #define RG_SPI_CON 0x0188 |
| 202 | #define DEW_DIO_EN 0x018A |
| 203 | #define DEW_READ_TEST 0x018C |
| 204 | #define DEW_WRITE_TEST 0x018E |
| 205 | #define DEW_CRC_SWRST 0x0190 |
| 206 | #define DEW_CRC_EN 0x0192 |
| 207 | #define DEW_CRC_VAL 0x0194 |
| 208 | #define DEW_DBG_MON_SEL 0x0196 |
| 209 | #define DEW_CIPHER_KEY_SEL 0x0198 |
| 210 | #define DEW_CIPHER_IV_SEL 0x019A |
| 211 | #define DEW_CIPHER_EN 0x019C |
| 212 | #define DEW_CIPHER_RDY 0x019E |
| 213 | #define DEW_CIPHER_MODE 0x01A0 |
| 214 | #define DEW_CIPHER_SWRST 0x01A2 |
| 215 | #define DEW_RDDMY_NO 0x01A4 |
| 216 | #define DEW_RDATA_DLY_SEL 0x01A6 |
| 217 | #define BUCK_CON0 0x0200 |
| 218 | #define BUCK_CON1 0x0202 |
| 219 | #define BUCK_CON2 0x0204 |
| 220 | #define BUCK_CON3 0x0206 |
| 221 | #define BUCK_CON4 0x0208 |
| 222 | #define BUCK_CON5 0x020A |
| 223 | #define VPROC_CON0 0x020C |
| 224 | #define VPROC_CON1 0x020E |
| 225 | #define VPROC_CON2 0x0210 |
| 226 | #define VPROC_CON3 0x0212 |
| 227 | #define VPROC_CON4 0x0214 |
| 228 | #define VPROC_CON5 0x0216 |
| 229 | #define VPROC_CON7 0x021A |
| 230 | #define VPROC_CON8 0x021C |
| 231 | #define VPROC_CON9 0x021E |
| 232 | #define VPROC_CON10 0x0220 |
| 233 | #define VPROC_CON11 0x0222 |
| 234 | #define VPROC_CON12 0x0224 |
| 235 | #define VPROC_CON13 0x0226 |
| 236 | #define VPROC_CON14 0x0228 |
| 237 | #define VPROC_CON15 0x022A |
| 238 | #define VPROC_CON18 0x0230 |
| 239 | #define VSYS_CON0 0x0232 |
| 240 | #define VSYS_CON1 0x0234 |
| 241 | #define VSYS_CON2 0x0236 |
| 242 | #define VSYS_CON3 0x0238 |
| 243 | #define VSYS_CON4 0x023A |
| 244 | #define VSYS_CON5 0x023C |
| 245 | #define VSYS_CON7 0x0240 |
| 246 | #define VSYS_CON8 0x0242 |
| 247 | #define VSYS_CON9 0x0244 |
| 248 | #define VSYS_CON10 0x0246 |
| 249 | #define VSYS_CON11 0x0248 |
| 250 | #define VSYS_CON12 0x024A |
| 251 | #define VSYS_CON13 0x024C |
| 252 | #define VSYS_CON14 0x024E |
| 253 | #define VSYS_CON15 0x0250 |
| 254 | #define VSYS_CON18 0x0256 |
| 255 | #define VPA_CON0 0x0300 |
| 256 | #define VPA_CON1 0x0302 |
| 257 | #define VPA_CON2 0x0304 |
| 258 | #define VPA_CON3 0x0306 |
| 259 | #define VPA_CON4 0x0308 |
| 260 | #define VPA_CON5 0x030A |
| 261 | #define VPA_CON7 0x030E |
| 262 | #define VPA_CON8 0x0310 |
| 263 | #define VPA_CON9 0x0312 |
| 264 | #define VPA_CON10 0x0314 |
| 265 | #define VPA_CON11 0x0316 |
| 266 | #define VPA_CON12 0x0318 |
| 267 | #define VPA_CON14 0x031C |
| 268 | #define VPA_CON16 0x0320 |
| 269 | #define VPA_CON17 0x0322 |
| 270 | #define VPA_CON18 0x0324 |
| 271 | #define VPA_CON19 0x0326 |
| 272 | #define VPA_CON20 0x0328 |
| 273 | #define BUCK_K_CON0 0x032A |
| 274 | #define BUCK_K_CON1 0x032C |
| 275 | #define BUCK_K_CON2 0x032E |
| 276 | #define ISINK0_CON0 0x0330 |
| 277 | #define ISINK0_CON1 0x0332 |
| 278 | #define ISINK0_CON2 0x0334 |
| 279 | #define ISINK0_CON3 0x0336 |
| 280 | #define ISINK1_CON0 0x0338 |
| 281 | #define ISINK1_CON1 0x033A |
| 282 | #define ISINK1_CON2 0x033C |
| 283 | #define ISINK1_CON3 0x033E |
| 284 | #define ISINK2_CON0 0x0340 |
| 285 | #define ISINK2_CON1 0x0342 |
| 286 | #define ISINK2_CON2 0x0344 |
| 287 | #define ISINK2_CON3 0x0346 |
| 288 | #define ISINK3_CON0 0x0348 |
| 289 | #define ISINK3_CON1 0x034A |
| 290 | #define ISINK3_CON2 0x034C |
| 291 | #define ISINK3_CON3 0x034E |
| 292 | #define ISINK_ANA0 0x0350 |
| 293 | #define ISINK_ANA1 0x0352 |
| 294 | #define ISINK_PHASE_DLY 0x0354 |
| 295 | #define ISINK_EN_CTRL 0x0356 |
| 296 | #define ANALDO_CON0 0x0400 |
| 297 | #define ANALDO_CON1 0x0402 |
| 298 | #define ANALDO_CON2 0x0404 |
| 299 | #define ANALDO_CON3 0x0406 |
| 300 | #define ANALDO_CON4 0x0408 |
| 301 | #define ANALDO_CON5 0x040A |
| 302 | #define ANALDO_CON6 0x040C |
| 303 | #define ANALDO_CON7 0x040E |
| 304 | #define ANALDO_CON8 0x0410 |
| 305 | #define ANALDO_CON10 0x0412 |
| 306 | #define ANALDO_CON15 0x0414 |
| 307 | #define ANALDO_CON16 0x0416 |
| 308 | #define ANALDO_CON17 0x0418 |
| 309 | #define ANALDO_CON18 0x041A |
| 310 | #define ANALDO_CON19 0x041C |
| 311 | #define ANALDO_CON20 0x041E |
| 312 | #define ANALDO_CON21 0x0420 |
| 313 | #define DIGLDO_CON0 0x0500 |
| 314 | #define DIGLDO_CON2 0x0502 |
| 315 | #define DIGLDO_CON3 0x0504 |
| 316 | #define DIGLDO_CON5 0x0506 |
| 317 | #define DIGLDO_CON6 0x0508 |
| 318 | #define DIGLDO_CON7 0x050A |
| 319 | #define DIGLDO_CON8 0x050C |
| 320 | #define DIGLDO_CON9 0x050E |
| 321 | #define DIGLDO_CON10 0x0510 |
| 322 | #define DIGLDO_CON11 0x0512 |
| 323 | #define DIGLDO_CON12 0x0514 |
| 324 | #define DIGLDO_CON13 0x0516 |
| 325 | #define DIGLDO_CON14 0x0518 |
| 326 | #define DIGLDO_CON15 0x051A |
| 327 | #define DIGLDO_CON16 0x051C |
| 328 | #define DIGLDO_CON17 0x051E |
| 329 | #define DIGLDO_CON18 0x0520 |
| 330 | #define DIGLDO_CON19 0x0522 |
| 331 | #define DIGLDO_CON20 0x0524 |
| 332 | #define DIGLDO_CON21 0x0526 |
| 333 | #define DIGLDO_CON23 0x0528 |
| 334 | #define DIGLDO_CON24 0x052A |
| 335 | #define DIGLDO_CON26 0x052C |
| 336 | #define DIGLDO_CON27 0x052E |
| 337 | #define DIGLDO_CON28 0x0530 |
| 338 | #define DIGLDO_CON29 0x0532 |
| 339 | #define DIGLDO_CON30 0x0534 |
| 340 | #define DIGLDO_CON31 0x0536 |
| 341 | #define DIGLDO_CON32 0x0538 |
| 342 | #define DIGLDO_CON33 0x053A |
| 343 | #define DIGLDO_CON34 0x053C |
| 344 | #define DIGLDO_CON35 0x053E |
| 345 | #define DIGLDO_CON36 0x0540 |
| 346 | #define DIGLDO_CON39 0x0542 |
| 347 | #define DIGLDO_CON40 0x0544 |
| 348 | #define DIGLDO_CON41 0x0546 |
| 349 | #define DIGLDO_CON42 0x0548 |
| 350 | #define DIGLDO_CON43 0x054A |
| 351 | #define DIGLDO_CON44 0x054C |
| 352 | #define DIGLDO_CON45 0x054E |
| 353 | #define DIGLDO_CON46 0x0550 |
| 354 | #define DIGLDO_CON47 0x0552 |
| 355 | #define DIGLDO_CON48 0x0554 |
| 356 | #define DIGLDO_CON49 0x0556 |
| 357 | #define DIGLDO_CON50 0x0558 |
| 358 | #define DIGLDO_CON51 0x055A |
| 359 | #define DIGLDO_CON52 0x055C |
| 360 | #define DIGLDO_CON53 0x055E |
| 361 | #define DIGLDO_CON54 0x0560 |
| 362 | #define EFUSE_CON0 0x0600 |
| 363 | #define EFUSE_CON1 0x0602 |
| 364 | #define EFUSE_CON2 0x0604 |
| 365 | #define EFUSE_CON3 0x0606 |
| 366 | #define EFUSE_CON4 0x0608 |
| 367 | #define EFUSE_CON5 0x060A |
| 368 | #define EFUSE_CON6 0x060C |
| 369 | #define EFUSE_VAL_0_15 0x060E |
| 370 | #define EFUSE_VAL_16_31 0x0610 |
| 371 | #define EFUSE_VAL_32_47 0x0612 |
| 372 | #define EFUSE_VAL_48_63 0x0614 |
| 373 | #define EFUSE_VAL_64_79 0x0616 |
| 374 | #define EFUSE_VAL_80_95 0x0618 |
| 375 | #define EFUSE_VAL_96_111 0x061A |
| 376 | #define EFUSE_VAL_112_127 0x061C |
| 377 | #define EFUSE_VAL_128_143 0x061E |
| 378 | #define EFUSE_VAL_144_159 0x0620 |
| 379 | #define EFUSE_VAL_160_175 0x0622 |
| 380 | #define EFUSE_VAL_176_191 0x0624 |
| 381 | #define EFUSE_DOUT_0_15 0x0626 |
| 382 | #define EFUSE_DOUT_16_31 0x0628 |
| 383 | #define EFUSE_DOUT_32_47 0x062A |
| 384 | #define EFUSE_DOUT_48_63 0x062C |
| 385 | #define EFUSE_DOUT_64_79 0x062E |
| 386 | #define EFUSE_DOUT_80_95 0x0630 |
| 387 | #define EFUSE_DOUT_96_111 0x0632 |
| 388 | #define EFUSE_DOUT_112_127 0x0634 |
| 389 | #define EFUSE_DOUT_128_143 0x0636 |
| 390 | #define EFUSE_DOUT_144_159 0x0638 |
| 391 | #define EFUSE_DOUT_160_175 0x063A |
| 392 | #define EFUSE_DOUT_176_191 0x063C |
| 393 | #define EFUSE_CON7 0x063E |
| 394 | #define EFUSE_CON8 0x0640 |
| 395 | #define EFUSE_CON9 0x0642 |
| 396 | #define RTC_MIX_CON0 0x0644 |
| 397 | #define RTC_MIX_CON1 0x0646 |
| 398 | #define AUDTOP_CON0 0x0700 |
| 399 | #define AUDTOP_CON1 0x0702 |
| 400 | #define AUDTOP_CON2 0x0704 |
| 401 | #define AUDTOP_CON3 0x0706 |
| 402 | #define AUDTOP_CON4 0x0708 |
| 403 | #define AUDTOP_CON5 0x070A |
| 404 | #define AUDTOP_CON6 0x070C |
| 405 | #define AUDTOP_CON7 0x070E |
| 406 | #define AUDTOP_CON8 0x0710 |
| 407 | #define AUDTOP_CON9 0x0712 |
| 408 | #define AUXADC_ADC0 0x0714 |
| 409 | #define AUXADC_ADC1 0x0716 |
| 410 | #define AUXADC_ADC2 0x0718 |
| 411 | #define AUXADC_ADC3 0x071A |
| 412 | #define AUXADC_ADC4 0x071C |
| 413 | #define AUXADC_ADC5 0x071E |
| 414 | #define AUXADC_ADC6 0x0720 |
| 415 | #define AUXADC_ADC7 0x0722 |
| 416 | #define AUXADC_ADC8 0x0724 |
| 417 | #define AUXADC_ADC9 0x0726 |
| 418 | #define AUXADC_ADC10 0x0728 |
| 419 | #define AUXADC_ADC11 0x072A |
| 420 | #define AUXADC_ADC12 0x072C |
| 421 | #define AUXADC_ADC13 0x072E |
| 422 | #define AUXADC_ADC14 0x0730 |
| 423 | #define AUXADC_ADC15 0x0732 |
| 424 | #define AUXADC_ADC16 0x0734 |
| 425 | #define AUXADC_ADC17 0x0736 |
| 426 | #define AUXADC_ADC18 0x0738 |
| 427 | #define AUXADC_ADC19 0x073A |
| 428 | #define AUXADC_ADC20 0x073C |
| 429 | #define AUXADC_RSV1 0x073E |
| 430 | #define AUXADC_RSV2 0x0740 |
| 431 | #define AUXADC_CON0 0x0742 |
| 432 | #define AUXADC_CON1 0x0744 |
| 433 | #define AUXADC_CON2 0x0746 |
| 434 | #define AUXADC_CON3 0x0748 |
| 435 | #define AUXADC_CON4 0x074A |
| 436 | #define AUXADC_CON5 0x074C |
| 437 | #define AUXADC_CON6 0x074E |
| 438 | #define AUXADC_CON7 0x0750 |
| 439 | #define AUXADC_CON8 0x0752 |
| 440 | #define AUXADC_CON9 0x0754 |
| 441 | #define AUXADC_CON10 0x0756 |
| 442 | #define AUXADC_CON11 0x0758 |
| 443 | #define AUXADC_CON12 0x075A |
| 444 | #define AUXADC_CON13 0x075C |
| 445 | #define AUXADC_CON14 0x075E |
| 446 | #define AUXADC_CON15 0x0760 |
| 447 | #define AUXADC_CON16 0x0762 |
| 448 | #define AUXADC_CON17 0x0764 |
| 449 | #define AUXADC_CON18 0x0766 |
| 450 | #define AUXADC_CON19 0x0768 |
| 451 | #define AUXADC_CON20 0x076A |
| 452 | #define AUXADC_CON21 0x076C |
| 453 | #define AUXADC_CON22 0x076E |
| 454 | #define AUXADC_CON23 0x0770 |
| 455 | #define AUXADC_CON24 0x0772 |
| 456 | #define AUXADC_CON25 0x0774 |
| 457 | #define AUXADC_CON26 0x0776 |
| 458 | #define AUXADC_CON27 0x0778 |
| 459 | #define ACCDET_CON0 0x077A |
| 460 | #define ACCDET_CON1 0x077C |
| 461 | #define ACCDET_CON2 0x077E |
| 462 | #define ACCDET_CON3 0x0780 |
| 463 | #define ACCDET_CON4 0x0782 |
| 464 | #define ACCDET_CON5 0x0784 |
| 465 | #define ACCDET_CON6 0x0786 |
| 466 | #define ACCDET_CON7 0x0788 |
| 467 | #define ACCDET_CON8 0x078A |
| 468 | #define ACCDET_CON9 0x078C |
| 469 | #define ACCDET_CON10 0x078E |
| 470 | #define ACCDET_CON11 0x0790 |
| 471 | #define ACCDET_CON12 0x0792 |
| 472 | #define ACCDET_CON13 0x0794 |
| 473 | #define ACCDET_CON14 0x0796 |
| 474 | #define ACCDET_CON15 0x0798 |
| 475 | #define ACCDET_CON16 0x079A |
| 476 | |
| 477 | //mask is HEX |
| 478 | //shift is Integer |
| 479 | #define RG_CLKSQ_EN_AUX_MD_MASK 0x1 |
| 480 | #define RG_CLKSQ_EN_AUX_MD_SHIFT 14 |
| 481 | #define RG_VPA_MODESET_MASK 0x1 |
| 482 | #define RG_VPA_MODESET_SHIFT 8 |
| 483 | #define VPA_EN_MASK 0x1 |
| 484 | #define VPA_EN_SHIFT 0 |
| 485 | #define RG_STB_SIM1_SIO_MASK 0x1 |
| 486 | #define RG_STB_SIM1_SIO_SHIFT 0 |
| 487 | #define RG_VSIM1_EN_MASK 0x1 |
| 488 | #define RG_VSIM1_EN_SHIFT 15 |
| 489 | #define VSIM1_LP_MODE_SET_MASK 0x1 |
| 490 | #define VSIM1_LP_MODE_SET_SHIFT 1 |
| 491 | #define VSIM1_LP_SEL_MASK 0x1 |
| 492 | #define VSIM1_LP_SEL_SHIFT 0 |
| 493 | #define RG_VSIM2_EN_MASK 0x1 |
| 494 | #define RG_VSIM2_EN_SHIFT 15 |
| 495 | #define VSIM2_LP_MODE_SET_MASK 0x1 |
| 496 | #define VSIM2_LP_MODE_SET_SHIFT 1 |
| 497 | #define VSIM2_LP_SEL_MASK 0x1 |
| 498 | #define VSIM2_LP_SEL_SHIFT 0 |
| 499 | #define RG_STB_SIM2_SIO_MASK 0x1 |
| 500 | #define RG_STB_SIM2_SIO_SHIFT 0 |
| 501 | #define RG_VSIM1_VOSEL_MASK 0x1 |
| 502 | #define RG_VSIM1_VOSEL_SHIFT 5 |
| 503 | #define RG_VSIM2_VOSEL_MASK 0x1 |
| 504 | #define RG_VSIM2_VOSEL_SHIFT 5 |
| 505 | #define RG_VRF18_EN_MASK 0x1 |
| 506 | #define RG_VRF18_EN_SHIFT 15 |
| 507 | #define VRF18_LP_MODE_SET_MASK 0x1 |
| 508 | #define VRF18_LP_MODE_SET_SHIFT 1 |
| 509 | #define VRF18_LP_SEL_MASK 0x1 |
| 510 | #define VRF18_LP_SEL_SHIFT 0 |
| 511 | #define VRF18_ON_CTRL_MASK 0x1 |
| 512 | #define VRF18_ON_CTRL_SHIFT 1 |
| 513 | #define RG_ADC_OUT_MD_MASK 0xFFFF |
| 514 | #define RG_ADC_OUT_MD_SHIFT 0 |
| 515 | #define RG_ADC_RDY_MD_MASK 0x1 |
| 516 | #define RG_ADC_RDY_MD_SHIFT 15 |
| 517 | #define RG_MD_RQST_MASK 0x1 |
| 518 | #define RG_MD_RQST_SHIFT 15 |
| 519 | |
| 520 | // ====================================================================== // |
| 521 | #define GPIO_DOUT1_SET 0x0082 |
| 522 | #define GPIO_DOUT1_CLR 0x0084 |
| 523 | #define GPIO_DOUT2_SET 0x008A |
| 524 | #define GPIO_DOUT2_CLR 0x008C |
| 525 | |
| 526 | #define GPIO15_DOUT_SET_MASK 0x1 |
| 527 | #define GPIO15_DOUT_SET_SHIFT 15 |
| 528 | #define GPIO15_DOUT_CLR_MASK 0x1 |
| 529 | #define GPIO15_DOUT_CLR_SHIFT 15 |
| 530 | #define GPIO17_DOUT_SET_MASK 0x1 |
| 531 | #define GPIO17_DOUT_SET_SHIFT 1 |
| 532 | #define GPIO17_DOUT_CLR_MASK 0x1 |
| 533 | #define GPIO17_DOUT_CLR_SHIFT 1 |
| 534 | |
| 535 | #endif // #ifdef PMIC_6323_REG_API |
| 536 | #endif // #ifndef __DCL_PMIC6323_HW_H_STRUCT__ |
| 537 | |