| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame^] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2014 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * dcl_pmic6325_hw.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * MOLY Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This file is for PMIC 6325 |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
| 58 | * removed! |
| 59 | * removed! |
| 60 | * removed! |
| 61 | *------------------------------------------------------------------------------ |
| 62 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 63 | *============================================================================ |
| 64 | ****************************************************************************/ |
| 65 | |
| 66 | #ifndef __DCL_PMIC6325_HW_H_STRUCT__ |
| 67 | #define __DCL_PMIC6325_HW_H_STRUCT__ |
| 68 | |
| 69 | #include "dcl_pmic_features.h" |
| 70 | |
| 71 | #ifdef PMIC_6325_REG_API |
| 72 | |
| 73 | #define MT6325_PMIC_REG_BASE (0x0000) |
| 74 | |
| 75 | #define MT6325_STRUP_CON0 (MT6325_PMIC_REG_BASE + 0x0000) |
| 76 | #define MT6325_STRUP_CON2 (MT6325_PMIC_REG_BASE + 0x0002) |
| 77 | #define MT6325_STRUP_CON3 (MT6325_PMIC_REG_BASE + 0x0004) |
| 78 | #define MT6325_STRUP_CON4 (MT6325_PMIC_REG_BASE + 0x0006) |
| 79 | #define MT6325_STRUP_CON5 (MT6325_PMIC_REG_BASE + 0x0008) |
| 80 | #define MT6325_STRUP_CON6 (MT6325_PMIC_REG_BASE + 0x000A) |
| 81 | #define MT6325_STRUP_CON7 (MT6325_PMIC_REG_BASE + 0x000C) |
| 82 | #define MT6325_STRUP_CON8 (MT6325_PMIC_REG_BASE + 0x000E) |
| 83 | #define MT6325_STRUP_CON9 (MT6325_PMIC_REG_BASE + 0x0010) |
| 84 | #define MT6325_STRUP_CON10 (MT6325_PMIC_REG_BASE + 0x0012) |
| 85 | #define MT6325_STRUP_CON11 (MT6325_PMIC_REG_BASE + 0x0014) |
| 86 | #define MT6325_STRUP_CON12 (MT6325_PMIC_REG_BASE + 0x0016) |
| 87 | #define MT6325_STRUP_CON13 (MT6325_PMIC_REG_BASE + 0x0018) |
| 88 | #define MT6325_STRUP_CON14 (MT6325_PMIC_REG_BASE + 0x001A) |
| 89 | #define MT6325_STRUP_CON15 (MT6325_PMIC_REG_BASE + 0x001C) |
| 90 | #define MT6325_STRUP_CON16 (MT6325_PMIC_REG_BASE + 0x001E) |
| 91 | #define MT6325_STRUP_CON17 (MT6325_PMIC_REG_BASE + 0x0020) |
| 92 | #define MT6325_STRUP_CON18 (MT6325_PMIC_REG_BASE + 0x0022) |
| 93 | #define MT6325_STRUP_CON19 (MT6325_PMIC_REG_BASE + 0x0024) |
| 94 | #define MT6325_STRUP_CON20 (MT6325_PMIC_REG_BASE + 0x0026) |
| 95 | #define MT6325_STRUP_CON21 (MT6325_PMIC_REG_BASE + 0x0028) |
| 96 | #define MT6325_STRUP_CON22 (MT6325_PMIC_REG_BASE + 0x002A) |
| 97 | #define MT6325_STRUP_CON23 (MT6325_PMIC_REG_BASE + 0x002C) |
| 98 | #define MT6325_STRUP_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x002E) |
| 99 | #define MT6325_HWCID (MT6325_PMIC_REG_BASE + 0x0200) |
| 100 | #define MT6325_SWCID (MT6325_PMIC_REG_BASE + 0x0202) |
| 101 | #define MT6325_TOP_CON (MT6325_PMIC_REG_BASE + 0x0204) |
| 102 | #define MT6325_TEST_OUT (MT6325_PMIC_REG_BASE + 0x0206) |
| 103 | #define MT6325_TEST_CON0 (MT6325_PMIC_REG_BASE + 0x0208) |
| 104 | #define MT6325_TEST_CON1 (MT6325_PMIC_REG_BASE + 0x020A) |
| 105 | #define MT6325_TESTMODE_SW (MT6325_PMIC_REG_BASE + 0x020C) |
| 106 | #define MT6325_EN_STATUS0 (MT6325_PMIC_REG_BASE + 0x020E) |
| 107 | #define MT6325_EN_STATUS1 (MT6325_PMIC_REG_BASE + 0x0210) |
| 108 | #define MT6325_EN_STATUS2 (MT6325_PMIC_REG_BASE + 0x0212) |
| 109 | #define MT6325_OCSTATUS0 (MT6325_PMIC_REG_BASE + 0x0214) |
| 110 | #define MT6325_OCSTATUS1 (MT6325_PMIC_REG_BASE + 0x0216) |
| 111 | #define MT6325_OCSTATUS2 (MT6325_PMIC_REG_BASE + 0x0218) |
| 112 | #define MT6325_PGSTATUS (MT6325_PMIC_REG_BASE + 0x021A) |
| 113 | #define MT6325_TOPSTATUS (MT6325_PMIC_REG_BASE + 0x021C) |
| 114 | #define MT6325_TDSEL_CON (MT6325_PMIC_REG_BASE + 0x021E) |
| 115 | #define MT6325_RDSEL_CON (MT6325_PMIC_REG_BASE + 0x0220) |
| 116 | #define MT6325_SMT_CON0 (MT6325_PMIC_REG_BASE + 0x0222) |
| 117 | #define MT6325_SMT_CON1 (MT6325_PMIC_REG_BASE + 0x0224) |
| 118 | #define MT6325_SMT_CON2 (MT6325_PMIC_REG_BASE + 0x0226) |
| 119 | #define MT6325_DRV_CON0 (MT6325_PMIC_REG_BASE + 0x0228) |
| 120 | #define MT6325_DRV_CON1 (MT6325_PMIC_REG_BASE + 0x022A) |
| 121 | #define MT6325_DRV_CON2 (MT6325_PMIC_REG_BASE + 0x022C) |
| 122 | #define MT6325_DRV_CON3 (MT6325_PMIC_REG_BASE + 0x022E) |
| 123 | #define MT6325_TOP_STATUS (MT6325_PMIC_REG_BASE + 0x0230) |
| 124 | #define MT6325_TOP_STATUS_SET (MT6325_PMIC_REG_BASE + 0x0232) |
| 125 | #define MT6325_TOP_STATUS_CLR (MT6325_PMIC_REG_BASE + 0x0234) |
| 126 | #define MT6325_RGS_ANA_MON (MT6325_PMIC_REG_BASE + 0x0236) |
| 127 | #define MT6325_TOP_CKPDN_CON0 (MT6325_PMIC_REG_BASE + 0x0238) |
| 128 | #define MT6325_TOP_CKPDN_CON0_SET (MT6325_PMIC_REG_BASE + 0x023A) |
| 129 | #define MT6325_TOP_CKPDN_CON0_CLR (MT6325_PMIC_REG_BASE + 0x023C) |
| 130 | #define MT6325_TOP_CKPDN_CON1 (MT6325_PMIC_REG_BASE + 0x023E) |
| 131 | #define MT6325_TOP_CKPDN_CON1_SET (MT6325_PMIC_REG_BASE + 0x0240) |
| 132 | #define MT6325_TOP_CKPDN_CON1_CLR (MT6325_PMIC_REG_BASE + 0x0242) |
| 133 | #define MT6325_TOP_CKPDN_CON2 (MT6325_PMIC_REG_BASE + 0x0244) |
| 134 | #define MT6325_TOP_CKPDN_CON2_SET (MT6325_PMIC_REG_BASE + 0x0246) |
| 135 | #define MT6325_TOP_CKPDN_CON2_CLR (MT6325_PMIC_REG_BASE + 0x0248) |
| 136 | #define MT6325_TOP_CKPDN_CON3 (MT6325_PMIC_REG_BASE + 0x024A) |
| 137 | #define MT6325_TOP_CKPDN_CON3_SET (MT6325_PMIC_REG_BASE + 0x024C) |
| 138 | #define MT6325_TOP_CKPDN_CON3_CLR (MT6325_PMIC_REG_BASE + 0x024E) |
| 139 | #define MT6325_TOP_CKSEL_CON0 (MT6325_PMIC_REG_BASE + 0x0250) |
| 140 | #define MT6325_TOP_CKSEL_CON0_SET (MT6325_PMIC_REG_BASE + 0x0252) |
| 141 | #define MT6325_TOP_CKSEL_CON0_CLR (MT6325_PMIC_REG_BASE + 0x0254) |
| 142 | #define MT6325_TOP_CKSEL_CON1 (MT6325_PMIC_REG_BASE + 0x0256) |
| 143 | #define MT6325_TOP_CKSEL_CON1_SET (MT6325_PMIC_REG_BASE + 0x0258) |
| 144 | #define MT6325_TOP_CKSEL_CON1_CLR (MT6325_PMIC_REG_BASE + 0x025A) |
| 145 | #define MT6325_TOP_CKSEL_CON2 (MT6325_PMIC_REG_BASE + 0x025C) |
| 146 | #define MT6325_TOP_CKSEL_CON2_SET (MT6325_PMIC_REG_BASE + 0x025E) |
| 147 | #define MT6325_TOP_CKSEL_CON2_CLR (MT6325_PMIC_REG_BASE + 0x0260) |
| 148 | #define MT6325_TOP_CKDIVSEL_CON (MT6325_PMIC_REG_BASE + 0x0262) |
| 149 | #define MT6325_TOP_CKDIVSEL_CON_SET (MT6325_PMIC_REG_BASE + 0x0264) |
| 150 | #define MT6325_TOP_CKDIVSEL_CON_CLR (MT6325_PMIC_REG_BASE + 0x0266) |
| 151 | #define MT6325_TOP_CKHWEN_CON (MT6325_PMIC_REG_BASE + 0x0268) |
| 152 | #define MT6325_TOP_CKHWEN_CON_SET (MT6325_PMIC_REG_BASE + 0x026A) |
| 153 | #define MT6325_TOP_CKHWEN_CON_CLR (MT6325_PMIC_REG_BASE + 0x026C) |
| 154 | #define MT6325_TOP_CKTST_CON0 (MT6325_PMIC_REG_BASE + 0x026E) |
| 155 | #define MT6325_TOP_CKTST_CON1 (MT6325_PMIC_REG_BASE + 0x0270) |
| 156 | #define MT6325_TOP_CKTST_CON2 (MT6325_PMIC_REG_BASE + 0x0272) |
| 157 | #define MT6325_TOP_CLKSQ (MT6325_PMIC_REG_BASE + 0x0274) |
| 158 | #define MT6325_TOP_CLKSQ_SET (MT6325_PMIC_REG_BASE + 0x0276) |
| 159 | #define MT6325_TOP_CLKSQ_CLR (MT6325_PMIC_REG_BASE + 0x0278) |
| 160 | #define MT6325_TOP_CLKSQ_RTC (MT6325_PMIC_REG_BASE + 0x027A) |
| 161 | #define MT6325_TOP_CLKSQ_RTC_SET (MT6325_PMIC_REG_BASE + 0x027C) |
| 162 | #define MT6325_TOP_CLKSQ_RTC_CLR (MT6325_PMIC_REG_BASE + 0x027E) |
| 163 | #define MT6325_TOP_CLK_TRIM (MT6325_PMIC_REG_BASE + 0x0280) |
| 164 | #define MT6325_TOP_RST_CON0 (MT6325_PMIC_REG_BASE + 0x0282) |
| 165 | #define MT6325_TOP_RST_CON0_SET (MT6325_PMIC_REG_BASE + 0x0284) |
| 166 | #define MT6325_TOP_RST_CON0_CLR (MT6325_PMIC_REG_BASE + 0x0286) |
| 167 | #define MT6325_TOP_RST_CON1 (MT6325_PMIC_REG_BASE + 0x0288) |
| 168 | #define MT6325_TOP_RST_MISC (MT6325_PMIC_REG_BASE + 0x028A) |
| 169 | #define MT6325_TOP_RST_MISC_SET (MT6325_PMIC_REG_BASE + 0x028C) |
| 170 | #define MT6325_TOP_RST_MISC_CLR (MT6325_PMIC_REG_BASE + 0x028E) |
| 171 | #define MT6325_TOP_RST_STATUS (MT6325_PMIC_REG_BASE + 0x0290) |
| 172 | #define MT6325_TOP_RST_STATUS_SET (MT6325_PMIC_REG_BASE + 0x0292) |
| 173 | #define MT6325_TOP_RST_STATUS_CLR (MT6325_PMIC_REG_BASE + 0x0294) |
| 174 | #define MT6325_INT_CON0 (MT6325_PMIC_REG_BASE + 0x0296) |
| 175 | #define MT6325_INT_CON0_SET (MT6325_PMIC_REG_BASE + 0x0298) |
| 176 | #define MT6325_INT_CON0_CLR (MT6325_PMIC_REG_BASE + 0x029A) |
| 177 | #define MT6325_INT_CON1 (MT6325_PMIC_REG_BASE + 0x029C) |
| 178 | #define MT6325_INT_CON1_SET (MT6325_PMIC_REG_BASE + 0x029E) |
| 179 | #define MT6325_INT_CON1_CLR (MT6325_PMIC_REG_BASE + 0x02A0) |
| 180 | #define MT6325_INT_CON2 (MT6325_PMIC_REG_BASE + 0x02A2) |
| 181 | #define MT6325_INT_CON2_SET (MT6325_PMIC_REG_BASE + 0x02A4) |
| 182 | #define MT6325_INT_CON2_CLR (MT6325_PMIC_REG_BASE + 0x02A6) |
| 183 | #define MT6325_INT_MISC_CON (MT6325_PMIC_REG_BASE + 0x02A8) |
| 184 | #define MT6325_INT_MISC_CON_SET (MT6325_PMIC_REG_BASE + 0x02AA) |
| 185 | #define MT6325_INT_MISC_CON_CLR (MT6325_PMIC_REG_BASE + 0x02AC) |
| 186 | #define MT6325_INT_STATUS0 (MT6325_PMIC_REG_BASE + 0x02AE) |
| 187 | #define MT6325_INT_STATUS1 (MT6325_PMIC_REG_BASE + 0x02B0) |
| 188 | #define MT6325_INT_STATUS2 (MT6325_PMIC_REG_BASE + 0x02B2) |
| 189 | #define MT6325_OC_GEAR_0 (MT6325_PMIC_REG_BASE + 0x02B4) |
| 190 | #define MT6325_FQMTR_CON0 (MT6325_PMIC_REG_BASE + 0x02B6) |
| 191 | #define MT6325_FQMTR_CON1 (MT6325_PMIC_REG_BASE + 0x02B8) |
| 192 | #define MT6325_FQMTR_CON2 (MT6325_PMIC_REG_BASE + 0x02BA) |
| 193 | #define MT6325_RG_SPI_CON (MT6325_PMIC_REG_BASE + 0x02BC) |
| 194 | #define MT6325_DEW_DIO_EN (MT6325_PMIC_REG_BASE + 0x02BE) |
| 195 | #define MT6325_DEW_READ_TEST (MT6325_PMIC_REG_BASE + 0x02C0) |
| 196 | #define MT6325_DEW_WRITE_TEST (MT6325_PMIC_REG_BASE + 0x02C2) |
| 197 | #define MT6325_DEW_CRC_SWRST (MT6325_PMIC_REG_BASE + 0x02C4) |
| 198 | #define MT6325_DEW_CRC_EN (MT6325_PMIC_REG_BASE + 0x02C6) |
| 199 | #define MT6325_DEW_CRC_VAL (MT6325_PMIC_REG_BASE + 0x02C8) |
| 200 | #define MT6325_DEW_DBG_MON_SEL (MT6325_PMIC_REG_BASE + 0x02CA) |
| 201 | #define MT6325_DEW_CIPHER_KEY_SEL (MT6325_PMIC_REG_BASE + 0x02CC) |
| 202 | #define MT6325_DEW_CIPHER_IV_SEL (MT6325_PMIC_REG_BASE + 0x02CE) |
| 203 | #define MT6325_DEW_CIPHER_EN (MT6325_PMIC_REG_BASE + 0x02D0) |
| 204 | #define MT6325_DEW_CIPHER_RDY (MT6325_PMIC_REG_BASE + 0x02D2) |
| 205 | #define MT6325_DEW_CIPHER_MODE (MT6325_PMIC_REG_BASE + 0x02D4) |
| 206 | #define MT6325_DEW_CIPHER_SWRST (MT6325_PMIC_REG_BASE + 0x02D6) |
| 207 | #define MT6325_DEW_RDDMY_NO (MT6325_PMIC_REG_BASE + 0x02D8) |
| 208 | #define MT6325_INT_TYPE_CON0 (MT6325_PMIC_REG_BASE + 0x02DA) |
| 209 | #define MT6325_INT_TYPE_CON0_SET (MT6325_PMIC_REG_BASE + 0x02DC) |
| 210 | #define MT6325_INT_TYPE_CON0_CLR (MT6325_PMIC_REG_BASE + 0x02DE) |
| 211 | #define MT6325_INT_TYPE_CON1 (MT6325_PMIC_REG_BASE + 0x02E0) |
| 212 | #define MT6325_INT_TYPE_CON1_SET (MT6325_PMIC_REG_BASE + 0x02E2) |
| 213 | #define MT6325_INT_TYPE_CON1_CLR (MT6325_PMIC_REG_BASE + 0x02E4) |
| 214 | #define MT6325_INT_TYPE_CON2 (MT6325_PMIC_REG_BASE + 0x02E6) |
| 215 | #define MT6325_INT_TYPE_CON2_SET (MT6325_PMIC_REG_BASE + 0x02E8) |
| 216 | #define MT6325_INT_TYPE_CON2_CLR (MT6325_PMIC_REG_BASE + 0x02EA) |
| 217 | #define MT6325_INT_STA (MT6325_PMIC_REG_BASE + 0x02EC) |
| 218 | #define MT6325_BUCK_ALL_CON0 (MT6325_PMIC_REG_BASE + 0x0400) |
| 219 | #define MT6325_BUCK_ALL_CON1 (MT6325_PMIC_REG_BASE + 0x0402) |
| 220 | #define MT6325_BUCK_ALL_CON2 (MT6325_PMIC_REG_BASE + 0x0404) |
| 221 | #define MT6325_BUCK_ALL_CON3 (MT6325_PMIC_REG_BASE + 0x0406) |
| 222 | #define MT6325_BUCK_ALL_CON4 (MT6325_PMIC_REG_BASE + 0x0408) |
| 223 | #define MT6325_BUCK_ALL_CON5 (MT6325_PMIC_REG_BASE + 0x040A) |
| 224 | #define MT6325_BUCK_ALL_CON6 (MT6325_PMIC_REG_BASE + 0x040C) |
| 225 | #define MT6325_BUCK_ALL_CON7 (MT6325_PMIC_REG_BASE + 0x040E) |
| 226 | #define MT6325_BUCK_ALL_CON8 (MT6325_PMIC_REG_BASE + 0x0410) |
| 227 | #define MT6325_BUCK_ALL_CON9 (MT6325_PMIC_REG_BASE + 0x0412) |
| 228 | #define MT6325_BUCK_ALL_CON10 (MT6325_PMIC_REG_BASE + 0x0414) |
| 229 | #define MT6325_BUCK_ALL_CON11 (MT6325_PMIC_REG_BASE + 0x0416) |
| 230 | #define MT6325_BUCK_ALL_CON12 (MT6325_PMIC_REG_BASE + 0x0418) |
| 231 | #define MT6325_BUCK_ALL_CON13 (MT6325_PMIC_REG_BASE + 0x041A) |
| 232 | #define MT6325_BUCK_ALL_CON14 (MT6325_PMIC_REG_BASE + 0x041C) |
| 233 | #define MT6325_BUCK_ALL_CON15 (MT6325_PMIC_REG_BASE + 0x041E) |
| 234 | #define MT6325_BUCK_ALL_CON16 (MT6325_PMIC_REG_BASE + 0x0420) |
| 235 | #define MT6325_BUCK_ALL_CON17 (MT6325_PMIC_REG_BASE + 0x0422) |
| 236 | #define MT6325_BUCK_ALL_CON18 (MT6325_PMIC_REG_BASE + 0x0424) |
| 237 | #define MT6325_BUCK_ALL_CON19 (MT6325_PMIC_REG_BASE + 0x0426) |
| 238 | #define MT6325_BUCK_ALL_CON20 (MT6325_PMIC_REG_BASE + 0x0428) |
| 239 | #define MT6325_BUCK_ALL_CON21 (MT6325_PMIC_REG_BASE + 0x042A) |
| 240 | #define MT6325_BUCK_ALL_CON22 (MT6325_PMIC_REG_BASE + 0x042C) |
| 241 | #define MT6325_BUCK_ALL_CON23 (MT6325_PMIC_REG_BASE + 0x042E) |
| 242 | #define MT6325_BUCK_ALL_CON24 (MT6325_PMIC_REG_BASE + 0x0430) |
| 243 | #define MT6325_BUCK_ALL_CON25 (MT6325_PMIC_REG_BASE + 0x0432) |
| 244 | #define MT6325_BUCK_ALL_CON26 (MT6325_PMIC_REG_BASE + 0x0434) |
| 245 | #define MT6325_BUCK_ALL_CON27 (MT6325_PMIC_REG_BASE + 0x0436) |
| 246 | #define MT6325_BUCK_ALL_CON28 (MT6325_PMIC_REG_BASE + 0x0438) |
| 247 | #define MT6325_VDRAM_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x043A) |
| 248 | #define MT6325_VDRAM_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x043C) |
| 249 | #define MT6325_VDRAM_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x043E) |
| 250 | #define MT6325_VDRAM_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0440) |
| 251 | #define MT6325_VDRAM_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0442) |
| 252 | #define MT6325_VCORE1_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0444) |
| 253 | #define MT6325_VCORE1_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0446) |
| 254 | #define MT6325_VCORE1_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0448) |
| 255 | #define MT6325_VCORE1_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x044A) |
| 256 | #define MT6325_VCORE1_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x044C) |
| 257 | #define MT6325_SMPS_TOP_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x044E) |
| 258 | #define MT6325_SMPS_TOP_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0450) |
| 259 | #define MT6325_SMPS_TOP_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0452) |
| 260 | #define MT6325_SMPS_TOP_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0454) |
| 261 | #define MT6325_SMPS_TOP_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0456) |
| 262 | #define MT6325_SMPS_TOP_ANA_CON5 (MT6325_PMIC_REG_BASE + 0x0458) |
| 263 | #define MT6325_SMPS_TOP_ANA_CON6 (MT6325_PMIC_REG_BASE + 0x045A) |
| 264 | #define MT6325_SMPS_TOP_ANA_CON7 (MT6325_PMIC_REG_BASE + 0x045C) |
| 265 | #define MT6325_SMPS_TOP_ANA_CON8 (MT6325_PMIC_REG_BASE + 0x045E) |
| 266 | #define MT6325_SMPS_TOP_ANA_CON9 (MT6325_PMIC_REG_BASE + 0x0460) |
| 267 | #define MT6325_VDVFS1_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0462) |
| 268 | #define MT6325_VDVFS1_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0464) |
| 269 | #define MT6325_VDVFS1_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0466) |
| 270 | #define MT6325_VDVFS1_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0468) |
| 271 | #define MT6325_VDVFS1_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x046A) |
| 272 | #define MT6325_VDVFS1_ANA_CON5 (MT6325_PMIC_REG_BASE + 0x046C) |
| 273 | #define MT6325_VDVFS1_ANA_CON6 (MT6325_PMIC_REG_BASE + 0x046E) |
| 274 | #define MT6325_VDVFS1_ANA_CON7 (MT6325_PMIC_REG_BASE + 0x0470) |
| 275 | #define MT6325_VGPU_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0472) |
| 276 | #define MT6325_VGPU_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0474) |
| 277 | #define MT6325_VGPU_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0476) |
| 278 | #define MT6325_VGPU_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0478) |
| 279 | #define MT6325_VGPU_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x047A) |
| 280 | #define MT6325_VPA_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x047C) |
| 281 | #define MT6325_VPA_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x047E) |
| 282 | #define MT6325_VPA_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0480) |
| 283 | #define MT6325_VPA_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0482) |
| 284 | #define MT6325_VCORE2_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0484) |
| 285 | #define MT6325_VCORE2_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0486) |
| 286 | #define MT6325_VCORE2_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0488) |
| 287 | #define MT6325_VCORE2_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x048A) |
| 288 | #define MT6325_VCORE2_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x048C) |
| 289 | #define MT6325_VIO18_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x048E) |
| 290 | #define MT6325_VIO18_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0490) |
| 291 | #define MT6325_VIO18_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0492) |
| 292 | #define MT6325_VIO18_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0494) |
| 293 | #define MT6325_VIO18_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0496) |
| 294 | #define MT6325_VRF18_0_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0498) |
| 295 | #define MT6325_VRF18_0_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x049A) |
| 296 | #define MT6325_VRF18_0_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x049C) |
| 297 | #define MT6325_VRF18_0_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x049E) |
| 298 | #define MT6325_VRF18_0_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x04A0) |
| 299 | #define MT6325_VDVFS11_CON0 (MT6325_PMIC_REG_BASE + 0x04A2) |
| 300 | #define MT6325_VDVFS11_CON7 (MT6325_PMIC_REG_BASE + 0x04B0) |
| 301 | #define MT6325_VDVFS11_CON8 (MT6325_PMIC_REG_BASE + 0x04B2) |
| 302 | #define MT6325_VDVFS11_CON9 (MT6325_PMIC_REG_BASE + 0x04B4) |
| 303 | #define MT6325_VDVFS11_CON10 (MT6325_PMIC_REG_BASE + 0x04B6) |
| 304 | #define MT6325_VDVFS11_CON11 (MT6325_PMIC_REG_BASE + 0x04B8) |
| 305 | #define MT6325_VDVFS11_CON12 (MT6325_PMIC_REG_BASE + 0x04BA) |
| 306 | #define MT6325_VDVFS11_CON13 (MT6325_PMIC_REG_BASE + 0x04BC) |
| 307 | #define MT6325_VDVFS11_CON14 (MT6325_PMIC_REG_BASE + 0x04BE) |
| 308 | #define MT6325_VDVFS11_CON18 (MT6325_PMIC_REG_BASE + 0x04C6) |
| 309 | #define MT6325_VDVFS12_CON0 (MT6325_PMIC_REG_BASE + 0x04C8) |
| 310 | #define MT6325_VDVFS12_CON7 (MT6325_PMIC_REG_BASE + 0x04D6) |
| 311 | #define MT6325_VDVFS12_CON8 (MT6325_PMIC_REG_BASE + 0x04D8) |
| 312 | #define MT6325_VDVFS12_CON9 (MT6325_PMIC_REG_BASE + 0x04DA) |
| 313 | #define MT6325_VDVFS12_CON10 (MT6325_PMIC_REG_BASE + 0x04DC) |
| 314 | #define MT6325_VDVFS12_CON11 (MT6325_PMIC_REG_BASE + 0x04DE) |
| 315 | #define MT6325_VDVFS12_CON12 (MT6325_PMIC_REG_BASE + 0x04E0) |
| 316 | #define MT6325_VDVFS12_CON13 (MT6325_PMIC_REG_BASE + 0x04E2) |
| 317 | #define MT6325_VDVFS12_CON14 (MT6325_PMIC_REG_BASE + 0x04E4) |
| 318 | #define MT6325_VDVFS12_CON18 (MT6325_PMIC_REG_BASE + 0x04EC) |
| 319 | #define MT6325_VSRAM_DVFS1_CON0 (MT6325_PMIC_REG_BASE + 0x04EE) |
| 320 | #define MT6325_VSRAM_DVFS1_CON7 (MT6325_PMIC_REG_BASE + 0x04FC) |
| 321 | #define MT6325_VSRAM_DVFS1_CON8 (MT6325_PMIC_REG_BASE + 0x04FE) |
| 322 | #define MT6325_VSRAM_DVFS1_CON9 (MT6325_PMIC_REG_BASE + 0x0500) |
| 323 | #define MT6325_VSRAM_DVFS1_CON10 (MT6325_PMIC_REG_BASE + 0x0502) |
| 324 | #define MT6325_VSRAM_DVFS1_CON11 (MT6325_PMIC_REG_BASE + 0x0504) |
| 325 | #define MT6325_VSRAM_DVFS1_CON12 (MT6325_PMIC_REG_BASE + 0x0506) |
| 326 | #define MT6325_VSRAM_DVFS1_CON13 (MT6325_PMIC_REG_BASE + 0x0508) |
| 327 | #define MT6325_VSRAM_DVFS1_CON14 (MT6325_PMIC_REG_BASE + 0x050A) |
| 328 | #define MT6325_VSRAM_DVFS1_CON18 (MT6325_PMIC_REG_BASE + 0x0512) |
| 329 | #define MT6325_VDRAM_CON0 (MT6325_PMIC_REG_BASE + 0x0514) |
| 330 | #define MT6325_VDRAM_CON7 (MT6325_PMIC_REG_BASE + 0x0522) |
| 331 | #define MT6325_VDRAM_CON8 (MT6325_PMIC_REG_BASE + 0x0524) |
| 332 | #define MT6325_VDRAM_CON9 (MT6325_PMIC_REG_BASE + 0x0526) |
| 333 | #define MT6325_VDRAM_CON10 (MT6325_PMIC_REG_BASE + 0x0528) |
| 334 | #define MT6325_VDRAM_CON11 (MT6325_PMIC_REG_BASE + 0x052A) |
| 335 | #define MT6325_VDRAM_CON12 (MT6325_PMIC_REG_BASE + 0x052C) |
| 336 | #define MT6325_VDRAM_CON13 (MT6325_PMIC_REG_BASE + 0x052E) |
| 337 | #define MT6325_VDRAM_CON14 (MT6325_PMIC_REG_BASE + 0x0530) |
| 338 | #define MT6325_VDRAM_CON15 (MT6325_PMIC_REG_BASE + 0x0532) |
| 339 | #define MT6325_VDRAM_CON18 (MT6325_PMIC_REG_BASE + 0x0538) |
| 340 | #define MT6325_VRF18_0_CON0 (MT6325_PMIC_REG_BASE + 0x053A) |
| 341 | #define MT6325_VRF18_0_CON7 (MT6325_PMIC_REG_BASE + 0x0548) |
| 342 | #define MT6325_VRF18_0_CON8 (MT6325_PMIC_REG_BASE + 0x054A) |
| 343 | #define MT6325_VRF18_0_CON9 (MT6325_PMIC_REG_BASE + 0x054C) |
| 344 | #define MT6325_VRF18_0_CON10 (MT6325_PMIC_REG_BASE + 0x054E) |
| 345 | #define MT6325_VRF18_0_CON11 (MT6325_PMIC_REG_BASE + 0x0550) |
| 346 | #define MT6325_VRF18_0_CON12 (MT6325_PMIC_REG_BASE + 0x0552) |
| 347 | #define MT6325_VRF18_0_CON13 (MT6325_PMIC_REG_BASE + 0x0554) |
| 348 | #define MT6325_VRF18_0_CON14 (MT6325_PMIC_REG_BASE + 0x0556) |
| 349 | #define MT6325_VRF18_0_CON15 (MT6325_PMIC_REG_BASE + 0x0558) |
| 350 | #define MT6325_VRF18_0_CON18 (MT6325_PMIC_REG_BASE + 0x055E) |
| 351 | #define MT6325_VGPU_CON0 (MT6325_PMIC_REG_BASE + 0x0600) |
| 352 | #define MT6325_VGPU_CON7 (MT6325_PMIC_REG_BASE + 0x060E) |
| 353 | #define MT6325_VGPU_CON8 (MT6325_PMIC_REG_BASE + 0x0610) |
| 354 | #define MT6325_VGPU_CON9 (MT6325_PMIC_REG_BASE + 0x0612) |
| 355 | #define MT6325_VGPU_CON10 (MT6325_PMIC_REG_BASE + 0x0614) |
| 356 | #define MT6325_VGPU_CON11 (MT6325_PMIC_REG_BASE + 0x0616) |
| 357 | #define MT6325_VGPU_CON12 (MT6325_PMIC_REG_BASE + 0x0618) |
| 358 | #define MT6325_VGPU_CON13 (MT6325_PMIC_REG_BASE + 0x061A) |
| 359 | #define MT6325_VGPU_CON14 (MT6325_PMIC_REG_BASE + 0x061C) |
| 360 | #define MT6325_VGPU_CON15 (MT6325_PMIC_REG_BASE + 0x061E) |
| 361 | #define MT6325_VGPU_CON16 (MT6325_PMIC_REG_BASE + 0x0620) |
| 362 | #define MT6325_VGPU_CON17 (MT6325_PMIC_REG_BASE + 0x0622) |
| 363 | #define MT6325_VGPU_CON18 (MT6325_PMIC_REG_BASE + 0x0624) |
| 364 | #define MT6325_VCORE1_CON0 (MT6325_PMIC_REG_BASE + 0x0626) |
| 365 | #define MT6325_VCORE1_CON7 (MT6325_PMIC_REG_BASE + 0x0634) |
| 366 | #define MT6325_VCORE1_CON8 (MT6325_PMIC_REG_BASE + 0x0636) |
| 367 | #define MT6325_VCORE1_CON9 (MT6325_PMIC_REG_BASE + 0x0638) |
| 368 | #define MT6325_VCORE1_CON10 (MT6325_PMIC_REG_BASE + 0x063A) |
| 369 | #define MT6325_VCORE1_CON11 (MT6325_PMIC_REG_BASE + 0x063C) |
| 370 | #define MT6325_VCORE1_CON12 (MT6325_PMIC_REG_BASE + 0x063E) |
| 371 | #define MT6325_VCORE1_CON13 (MT6325_PMIC_REG_BASE + 0x0640) |
| 372 | #define MT6325_VCORE1_CON14 (MT6325_PMIC_REG_BASE + 0x0642) |
| 373 | #define MT6325_VCORE1_CON15 (MT6325_PMIC_REG_BASE + 0x0644) |
| 374 | #define MT6325_VCORE1_CON16 (MT6325_PMIC_REG_BASE + 0x0646) |
| 375 | #define MT6325_VCORE1_CON17 (MT6325_PMIC_REG_BASE + 0x0648) |
| 376 | #define MT6325_VCORE1_CON18 (MT6325_PMIC_REG_BASE + 0x064A) |
| 377 | #define MT6325_VCORE2_CON0 (MT6325_PMIC_REG_BASE + 0x064C) |
| 378 | #define MT6325_VCORE2_CON7 (MT6325_PMIC_REG_BASE + 0x065A) |
| 379 | #define MT6325_VCORE2_CON8 (MT6325_PMIC_REG_BASE + 0x065C) |
| 380 | #define MT6325_VCORE2_CON9 (MT6325_PMIC_REG_BASE + 0x065E) |
| 381 | #define MT6325_VCORE2_CON10 (MT6325_PMIC_REG_BASE + 0x0660) |
| 382 | #define MT6325_VCORE2_CON11 (MT6325_PMIC_REG_BASE + 0x0662) |
| 383 | #define MT6325_VCORE2_CON12 (MT6325_PMIC_REG_BASE + 0x0664) |
| 384 | #define MT6325_VCORE2_CON13 (MT6325_PMIC_REG_BASE + 0x0666) |
| 385 | #define MT6325_VCORE2_CON14 (MT6325_PMIC_REG_BASE + 0x0668) |
| 386 | #define MT6325_VCORE2_CON15 (MT6325_PMIC_REG_BASE + 0x066A) |
| 387 | #define MT6325_VCORE2_CON16 (MT6325_PMIC_REG_BASE + 0x066C) |
| 388 | #define MT6325_VCORE2_CON17 (MT6325_PMIC_REG_BASE + 0x066E) |
| 389 | #define MT6325_VCORE2_CON18 (MT6325_PMIC_REG_BASE + 0x0670) |
| 390 | #define MT6325_VCORE2_CON19 (MT6325_PMIC_REG_BASE + 0x0672) |
| 391 | #define MT6325_VCORE2_CON20 (MT6325_PMIC_REG_BASE + 0x0674) |
| 392 | #define MT6325_VIO18_CON0 (MT6325_PMIC_REG_BASE + 0x0676) |
| 393 | #define MT6325_VIO18_CON7 (MT6325_PMIC_REG_BASE + 0x0684) |
| 394 | #define MT6325_VIO18_CON8 (MT6325_PMIC_REG_BASE + 0x0686) |
| 395 | #define MT6325_VIO18_CON9 (MT6325_PMIC_REG_BASE + 0x0688) |
| 396 | #define MT6325_VIO18_CON10 (MT6325_PMIC_REG_BASE + 0x068A) |
| 397 | #define MT6325_VIO18_CON11 (MT6325_PMIC_REG_BASE + 0x068C) |
| 398 | #define MT6325_VIO18_CON12 (MT6325_PMIC_REG_BASE + 0x068E) |
| 399 | #define MT6325_VIO18_CON13 (MT6325_PMIC_REG_BASE + 0x0690) |
| 400 | #define MT6325_VIO18_CON14 (MT6325_PMIC_REG_BASE + 0x0692) |
| 401 | #define MT6325_VIO18_CON15 (MT6325_PMIC_REG_BASE + 0x0694) |
| 402 | #define MT6325_VIO18_CON16 (MT6325_PMIC_REG_BASE + 0x0696) |
| 403 | #define MT6325_VIO18_CON17 (MT6325_PMIC_REG_BASE + 0x0698) |
| 404 | #define MT6325_VIO18_CON18 (MT6325_PMIC_REG_BASE + 0x069A) |
| 405 | #define MT6325_VPA_CON0 (MT6325_PMIC_REG_BASE + 0x069C) |
| 406 | #define MT6325_VPA_CON7 (MT6325_PMIC_REG_BASE + 0x06AA) |
| 407 | #define MT6325_VPA_CON8 (MT6325_PMIC_REG_BASE + 0x06AC) |
| 408 | #define MT6325_VPA_CON9 (MT6325_PMIC_REG_BASE + 0x06AE) |
| 409 | #define MT6325_VPA_CON10 (MT6325_PMIC_REG_BASE + 0x06B0) |
| 410 | #define MT6325_VPA_CON11 (MT6325_PMIC_REG_BASE + 0x06B2) |
| 411 | #define MT6325_VPA_CON12 (MT6325_PMIC_REG_BASE + 0x06B4) |
| 412 | #define MT6325_VPA_CON13 (MT6325_PMIC_REG_BASE + 0x06B6) |
| 413 | #define MT6325_VPA_CON14 (MT6325_PMIC_REG_BASE + 0x06B8) |
| 414 | #define MT6325_VPA_CON15 (MT6325_PMIC_REG_BASE + 0x06BA) |
| 415 | #define MT6325_VPA_CON16 (MT6325_PMIC_REG_BASE + 0x06BC) |
| 416 | #define MT6325_VPA_CON17 (MT6325_PMIC_REG_BASE + 0x06BE) |
| 417 | #define MT6325_VPA_CON18 (MT6325_PMIC_REG_BASE + 0x06C0) |
| 418 | #define MT6325_VPA_CON19 (MT6325_PMIC_REG_BASE + 0x06C2) |
| 419 | #define MT6325_VPA_CON20 (MT6325_PMIC_REG_BASE + 0x06C4) |
| 420 | #define MT6325_VPA_CON21 (MT6325_PMIC_REG_BASE + 0x06C6) |
| 421 | #define MT6325_VPA_CON22 (MT6325_PMIC_REG_BASE + 0x06C8) |
| 422 | #define MT6325_VPA_CON23 (MT6325_PMIC_REG_BASE + 0x06CA) |
| 423 | #define MT6325_BUCK_K_CON0 (MT6325_PMIC_REG_BASE + 0x06CC) |
| 424 | #define MT6325_BUCK_K_CON1 (MT6325_PMIC_REG_BASE + 0x06CE) |
| 425 | #define MT6325_BUCK_K_CON2 (MT6325_PMIC_REG_BASE + 0x06D0) |
| 426 | #define MT6325_BUCK_K_CON3 (MT6325_PMIC_REG_BASE + 0x06D2) |
| 427 | #define MT6325_ZCD_CON0 (MT6325_PMIC_REG_BASE + 0x0800) |
| 428 | #define MT6325_ZCD_CON1 (MT6325_PMIC_REG_BASE + 0x0802) |
| 429 | #define MT6325_ZCD_CON2 (MT6325_PMIC_REG_BASE + 0x0804) |
| 430 | #define MT6325_ZCD_CON3 (MT6325_PMIC_REG_BASE + 0x0806) |
| 431 | #define MT6325_ZCD_CON4 (MT6325_PMIC_REG_BASE + 0x0808) |
| 432 | #define MT6325_ZCD_CON5 (MT6325_PMIC_REG_BASE + 0x080A) |
| 433 | #define MT6325_ISINK0_CON0 (MT6325_PMIC_REG_BASE + 0x080C) |
| 434 | #define MT6325_ISINK0_CON1 (MT6325_PMIC_REG_BASE + 0x080E) |
| 435 | #define MT6325_ISINK0_CON2 (MT6325_PMIC_REG_BASE + 0x0810) |
| 436 | #define MT6325_ISINK0_CON3 (MT6325_PMIC_REG_BASE + 0x0812) |
| 437 | #define MT6325_ISINK1_CON0 (MT6325_PMIC_REG_BASE + 0x0814) |
| 438 | #define MT6325_ISINK1_CON1 (MT6325_PMIC_REG_BASE + 0x0816) |
| 439 | #define MT6325_ISINK1_CON2 (MT6325_PMIC_REG_BASE + 0x0818) |
| 440 | #define MT6325_ISINK1_CON3 (MT6325_PMIC_REG_BASE + 0x081A) |
| 441 | #define MT6325_ISINK2_CON0 (MT6325_PMIC_REG_BASE + 0x081C) |
| 442 | #define MT6325_ISINK2_CON1 (MT6325_PMIC_REG_BASE + 0x081E) |
| 443 | #define MT6325_ISINK2_CON2 (MT6325_PMIC_REG_BASE + 0x0820) |
| 444 | #define MT6325_ISINK2_CON3 (MT6325_PMIC_REG_BASE + 0x0822) |
| 445 | #define MT6325_ISINK3_CON0 (MT6325_PMIC_REG_BASE + 0x0824) |
| 446 | #define MT6325_ISINK3_CON1 (MT6325_PMIC_REG_BASE + 0x0826) |
| 447 | #define MT6325_ISINK3_CON2 (MT6325_PMIC_REG_BASE + 0x0828) |
| 448 | #define MT6325_ISINK3_CON3 (MT6325_PMIC_REG_BASE + 0x082A) |
| 449 | #define MT6325_ISINK_ANA0 (MT6325_PMIC_REG_BASE + 0x082C) |
| 450 | #define MT6325_ISINK_ANA1 (MT6325_PMIC_REG_BASE + 0x082E) |
| 451 | #define MT6325_ISINK_PHASE_DLY (MT6325_PMIC_REG_BASE + 0x0830) |
| 452 | #define MT6325_ISINK_SFSTR (MT6325_PMIC_REG_BASE + 0x0832) |
| 453 | #define MT6325_ISINK_EN_CTRL (MT6325_PMIC_REG_BASE + 0x0834) |
| 454 | #define MT6325_ISINK_MODE_CTRL (MT6325_PMIC_REG_BASE + 0x0836) |
| 455 | #define MT6325_ISINK_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0838) |
| 456 | #define MT6325_LDO_CON0 (MT6325_PMIC_REG_BASE + 0x0A00) |
| 457 | #define MT6325_LDO_CON1 (MT6325_PMIC_REG_BASE + 0x0A02) |
| 458 | #define MT6325_LDO_CON2 (MT6325_PMIC_REG_BASE + 0x0A04) |
| 459 | #define MT6325_LDO_CON3 (MT6325_PMIC_REG_BASE + 0x0A06) |
| 460 | #define MT6325_LDO_CON4 (MT6325_PMIC_REG_BASE + 0x0A08) |
| 461 | #define MT6325_LDO_CON5 (MT6325_PMIC_REG_BASE + 0x0A0A) |
| 462 | #define MT6325_LDO_CON6 (MT6325_PMIC_REG_BASE + 0x0A0C) |
| 463 | #define MT6325_LDO_CON7 (MT6325_PMIC_REG_BASE + 0x0A0E) |
| 464 | #define MT6325_LDO_CON8 (MT6325_PMIC_REG_BASE + 0x0A10) |
| 465 | #define MT6325_LDO_CON9 (MT6325_PMIC_REG_BASE + 0x0A12) |
| 466 | #define MT6325_LDO_CON10 (MT6325_PMIC_REG_BASE + 0x0A14) |
| 467 | #define MT6325_LDO_CON11 (MT6325_PMIC_REG_BASE + 0x0A16) |
| 468 | #define MT6325_LDO_CON12 (MT6325_PMIC_REG_BASE + 0x0A18) |
| 469 | #define MT6325_LDO_CON13 (MT6325_PMIC_REG_BASE + 0x0A1A) |
| 470 | #define MT6325_LDO_CON14 (MT6325_PMIC_REG_BASE + 0x0A1C) |
| 471 | #define MT6325_LDO_CON15 (MT6325_PMIC_REG_BASE + 0x0A1E) |
| 472 | #define MT6325_LDO_CON16 (MT6325_PMIC_REG_BASE + 0x0A20) |
| 473 | #define MT6325_LDO_CON17 (MT6325_PMIC_REG_BASE + 0x0A22) |
| 474 | #define MT6325_LDO_CON18 (MT6325_PMIC_REG_BASE + 0x0A24) |
| 475 | #define MT6325_LDO_CON19 (MT6325_PMIC_REG_BASE + 0x0A26) |
| 476 | #define MT6325_LDO_CON20 (MT6325_PMIC_REG_BASE + 0x0A28) |
| 477 | #define MT6325_LDO_CON21 (MT6325_PMIC_REG_BASE + 0x0A2A) |
| 478 | #define MT6325_LDO_CON22 (MT6325_PMIC_REG_BASE + 0x0A2C) |
| 479 | #define MT6325_LDO_CON23 (MT6325_PMIC_REG_BASE + 0x0A2E) |
| 480 | #define MT6325_LDO_CON24 (MT6325_PMIC_REG_BASE + 0x0A30) |
| 481 | #define MT6325_LDO_CON25 (MT6325_PMIC_REG_BASE + 0x0A32) |
| 482 | #define MT6325_LDO_CON26 (MT6325_PMIC_REG_BASE + 0x0A34) |
| 483 | #define MT6325_LDO_CON27 (MT6325_PMIC_REG_BASE + 0x0A36) |
| 484 | #define MT6325_LDO_CON28 (MT6325_PMIC_REG_BASE + 0x0A38) |
| 485 | #define MT6325_LDO_CON29 (MT6325_PMIC_REG_BASE + 0x0A3A) |
| 486 | #define MT6325_LDO_CON30 (MT6325_PMIC_REG_BASE + 0x0A3C) |
| 487 | #define MT6325_LDO_VCON0 (MT6325_PMIC_REG_BASE + 0x0A3E) |
| 488 | #define MT6325_LDO_VCON1 (MT6325_PMIC_REG_BASE + 0x0A40) |
| 489 | #define MT6325_LDO_VCON2 (MT6325_PMIC_REG_BASE + 0x0A42) |
| 490 | #define MT6325_LDO_VCON3 (MT6325_PMIC_REG_BASE + 0x0A44) |
| 491 | #define MT6325_LDO_VCON4 (MT6325_PMIC_REG_BASE + 0x0A46) |
| 492 | #define MT6325_LDO_VCON5 (MT6325_PMIC_REG_BASE + 0x0A48) |
| 493 | #define MT6325_LDO_VCON6 (MT6325_PMIC_REG_BASE + 0x0A4A) |
| 494 | #define MT6325_LDO_VCON7 (MT6325_PMIC_REG_BASE + 0x0A4C) |
| 495 | #define MT6325_LDO_VCON8 (MT6325_PMIC_REG_BASE + 0x0A4E) |
| 496 | #define MT6325_LDO_VCON9 (MT6325_PMIC_REG_BASE + 0x0A50) |
| 497 | #define MT6325_LDO_VCON10 (MT6325_PMIC_REG_BASE + 0x0A52) |
| 498 | #define MT6325_LDO_VCON11 (MT6325_PMIC_REG_BASE + 0x0A54) |
| 499 | #define MT6325_LDO_VCON13 (MT6325_PMIC_REG_BASE + 0x0A56) |
| 500 | #define MT6325_LDO_VCON14 (MT6325_PMIC_REG_BASE + 0x0A58) |
| 501 | #define MT6325_LDO_VCON15 (MT6325_PMIC_REG_BASE + 0x0A5A) |
| 502 | #define MT6325_LDO_VCON16 (MT6325_PMIC_REG_BASE + 0x0A5C) |
| 503 | #define MT6325_LDO_RSV0 (MT6325_PMIC_REG_BASE + 0x0A5E) |
| 504 | #define MT6325_LDO_RSV1 (MT6325_PMIC_REG_BASE + 0x0A60) |
| 505 | #define MT6325_LDO_RSV2 (MT6325_PMIC_REG_BASE + 0x0A62) |
| 506 | #define MT6325_LDO_RSV3 (MT6325_PMIC_REG_BASE + 0x0A64) |
| 507 | #define MT6325_LDO_OCFB0 (MT6325_PMIC_REG_BASE + 0x0A66) |
| 508 | #define MT6325_LDO_OCFB1 (MT6325_PMIC_REG_BASE + 0x0A68) |
| 509 | #define MT6325_LDO_OCFB2 (MT6325_PMIC_REG_BASE + 0x0A6A) |
| 510 | #define MT6325_LDO_OCFB3 (MT6325_PMIC_REG_BASE + 0x0A6C) |
| 511 | #define MT6325_LDO_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0A6E) |
| 512 | #define MT6325_BIF_CON0 (MT6325_PMIC_REG_BASE + 0x0A70) |
| 513 | #define MT6325_BIF_CON1 (MT6325_PMIC_REG_BASE + 0x0A72) |
| 514 | #define MT6325_BIF_CON2 (MT6325_PMIC_REG_BASE + 0x0A74) |
| 515 | #define MT6325_BIF_CON3 (MT6325_PMIC_REG_BASE + 0x0A76) |
| 516 | #define MT6325_BIF_CON4 (MT6325_PMIC_REG_BASE + 0x0A78) |
| 517 | #define MT6325_BIF_CON5 (MT6325_PMIC_REG_BASE + 0x0A7A) |
| 518 | #define MT6325_BIF_CON6 (MT6325_PMIC_REG_BASE + 0x0A7C) |
| 519 | #define MT6325_BIF_CON7 (MT6325_PMIC_REG_BASE + 0x0A7E) |
| 520 | #define MT6325_BIF_CON8 (MT6325_PMIC_REG_BASE + 0x0A80) |
| 521 | #define MT6325_BIF_CON9 (MT6325_PMIC_REG_BASE + 0x0A82) |
| 522 | #define MT6325_BIF_CON10 (MT6325_PMIC_REG_BASE + 0x0A84) |
| 523 | #define MT6325_BIF_CON11 (MT6325_PMIC_REG_BASE + 0x0A86) |
| 524 | #define MT6325_BIF_CON12 (MT6325_PMIC_REG_BASE + 0x0A88) |
| 525 | #define MT6325_BIF_CON13 (MT6325_PMIC_REG_BASE + 0x0A8A) |
| 526 | #define MT6325_BIF_CON14 (MT6325_PMIC_REG_BASE + 0x0A8C) |
| 527 | #define MT6325_BIF_CON15 (MT6325_PMIC_REG_BASE + 0x0A8E) |
| 528 | #define MT6325_BIF_CON16 (MT6325_PMIC_REG_BASE + 0x0A90) |
| 529 | #define MT6325_BIF_CON17 (MT6325_PMIC_REG_BASE + 0x0A92) |
| 530 | #define MT6325_BIF_CON18 (MT6325_PMIC_REG_BASE + 0x0A94) |
| 531 | #define MT6325_BIF_CON19 (MT6325_PMIC_REG_BASE + 0x0A96) |
| 532 | #define MT6325_BIF_CON20 (MT6325_PMIC_REG_BASE + 0x0A98) |
| 533 | #define MT6325_BIF_CON21 (MT6325_PMIC_REG_BASE + 0x0A9A) |
| 534 | #define MT6325_BIF_CON22 (MT6325_PMIC_REG_BASE + 0x0A9C) |
| 535 | #define MT6325_BIF_CON23 (MT6325_PMIC_REG_BASE + 0x0A9E) |
| 536 | #define MT6325_BIF_CON24 (MT6325_PMIC_REG_BASE + 0x0AA0) |
| 537 | #define MT6325_BIF_CON25 (MT6325_PMIC_REG_BASE + 0x0AA2) |
| 538 | #define MT6325_BIF_CON26 (MT6325_PMIC_REG_BASE + 0x0AA4) |
| 539 | #define MT6325_BIF_CON27 (MT6325_PMIC_REG_BASE + 0x0AA6) |
| 540 | #define MT6325_BIF_CON28 (MT6325_PMIC_REG_BASE + 0x0AA8) |
| 541 | #define MT6325_BIF_CON29 (MT6325_PMIC_REG_BASE + 0x0AAA) |
| 542 | #define MT6325_BIF_CON30 (MT6325_PMIC_REG_BASE + 0x0AAC) |
| 543 | #define MT6325_BIF_CON31 (MT6325_PMIC_REG_BASE + 0x0AAE) |
| 544 | #define MT6325_BIF_CON32 (MT6325_PMIC_REG_BASE + 0x0AB0) |
| 545 | #define MT6325_BIF_CON33 (MT6325_PMIC_REG_BASE + 0x0AB2) |
| 546 | #define MT6325_BIF_CON34 (MT6325_PMIC_REG_BASE + 0x0AB4) |
| 547 | #define MT6325_BIF_CON35 (MT6325_PMIC_REG_BASE + 0x0AB6) |
| 548 | #define MT6325_BIF_CON36 (MT6325_PMIC_REG_BASE + 0x0AB8) |
| 549 | #define MT6325_BATON_CON0 (MT6325_PMIC_REG_BASE + 0x0ABA) |
| 550 | #define MT6325_BIF_CON37 (MT6325_PMIC_REG_BASE + 0x0ABC) |
| 551 | #define MT6325_BIF_CON38 (MT6325_PMIC_REG_BASE + 0x0ABE) |
| 552 | #define MT6325_BIF_CON39 (MT6325_PMIC_REG_BASE + 0x0AC0) |
| 553 | #define MT6325_SPK_CON0 (MT6325_PMIC_REG_BASE + 0x0AC2) |
| 554 | #define MT6325_SPK_CON1 (MT6325_PMIC_REG_BASE + 0x0AC4) |
| 555 | #define MT6325_SPK_CON2 (MT6325_PMIC_REG_BASE + 0x0AC6) |
| 556 | #define MT6325_SPK_CON3 (MT6325_PMIC_REG_BASE + 0x0AC8) |
| 557 | #define MT6325_SPK_CON4 (MT6325_PMIC_REG_BASE + 0x0ACA) |
| 558 | #define MT6325_SPK_CON5 (MT6325_PMIC_REG_BASE + 0x0ACC) |
| 559 | #define MT6325_SPK_CON6 (MT6325_PMIC_REG_BASE + 0x0ACE) |
| 560 | #define MT6325_SPK_CON7 (MT6325_PMIC_REG_BASE + 0x0AD0) |
| 561 | #define MT6325_SPK_CON8 (MT6325_PMIC_REG_BASE + 0x0AD2) |
| 562 | #define MT6325_SPK_CON9 (MT6325_PMIC_REG_BASE + 0x0AD4) |
| 563 | #define MT6325_SPK_CON10 (MT6325_PMIC_REG_BASE + 0x0AD6) |
| 564 | #define MT6325_SPK_CON11 (MT6325_PMIC_REG_BASE + 0x0AD8) |
| 565 | #define MT6325_SPK_CON12 (MT6325_PMIC_REG_BASE + 0x0ADA) |
| 566 | #define MT6325_SPK_CON13 (MT6325_PMIC_REG_BASE + 0x0ADC) |
| 567 | #define MT6325_SPK_CON14 (MT6325_PMIC_REG_BASE + 0x0ADE) |
| 568 | #define MT6325_SPK_CON15 (MT6325_PMIC_REG_BASE + 0x0AE0) |
| 569 | #define MT6325_SPK_CON16 (MT6325_PMIC_REG_BASE + 0x0AE2) |
| 570 | #define MT6325_SPK_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0AE4) |
| 571 | #define MT6325_SPK_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0AE6) |
| 572 | #define MT6325_SPK_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0AE8) |
| 573 | #define MT6325_OTP_CON0 (MT6325_PMIC_REG_BASE + 0x0C00) |
| 574 | #define MT6325_OTP_CON1 (MT6325_PMIC_REG_BASE + 0x0C02) |
| 575 | #define MT6325_OTP_CON2 (MT6325_PMIC_REG_BASE + 0x0C04) |
| 576 | #define MT6325_OTP_CON3 (MT6325_PMIC_REG_BASE + 0x0C06) |
| 577 | #define MT6325_OTP_CON4 (MT6325_PMIC_REG_BASE + 0x0C08) |
| 578 | #define MT6325_OTP_CON5 (MT6325_PMIC_REG_BASE + 0x0C0A) |
| 579 | #define MT6325_OTP_CON6 (MT6325_PMIC_REG_BASE + 0x0C0C) |
| 580 | #define MT6325_OTP_CON7 (MT6325_PMIC_REG_BASE + 0x0C0E) |
| 581 | #define MT6325_OTP_CON8 (MT6325_PMIC_REG_BASE + 0x0C10) |
| 582 | #define MT6325_OTP_CON9 (MT6325_PMIC_REG_BASE + 0x0C12) |
| 583 | #define MT6325_OTP_CON10 (MT6325_PMIC_REG_BASE + 0x0C14) |
| 584 | #define MT6325_OTP_CON11 (MT6325_PMIC_REG_BASE + 0x0C16) |
| 585 | #define MT6325_OTP_CON12 (MT6325_PMIC_REG_BASE + 0x0C18) |
| 586 | #define MT6325_OTP_CON13 (MT6325_PMIC_REG_BASE + 0x0C1A) |
| 587 | #define MT6325_OTP_CON14 (MT6325_PMIC_REG_BASE + 0x0C1C) |
| 588 | #define MT6325_OTP_DOUT_0_15 (MT6325_PMIC_REG_BASE + 0x0C1E) |
| 589 | #define MT6325_OTP_DOUT_16_31 (MT6325_PMIC_REG_BASE + 0x0C20) |
| 590 | #define MT6325_OTP_DOUT_32_47 (MT6325_PMIC_REG_BASE + 0x0C22) |
| 591 | #define MT6325_OTP_DOUT_48_63 (MT6325_PMIC_REG_BASE + 0x0C24) |
| 592 | #define MT6325_OTP_DOUT_64_79 (MT6325_PMIC_REG_BASE + 0x0C26) |
| 593 | #define MT6325_OTP_DOUT_80_95 (MT6325_PMIC_REG_BASE + 0x0C28) |
| 594 | #define MT6325_OTP_DOUT_96_111 (MT6325_PMIC_REG_BASE + 0x0C2A) |
| 595 | #define MT6325_OTP_DOUT_112_127 (MT6325_PMIC_REG_BASE + 0x0C2C) |
| 596 | #define MT6325_OTP_DOUT_128_143 (MT6325_PMIC_REG_BASE + 0x0C2E) |
| 597 | #define MT6325_OTP_DOUT_144_159 (MT6325_PMIC_REG_BASE + 0x0C30) |
| 598 | #define MT6325_OTP_DOUT_160_175 (MT6325_PMIC_REG_BASE + 0x0C32) |
| 599 | #define MT6325_OTP_DOUT_176_191 (MT6325_PMIC_REG_BASE + 0x0C34) |
| 600 | #define MT6325_OTP_DOUT_192_207 (MT6325_PMIC_REG_BASE + 0x0C36) |
| 601 | #define MT6325_OTP_DOUT_208_223 (MT6325_PMIC_REG_BASE + 0x0C38) |
| 602 | #define MT6325_OTP_DOUT_224_239 (MT6325_PMIC_REG_BASE + 0x0C3A) |
| 603 | #define MT6325_OTP_DOUT_240_255 (MT6325_PMIC_REG_BASE + 0x0C3C) |
| 604 | #define MT6325_OTP_DOUT_256_271 (MT6325_PMIC_REG_BASE + 0x0C3E) |
| 605 | #define MT6325_OTP_DOUT_272_287 (MT6325_PMIC_REG_BASE + 0x0C40) |
| 606 | #define MT6325_OTP_DOUT_288_303 (MT6325_PMIC_REG_BASE + 0x0C42) |
| 607 | #define MT6325_OTP_DOUT_304_319 (MT6325_PMIC_REG_BASE + 0x0C44) |
| 608 | #define MT6325_OTP_DOUT_320_335 (MT6325_PMIC_REG_BASE + 0x0C46) |
| 609 | #define MT6325_OTP_DOUT_336_351 (MT6325_PMIC_REG_BASE + 0x0C48) |
| 610 | #define MT6325_OTP_DOUT_352_367 (MT6325_PMIC_REG_BASE + 0x0C4A) |
| 611 | #define MT6325_OTP_DOUT_368_383 (MT6325_PMIC_REG_BASE + 0x0C4C) |
| 612 | #define MT6325_OTP_DOUT_384_399 (MT6325_PMIC_REG_BASE + 0x0C4E) |
| 613 | #define MT6325_OTP_DOUT_400_415 (MT6325_PMIC_REG_BASE + 0x0C50) |
| 614 | #define MT6325_OTP_DOUT_416_431 (MT6325_PMIC_REG_BASE + 0x0C52) |
| 615 | #define MT6325_OTP_DOUT_432_447 (MT6325_PMIC_REG_BASE + 0x0C54) |
| 616 | #define MT6325_OTP_DOUT_448_463 (MT6325_PMIC_REG_BASE + 0x0C56) |
| 617 | #define MT6325_OTP_DOUT_464_479 (MT6325_PMIC_REG_BASE + 0x0C58) |
| 618 | #define MT6325_OTP_DOUT_480_495 (MT6325_PMIC_REG_BASE + 0x0C5A) |
| 619 | #define MT6325_OTP_DOUT_496_511 (MT6325_PMIC_REG_BASE + 0x0C5C) |
| 620 | #define MT6325_OTP_VAL_0_15 (MT6325_PMIC_REG_BASE + 0x0C5E) |
| 621 | #define MT6325_OTP_VAL_16_31 (MT6325_PMIC_REG_BASE + 0x0C60) |
| 622 | #define MT6325_OTP_VAL_32_47 (MT6325_PMIC_REG_BASE + 0x0C62) |
| 623 | #define MT6325_OTP_VAL_48_63 (MT6325_PMIC_REG_BASE + 0x0C64) |
| 624 | #define MT6325_OTP_VAL_64_79 (MT6325_PMIC_REG_BASE + 0x0C66) |
| 625 | #define MT6325_OTP_VAL_80_95 (MT6325_PMIC_REG_BASE + 0x0C68) |
| 626 | #define MT6325_OTP_VAL_96_111 (MT6325_PMIC_REG_BASE + 0x0C6A) |
| 627 | #define MT6325_OTP_VAL_112_127 (MT6325_PMIC_REG_BASE + 0x0C6C) |
| 628 | #define MT6325_OTP_VAL_128_143 (MT6325_PMIC_REG_BASE + 0x0C6E) |
| 629 | #define MT6325_OTP_VAL_144_159 (MT6325_PMIC_REG_BASE + 0x0C70) |
| 630 | #define MT6325_OTP_VAL_160_175 (MT6325_PMIC_REG_BASE + 0x0C72) |
| 631 | #define MT6325_OTP_VAL_176_191 (MT6325_PMIC_REG_BASE + 0x0C74) |
| 632 | #define MT6325_OTP_VAL_192_207 (MT6325_PMIC_REG_BASE + 0x0C76) |
| 633 | #define MT6325_OTP_VAL_208_223 (MT6325_PMIC_REG_BASE + 0x0C78) |
| 634 | #define MT6325_OTP_VAL_224_239 (MT6325_PMIC_REG_BASE + 0x0C7A) |
| 635 | #define MT6325_OTP_VAL_240_255 (MT6325_PMIC_REG_BASE + 0x0C7C) |
| 636 | #define MT6325_OTP_VAL_256_271 (MT6325_PMIC_REG_BASE + 0x0C7E) |
| 637 | #define MT6325_OTP_VAL_272_287 (MT6325_PMIC_REG_BASE + 0x0C80) |
| 638 | #define MT6325_OTP_VAL_288_303 (MT6325_PMIC_REG_BASE + 0x0C82) |
| 639 | #define MT6325_OTP_VAL_304_319 (MT6325_PMIC_REG_BASE + 0x0C84) |
| 640 | #define MT6325_OTP_VAL_320_335 (MT6325_PMIC_REG_BASE + 0x0C86) |
| 641 | #define MT6325_OTP_VAL_336_351 (MT6325_PMIC_REG_BASE + 0x0C88) |
| 642 | #define MT6325_OTP_VAL_352_367 (MT6325_PMIC_REG_BASE + 0x0C8A) |
| 643 | #define MT6325_OTP_VAL_368_383 (MT6325_PMIC_REG_BASE + 0x0C8C) |
| 644 | #define MT6325_OTP_VAL_384_399 (MT6325_PMIC_REG_BASE + 0x0C8E) |
| 645 | #define MT6325_OTP_VAL_400_415 (MT6325_PMIC_REG_BASE + 0x0C90) |
| 646 | #define MT6325_OTP_VAL_416_431 (MT6325_PMIC_REG_BASE + 0x0C92) |
| 647 | #define MT6325_OTP_VAL_432_447 (MT6325_PMIC_REG_BASE + 0x0C94) |
| 648 | #define MT6325_OTP_VAL_448_463 (MT6325_PMIC_REG_BASE + 0x0C96) |
| 649 | #define MT6325_OTP_VAL_464_479 (MT6325_PMIC_REG_BASE + 0x0C98) |
| 650 | #define MT6325_OTP_VAL_480_495 (MT6325_PMIC_REG_BASE + 0x0C9A) |
| 651 | #define MT6325_OTP_VAL_496_511 (MT6325_PMIC_REG_BASE + 0x0C9C) |
| 652 | #define MT6325_RTC_MIX_CON0 (MT6325_PMIC_REG_BASE + 0x0C9E) |
| 653 | #define MT6325_RTC_MIX_CON1 (MT6325_PMIC_REG_BASE + 0x0CA0) |
| 654 | #define MT6325_RTC_MIX_CON2 (MT6325_PMIC_REG_BASE + 0x0CA2) |
| 655 | #define MT6325_FGADC_CON0 (MT6325_PMIC_REG_BASE + 0x0CA4) |
| 656 | #define MT6325_FGADC_CON1 (MT6325_PMIC_REG_BASE + 0x0CA6) |
| 657 | #define MT6325_FGADC_CON2 (MT6325_PMIC_REG_BASE + 0x0CA8) |
| 658 | #define MT6325_FGADC_CON3 (MT6325_PMIC_REG_BASE + 0x0CAA) |
| 659 | #define MT6325_FGADC_CON4 (MT6325_PMIC_REG_BASE + 0x0CAC) |
| 660 | #define MT6325_FGADC_CON5 (MT6325_PMIC_REG_BASE + 0x0CAE) |
| 661 | #define MT6325_FGADC_CON6 (MT6325_PMIC_REG_BASE + 0x0CB0) |
| 662 | #define MT6325_FGADC_CON7 (MT6325_PMIC_REG_BASE + 0x0CB2) |
| 663 | #define MT6325_FGADC_CON8 (MT6325_PMIC_REG_BASE + 0x0CB4) |
| 664 | #define MT6325_FGADC_CON9 (MT6325_PMIC_REG_BASE + 0x0CB6) |
| 665 | #define MT6325_FGADC_CON10 (MT6325_PMIC_REG_BASE + 0x0CB8) |
| 666 | #define MT6325_FGADC_CON11 (MT6325_PMIC_REG_BASE + 0x0CBA) |
| 667 | #define MT6325_FGADC_CON12 (MT6325_PMIC_REG_BASE + 0x0CBC) |
| 668 | #define MT6325_FGADC_CON13 (MT6325_PMIC_REG_BASE + 0x0CBE) |
| 669 | #define MT6325_FGADC_CON14 (MT6325_PMIC_REG_BASE + 0x0CC0) |
| 670 | #define MT6325_FGADC_CON15 (MT6325_PMIC_REG_BASE + 0x0CC2) |
| 671 | #define MT6325_FGADC_CON16 (MT6325_PMIC_REG_BASE + 0x0CC4) |
| 672 | #define MT6325_FGADC_CON17 (MT6325_PMIC_REG_BASE + 0x0CC6) |
| 673 | #define MT6325_FGADC_CON18 (MT6325_PMIC_REG_BASE + 0x0CC8) |
| 674 | #define MT6325_FGADC_CON19 (MT6325_PMIC_REG_BASE + 0x0CCA) |
| 675 | #define MT6325_FGADC_CON20 (MT6325_PMIC_REG_BASE + 0x0CCC) |
| 676 | #define MT6325_FGADC_CON21 (MT6325_PMIC_REG_BASE + 0x0CCE) |
| 677 | #define MT6325_FGADC_CON22 (MT6325_PMIC_REG_BASE + 0x0CD0) |
| 678 | #define MT6325_FGADC_CON23 (MT6325_PMIC_REG_BASE + 0x0CD2) |
| 679 | #define MT6325_FGADC_CON24 (MT6325_PMIC_REG_BASE + 0x0CD4) |
| 680 | #define MT6325_FGADC_CON25 (MT6325_PMIC_REG_BASE + 0x0CD6) |
| 681 | #define MT6325_FGADC_CON26 (MT6325_PMIC_REG_BASE + 0x0CD8) |
| 682 | #define MT6325_FGADC_CON27 (MT6325_PMIC_REG_BASE + 0x0CDA) |
| 683 | #define MT6325_FGADC_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0CDC) |
| 684 | #define MT6325_AUDDEC_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0CDE) |
| 685 | #define MT6325_AUDDEC_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0CE0) |
| 686 | #define MT6325_AUDDEC_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0CE2) |
| 687 | #define MT6325_AUDDEC_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0CE4) |
| 688 | #define MT6325_AUDDEC_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0CE6) |
| 689 | #define MT6325_AUDDEC_ANA_CON5 (MT6325_PMIC_REG_BASE + 0x0CE8) |
| 690 | #define MT6325_AUDDEC_ANA_CON6 (MT6325_PMIC_REG_BASE + 0x0CEA) |
| 691 | #define MT6325_AUDDEC_ANA_CON7 (MT6325_PMIC_REG_BASE + 0x0CEC) |
| 692 | #define MT6325_AUDDEC_ANA_CON8 (MT6325_PMIC_REG_BASE + 0x0CEE) |
| 693 | #define MT6325_AUDENC_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0CF0) |
| 694 | #define MT6325_AUDENC_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0CF2) |
| 695 | #define MT6325_AUDENC_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0CF4) |
| 696 | #define MT6325_AUDENC_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0CF6) |
| 697 | #define MT6325_AUDENC_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0CF8) |
| 698 | #define MT6325_AUDENC_ANA_CON5 (MT6325_PMIC_REG_BASE + 0x0CFA) |
| 699 | #define MT6325_AUDENC_ANA_CON6 (MT6325_PMIC_REG_BASE + 0x0CFC) |
| 700 | #define MT6325_AUDENC_ANA_CON7 (MT6325_PMIC_REG_BASE + 0x0CFE) |
| 701 | #define MT6325_AUDENC_ANA_CON8 (MT6325_PMIC_REG_BASE + 0x0D00) |
| 702 | #define MT6325_AUDENC_ANA_CON9 (MT6325_PMIC_REG_BASE + 0x0D02) |
| 703 | #define MT6325_AUDENC_ANA_CON11 (MT6325_PMIC_REG_BASE + 0x0D04) |
| 704 | #define MT6325_AUDENC_ANA_CON12 (MT6325_PMIC_REG_BASE + 0x0D06) |
| 705 | #define MT6325_AUDENC_ANA_CON13 (MT6325_PMIC_REG_BASE + 0x0D08) |
| 706 | #define MT6325_AUDENC_ANA_CON14 (MT6325_PMIC_REG_BASE + 0x0D0A) |
| 707 | #define MT6325_AUDENC_ANA_CON15 (MT6325_PMIC_REG_BASE + 0x0D0C) |
| 708 | #define MT6325_AUDNCP_CLKDIV_CON0 (MT6325_PMIC_REG_BASE + 0x0D0E) |
| 709 | #define MT6325_AUDNCP_CLKDIV_CON1 (MT6325_PMIC_REG_BASE + 0x0D10) |
| 710 | #define MT6325_AUDNCP_CLKDIV_CON2 (MT6325_PMIC_REG_BASE + 0x0D12) |
| 711 | #define MT6325_AUDNCP_CLKDIV_CON3 (MT6325_PMIC_REG_BASE + 0x0D14) |
| 712 | #define MT6325_AUDNCP_CLKDIV_CON4 (MT6325_PMIC_REG_BASE + 0x0D16) |
| 713 | #define MT6325_AUXADC_RSV0 (MT6325_PMIC_REG_BASE + 0x0E00) |
| 714 | #define MT6325_AUXADC_STA0 (MT6325_PMIC_REG_BASE + 0x0E02) |
| 715 | #define MT6325_AUXADC_STA1 (MT6325_PMIC_REG_BASE + 0x0E04) |
| 716 | #define MT6325_AUXADC_RQST0 (MT6325_PMIC_REG_BASE + 0x0E06) |
| 717 | #define MT6325_AUXADC_RQST0_SET (MT6325_PMIC_REG_BASE + 0x0E08) |
| 718 | #define MT6325_AUXADC_RQST0_CLR (MT6325_PMIC_REG_BASE + 0x0E0A) |
| 719 | #define MT6325_AUXADC_RQST1 (MT6325_PMIC_REG_BASE + 0x0E0C) |
| 720 | #define MT6325_AUXADC_RQST1_SET (MT6325_PMIC_REG_BASE + 0x0E0E) |
| 721 | #define MT6325_AUXADC_RQST1_CLR (MT6325_PMIC_REG_BASE + 0x0E10) |
| 722 | #define MT6325_AUXADC_CK0 (MT6325_PMIC_REG_BASE + 0x0E12) |
| 723 | #define MT6325_AUXADC_THR0 (MT6325_PMIC_REG_BASE + 0x0E14) |
| 724 | #define MT6325_AUXADC_THR1 (MT6325_PMIC_REG_BASE + 0x0E16) |
| 725 | #define MT6325_AUXADC_THR2 (MT6325_PMIC_REG_BASE + 0x0E18) |
| 726 | #define MT6325_AUXADC_THR3 (MT6325_PMIC_REG_BASE + 0x0E1A) |
| 727 | #define MT6325_AUXADC_THR4 (MT6325_PMIC_REG_BASE + 0x0E1C) |
| 728 | #define MT6325_AUXADC_THR5 (MT6325_PMIC_REG_BASE + 0x0E1E) |
| 729 | #define MT6325_AUXADC_THR6 (MT6325_PMIC_REG_BASE + 0x0E20) |
| 730 | #define MT6325_AUXADC_THR7 (MT6325_PMIC_REG_BASE + 0x0E22) |
| 731 | #define MT6325_AUXADC_DBG0 (MT6325_PMIC_REG_BASE + 0x0E24) |
| 732 | #define MT6325_AUXADC_AUTORPT0 (MT6325_PMIC_REG_BASE + 0x0E26) |
| 733 | #define MT6325_AUXADC_IMP0 (MT6325_PMIC_REG_BASE + 0x0E28) |
| 734 | #define MT6325_AUXADC_VISMPS0_1 (MT6325_PMIC_REG_BASE + 0x0E2A) |
| 735 | #define MT6325_AUXADC_VISMPS0_2 (MT6325_PMIC_REG_BASE + 0x0E2C) |
| 736 | #define MT6325_AUXADC_VISMPS0_3 (MT6325_PMIC_REG_BASE + 0x0E2E) |
| 737 | #define MT6325_AUXADC_VISMPS0_4 (MT6325_PMIC_REG_BASE + 0x0E30) |
| 738 | #define MT6325_AUXADC_VISMPS0_5 (MT6325_PMIC_REG_BASE + 0x0E32) |
| 739 | #define MT6325_AUXADC_VISMPS0_6 (MT6325_PMIC_REG_BASE + 0x0E34) |
| 740 | #define MT6325_AUXADC_VISMPS0_7 (MT6325_PMIC_REG_BASE + 0x0E36) |
| 741 | #define MT6325_AUXADC_LBAT2_1 (MT6325_PMIC_REG_BASE + 0x0E38) |
| 742 | #define MT6325_AUXADC_LBAT2_2 (MT6325_PMIC_REG_BASE + 0x0E3A) |
| 743 | #define MT6325_AUXADC_LBAT2_3 (MT6325_PMIC_REG_BASE + 0x0E3C) |
| 744 | #define MT6325_AUXADC_LBAT2_4 (MT6325_PMIC_REG_BASE + 0x0E3E) |
| 745 | #define MT6325_AUXADC_LBAT2_5 (MT6325_PMIC_REG_BASE + 0x0E40) |
| 746 | #define MT6325_AUXADC_LBAT2_6 (MT6325_PMIC_REG_BASE + 0x0E42) |
| 747 | #define MT6325_AUXADC_LBAT2_7 (MT6325_PMIC_REG_BASE + 0x0E44) |
| 748 | #define MT6325_AUXADC_ADC0 (MT6325_PMIC_REG_BASE + 0x0E46) |
| 749 | #define MT6325_AUXADC_ADC1 (MT6325_PMIC_REG_BASE + 0x0E48) |
| 750 | #define MT6325_AUXADC_ADC2 (MT6325_PMIC_REG_BASE + 0x0E4A) |
| 751 | #define MT6325_AUXADC_ADC3 (MT6325_PMIC_REG_BASE + 0x0E4C) |
| 752 | #define MT6325_AUXADC_ADC4 (MT6325_PMIC_REG_BASE + 0x0E4E) |
| 753 | #define MT6325_AUXADC_ADC5 (MT6325_PMIC_REG_BASE + 0x0E50) |
| 754 | #define MT6325_AUXADC_ADC6 (MT6325_PMIC_REG_BASE + 0x0E52) |
| 755 | #define MT6325_AUXADC_ADC7 (MT6325_PMIC_REG_BASE + 0x0E54) |
| 756 | #define MT6325_AUXADC_ADC8 (MT6325_PMIC_REG_BASE + 0x0E56) |
| 757 | #define MT6325_AUXADC_ADC9 (MT6325_PMIC_REG_BASE + 0x0E58) |
| 758 | #define MT6325_AUXADC_ADC10 (MT6325_PMIC_REG_BASE + 0x0E5A) |
| 759 | #define MT6325_AUXADC_ADC11 (MT6325_PMIC_REG_BASE + 0x0E5C) |
| 760 | #define MT6325_AUXADC_ADC12 (MT6325_PMIC_REG_BASE + 0x0E5E) |
| 761 | #define MT6325_AUXADC_ADC13 (MT6325_PMIC_REG_BASE + 0x0E60) |
| 762 | #define MT6325_AUXADC_ADC14 (MT6325_PMIC_REG_BASE + 0x0E62) |
| 763 | #define MT6325_AUXADC_ADC15 (MT6325_PMIC_REG_BASE + 0x0E64) |
| 764 | #define MT6325_AUXADC_ADC16 (MT6325_PMIC_REG_BASE + 0x0E66) |
| 765 | #define MT6325_AUXADC_ADC17 (MT6325_PMIC_REG_BASE + 0x0E68) |
| 766 | #define MT6325_AUXADC_ADC18 (MT6325_PMIC_REG_BASE + 0x0E6A) |
| 767 | #define MT6325_AUXADC_ADC19 (MT6325_PMIC_REG_BASE + 0x0E6C) |
| 768 | #define MT6325_AUXADC_ADC20 (MT6325_PMIC_REG_BASE + 0x0E6E) |
| 769 | #define MT6325_AUXADC_ADC21 (MT6325_PMIC_REG_BASE + 0x0E70) |
| 770 | #define MT6325_AUXADC_ADC22 (MT6325_PMIC_REG_BASE + 0x0E72) |
| 771 | #define MT6325_AUXADC_ADC23 (MT6325_PMIC_REG_BASE + 0x0E74) |
| 772 | #define MT6325_AUXADC_ADC24 (MT6325_PMIC_REG_BASE + 0x0E76) |
| 773 | #define MT6325_AUXADC_ADC25 (MT6325_PMIC_REG_BASE + 0x0E78) |
| 774 | #define MT6325_AUXADC_ADC26 (MT6325_PMIC_REG_BASE + 0x0E7A) |
| 775 | #define MT6325_AUXADC_ADC27 (MT6325_PMIC_REG_BASE + 0x0E7C) |
| 776 | #define MT6325_AUXADC_ADC28 (MT6325_PMIC_REG_BASE + 0x0E7E) |
| 777 | #define MT6325_AUXADC_ADC29 (MT6325_PMIC_REG_BASE + 0x0E80) |
| 778 | #define MT6325_AUXADC_ADC30 (MT6325_PMIC_REG_BASE + 0x0E82) |
| 779 | #define MT6325_AUXADC_RSV1 (MT6325_PMIC_REG_BASE + 0x0E84) |
| 780 | #define MT6325_AUXADC_RSV2 (MT6325_PMIC_REG_BASE + 0x0E86) |
| 781 | #define MT6325_AUXADC_CON0 (MT6325_PMIC_REG_BASE + 0x0E88) |
| 782 | #define MT6325_AUXADC_CON1 (MT6325_PMIC_REG_BASE + 0x0E8A) |
| 783 | #define MT6325_AUXADC_CON2 (MT6325_PMIC_REG_BASE + 0x0E8C) |
| 784 | #define MT6325_AUXADC_CON3 (MT6325_PMIC_REG_BASE + 0x0E8E) |
| 785 | #define MT6325_AUXADC_CON4 (MT6325_PMIC_REG_BASE + 0x0E90) |
| 786 | #define MT6325_AUXADC_CON5 (MT6325_PMIC_REG_BASE + 0x0E92) |
| 787 | #define MT6325_AUXADC_CON6 (MT6325_PMIC_REG_BASE + 0x0E94) |
| 788 | #define MT6325_AUXADC_CON7 (MT6325_PMIC_REG_BASE + 0x0E96) |
| 789 | #define MT6325_AUXADC_CON8 (MT6325_PMIC_REG_BASE + 0x0E98) |
| 790 | #define MT6325_AUXADC_CON9 (MT6325_PMIC_REG_BASE + 0x0E9A) |
| 791 | #define MT6325_AUXADC_CON10 (MT6325_PMIC_REG_BASE + 0x0E9C) |
| 792 | #define MT6325_AUXADC_CON11 (MT6325_PMIC_REG_BASE + 0x0E9E) |
| 793 | #define MT6325_AUXADC_CON12 (MT6325_PMIC_REG_BASE + 0x0EA0) |
| 794 | #define MT6325_AUXADC_CON13 (MT6325_PMIC_REG_BASE + 0x0EA2) |
| 795 | #define MT6325_AUXADC_CON14 (MT6325_PMIC_REG_BASE + 0x0EA4) |
| 796 | #define MT6325_AUXADC_CON15 (MT6325_PMIC_REG_BASE + 0x0EA6) |
| 797 | #define MT6325_AUXADC_CON16 (MT6325_PMIC_REG_BASE + 0x0EA8) |
| 798 | #define MT6325_AUXADC_CON17 (MT6325_PMIC_REG_BASE + 0x0EAA) |
| 799 | #define MT6325_AUXADC_CON18 (MT6325_PMIC_REG_BASE + 0x0EAC) |
| 800 | #define MT6325_AUXADC_CON19 (MT6325_PMIC_REG_BASE + 0x0EAE) |
| 801 | #define MT6325_AUXADC_CON20 (MT6325_PMIC_REG_BASE + 0x0EB0) |
| 802 | #define MT6325_AUXADC_CON21 (MT6325_PMIC_REG_BASE + 0x0EB2) |
| 803 | #define MT6325_AUXADC_CON22 (MT6325_PMIC_REG_BASE + 0x0EB4) |
| 804 | #define MT6325_AUXADC_CON23 (MT6325_PMIC_REG_BASE + 0x0EB6) |
| 805 | #define MT6325_AUXADC_CON24 (MT6325_PMIC_REG_BASE + 0x0EB8) |
| 806 | #define MT6325_AUXADC_CON25 (MT6325_PMIC_REG_BASE + 0x0EBA) |
| 807 | #define MT6325_AUXADC_CON26 (MT6325_PMIC_REG_BASE + 0x0EBC) |
| 808 | #define MT6325_AUXADC_CON27 (MT6325_PMIC_REG_BASE + 0x0EBE) |
| 809 | #define MT6325_ACCDET_CON0 (MT6325_PMIC_REG_BASE + 0x0EC0) |
| 810 | #define MT6325_ACCDET_CON1 (MT6325_PMIC_REG_BASE + 0x0EC2) |
| 811 | #define MT6325_ACCDET_CON2 (MT6325_PMIC_REG_BASE + 0x0EC4) |
| 812 | #define MT6325_ACCDET_CON3 (MT6325_PMIC_REG_BASE + 0x0EC6) |
| 813 | #define MT6325_ACCDET_CON4 (MT6325_PMIC_REG_BASE + 0x0EC8) |
| 814 | #define MT6325_ACCDET_CON5 (MT6325_PMIC_REG_BASE + 0x0ECA) |
| 815 | #define MT6325_ACCDET_CON6 (MT6325_PMIC_REG_BASE + 0x0ECC) |
| 816 | #define MT6325_ACCDET_CON7 (MT6325_PMIC_REG_BASE + 0x0ECE) |
| 817 | #define MT6325_ACCDET_CON8 (MT6325_PMIC_REG_BASE + 0x0ED0) |
| 818 | #define MT6325_ACCDET_CON9 (MT6325_PMIC_REG_BASE + 0x0ED2) |
| 819 | #define MT6325_ACCDET_CON10 (MT6325_PMIC_REG_BASE + 0x0ED4) |
| 820 | #define MT6325_ACCDET_CON11 (MT6325_PMIC_REG_BASE + 0x0ED6) |
| 821 | #define MT6325_ACCDET_CON12 (MT6325_PMIC_REG_BASE + 0x0ED8) |
| 822 | #define MT6325_ACCDET_CON13 (MT6325_PMIC_REG_BASE + 0x0EDA) |
| 823 | #define MT6325_ACCDET_CON14 (MT6325_PMIC_REG_BASE + 0x0EDC) |
| 824 | #define MT6325_ACCDET_CON15 (MT6325_PMIC_REG_BASE + 0x0EDE) |
| 825 | #define MT6325_ACCDET_CON16 (MT6325_PMIC_REG_BASE + 0x0EE0) |
| 826 | #define MT6325_ACCDET_CON17 (MT6325_PMIC_REG_BASE + 0x0EE2) |
| 827 | #define MT6325_ACCDET_CON18 (MT6325_PMIC_REG_BASE + 0x0EE4) |
| 828 | #define MT6325_ACCDET_CON19 (MT6325_PMIC_REG_BASE + 0x0EE6) |
| 829 | #define MT6325_ACCDET_CON20 (MT6325_PMIC_REG_BASE + 0x0EE8) |
| 830 | #define MT6325_ACCDET_CON21 (MT6325_PMIC_REG_BASE + 0x0EEA) |
| 831 | #define MT6325_ACCDET_CON22 (MT6325_PMIC_REG_BASE + 0x0EEC) |
| 832 | #define MT6325_ACCDET_CON23 (MT6325_PMIC_REG_BASE + 0x0EEE) |
| 833 | #define MT6325_ACCDET_CON24 (MT6325_PMIC_REG_BASE + 0x0EF0) |
| 834 | #define MT6325_CHR_CON0 (MT6325_PMIC_REG_BASE + 0x0EF2) |
| 835 | #define MT6325_CHR_CON1 (MT6325_PMIC_REG_BASE + 0x0EF4) |
| 836 | #define MT6325_CHR_CON2 (MT6325_PMIC_REG_BASE + 0x0EF6) |
| 837 | #define MT6325_CHR_CON3 (MT6325_PMIC_REG_BASE + 0x0EF8) |
| 838 | #define MT6325_CHR_CON4 (MT6325_PMIC_REG_BASE + 0x0EFA) |
| 839 | #define MT6325_CHR_CON5 (MT6325_PMIC_REG_BASE + 0x0EFC) |
| 840 | #define MT6325_CHR_CON6 (MT6325_PMIC_REG_BASE + 0x0EFE) |
| 841 | #define MT6325_CHR_CON7 (MT6325_PMIC_REG_BASE + 0x0F00) |
| 842 | #define MT6325_CHR_CON8 (MT6325_PMIC_REG_BASE + 0x0F02) |
| 843 | #define MT6325_CHR_CON9 (MT6325_PMIC_REG_BASE + 0x0F04) |
| 844 | #define MT6325_CHR_CON10 (MT6325_PMIC_REG_BASE + 0x0F06) |
| 845 | #define MT6325_CHR_CON11 (MT6325_PMIC_REG_BASE + 0x0F08) |
| 846 | #define MT6325_CHR_CON12 (MT6325_PMIC_REG_BASE + 0x0F0A) |
| 847 | #define MT6325_CHR_CON13 (MT6325_PMIC_REG_BASE + 0x0F0C) |
| 848 | #define MT6325_CHR_CON14 (MT6325_PMIC_REG_BASE + 0x0F0E) |
| 849 | #define MT6325_CHR_CON15 (MT6325_PMIC_REG_BASE + 0x0F10) |
| 850 | #define MT6325_CHR_CON16 (MT6325_PMIC_REG_BASE + 0x0F12) |
| 851 | #define MT6325_CHR_CON17 (MT6325_PMIC_REG_BASE + 0x0F14) |
| 852 | #define MT6325_CHR_CON18 (MT6325_PMIC_REG_BASE + 0x0F16) |
| 853 | #define MT6325_CHR_CON19 (MT6325_PMIC_REG_BASE + 0x0F18) |
| 854 | #define MT6325_CHR_CON20 (MT6325_PMIC_REG_BASE + 0x0F1A) |
| 855 | #define MT6325_CHR_CON21 (MT6325_PMIC_REG_BASE + 0x0F1C) |
| 856 | #define MT6325_CHR_CON22 (MT6325_PMIC_REG_BASE + 0x0F1E) |
| 857 | #define MT6325_CHR_CON23 (MT6325_PMIC_REG_BASE + 0x0F20) |
| 858 | #define MT6325_CHR_CON24 (MT6325_PMIC_REG_BASE + 0x0F22) |
| 859 | #define MT6325_CHR_CON25 (MT6325_PMIC_REG_BASE + 0x0F24) |
| 860 | #define MT6325_CHR_CON26 (MT6325_PMIC_REG_BASE + 0x0F26) |
| 861 | #define MT6325_CHR_CON27 (MT6325_PMIC_REG_BASE + 0x0F28) |
| 862 | #define MT6325_CHR_CON28 (MT6325_PMIC_REG_BASE + 0x0F2A) |
| 863 | #define MT6325_CHR_CON29 (MT6325_PMIC_REG_BASE + 0x0F2C) |
| 864 | #define MT6325_CHR_CON30 (MT6325_PMIC_REG_BASE + 0x0F2E) |
| 865 | #define MT6325_CHR_CON31 (MT6325_PMIC_REG_BASE + 0x0F30) |
| 866 | #define MT6325_CHR_CON32 (MT6325_PMIC_REG_BASE + 0x0F32) |
| 867 | #define MT6325_CHR_CON33 (MT6325_PMIC_REG_BASE + 0x0F34) |
| 868 | #define MT6325_CHR_CON34 (MT6325_PMIC_REG_BASE + 0x0F36) |
| 869 | #define MT6325_CHR_CON35 (MT6325_PMIC_REG_BASE + 0x0F38) |
| 870 | #define MT6325_CHR_CON36 (MT6325_PMIC_REG_BASE + 0x0F3A) |
| 871 | #define MT6325_CHR_CON37 (MT6325_PMIC_REG_BASE + 0x0F3C) |
| 872 | #define MT6325_CHR_CON38 (MT6325_PMIC_REG_BASE + 0x0F3E) |
| 873 | #define MT6325_CHR_CON39 (MT6325_PMIC_REG_BASE + 0x0F40) |
| 874 | #define MT6325_CHR_CON40 (MT6325_PMIC_REG_BASE + 0x0F42) |
| 875 | #define MT6325_CHR_CON41 (MT6325_PMIC_REG_BASE + 0x0F44) |
| 876 | #define MT6325_EOSC_CALI_CON0 (MT6325_PMIC_REG_BASE + 0x0F46) |
| 877 | #define MT6325_EOSC_CALI_CON1 (MT6325_PMIC_REG_BASE + 0x0F48) |
| 878 | // mask is HEX; shift is Integer |
| 879 | #define MT6325_THR_DET_DIS_MASK 0x1 |
| 880 | #define MT6325_THR_DET_DIS_SHIFT 0 |
| 881 | #define MT6325_RG_THR_TMODE_MASK 0x1 |
| 882 | #define MT6325_RG_THR_TMODE_SHIFT 1 |
| 883 | #define MT6325_RG_THR_TEMP_SEL_MASK 0x1 |
| 884 | #define MT6325_RG_THR_TEMP_SEL_SHIFT 2 |
| 885 | #define MT6325_RG_STRUP_THR_SEL_MASK 0x3 |
| 886 | #define MT6325_RG_STRUP_THR_SEL_SHIFT 3 |
| 887 | #define MT6325_THR_HWPDN_EN_MASK 0x1 |
| 888 | #define MT6325_THR_HWPDN_EN_SHIFT 5 |
| 889 | #define MT6325_RG_THRDET_SEL_MASK 0x1 |
| 890 | #define MT6325_RG_THRDET_SEL_SHIFT 6 |
| 891 | #define MT6325_RG_STRUP_IREF_TRIM_MASK 0x1F |
| 892 | #define MT6325_RG_STRUP_IREF_TRIM_SHIFT 0 |
| 893 | #define MT6325_RG_USBDL_EN_MASK 0x1 |
| 894 | #define MT6325_RG_USBDL_EN_SHIFT 0 |
| 895 | #define MT6325_RG_FCHR_KEYDET_EN_MASK 0x1 |
| 896 | #define MT6325_RG_FCHR_KEYDET_EN_SHIFT 1 |
| 897 | #define MT6325_RG_FCHR_PU_EN_MASK 0x1 |
| 898 | #define MT6325_RG_FCHR_PU_EN_SHIFT 2 |
| 899 | #define MT6325_RG_EN_DRVSEL_MASK 0x1 |
| 900 | #define MT6325_RG_EN_DRVSEL_SHIFT 4 |
| 901 | #define MT6325_RG_RSTB_DRV_SEL_MASK 0x1 |
| 902 | #define MT6325_RG_RSTB_DRV_SEL_SHIFT 5 |
| 903 | #define MT6325_RG_VREF_BG_MASK 0x7 |
| 904 | #define MT6325_RG_VREF_BG_SHIFT 12 |
| 905 | #define MT6325_RG_PMU_RSV_MASK 0xF |
| 906 | #define MT6325_RG_PMU_RSV_SHIFT 0 |
| 907 | #define MT6325_THR_TEST_MASK 0x3 |
| 908 | #define MT6325_THR_TEST_SHIFT 0 |
| 909 | #define MT6325_PMU_THR_DEB_MASK 0x7 |
| 910 | #define MT6325_PMU_THR_DEB_SHIFT 4 |
| 911 | #define MT6325_PMU_THR_STATUS_MASK 0x7 |
| 912 | #define MT6325_PMU_THR_STATUS_SHIFT 8 |
| 913 | #define MT6325_DDUVLO_DEB_EN_MASK 0x1 |
| 914 | #define MT6325_DDUVLO_DEB_EN_SHIFT 0 |
| 915 | #define MT6325_PWRBB_DEB_EN_MASK 0x1 |
| 916 | #define MT6325_PWRBB_DEB_EN_SHIFT 1 |
| 917 | #define MT6325_STRUP_OSC_EN_MASK 0x1 |
| 918 | #define MT6325_STRUP_OSC_EN_SHIFT 2 |
| 919 | #define MT6325_STRUP_OSC_EN_SEL_MASK 0x1 |
| 920 | #define MT6325_STRUP_OSC_EN_SEL_SHIFT 3 |
| 921 | #define MT6325_STRUP_FT_CTRL_MASK 0x3 |
| 922 | #define MT6325_STRUP_FT_CTRL_SHIFT 4 |
| 923 | #define MT6325_STRUP_PWRON_FORCE_MASK 0x1 |
| 924 | #define MT6325_STRUP_PWRON_FORCE_SHIFT 6 |
| 925 | #define MT6325_BIAS_GEN_EN_FORCE_MASK 0x1 |
| 926 | #define MT6325_BIAS_GEN_EN_FORCE_SHIFT 7 |
| 927 | #define MT6325_STRUP_PWRON_MASK 0x1 |
| 928 | #define MT6325_STRUP_PWRON_SHIFT 8 |
| 929 | #define MT6325_STRUP_PWRON_SEL_MASK 0x1 |
| 930 | #define MT6325_STRUP_PWRON_SEL_SHIFT 9 |
| 931 | #define MT6325_BIAS_GEN_EN_MASK 0x1 |
| 932 | #define MT6325_BIAS_GEN_EN_SHIFT 10 |
| 933 | #define MT6325_BIAS_GEN_EN_SEL_MASK 0x1 |
| 934 | #define MT6325_BIAS_GEN_EN_SEL_SHIFT 11 |
| 935 | #define MT6325_RTC_XOSC32_ENB_SW_MASK 0x1 |
| 936 | #define MT6325_RTC_XOSC32_ENB_SW_SHIFT 12 |
| 937 | #define MT6325_RTC_XOSC32_ENB_SEL_MASK 0x1 |
| 938 | #define MT6325_RTC_XOSC32_ENB_SEL_SHIFT 13 |
| 939 | #define MT6325_STRUP_DIG_IO_PG_FORCE_MASK 0x1 |
| 940 | #define MT6325_STRUP_DIG_IO_PG_FORCE_SHIFT 15 |
| 941 | #define MT6325_VDVFS11_PG_H2L_EN_MASK 0x1 |
| 942 | #define MT6325_VDVFS11_PG_H2L_EN_SHIFT 0 |
| 943 | #define MT6325_VDVFS12_PG_H2L_EN_MASK 0x1 |
| 944 | #define MT6325_VDVFS12_PG_H2L_EN_SHIFT 1 |
| 945 | #define MT6325_VCORE1_PG_H2L_EN_MASK 0x1 |
| 946 | #define MT6325_VCORE1_PG_H2L_EN_SHIFT 4 |
| 947 | #define MT6325_VCORE2_PG_H2L_EN_MASK 0x1 |
| 948 | #define MT6325_VCORE2_PG_H2L_EN_SHIFT 5 |
| 949 | #define MT6325_VGPU_PG_H2L_EN_MASK 0x1 |
| 950 | #define MT6325_VGPU_PG_H2L_EN_SHIFT 6 |
| 951 | #define MT6325_VIO18_PG_H2L_EN_MASK 0x1 |
| 952 | #define MT6325_VIO18_PG_H2L_EN_SHIFT 7 |
| 953 | #define MT6325_VAUD28_PG_H2L_EN_MASK 0x1 |
| 954 | #define MT6325_VAUD28_PG_H2L_EN_SHIFT 8 |
| 955 | #define MT6325_VTCXO_PG_H2L_EN_MASK 0x1 |
| 956 | #define MT6325_VTCXO_PG_H2L_EN_SHIFT 9 |
| 957 | #define MT6325_VUSB_PG_H2L_EN_MASK 0x1 |
| 958 | #define MT6325_VUSB_PG_H2L_EN_SHIFT 10 |
| 959 | #define MT6325_VSRAM_DVFS1_PG_H2L_EN_MASK 0x1 |
| 960 | #define MT6325_VSRAM_DVFS1_PG_H2L_EN_SHIFT 11 |
| 961 | #define MT6325_VIO28_PG_H2L_EN_MASK 0x1 |
| 962 | #define MT6325_VIO28_PG_H2L_EN_SHIFT 12 |
| 963 | #define MT6325_VDRAM_PG_H2L_EN_MASK 0x1 |
| 964 | #define MT6325_VDRAM_PG_H2L_EN_SHIFT 13 |
| 965 | #define MT6325_VDVFS11_PG_ENB_MASK 0x1 |
| 966 | #define MT6325_VDVFS11_PG_ENB_SHIFT 0 |
| 967 | #define MT6325_VDVFS12_PG_ENB_MASK 0x1 |
| 968 | #define MT6325_VDVFS12_PG_ENB_SHIFT 1 |
| 969 | #define MT6325_VCORE1_PG_ENB_MASK 0x1 |
| 970 | #define MT6325_VCORE1_PG_ENB_SHIFT 4 |
| 971 | #define MT6325_VCORE2_PG_ENB_MASK 0x1 |
| 972 | #define MT6325_VCORE2_PG_ENB_SHIFT 5 |
| 973 | #define MT6325_VGPU_PG_ENB_MASK 0x1 |
| 974 | #define MT6325_VGPU_PG_ENB_SHIFT 6 |
| 975 | #define MT6325_VIO18_PG_ENB_MASK 0x1 |
| 976 | #define MT6325_VIO18_PG_ENB_SHIFT 7 |
| 977 | #define MT6325_VAUD28_PG_ENB_MASK 0x1 |
| 978 | #define MT6325_VAUD28_PG_ENB_SHIFT 8 |
| 979 | #define MT6325_VTCXO_PG_ENB_MASK 0x1 |
| 980 | #define MT6325_VTCXO_PG_ENB_SHIFT 9 |
| 981 | #define MT6325_VUSB_PG_ENB_MASK 0x1 |
| 982 | #define MT6325_VUSB_PG_ENB_SHIFT 10 |
| 983 | #define MT6325_VSRAM_DVFS1_PG_ENB_MASK 0x1 |
| 984 | #define MT6325_VSRAM_DVFS1_PG_ENB_SHIFT 11 |
| 985 | #define MT6325_VIO28_PG_ENB_MASK 0x1 |
| 986 | #define MT6325_VIO28_PG_ENB_SHIFT 12 |
| 987 | #define MT6325_VDRAM_PG_ENB_MASK 0x1 |
| 988 | #define MT6325_VDRAM_PG_ENB_SHIFT 13 |
| 989 | #define MT6325_RG_EXT_PMIC_EN_PG_ENB_MASK 0x1 |
| 990 | #define MT6325_RG_EXT_PMIC_EN_PG_ENB_SHIFT 14 |
| 991 | #define MT6325_CLR_JUST_RST_MASK 0x1 |
| 992 | #define MT6325_CLR_JUST_RST_SHIFT 4 |
| 993 | #define MT6325_UVLO_L2H_DEB_EN_MASK 0x1 |
| 994 | #define MT6325_UVLO_L2H_DEB_EN_SHIFT 5 |
| 995 | #define MT6325_JUST_PWRKEY_RST_MASK 0x1 |
| 996 | #define MT6325_JUST_PWRKEY_RST_SHIFT 14 |
| 997 | #define MT6325_QI_OSC_EN_MASK 0x1 |
| 998 | #define MT6325_QI_OSC_EN_SHIFT 15 |
| 999 | #define MT6325_STRUP_EXT_PMIC_EN_MASK 0x1 |
| 1000 | #define MT6325_STRUP_EXT_PMIC_EN_SHIFT 0 |
| 1001 | #define MT6325_STRUP_EXT_PMIC_SEL_MASK 0x1 |
| 1002 | #define MT6325_STRUP_EXT_PMIC_SEL_SHIFT 1 |
| 1003 | #define MT6325_STRUP_CON8_RSV0_MASK 0x7F |
| 1004 | #define MT6325_STRUP_CON8_RSV0_SHIFT 8 |
| 1005 | #define MT6325_QI_EXT_PMIC_EN_MASK 0x1 |
| 1006 | #define MT6325_QI_EXT_PMIC_EN_SHIFT 15 |
| 1007 | #define MT6325_STRUP_AUXADC_START_SW_MASK 0x1 |
| 1008 | #define MT6325_STRUP_AUXADC_START_SW_SHIFT 4 |
| 1009 | #define MT6325_STRUP_AUXADC_RSTB_SW_MASK 0x1 |
| 1010 | #define MT6325_STRUP_AUXADC_RSTB_SW_SHIFT 5 |
| 1011 | #define MT6325_STRUP_AUXADC_START_SEL_MASK 0x1 |
| 1012 | #define MT6325_STRUP_AUXADC_START_SEL_SHIFT 6 |
| 1013 | #define MT6325_STRUP_AUXADC_RSTB_SEL_MASK 0x1 |
| 1014 | #define MT6325_STRUP_AUXADC_RSTB_SEL_SHIFT 7 |
| 1015 | #define MT6325_STRUP_PWROFF_SEQ_EN_MASK 0x1 |
| 1016 | #define MT6325_STRUP_PWROFF_SEQ_EN_SHIFT 0 |
| 1017 | #define MT6325_STRUP_PWROFF_PREOFF_EN_MASK 0x1 |
| 1018 | #define MT6325_STRUP_PWROFF_PREOFF_EN_SHIFT 1 |
| 1019 | #define MT6325_STRUP_PP_EN_MASK 0x1 |
| 1020 | #define MT6325_STRUP_PP_EN_SHIFT 0 |
| 1021 | #define MT6325_STRUP_PP_EN_SEL_MASK 0x1 |
| 1022 | #define MT6325_STRUP_PP_EN_SEL_SHIFT 1 |
| 1023 | #define MT6325_STRUP_DIG0_RSV0_MASK 0xF |
| 1024 | #define MT6325_STRUP_DIG0_RSV0_SHIFT 2 |
| 1025 | #define MT6325_STRUP_DIG1_RSV0_MASK 0x1F |
| 1026 | #define MT6325_STRUP_DIG1_RSV0_SHIFT 6 |
| 1027 | #define MT6325_RG_UVLO_VTHL_RSV0_MASK 0x1F |
| 1028 | #define MT6325_RG_UVLO_VTHL_RSV0_SHIFT 11 |
| 1029 | #define MT6325_RG_BGR_RSV6_MASK 0x1 |
| 1030 | #define MT6325_RG_BGR_RSV6_SHIFT 0 |
| 1031 | #define MT6325_RG_BGR_RSV5_MASK 0x1 |
| 1032 | #define MT6325_RG_BGR_RSV5_SHIFT 1 |
| 1033 | #define MT6325_RG_BGR_RSV4_MASK 0x1F |
| 1034 | #define MT6325_RG_BGR_RSV4_SHIFT 5 |
| 1035 | #define MT6325_RG_BGR_RSV3_MASK 0x1 |
| 1036 | #define MT6325_RG_BGR_RSV3_SHIFT 10 |
| 1037 | #define MT6325_RG_BGR_RSV2_MASK 0x7 |
| 1038 | #define MT6325_RG_BGR_RSV2_SHIFT 11 |
| 1039 | #define MT6325_RG_BGR_RSV1_MASK 0x1 |
| 1040 | #define MT6325_RG_BGR_RSV1_SHIFT 14 |
| 1041 | #define MT6325_RG_BGR_RSV0_MASK 0x1 |
| 1042 | #define MT6325_RG_BGR_RSV0_SHIFT 15 |
| 1043 | #define MT6325_RG_STRUP_RSV_MASK 0xFF |
| 1044 | #define MT6325_RG_STRUP_RSV_SHIFT 0 |
| 1045 | #define MT6325_RG_EN_SMT_MASK 0x1 |
| 1046 | #define MT6325_RG_EN_SMT_SHIFT 0 |
| 1047 | #define MT6325_RG_EN_SR_MASK 0x1 |
| 1048 | #define MT6325_RG_EN_SR_SHIFT 1 |
| 1049 | #define MT6325_RG_EN_E8_MASK 0x1 |
| 1050 | #define MT6325_RG_EN_E8_SHIFT 2 |
| 1051 | #define MT6325_RG_EN_E4_MASK 0x1 |
| 1052 | #define MT6325_RG_EN_E4_SHIFT 3 |
| 1053 | #define MT6325_RG_TESTMODE_SWEN_MASK 0x1 |
| 1054 | #define MT6325_RG_TESTMODE_SWEN_SHIFT 11 |
| 1055 | #define MT6325_STRUP_DIG0_RSV1_MASK 0xF |
| 1056 | #define MT6325_STRUP_DIG0_RSV1_SHIFT 12 |
| 1057 | #define MT6325_RG_RSV_SWREG_MASK 0xFFFF |
| 1058 | #define MT6325_RG_RSV_SWREG_SHIFT 0 |
| 1059 | #define MT6325_STRUP_PG_STATUS_MASK 0x1 |
| 1060 | #define MT6325_STRUP_PG_STATUS_SHIFT 0 |
| 1061 | #define MT6325_USBDL_MASK 0x1 |
| 1062 | #define MT6325_USBDL_SHIFT 1 |
| 1063 | #define MT6325_STRUP_PG_STATUS_CLR_MASK 0x1 |
| 1064 | #define MT6325_STRUP_PG_STATUS_CLR_SHIFT 15 |
| 1065 | #define MT6325_STRUP_PP_EN_PWROFF_CNT_MASK 0x3FF |
| 1066 | #define MT6325_STRUP_PP_EN_PWROFF_CNT_SHIFT 0 |
| 1067 | #define MT6325_STRUP_DIG0_RSV2_MASK 0x3F |
| 1068 | #define MT6325_STRUP_DIG0_RSV2_SHIFT 10 |
| 1069 | #define MT6325_STRUP_UVLO_U1U2_SEL_MASK 0x1 |
| 1070 | #define MT6325_STRUP_UVLO_U1U2_SEL_SHIFT 0 |
| 1071 | #define MT6325_STRUP_UVLO_U1U2_SEL_SWCTRL_MASK 0x1 |
| 1072 | #define MT6325_STRUP_UVLO_U1U2_SEL_SWCTRL_SHIFT 1 |
| 1073 | #define MT6325_STRUP_LBAT_INT_SEL_CLR_MASK 0x1 |
| 1074 | #define MT6325_STRUP_LBAT_INT_SEL_CLR_SHIFT 2 |
| 1075 | #define MT6325_STRUP_LBAT_INT_SEL_SWCTRL_MASK 0x1 |
| 1076 | #define MT6325_STRUP_LBAT_INT_SEL_SWCTRL_SHIFT 3 |
| 1077 | #define MT6325_STRUP_LBAT_INT_SEL_MASK 0x1 |
| 1078 | #define MT6325_STRUP_LBAT_INT_SEL_SHIFT 4 |
| 1079 | #define MT6325_STRUP_LBAT_IRQ_SET_MASK 0x1 |
| 1080 | #define MT6325_STRUP_LBAT_IRQ_SET_SHIFT 0 |
| 1081 | #define MT6325_STRUP_LBAT_IRQ_CLR_MASK 0x1 |
| 1082 | #define MT6325_STRUP_LBAT_IRQ_CLR_SHIFT 1 |
| 1083 | #define MT6325_STRUP_LBAT_IRQ_SWCTRL_MASK 0x1 |
| 1084 | #define MT6325_STRUP_LBAT_IRQ_SWCTRL_SHIFT 2 |
| 1085 | #define MT6325_RG_UVLO_VSYS_DEB_75K_RPCNT_MAX_MASK 0xF |
| 1086 | #define MT6325_RG_UVLO_VSYS_DEB_75K_RPCNT_MAX_SHIFT 0 |
| 1087 | #define MT6325_RG_UVLO_VSYS_DEB_2M_RPCNT_MAX_MASK 0xF |
| 1088 | #define MT6325_RG_UVLO_VSYS_DEB_2M_RPCNT_MAX_SHIFT 4 |
| 1089 | #define MT6325_STRUP_AUXADC_RPCNT_MAX_MASK 0x7F |
| 1090 | #define MT6325_STRUP_AUXADC_RPCNT_MAX_SHIFT 0 |
| 1091 | #define MT6325_RG_RST_DRVSEL_MASK 0x1 |
| 1092 | #define MT6325_RG_RST_DRVSEL_SHIFT 12 |
| 1093 | #define MT6325_HWCID_MASK 0xFFFF |
| 1094 | #define MT6325_HWCID_SHIFT 0 |
| 1095 | #define MT6325_SWCID_MASK 0xFFFF |
| 1096 | #define MT6325_SWCID_SHIFT 0 |
| 1097 | #define MT6325_RG_SRCLKEN_IN0_EN_MASK 0x1 |
| 1098 | #define MT6325_RG_SRCLKEN_IN0_EN_SHIFT 0 |
| 1099 | #define MT6325_RG_SRCLKEN_IN1_EN_MASK 0x1 |
| 1100 | #define MT6325_RG_SRCLKEN_IN1_EN_SHIFT 1 |
| 1101 | #define MT6325_RG_OSC_SEL_MASK 0x1 |
| 1102 | #define MT6325_RG_OSC_SEL_SHIFT 2 |
| 1103 | #define MT6325_RG_SRCLKEN_IN0_HW_MODE_MASK 0x1 |
| 1104 | #define MT6325_RG_SRCLKEN_IN0_HW_MODE_SHIFT 4 |
| 1105 | #define MT6325_RG_SRCLKEN_IN1_HW_MODE_MASK 0x1 |
| 1106 | #define MT6325_RG_SRCLKEN_IN1_HW_MODE_SHIFT 5 |
| 1107 | #define MT6325_RG_OSC_SEL_HW_MODE_MASK 0x1 |
| 1108 | #define MT6325_RG_OSC_SEL_HW_MODE_SHIFT 6 |
| 1109 | #define MT6325_RG_SRCLKEN_IN_SYNC_EN_MASK 0x1 |
| 1110 | #define MT6325_RG_SRCLKEN_IN_SYNC_EN_SHIFT 8 |
| 1111 | #define MT6325_RG_OSC_EN_AUTO_OFF_MASK 0x1 |
| 1112 | #define MT6325_RG_OSC_EN_AUTO_OFF_SHIFT 9 |
| 1113 | #define MT6325_TEST_OUT_MASK 0xFF |
| 1114 | #define MT6325_TEST_OUT_SHIFT 0 |
| 1115 | #define MT6325_RG_MON_FLAG_SEL_MASK 0xFF |
| 1116 | #define MT6325_RG_MON_FLAG_SEL_SHIFT 0 |
| 1117 | #define MT6325_RG_MON_GRP_SEL_MASK 0x1F |
| 1118 | #define MT6325_RG_MON_GRP_SEL_SHIFT 8 |
| 1119 | #define MT6325_RG_NANDTREE_MODE_MASK 0x1 |
| 1120 | #define MT6325_RG_NANDTREE_MODE_SHIFT 0 |
| 1121 | #define MT6325_RG_TEST_AUXADC_MASK 0x1 |
| 1122 | #define MT6325_RG_TEST_AUXADC_SHIFT 1 |
| 1123 | #define MT6325_RG_EFUSE_MODE_MASK 0x1 |
| 1124 | #define MT6325_RG_EFUSE_MODE_SHIFT 2 |
| 1125 | #define MT6325_RG_TEST_STRUP_MASK 0x1 |
| 1126 | #define MT6325_RG_TEST_STRUP_SHIFT 3 |
| 1127 | #define MT6325_TESTMODE_SW_MASK 0x1 |
| 1128 | #define MT6325_TESTMODE_SW_SHIFT 0 |
| 1129 | #define MT6325_EN_STATUS_VDVFS11_MASK 0x1 |
| 1130 | #define MT6325_EN_STATUS_VDVFS11_SHIFT 0 |
| 1131 | #define MT6325_EN_STATUS_VDVFS12_MASK 0x1 |
| 1132 | #define MT6325_EN_STATUS_VDVFS12_SHIFT 1 |
| 1133 | #define MT6325_EN_STATUS_VDRAM_MASK 0x1 |
| 1134 | #define MT6325_EN_STATUS_VDRAM_SHIFT 2 |
| 1135 | #define MT6325_EN_STATUS_VRF18_0_MASK 0x1 |
| 1136 | #define MT6325_EN_STATUS_VRF18_0_SHIFT 3 |
| 1137 | #define MT6325_EN_STATUS_VGPU_MASK 0x1 |
| 1138 | #define MT6325_EN_STATUS_VGPU_SHIFT 4 |
| 1139 | #define MT6325_EN_STATUS_VCORE1_MASK 0x1 |
| 1140 | #define MT6325_EN_STATUS_VCORE1_SHIFT 5 |
| 1141 | #define MT6325_EN_STATUS_VCORE2_MASK 0x1 |
| 1142 | #define MT6325_EN_STATUS_VCORE2_SHIFT 6 |
| 1143 | #define MT6325_EN_STATUS_VIO18_MASK 0x1 |
| 1144 | #define MT6325_EN_STATUS_VIO18_SHIFT 7 |
| 1145 | #define MT6325_EN_STATUS_VPA_MASK 0x1 |
| 1146 | #define MT6325_EN_STATUS_VPA_SHIFT 8 |
| 1147 | #define MT6325_EN_STATUS_VRTC_MASK 0x1 |
| 1148 | #define MT6325_EN_STATUS_VRTC_SHIFT 9 |
| 1149 | #define MT6325_EN_STATUS_VTCXO0_MASK 0x1 |
| 1150 | #define MT6325_EN_STATUS_VTCXO0_SHIFT 10 |
| 1151 | #define MT6325_EN_STATUS_VTCXO1_MASK 0x1 |
| 1152 | #define MT6325_EN_STATUS_VTCXO1_SHIFT 11 |
| 1153 | #define MT6325_EN_STATUS_VAUD28_MASK 0x1 |
| 1154 | #define MT6325_EN_STATUS_VAUD28_SHIFT 12 |
| 1155 | #define MT6325_EN_STATUS_VAUXA28_MASK 0x1 |
| 1156 | #define MT6325_EN_STATUS_VAUXA28_SHIFT 13 |
| 1157 | #define MT6325_EN_STATUS_VCAMA_MASK 0x1 |
| 1158 | #define MT6325_EN_STATUS_VCAMA_SHIFT 14 |
| 1159 | #define MT6325_EN_STATUS_VIO28_MASK 0x1 |
| 1160 | #define MT6325_EN_STATUS_VIO28_SHIFT 15 |
| 1161 | #define MT6325_EN_STATUS_VCAM_AF_MASK 0x1 |
| 1162 | #define MT6325_EN_STATUS_VCAM_AF_SHIFT 0 |
| 1163 | #define MT6325_EN_STATUS_VMC_MASK 0x1 |
| 1164 | #define MT6325_EN_STATUS_VMC_SHIFT 1 |
| 1165 | #define MT6325_EN_STATUS_VMCH_MASK 0x1 |
| 1166 | #define MT6325_EN_STATUS_VMCH_SHIFT 2 |
| 1167 | #define MT6325_EN_STATUS_VEMC33_MASK 0x1 |
| 1168 | #define MT6325_EN_STATUS_VEMC33_SHIFT 3 |
| 1169 | #define MT6325_EN_STATUS_VGP1_MASK 0x1 |
| 1170 | #define MT6325_EN_STATUS_VGP1_SHIFT 4 |
| 1171 | #define MT6325_EN_STATUS_VEFUSE_MASK 0x1 |
| 1172 | #define MT6325_EN_STATUS_VEFUSE_SHIFT 5 |
| 1173 | #define MT6325_EN_STATUS_VSIM1_MASK 0x1 |
| 1174 | #define MT6325_EN_STATUS_VSIM1_SHIFT 6 |
| 1175 | #define MT6325_EN_STATUS_VSIM2_MASK 0x1 |
| 1176 | #define MT6325_EN_STATUS_VSIM2_SHIFT 7 |
| 1177 | #define MT6325_EN_STATUS_VCN28_MASK 0x1 |
| 1178 | #define MT6325_EN_STATUS_VCN28_SHIFT 8 |
| 1179 | #define MT6325_EN_STATUS_VMIPI_MASK 0x1 |
| 1180 | #define MT6325_EN_STATUS_VMIPI_SHIFT 9 |
| 1181 | #define MT6325_EN_STATUS_VIBR_MASK 0x1 |
| 1182 | #define MT6325_EN_STATUS_VIBR_SHIFT 10 |
| 1183 | #define MT6325_EN_STATUS_VCAMD_MASK 0x1 |
| 1184 | #define MT6325_EN_STATUS_VCAMD_SHIFT 11 |
| 1185 | #define MT6325_EN_STATUS_VUSB33_MASK 0x1 |
| 1186 | #define MT6325_EN_STATUS_VUSB33_SHIFT 12 |
| 1187 | #define MT6325_EN_STATUS_VCAM_IO_MASK 0x1 |
| 1188 | #define MT6325_EN_STATUS_VCAM_IO_SHIFT 13 |
| 1189 | #define MT6325_EN_STATUS_VSRAM_DVFS1_MASK 0x1 |
| 1190 | #define MT6325_EN_STATUS_VSRAM_DVFS1_SHIFT 14 |
| 1191 | #define MT6325_EN_STATUS_VGP2_MASK 0x1 |
| 1192 | #define MT6325_EN_STATUS_VGP2_SHIFT 15 |
| 1193 | #define MT6325_EN_STATUS_VGP3_MASK 0x1 |
| 1194 | #define MT6325_EN_STATUS_VGP3_SHIFT 0 |
| 1195 | #define MT6325_EN_STATUS_VBIASN_MASK 0x1 |
| 1196 | #define MT6325_EN_STATUS_VBIASN_SHIFT 1 |
| 1197 | #define MT6325_EN_STATUS_VCN33_MASK 0x1 |
| 1198 | #define MT6325_EN_STATUS_VCN33_SHIFT 2 |
| 1199 | #define MT6325_EN_STATUS_VCN18_MASK 0x1 |
| 1200 | #define MT6325_EN_STATUS_VCN18_SHIFT 3 |
| 1201 | #define MT6325_EN_STATUS_VRF18_1_MASK 0x1 |
| 1202 | #define MT6325_EN_STATUS_VRF18_1_SHIFT 4 |
| 1203 | #define MT6325_OC_STATUS_VDVFS11_MASK 0x1 |
| 1204 | #define MT6325_OC_STATUS_VDVFS11_SHIFT 0 |
| 1205 | #define MT6325_OC_STATUS_VDVFS12_MASK 0x1 |
| 1206 | #define MT6325_OC_STATUS_VDVFS12_SHIFT 1 |
| 1207 | #define MT6325_OC_STATUS_VDRAM_MASK 0x1 |
| 1208 | #define MT6325_OC_STATUS_VDRAM_SHIFT 2 |
| 1209 | #define MT6325_OC_STATUS_VRF18_0_MASK 0x1 |
| 1210 | #define MT6325_OC_STATUS_VRF18_0_SHIFT 3 |
| 1211 | #define MT6325_OC_STATUS_VGPU_MASK 0x1 |
| 1212 | #define MT6325_OC_STATUS_VGPU_SHIFT 4 |
| 1213 | #define MT6325_OC_STATUS_VCORE1_MASK 0x1 |
| 1214 | #define MT6325_OC_STATUS_VCORE1_SHIFT 5 |
| 1215 | #define MT6325_OC_STATUS_VCORE2_MASK 0x1 |
| 1216 | #define MT6325_OC_STATUS_VCORE2_SHIFT 6 |
| 1217 | #define MT6325_OC_STATUS_VIO18_MASK 0x1 |
| 1218 | #define MT6325_OC_STATUS_VIO18_SHIFT 7 |
| 1219 | #define MT6325_OC_STATUS_VPA_MASK 0x1 |
| 1220 | #define MT6325_OC_STATUS_VPA_SHIFT 8 |
| 1221 | #define MT6325_OC_STATUS_VTCXO0_MASK 0x1 |
| 1222 | #define MT6325_OC_STATUS_VTCXO0_SHIFT 9 |
| 1223 | #define MT6325_OC_STATUS_VTCXO1_MASK 0x1 |
| 1224 | #define MT6325_OC_STATUS_VTCXO1_SHIFT 10 |
| 1225 | #define MT6325_OC_STATUS_VAUD28_MASK 0x1 |
| 1226 | #define MT6325_OC_STATUS_VAUD28_SHIFT 11 |
| 1227 | #define MT6325_OC_STATUS_VAUXA28_MASK 0x1 |
| 1228 | #define MT6325_OC_STATUS_VAUXA28_SHIFT 12 |
| 1229 | #define MT6325_OC_STATUS_VCAMA_MASK 0x1 |
| 1230 | #define MT6325_OC_STATUS_VCAMA_SHIFT 13 |
| 1231 | #define MT6325_OC_STATUS_VIO28_MASK 0x1 |
| 1232 | #define MT6325_OC_STATUS_VIO28_SHIFT 14 |
| 1233 | #define MT6325_OC_STATUS_VCAM_AF_MASK 0x1 |
| 1234 | #define MT6325_OC_STATUS_VCAM_AF_SHIFT 15 |
| 1235 | #define MT6325_OC_STATUS_VMC_MASK 0x1 |
| 1236 | #define MT6325_OC_STATUS_VMC_SHIFT 0 |
| 1237 | #define MT6325_OC_STATUS_VMCH_MASK 0x1 |
| 1238 | #define MT6325_OC_STATUS_VMCH_SHIFT 1 |
| 1239 | #define MT6325_OC_STATUS_VEMC33_MASK 0x1 |
| 1240 | #define MT6325_OC_STATUS_VEMC33_SHIFT 2 |
| 1241 | #define MT6325_OC_STATUS_VGP1_MASK 0x1 |
| 1242 | #define MT6325_OC_STATUS_VGP1_SHIFT 3 |
| 1243 | #define MT6325_OC_STATUS_VEFUSE_MASK 0x1 |
| 1244 | #define MT6325_OC_STATUS_VEFUSE_SHIFT 4 |
| 1245 | #define MT6325_OC_STATUS_VSIM1_MASK 0x1 |
| 1246 | #define MT6325_OC_STATUS_VSIM1_SHIFT 5 |
| 1247 | #define MT6325_OC_STATUS_VSIM2_MASK 0x1 |
| 1248 | #define MT6325_OC_STATUS_VSIM2_SHIFT 6 |
| 1249 | #define MT6325_OC_STATUS_VCN28_MASK 0x1 |
| 1250 | #define MT6325_OC_STATUS_VCN28_SHIFT 7 |
| 1251 | #define MT6325_OC_STATUS_VMIPI_MASK 0x1 |
| 1252 | #define MT6325_OC_STATUS_VMIPI_SHIFT 8 |
| 1253 | #define MT6325_OC_STATUS_VIBR_MASK 0x1 |
| 1254 | #define MT6325_OC_STATUS_VIBR_SHIFT 10 |
| 1255 | #define MT6325_OC_STATUS_VCAMD_MASK 0x1 |
| 1256 | #define MT6325_OC_STATUS_VCAMD_SHIFT 11 |
| 1257 | #define MT6325_OC_STATUS_VUSB33_MASK 0x1 |
| 1258 | #define MT6325_OC_STATUS_VUSB33_SHIFT 12 |
| 1259 | #define MT6325_OC_STATUS_VCAM_IO_MASK 0x1 |
| 1260 | #define MT6325_OC_STATUS_VCAM_IO_SHIFT 13 |
| 1261 | #define MT6325_OC_STATUS_VSRAM_DVFS1_MASK 0x1 |
| 1262 | #define MT6325_OC_STATUS_VSRAM_DVFS1_SHIFT 14 |
| 1263 | #define MT6325_OC_STATUS_VBIASN_MASK 0x1 |
| 1264 | #define MT6325_OC_STATUS_VBIASN_SHIFT 15 |
| 1265 | #define MT6325_OC_STATUS_VGP2_MASK 0x1 |
| 1266 | #define MT6325_OC_STATUS_VGP2_SHIFT 0 |
| 1267 | #define MT6325_OC_STATUS_VGP3_MASK 0x1 |
| 1268 | #define MT6325_OC_STATUS_VGP3_SHIFT 1 |
| 1269 | #define MT6325_OC_STATUS_VCN33_MASK 0x1 |
| 1270 | #define MT6325_OC_STATUS_VCN33_SHIFT 2 |
| 1271 | #define MT6325_OC_STATUS_VCN18_MASK 0x1 |
| 1272 | #define MT6325_OC_STATUS_VCN18_SHIFT 3 |
| 1273 | #define MT6325_OC_STATUS_VRF18_1_MASK 0x1 |
| 1274 | #define MT6325_OC_STATUS_VRF18_1_SHIFT 4 |
| 1275 | #define MT6325_VTCXO_PG_DEB_MASK 0x1 |
| 1276 | #define MT6325_VTCXO_PG_DEB_SHIFT 3 |
| 1277 | #define MT6325_VAUD28_PG_DEB_MASK 0x1 |
| 1278 | #define MT6325_VAUD28_PG_DEB_SHIFT 4 |
| 1279 | #define MT6325_VSRAM_DVFS1_PG_DEB_MASK 0x1 |
| 1280 | #define MT6325_VSRAM_DVFS1_PG_DEB_SHIFT 5 |
| 1281 | #define MT6325_VIO28_PG_DEB_MASK 0x1 |
| 1282 | #define MT6325_VIO28_PG_DEB_SHIFT 6 |
| 1283 | #define MT6325_VIO18_PG_DEB_MASK 0x1 |
| 1284 | #define MT6325_VIO18_PG_DEB_SHIFT 8 |
| 1285 | #define MT6325_VCORE2_PG_DEB_MASK 0x1 |
| 1286 | #define MT6325_VCORE2_PG_DEB_SHIFT 9 |
| 1287 | #define MT6325_VCORE1_PG_DEB_MASK 0x1 |
| 1288 | #define MT6325_VCORE1_PG_DEB_SHIFT 10 |
| 1289 | #define MT6325_VGPU_PG_DEB_MASK 0x1 |
| 1290 | #define MT6325_VGPU_PG_DEB_SHIFT 11 |
| 1291 | #define MT6325_VUSB_PG_DEB_MASK 0x1 |
| 1292 | #define MT6325_VUSB_PG_DEB_SHIFT 12 |
| 1293 | #define MT6325_VDRAM_PG_DEB_MASK 0x1 |
| 1294 | #define MT6325_VDRAM_PG_DEB_SHIFT 13 |
| 1295 | #define MT6325_VDVFS12_PG_DEB_MASK 0x1 |
| 1296 | #define MT6325_VDVFS12_PG_DEB_SHIFT 14 |
| 1297 | #define MT6325_VDVFS11_PG_DEB_MASK 0x1 |
| 1298 | #define MT6325_VDVFS11_PG_DEB_SHIFT 15 |
| 1299 | #define MT6325_PMU_TEST_MODE_SCAN_MASK 0x1 |
| 1300 | #define MT6325_PMU_TEST_MODE_SCAN_SHIFT 0 |
| 1301 | #define MT6325_PWRKEY_DEB_MASK 0x1 |
| 1302 | #define MT6325_PWRKEY_DEB_SHIFT 1 |
| 1303 | #define MT6325_HOMEKEY_DEB_MASK 0x1 |
| 1304 | #define MT6325_HOMEKEY_DEB_SHIFT 2 |
| 1305 | #define MT6325_RTC_XTAL_DET_DONE_MASK 0x1 |
| 1306 | #define MT6325_RTC_XTAL_DET_DONE_SHIFT 6 |
| 1307 | #define MT6325_XOSC32_ENB_DET_MASK 0x1 |
| 1308 | #define MT6325_XOSC32_ENB_DET_SHIFT 7 |
| 1309 | #define MT6325_RTC_XTAL_DET_RSV_MASK 0xF |
| 1310 | #define MT6325_RTC_XTAL_DET_RSV_SHIFT 8 |
| 1311 | #define MT6325_RG_PMU_TDSEL_MASK 0x1 |
| 1312 | #define MT6325_RG_PMU_TDSEL_SHIFT 0 |
| 1313 | #define MT6325_RG_SPI_TDSEL_MASK 0x1 |
| 1314 | #define MT6325_RG_SPI_TDSEL_SHIFT 1 |
| 1315 | #define MT6325_RG_AUD_TDSEL_MASK 0x1 |
| 1316 | #define MT6325_RG_AUD_TDSEL_SHIFT 2 |
| 1317 | #define MT6325_RG_E32CAL_TDSEL_MASK 0x1 |
| 1318 | #define MT6325_RG_E32CAL_TDSEL_SHIFT 3 |
| 1319 | #define MT6325_RG_PMU_RDSEL_MASK 0x1 |
| 1320 | #define MT6325_RG_PMU_RDSEL_SHIFT 0 |
| 1321 | #define MT6325_RG_SPI_RDSEL_MASK 0x1 |
| 1322 | #define MT6325_RG_SPI_RDSEL_SHIFT 1 |
| 1323 | #define MT6325_RG_AUD_RDSEL_MASK 0x1 |
| 1324 | #define MT6325_RG_AUD_RDSEL_SHIFT 2 |
| 1325 | #define MT6325_RG_E32CAL_RDSEL_MASK 0x1 |
| 1326 | #define MT6325_RG_E32CAL_RDSEL_SHIFT 3 |
| 1327 | #define MT6325_RG_SMT_WDTRSTB_IN_MASK 0x1 |
| 1328 | #define MT6325_RG_SMT_WDTRSTB_IN_SHIFT 0 |
| 1329 | #define MT6325_RG_SMT_HOMEKEY_MASK 0x1 |
| 1330 | #define MT6325_RG_SMT_HOMEKEY_SHIFT 1 |
| 1331 | #define MT6325_RG_SMT_SRCLKEN_IN0_MASK 0x1 |
| 1332 | #define MT6325_RG_SMT_SRCLKEN_IN0_SHIFT 2 |
| 1333 | #define MT6325_RG_SMT_SRCLKEN_IN1_MASK 0x1 |
| 1334 | #define MT6325_RG_SMT_SRCLKEN_IN1_SHIFT 3 |
| 1335 | #define MT6325_RG_SMT_RTC_32K1V8_0_MASK 0x1 |
| 1336 | #define MT6325_RG_SMT_RTC_32K1V8_0_SHIFT 4 |
| 1337 | #define MT6325_RG_SMT_RTC_32K1V8_1_MASK 0x1 |
| 1338 | #define MT6325_RG_SMT_RTC_32K1V8_1_SHIFT 5 |
| 1339 | #define MT6325_RG_SMT_SPI_CLK_MASK 0x1 |
| 1340 | #define MT6325_RG_SMT_SPI_CLK_SHIFT 0 |
| 1341 | #define MT6325_RG_SMT_SPI_CSN_MASK 0x1 |
| 1342 | #define MT6325_RG_SMT_SPI_CSN_SHIFT 1 |
| 1343 | #define MT6325_RG_SMT_SPI_MOSI_MASK 0x1 |
| 1344 | #define MT6325_RG_SMT_SPI_MOSI_SHIFT 2 |
| 1345 | #define MT6325_RG_SMT_SPI_MISO_MASK 0x1 |
| 1346 | #define MT6325_RG_SMT_SPI_MISO_SHIFT 3 |
| 1347 | #define MT6325_RG_SMT_AUD_CLK_MASK 0x1 |
| 1348 | #define MT6325_RG_SMT_AUD_CLK_SHIFT 0 |
| 1349 | #define MT6325_RG_SMT_AUD_DAT_MOSI_MASK 0x1 |
| 1350 | #define MT6325_RG_SMT_AUD_DAT_MOSI_SHIFT 1 |
| 1351 | #define MT6325_RG_SMT_AUD_DAT_MISO_MASK 0x1 |
| 1352 | #define MT6325_RG_SMT_AUD_DAT_MISO_SHIFT 2 |
| 1353 | #define MT6325_RG_SMT_VOICE_CLK_MISO_MASK 0x1 |
| 1354 | #define MT6325_RG_SMT_VOICE_CLK_MISO_SHIFT 3 |
| 1355 | #define MT6325_RG_SMT_ENBB_MASK 0x1 |
| 1356 | #define MT6325_RG_SMT_ENBB_SHIFT 4 |
| 1357 | #define MT6325_RG_SMT_XOSC_EN_MASK 0x1 |
| 1358 | #define MT6325_RG_SMT_XOSC_EN_SHIFT 5 |
| 1359 | #define MT6325_RG_OCTL_SRCLKEN_IN0_MASK 0xF |
| 1360 | #define MT6325_RG_OCTL_SRCLKEN_IN0_SHIFT 0 |
| 1361 | #define MT6325_RG_OCTL_SRCLKEN_IN1_MASK 0xF |
| 1362 | #define MT6325_RG_OCTL_SRCLKEN_IN1_SHIFT 4 |
| 1363 | #define MT6325_RG_OCTL_RTC_32K1V8_0_MASK 0xF |
| 1364 | #define MT6325_RG_OCTL_RTC_32K1V8_0_SHIFT 8 |
| 1365 | #define MT6325_RG_OCTL_RTC_32K1V8_1_MASK 0xF |
| 1366 | #define MT6325_RG_OCTL_RTC_32K1V8_1_SHIFT 12 |
| 1367 | #define MT6325_RG_OCTL_SPI_CLK_MASK 0xF |
| 1368 | #define MT6325_RG_OCTL_SPI_CLK_SHIFT 0 |
| 1369 | #define MT6325_RG_OCTL_SPI_CSN_MASK 0xF |
| 1370 | #define MT6325_RG_OCTL_SPI_CSN_SHIFT 4 |
| 1371 | #define MT6325_RG_OCTL_SPI_MOSI_MASK 0xF |
| 1372 | #define MT6325_RG_OCTL_SPI_MOSI_SHIFT 8 |
| 1373 | #define MT6325_RG_OCTL_SPI_MISO_MASK 0xF |
| 1374 | #define MT6325_RG_OCTL_SPI_MISO_SHIFT 12 |
| 1375 | #define MT6325_RG_OCTL_AUD_DAT_MOSI_MASK 0xF |
| 1376 | #define MT6325_RG_OCTL_AUD_DAT_MOSI_SHIFT 0 |
| 1377 | #define MT6325_RG_OCTL_AUD_DAT_MISO_MASK 0xF |
| 1378 | #define MT6325_RG_OCTL_AUD_DAT_MISO_SHIFT 4 |
| 1379 | #define MT6325_RG_OCTL_AUD_CLK_MASK 0xF |
| 1380 | #define MT6325_RG_OCTL_AUD_CLK_SHIFT 8 |
| 1381 | #define MT6325_RG_OCTL_VOICE_CLK_MISO_MASK 0xF |
| 1382 | #define MT6325_RG_OCTL_VOICE_CLK_MISO_SHIFT 12 |
| 1383 | #define MT6325_RG_OCTL_HOMEKEY_MASK 0xF |
| 1384 | #define MT6325_RG_OCTL_HOMEKEY_SHIFT 0 |
| 1385 | #define MT6325_RG_OCTL_ENBB_MASK 0xF |
| 1386 | #define MT6325_RG_OCTL_ENBB_SHIFT 4 |
| 1387 | #define MT6325_RG_OCTL_XOSC_EN_MASK 0xF |
| 1388 | #define MT6325_RG_OCTL_XOSC_EN_SHIFT 8 |
| 1389 | #define MT6325_TOP_STATUS_MASK 0xF |
| 1390 | #define MT6325_TOP_STATUS_SHIFT 0 |
| 1391 | #define MT6325_TOP_STATUS_SET_MASK 0x3 |
| 1392 | #define MT6325_TOP_STATUS_SET_SHIFT 0 |
| 1393 | #define MT6325_TOP_STATUS_CLR_MASK 0x3 |
| 1394 | #define MT6325_TOP_STATUS_CLR_SHIFT 0 |
| 1395 | #define MT6325_RGS_VDVFS11_ENPWM_STATUS_MASK 0x1 |
| 1396 | #define MT6325_RGS_VDVFS11_ENPWM_STATUS_SHIFT 0 |
| 1397 | #define MT6325_RGS_VDVFS12_ENPWM_STATUS_MASK 0x1 |
| 1398 | #define MT6325_RGS_VDVFS12_ENPWM_STATUS_SHIFT 1 |
| 1399 | #define MT6325_RGS_VGPU_ENPWM_STATUS_MASK 0x1 |
| 1400 | #define MT6325_RGS_VGPU_ENPWM_STATUS_SHIFT 2 |
| 1401 | #define MT6325_RGS_VIO18_ENPWM_STATUS_MASK 0x1 |
| 1402 | #define MT6325_RGS_VIO18_ENPWM_STATUS_SHIFT 3 |
| 1403 | #define MT6325_RGS_VCORE1_ENPWM_STATUS_MASK 0x1 |
| 1404 | #define MT6325_RGS_VCORE1_ENPWM_STATUS_SHIFT 4 |
| 1405 | #define MT6325_RGS_VCORE2_ENPWM_STATUS_MASK 0x1 |
| 1406 | #define MT6325_RGS_VCORE2_ENPWM_STATUS_SHIFT 5 |
| 1407 | #define MT6325_RGS_VRF18_0_ENPWM_STATUS_MASK 0x1 |
| 1408 | #define MT6325_RGS_VRF18_0_ENPWM_STATUS_SHIFT 6 |
| 1409 | #define MT6325_RGS_VDRAM_ENPWM_STATUS_MASK 0x1 |
| 1410 | #define MT6325_RGS_VDRAM_ENPWM_STATUS_SHIFT 7 |
| 1411 | #define MT6325_RGS_PP_EN_MASK 0x1 |
| 1412 | #define MT6325_RGS_PP_EN_SHIFT 8 |
| 1413 | #define MT6325_RGS_BC11_ID_FLOAT_MASK 0x1 |
| 1414 | #define MT6325_RGS_BC11_ID_FLOAT_SHIFT 9 |
| 1415 | #define MT6325_RGS_BC11_ID_A_MASK 0x1 |
| 1416 | #define MT6325_RGS_BC11_ID_A_SHIFT 10 |
| 1417 | #define MT6325_RGS_BC11_ID_B_MASK 0x1 |
| 1418 | #define MT6325_RGS_BC11_ID_B_SHIFT 11 |
| 1419 | #define MT6325_RGS_BC11_ID_C_MASK 0x1 |
| 1420 | #define MT6325_RGS_BC11_ID_C_SHIFT 12 |
| 1421 | #define MT6325_RGS_BC11_ID_GD_MASK 0x1 |
| 1422 | #define MT6325_RGS_BC11_ID_GD_SHIFT 13 |
| 1423 | #define MT6325_RG_G_SMPS_PD_CK_PDN_MASK 0x1 |
| 1424 | #define MT6325_RG_G_SMPS_PD_CK_PDN_SHIFT 0 |
| 1425 | #define MT6325_RG_G_SMPS_AUD_CK_PDN_MASK 0x1 |
| 1426 | #define MT6325_RG_G_SMPS_AUD_CK_PDN_SHIFT 1 |
| 1427 | #define MT6325_RG_G_DRV_2M_CK_PDN_MASK 0x1 |
| 1428 | #define MT6325_RG_G_DRV_2M_CK_PDN_SHIFT 2 |
| 1429 | #define MT6325_RG_DRV_32K_CK_PDN_MASK 0x1 |
| 1430 | #define MT6325_RG_DRV_32K_CK_PDN_SHIFT 3 |
| 1431 | #define MT6325_RG_DRV_ISINK0_CK_PDN_MASK 0x1 |
| 1432 | #define MT6325_RG_DRV_ISINK0_CK_PDN_SHIFT 4 |
| 1433 | #define MT6325_RG_DRV_ISINK1_CK_PDN_MASK 0x1 |
| 1434 | #define MT6325_RG_DRV_ISINK1_CK_PDN_SHIFT 5 |
| 1435 | #define MT6325_RG_DRV_ISINK2_CK_PDN_MASK 0x1 |
| 1436 | #define MT6325_RG_DRV_ISINK2_CK_PDN_SHIFT 6 |
| 1437 | #define MT6325_RG_DRV_ISINK3_CK_PDN_MASK 0x1 |
| 1438 | #define MT6325_RG_DRV_ISINK3_CK_PDN_SHIFT 7 |
| 1439 | #define MT6325_RG_AUXADC_1M_CK_PDN_MASK 0x1 |
| 1440 | #define MT6325_RG_AUXADC_1M_CK_PDN_SHIFT 8 |
| 1441 | #define MT6325_RG_AUXADC_CK_PDN_MASK 0x1 |
| 1442 | #define MT6325_RG_AUXADC_CK_PDN_SHIFT 9 |
| 1443 | #define MT6325_RG_AUXADC_32K_CK_PDN_MASK 0x1 |
| 1444 | #define MT6325_RG_AUXADC_32K_CK_PDN_SHIFT 10 |
| 1445 | #define MT6325_RG_AUDNCP_CK_PDN_MASK 0x1 |
| 1446 | #define MT6325_RG_AUDNCP_CK_PDN_SHIFT 11 |
| 1447 | #define MT6325_RG_AUDIF_CK_PDN_MASK 0x1 |
| 1448 | #define MT6325_RG_AUDIF_CK_PDN_SHIFT 12 |
| 1449 | #define MT6325_RG_AUD_CK_PDN_MASK 0x1 |
| 1450 | #define MT6325_RG_AUD_CK_PDN_SHIFT 13 |
| 1451 | #define MT6325_RG_ZCD13M_CK_PDN_MASK 0x1 |
| 1452 | #define MT6325_RG_ZCD13M_CK_PDN_SHIFT 14 |
| 1453 | #define MT6325_RG_VOW12M_CK_PDN_MASK 0x1 |
| 1454 | #define MT6325_RG_VOW12M_CK_PDN_SHIFT 15 |
| 1455 | #define MT6325_TOP_CKPDN_CON0_SET_MASK 0xFFFF |
| 1456 | #define MT6325_TOP_CKPDN_CON0_SET_SHIFT 0 |
| 1457 | #define MT6325_TOP_CKPDN_CON0_CLR_MASK 0xFFFF |
| 1458 | #define MT6325_TOP_CKPDN_CON0_CLR_SHIFT 0 |
| 1459 | #define MT6325_RG_RTC_32K_CK_PDN_MASK 0x1 |
| 1460 | #define MT6325_RG_RTC_32K_CK_PDN_SHIFT 0 |
| 1461 | #define MT6325_RG_RTC_MCLK_PDN_MASK 0x1 |
| 1462 | #define MT6325_RG_RTC_MCLK_PDN_SHIFT 1 |
| 1463 | #define MT6325_RG_RTC_75K_CK_PDN_MASK 0x1 |
| 1464 | #define MT6325_RG_RTC_75K_CK_PDN_SHIFT 2 |
| 1465 | #define MT6325_RG_RTCDET_CK_PDN_MASK 0x1 |
| 1466 | #define MT6325_RG_RTCDET_CK_PDN_SHIFT 3 |
| 1467 | #define MT6325_RG_RTC32K_1V8_0_O_PDN_MASK 0x1 |
| 1468 | #define MT6325_RG_RTC32K_1V8_0_O_PDN_SHIFT 4 |
| 1469 | #define MT6325_RG_RTC32K_1V8_1_O_PDN_MASK 0x1 |
| 1470 | #define MT6325_RG_RTC32K_1V8_1_O_PDN_SHIFT 5 |
| 1471 | #define MT6325_RG_RTC_2SEC_OFF_DET_PDN_MASK 0x1 |
| 1472 | #define MT6325_RG_RTC_2SEC_OFF_DET_PDN_SHIFT 6 |
| 1473 | #define MT6325_RG_FQMTR_CK_PDN_MASK 0x1 |
| 1474 | #define MT6325_RG_FQMTR_CK_PDN_SHIFT 7 |
| 1475 | #define MT6325_RG_STB_1M_CK_PDN_MASK 0x1 |
| 1476 | #define MT6325_RG_STB_1M_CK_PDN_SHIFT 8 |
| 1477 | #define MT6325_RG_BUCK_1M_CK_PDN_MASK 0x1 |
| 1478 | #define MT6325_RG_BUCK_1M_CK_PDN_SHIFT 9 |
| 1479 | #define MT6325_RG_BUCK_18M_CK_PDN_MASK 0x1 |
| 1480 | #define MT6325_RG_BUCK_18M_CK_PDN_SHIFT 10 |
| 1481 | #define MT6325_RG_PWMOC_6M_CK_PDN_MASK 0x1 |
| 1482 | #define MT6325_RG_PWMOC_6M_CK_PDN_SHIFT 11 |
| 1483 | #define MT6325_RG_STB_AUD_1M_CK_PDN_MASK 0x1 |
| 1484 | #define MT6325_RG_STB_AUD_1M_CK_PDN_SHIFT 12 |
| 1485 | #define MT6325_RG_BUCK_AUD_1M_CK_PDN_MASK 0x1 |
| 1486 | #define MT6325_RG_BUCK_AUD_1M_CK_PDN_SHIFT 13 |
| 1487 | #define MT6325_RG_BUCK_AUD_18M_CK_PDN_MASK 0x1 |
| 1488 | #define MT6325_RG_BUCK_AUD_18M_CK_PDN_SHIFT 14 |
| 1489 | #define MT6325_RG_PWMOC_AUD_6M_CK_PDN_MASK 0x1 |
| 1490 | #define MT6325_RG_PWMOC_AUD_6M_CK_PDN_SHIFT 15 |
| 1491 | #define MT6325_TOP_CKPDN_CON1_SET_MASK 0xFFFF |
| 1492 | #define MT6325_TOP_CKPDN_CON1_SET_SHIFT 0 |
| 1493 | #define MT6325_TOP_CKPDN_CON1_CLR_MASK 0xFFFF |
| 1494 | #define MT6325_TOP_CKPDN_CON1_CLR_SHIFT 0 |
| 1495 | #define MT6325_RG_SPK_CK_PDN_MASK 0x1 |
| 1496 | #define MT6325_RG_SPK_CK_PDN_SHIFT 0 |
| 1497 | #define MT6325_RG_SPK_PWM_CK_PDN_MASK 0x1 |
| 1498 | #define MT6325_RG_SPK_PWM_CK_PDN_SHIFT 1 |
| 1499 | #define MT6325_RG_FGADC_ANA_CK_PDN_MASK 0x1 |
| 1500 | #define MT6325_RG_FGADC_ANA_CK_PDN_SHIFT 2 |
| 1501 | #define MT6325_RG_FGADC_DIG_CK_PDN_MASK 0x1 |
| 1502 | #define MT6325_RG_FGADC_DIG_CK_PDN_SHIFT 3 |
| 1503 | #define MT6325_RG_BIF_X72_CK_PDN_MASK 0x1 |
| 1504 | #define MT6325_RG_BIF_X72_CK_PDN_SHIFT 4 |
| 1505 | #define MT6325_RG_BIF_X4_CK_PDN_MASK 0x1 |
| 1506 | #define MT6325_RG_BIF_X4_CK_PDN_SHIFT 5 |
| 1507 | #define MT6325_RG_BIF_X1_CK_PDN_MASK 0x1 |
| 1508 | #define MT6325_RG_BIF_X1_CK_PDN_SHIFT 6 |
| 1509 | #define MT6325_RG_PCHR_32K_CK_PDN_MASK 0x1 |
| 1510 | #define MT6325_RG_PCHR_32K_CK_PDN_SHIFT 7 |
| 1511 | #define MT6325_RG_AUD18M_CK_PDN_MASK 0x1 |
| 1512 | #define MT6325_RG_AUD18M_CK_PDN_SHIFT 8 |
| 1513 | #define MT6325_RG_ACCDET_CK_PDN_MASK 0x1 |
| 1514 | #define MT6325_RG_ACCDET_CK_PDN_SHIFT 9 |
| 1515 | #define MT6325_RG_FQMTR_32K_CK_PDN_MASK 0x1 |
| 1516 | #define MT6325_RG_FQMTR_32K_CK_PDN_SHIFT 10 |
| 1517 | #define MT6325_RG_INTRP_CK_PDN_MASK 0x1 |
| 1518 | #define MT6325_RG_INTRP_CK_PDN_SHIFT 11 |
| 1519 | #define MT6325_RG_RTC_26M_CK_PDN_MASK 0x1 |
| 1520 | #define MT6325_RG_RTC_26M_CK_PDN_SHIFT 12 |
| 1521 | #define MT6325_RG_RTC_EOSC32_CK_PDN_MASK 0x1 |
| 1522 | #define MT6325_RG_RTC_EOSC32_CK_PDN_SHIFT 13 |
| 1523 | #define MT6325_RG_TRIM_75K_CK_PDN_MASK 0x1 |
| 1524 | #define MT6325_RG_TRIM_75K_CK_PDN_SHIFT 14 |
| 1525 | #define MT6325_RG_STRUP_LBAT_SEL_CK_PDN_MASK 0x1 |
| 1526 | #define MT6325_RG_STRUP_LBAT_SEL_CK_PDN_SHIFT 15 |
| 1527 | #define MT6325_TOP_CKPDN_CON2_SET_MASK 0xFFFF |
| 1528 | #define MT6325_TOP_CKPDN_CON2_SET_SHIFT 0 |
| 1529 | #define MT6325_TOP_CKPDN_CON2_CLR_MASK 0xFFFF |
| 1530 | #define MT6325_TOP_CKPDN_CON2_CLR_SHIFT 0 |
| 1531 | #define MT6325_RG_STRUP_75K_CK_PDN_MASK 0x1 |
| 1532 | #define MT6325_RG_STRUP_75K_CK_PDN_SHIFT 0 |
| 1533 | #define MT6325_RG_STRUP_32K_CK_PDN_MASK 0x1 |
| 1534 | #define MT6325_RG_STRUP_32K_CK_PDN_SHIFT 1 |
| 1535 | #define MT6325_RG_EFUSE_CK_PDN_MASK 0x1 |
| 1536 | #define MT6325_RG_EFUSE_CK_PDN_SHIFT 2 |
| 1537 | #define MT6325_RG_SMPS_CK_DIV_PDN_MASK 0x1 |
| 1538 | #define MT6325_RG_SMPS_CK_DIV_PDN_SHIFT 3 |
| 1539 | #define MT6325_RG_SPI_CK_PDN_MASK 0x1 |
| 1540 | #define MT6325_RG_SPI_CK_PDN_SHIFT 4 |
| 1541 | #define MT6325_RG_BGR_TEST_CK_PDN_MASK 0x1 |
| 1542 | #define MT6325_RG_BGR_TEST_CK_PDN_SHIFT 5 |
| 1543 | #define MT6325_RG_FGADC_FT_CK_PDN_MASK 0x1 |
| 1544 | #define MT6325_RG_FGADC_FT_CK_PDN_SHIFT 6 |
| 1545 | #define MT6325_RG_PCHR_TEST_CK_PDN_MASK 0x1 |
| 1546 | #define MT6325_RG_PCHR_TEST_CK_PDN_SHIFT 7 |
| 1547 | #define MT6325_RG_BUCK_32K_CK_PDN_MASK 0x1 |
| 1548 | #define MT6325_RG_BUCK_32K_CK_PDN_SHIFT 8 |
| 1549 | #define MT6325_RG_BUCK_ANA_CK_PDN_MASK 0x1 |
| 1550 | #define MT6325_RG_BUCK_ANA_CK_PDN_SHIFT 9 |
| 1551 | #define MT6325_RG_EOSC_CALI_TEST_CK_PDN_MASK 0x1 |
| 1552 | #define MT6325_RG_EOSC_CALI_TEST_CK_PDN_SHIFT 10 |
| 1553 | #define MT6325_TOP_CKPDN_CON3_RSV_MASK 0x1F |
| 1554 | #define MT6325_TOP_CKPDN_CON3_RSV_SHIFT 11 |
| 1555 | #define MT6325_TOP_CKPDN_CON3_SET_MASK 0xFFFF |
| 1556 | #define MT6325_TOP_CKPDN_CON3_SET_SHIFT 0 |
| 1557 | #define MT6325_TOP_CKPDN_CON3_CLR_MASK 0xFFFF |
| 1558 | #define MT6325_TOP_CKPDN_CON3_CLR_SHIFT 0 |
| 1559 | #define MT6325_RG_AUDIF_CK_CKSEL_MASK 0x1 |
| 1560 | #define MT6325_RG_AUDIF_CK_CKSEL_SHIFT 0 |
| 1561 | #define MT6325_RG_AUD_CK_CKSEL_MASK 0x1 |
| 1562 | #define MT6325_RG_AUD_CK_CKSEL_SHIFT 1 |
| 1563 | #define MT6325_RG_DRV_ISINK0_CK_CKSEL_MASK 0x1 |
| 1564 | #define MT6325_RG_DRV_ISINK0_CK_CKSEL_SHIFT 4 |
| 1565 | #define MT6325_RG_DRV_ISINK1_CK_CKSEL_MASK 0x1 |
| 1566 | #define MT6325_RG_DRV_ISINK1_CK_CKSEL_SHIFT 5 |
| 1567 | #define MT6325_RG_DRV_ISINK2_CK_CKSEL_MASK 0x1 |
| 1568 | #define MT6325_RG_DRV_ISINK2_CK_CKSEL_SHIFT 6 |
| 1569 | #define MT6325_RG_DRV_ISINK3_CK_CKSEL_MASK 0x1 |
| 1570 | #define MT6325_RG_DRV_ISINK3_CK_CKSEL_SHIFT 7 |
| 1571 | #define MT6325_RG_FQMTR_CK_CKSEL_MASK 0x7 |
| 1572 | #define MT6325_RG_FQMTR_CK_CKSEL_SHIFT 8 |
| 1573 | #define MT6325_RG_75K_32K_SEL_MASK 0x1 |
| 1574 | #define MT6325_RG_75K_32K_SEL_SHIFT 11 |
| 1575 | #define MT6325_RG_AUXADC_CK_CKSEL_MASK 0x1 |
| 1576 | #define MT6325_RG_AUXADC_CK_CKSEL_SHIFT 12 |
| 1577 | #define MT6325_TOP_CKSEL_CON0_RSV_MASK 0x1 |
| 1578 | #define MT6325_TOP_CKSEL_CON0_RSV_SHIFT 13 |
| 1579 | #define MT6325_RG_OSC_SEL_HW_SRC_SEL_MASK 0x3 |
| 1580 | #define MT6325_RG_OSC_SEL_HW_SRC_SEL_SHIFT 14 |
| 1581 | #define MT6325_TOP_CKSEL_CON_SET_MASK 0xFFFF |
| 1582 | #define MT6325_TOP_CKSEL_CON_SET_SHIFT 0 |
| 1583 | #define MT6325_TOP_CKSEL_CON_CLR_MASK 0xFFFF |
| 1584 | #define MT6325_TOP_CKSEL_CON_CLR_SHIFT 0 |
| 1585 | #define MT6325_RG_STRUP_75K_CK_CKSEL_MASK 0x3 |
| 1586 | #define MT6325_RG_STRUP_75K_CK_CKSEL_SHIFT 0 |
| 1587 | #define MT6325_RG_BGR_TEST_CK_CKSEL_MASK 0x1 |
| 1588 | #define MT6325_RG_BGR_TEST_CK_CKSEL_SHIFT 2 |
| 1589 | #define MT6325_RG_PCHR_TEST_CK_CKSEL_MASK 0x1 |
| 1590 | #define MT6325_RG_PCHR_TEST_CK_CKSEL_SHIFT 3 |
| 1591 | #define MT6325_RG_FGADC_ANA_CK_CKSEL_MASK 0x1 |
| 1592 | #define MT6325_RG_FGADC_ANA_CK_CKSEL_SHIFT 4 |
| 1593 | #define MT6325_TOP_CKSEL_CON1_RSV_MASK 0x3 |
| 1594 | #define MT6325_TOP_CKSEL_CON1_RSV_SHIFT 8 |
| 1595 | #define MT6325_TOP_CKSEL_CON1_SET_MASK 0xFFFF |
| 1596 | #define MT6325_TOP_CKSEL_CON1_SET_SHIFT 0 |
| 1597 | #define MT6325_TOP_CKSEL_CON1_CLR_MASK 0xFFFF |
| 1598 | #define MT6325_TOP_CKSEL_CON1_CLR_SHIFT 0 |
| 1599 | #define MT6325_RG_SRCVOLTEN_SW_MASK 0x1 |
| 1600 | #define MT6325_RG_SRCVOLTEN_SW_SHIFT 0 |
| 1601 | #define MT6325_RG_VOWEN_SW_MASK 0x1 |
| 1602 | #define MT6325_RG_VOWEN_SW_SHIFT 1 |
| 1603 | #define MT6325_RG_BUCK_OSC_SEL_SW_MASK 0x1 |
| 1604 | #define MT6325_RG_BUCK_OSC_SEL_SW_SHIFT 2 |
| 1605 | #define MT6325_RG_VCORE2_OSC_SEL_SW_MASK 0x1 |
| 1606 | #define MT6325_RG_VCORE2_OSC_SEL_SW_SHIFT 3 |
| 1607 | #define MT6325_RG_SRCVOLTEN_MODE_MASK 0x1 |
| 1608 | #define MT6325_RG_SRCVOLTEN_MODE_SHIFT 4 |
| 1609 | #define MT6325_RG_VOWEN_MODE_MASK 0x1 |
| 1610 | #define MT6325_RG_VOWEN_MODE_SHIFT 5 |
| 1611 | #define MT6325_RG_BUCK_OSC_SEL_MODE_MASK 0x1 |
| 1612 | #define MT6325_RG_BUCK_OSC_SEL_MODE_SHIFT 6 |
| 1613 | #define MT6325_RG_VCORE2_OSC_SEL_MODE_MASK 0x1 |
| 1614 | #define MT6325_RG_VCORE2_OSC_SEL_MODE_SHIFT 7 |
| 1615 | #define MT6325_TOP_CKSEL_CON2_RSV_MASK 0x3 |
| 1616 | #define MT6325_TOP_CKSEL_CON2_RSV_SHIFT 8 |
| 1617 | #define MT6325_TOP_CKSEL_CON2_SET_MASK 0xFFFF |
| 1618 | #define MT6325_TOP_CKSEL_CON2_SET_SHIFT 0 |
| 1619 | #define MT6325_TOP_CKSEL_CON2_CLR_MASK 0xFFFF |
| 1620 | #define MT6325_TOP_CKSEL_CON2_CLR_SHIFT 0 |
| 1621 | #define MT6325_RG_STRUP_LBAT_SEL_CK_DIVSEL_MASK 0x3 |
| 1622 | #define MT6325_RG_STRUP_LBAT_SEL_CK_DIVSEL_SHIFT 0 |
| 1623 | #define MT6325_TOP_CKDIVSEL_CON_RSV_MASK 0x3 |
| 1624 | #define MT6325_TOP_CKDIVSEL_CON_RSV_SHIFT 2 |
| 1625 | #define MT6325_RG_BIF_X4_CK_DIVSEL_MASK 0x7 |
| 1626 | #define MT6325_RG_BIF_X4_CK_DIVSEL_SHIFT 4 |
| 1627 | #define MT6325_RG_REG_CK_DIVSEL_MASK 0x3 |
| 1628 | #define MT6325_RG_REG_CK_DIVSEL_SHIFT 8 |
| 1629 | #define MT6325_RG_BUCK_18M_CK_DIVSEL_MASK 0x1 |
| 1630 | #define MT6325_RG_BUCK_18M_CK_DIVSEL_SHIFT 10 |
| 1631 | #define MT6325_RG_AUXADC_SMPS_CK_DIVSEL_MASK 0x1 |
| 1632 | #define MT6325_RG_AUXADC_SMPS_CK_DIVSEL_SHIFT 11 |
| 1633 | #define MT6325_RG_SPK_CK_DIVSEL_MASK 0x3 |
| 1634 | #define MT6325_RG_SPK_CK_DIVSEL_SHIFT 12 |
| 1635 | #define MT6325_RG_SPK_PWM_CK_DIVSEL_MASK 0x3 |
| 1636 | #define MT6325_RG_SPK_PWM_CK_DIVSEL_SHIFT 14 |
| 1637 | #define MT6325_TOP_CKDIVSEL_CON1_SET_MASK 0xFFFF |
| 1638 | #define MT6325_TOP_CKDIVSEL_CON1_SET_SHIFT 0 |
| 1639 | #define MT6325_TOP_CKDIVSEL_CON1_CLR_MASK 0xFFFF |
| 1640 | #define MT6325_TOP_CKDIVSEL_CON1_CLR_SHIFT 0 |
| 1641 | #define MT6325_RG_G_SMPS_PD_CK_PDN_HWEN_MASK 0x1 |
| 1642 | #define MT6325_RG_G_SMPS_PD_CK_PDN_HWEN_SHIFT 0 |
| 1643 | #define MT6325_RG_G_SMPS_AUD_CK_PDN_HWEN_MASK 0x1 |
| 1644 | #define MT6325_RG_G_SMPS_AUD_CK_PDN_HWEN_SHIFT 1 |
| 1645 | #define MT6325_RG_G_DRV_2M_CK_PDN_HWEN_MASK 0x1 |
| 1646 | #define MT6325_RG_G_DRV_2M_CK_PDN_HWEN_SHIFT 2 |
| 1647 | #define MT6325_RG_AUXADC_CK_PDN_HWEN_MASK 0x1 |
| 1648 | #define MT6325_RG_AUXADC_CK_PDN_HWEN_SHIFT 3 |
| 1649 | #define MT6325_RG_BUCK_1M_CK_PDN_HWEN_MASK 0x1 |
| 1650 | #define MT6325_RG_BUCK_1M_CK_PDN_HWEN_SHIFT 4 |
| 1651 | #define MT6325_RG_BUCK_AUD_1M_CK_PDN_HWEN_MASK 0x1 |
| 1652 | #define MT6325_RG_BUCK_AUD_1M_CK_PDN_HWEN_SHIFT 5 |
| 1653 | #define MT6325_RG_EFUSE_CK_PDN_HWEN_MASK 0x1 |
| 1654 | #define MT6325_RG_EFUSE_CK_PDN_HWEN_SHIFT 6 |
| 1655 | #define MT6325_RG_RTC_26M_CK_PDN_HWEN_MASK 0x1 |
| 1656 | #define MT6325_RG_RTC_26M_CK_PDN_HWEN_SHIFT 7 |
| 1657 | #define MT6325_RG_AUD18M_CK_PDN_HWEN_MASK 0x1 |
| 1658 | #define MT6325_RG_AUD18M_CK_PDN_HWEN_SHIFT 8 |
| 1659 | #define MT6325_RG_AUXADC_SMPS_CK_DIVSEL_HWEN_MASK 0x1 |
| 1660 | #define MT6325_RG_AUXADC_SMPS_CK_DIVSEL_HWEN_SHIFT 9 |
| 1661 | #define MT6325_RG_AUXADC_CK_CKSEL_HWEN_MASK 0x1 |
| 1662 | #define MT6325_RG_AUXADC_CK_CKSEL_HWEN_SHIFT 10 |
| 1663 | #define MT6325_TOP_CKHWEN_CON_RSV_MASK 0x1F |
| 1664 | #define MT6325_TOP_CKHWEN_CON_RSV_SHIFT 11 |
| 1665 | #define MT6325_TOP_CKHWEN_CON_SET_MASK 0xFFFF |
| 1666 | #define MT6325_TOP_CKHWEN_CON_SET_SHIFT 0 |
| 1667 | #define MT6325_TOP_CKHWEN_CON_CLR_MASK 0xFFFF |
| 1668 | #define MT6325_TOP_CKHWEN_CON_CLR_SHIFT 0 |
| 1669 | #define MT6325_RG_PMU75K_CK_TST_DIS_MASK 0x1 |
| 1670 | #define MT6325_RG_PMU75K_CK_TST_DIS_SHIFT 0 |
| 1671 | #define MT6325_RG_SMPS_CK_TST_DIS_MASK 0x1 |
| 1672 | #define MT6325_RG_SMPS_CK_TST_DIS_SHIFT 1 |
| 1673 | #define MT6325_RG_AUD26M_CK_TST_DIS_MASK 0x1 |
| 1674 | #define MT6325_RG_AUD26M_CK_TST_DIS_SHIFT 2 |
| 1675 | #define MT6325_RG_VOW12M_CK_TST_DIS_MASK 0x1 |
| 1676 | #define MT6325_RG_VOW12M_CK_TST_DIS_SHIFT 3 |
| 1677 | #define MT6325_RG_RTC32K_CK_TST_DIS_MASK 0x1 |
| 1678 | #define MT6325_RG_RTC32K_CK_TST_DIS_SHIFT 4 |
| 1679 | #define MT6325_RG_SPK_CK_TST_DIS_MASK 0x1 |
| 1680 | #define MT6325_RG_SPK_CK_TST_DIS_SHIFT 5 |
| 1681 | #define MT6325_RG_FG_CK_TST_DIS_MASK 0x1 |
| 1682 | #define MT6325_RG_FG_CK_TST_DIS_SHIFT 6 |
| 1683 | #define MT6325_RG_RTC26M_CK_TST_DIS_MASK 0x1 |
| 1684 | #define MT6325_RG_RTC26M_CK_TST_DIS_SHIFT 7 |
| 1685 | #define MT6325_TOP_CKTST_CON0_RSV_MASK 0x7F |
| 1686 | #define MT6325_TOP_CKTST_CON0_RSV_SHIFT 8 |
| 1687 | #define MT6325_RG_BUCK_ANA_AUTO_OFF_DIS_MASK 0x1 |
| 1688 | #define MT6325_RG_BUCK_ANA_AUTO_OFF_DIS_SHIFT 15 |
| 1689 | #define MT6325_RG_DRV_ISINK0_CK_TSTSEL_MASK 0x1 |
| 1690 | #define MT6325_RG_DRV_ISINK0_CK_TSTSEL_SHIFT 0 |
| 1691 | #define MT6325_RG_DRV_ISINK1_CK_TSTSEL_MASK 0x1 |
| 1692 | #define MT6325_RG_DRV_ISINK1_CK_TSTSEL_SHIFT 1 |
| 1693 | #define MT6325_RG_DRV_ISINK2_CK_TSTSEL_MASK 0x1 |
| 1694 | #define MT6325_RG_DRV_ISINK2_CK_TSTSEL_SHIFT 2 |
| 1695 | #define MT6325_RG_DRV_ISINK3_CK_TSTSEL_MASK 0x1 |
| 1696 | #define MT6325_RG_DRV_ISINK3_CK_TSTSEL_SHIFT 3 |
| 1697 | #define MT6325_RG_FQMTR_CK_TSTSEL_MASK 0x1 |
| 1698 | #define MT6325_RG_FQMTR_CK_TSTSEL_SHIFT 4 |
| 1699 | #define MT6325_RG_RTCDET_CK_TSTSEL_MASK 0x1 |
| 1700 | #define MT6325_RG_RTCDET_CK_TSTSEL_SHIFT 5 |
| 1701 | #define MT6325_RG_PMU75K_CK_TSTSEL_MASK 0x1 |
| 1702 | #define MT6325_RG_PMU75K_CK_TSTSEL_SHIFT 6 |
| 1703 | #define MT6325_RG_SMPS_CK_TSTSEL_MASK 0x1 |
| 1704 | #define MT6325_RG_SMPS_CK_TSTSEL_SHIFT 7 |
| 1705 | #define MT6325_RG_AUD26M_CK_TSTSEL_MASK 0x1 |
| 1706 | #define MT6325_RG_AUD26M_CK_TSTSEL_SHIFT 8 |
| 1707 | #define MT6325_RG_VOW12M_CK_TSTSEL_MASK 0x1 |
| 1708 | #define MT6325_RG_VOW12M_CK_TSTSEL_SHIFT 9 |
| 1709 | #define MT6325_RG_AUDIF_CK_TSTSEL_MASK 0x1 |
| 1710 | #define MT6325_RG_AUDIF_CK_TSTSEL_SHIFT 10 |
| 1711 | #define MT6325_RG_AUD_CK_TSTSEL_MASK 0x1 |
| 1712 | #define MT6325_RG_AUD_CK_TSTSEL_SHIFT 11 |
| 1713 | #define MT6325_RG_STRUP_75K_CK_TSTSEL_MASK 0x1 |
| 1714 | #define MT6325_RG_STRUP_75K_CK_TSTSEL_SHIFT 12 |
| 1715 | #define MT6325_RG_RTC32K_CK_TSTSEL_MASK 0x1 |
| 1716 | #define MT6325_RG_RTC32K_CK_TSTSEL_SHIFT 13 |
| 1717 | #define MT6325_RG_PCHR_TEST_CK_TSTSEL_MASK 0x1 |
| 1718 | #define MT6325_RG_PCHR_TEST_CK_TSTSEL_SHIFT 14 |
| 1719 | #define MT6325_RG_BGR_TEST_CK_TSTSEL_MASK 0x1 |
| 1720 | #define MT6325_RG_BGR_TEST_CK_TSTSEL_SHIFT 15 |
| 1721 | #define MT6325_RG_FG_CK_TSTSEL_MASK 0x1 |
| 1722 | #define MT6325_RG_FG_CK_TSTSEL_SHIFT 0 |
| 1723 | #define MT6325_RG_FGADC_ANA_CK_TSTSEL_MASK 0x1 |
| 1724 | #define MT6325_RG_FGADC_ANA_CK_TSTSEL_SHIFT 1 |
| 1725 | #define MT6325_RG_SPK_CK_TSTSEL_MASK 0x1 |
| 1726 | #define MT6325_RG_SPK_CK_TSTSEL_SHIFT 2 |
| 1727 | #define MT6325_RG_RTC26M_CK_TSTSEL_MASK 0x1 |
| 1728 | #define MT6325_RG_RTC26M_CK_TSTSEL_SHIFT 3 |
| 1729 | #define MT6325_RG_RTC_EOSC32_CK_TSTSEL_MASK 0x1 |
| 1730 | #define MT6325_RG_RTC_EOSC32_CK_TSTSEL_SHIFT 4 |
| 1731 | #define MT6325_RG_EOSC_CALI_TEST_CK_TSTSEL_MASK 0x1 |
| 1732 | #define MT6325_RG_EOSC_CALI_TEST_CK_TSTSEL_SHIFT 5 |
| 1733 | #define MT6325_RG_AUXADC_CK_TSTSEL_MASK 0x1 |
| 1734 | #define MT6325_RG_AUXADC_CK_TSTSEL_SHIFT 6 |
| 1735 | #define MT6325_TOP_CKTST_CON2_RSV_MASK 0xF |
| 1736 | #define MT6325_TOP_CKTST_CON2_RSV_SHIFT 7 |
| 1737 | #define MT6325_RG_CLKSQ_EN_AUD_MASK 0x1 |
| 1738 | #define MT6325_RG_CLKSQ_EN_AUD_SHIFT 0 |
| 1739 | #define MT6325_RG_CLKSQ_EN_FQR_MASK 0x1 |
| 1740 | #define MT6325_RG_CLKSQ_EN_FQR_SHIFT 1 |
| 1741 | #define MT6325_RG_CLKSQ_EN_AUX_AP_MASK 0x1 |
| 1742 | #define MT6325_RG_CLKSQ_EN_AUX_AP_SHIFT 2 |
| 1743 | #define MT6325_RG_CLKSQ_EN_AUX_MD_MASK 0x1 |
| 1744 | #define MT6325_RG_CLKSQ_EN_AUX_MD_SHIFT 3 |
| 1745 | #define MT6325_RG_CLKSQ_EN_AUX_GPS_MASK 0x1 |
| 1746 | #define MT6325_RG_CLKSQ_EN_AUX_GPS_SHIFT 4 |
| 1747 | #define MT6325_RG_CLKSQ_EN_AUX_RSV_MASK 0x1 |
| 1748 | #define MT6325_RG_CLKSQ_EN_AUX_RSV_SHIFT 5 |
| 1749 | #define MT6325_RG_CLKSQ_EN_AUX_AP_MODE_MASK 0x1 |
| 1750 | #define MT6325_RG_CLKSQ_EN_AUX_AP_MODE_SHIFT 8 |
| 1751 | #define MT6325_RG_CLKSQ_EN_AUX_MD_MODE_MASK 0x1 |
| 1752 | #define MT6325_RG_CLKSQ_EN_AUX_MD_MODE_SHIFT 9 |
| 1753 | #define MT6325_TOP_CLKSQ_RSV_MASK 0x1F |
| 1754 | #define MT6325_TOP_CLKSQ_RSV_SHIFT 10 |
| 1755 | #define MT6325_DA_CLKSQ_EN_VA28_MASK 0x1 |
| 1756 | #define MT6325_DA_CLKSQ_EN_VA28_SHIFT 15 |
| 1757 | #define MT6325_TOP_CLKSQ_SET_MASK 0xFFFF |
| 1758 | #define MT6325_TOP_CLKSQ_SET_SHIFT 0 |
| 1759 | #define MT6325_TOP_CLKSQ_CLR_MASK 0xFFFF |
| 1760 | #define MT6325_TOP_CLKSQ_CLR_SHIFT 0 |
| 1761 | #define MT6325_RG_CLKSQ_RTC_EN_MASK 0x1 |
| 1762 | #define MT6325_RG_CLKSQ_RTC_EN_SHIFT 0 |
| 1763 | #define MT6325_RG_CLKSQ_RTC_EN_HW_MODE_MASK 0x1 |
| 1764 | #define MT6325_RG_CLKSQ_RTC_EN_HW_MODE_SHIFT 1 |
| 1765 | #define MT6325_TOP_CLKSQ_RTC_RSV0_MASK 0xF |
| 1766 | #define MT6325_TOP_CLKSQ_RTC_RSV0_SHIFT 2 |
| 1767 | #define MT6325_RG_ENBB_SEL_MASK 0x1 |
| 1768 | #define MT6325_RG_ENBB_SEL_SHIFT 8 |
| 1769 | #define MT6325_RG_XOSC_EN_SEL_MASK 0x1 |
| 1770 | #define MT6325_RG_XOSC_EN_SEL_SHIFT 9 |
| 1771 | #define MT6325_TOP_CLKSQ_RTC_RSV1_MASK 0x3 |
| 1772 | #define MT6325_TOP_CLKSQ_RTC_RSV1_SHIFT 10 |
| 1773 | #define MT6325_DA_CLKSQ_EN_VDIG18_MASK 0x1 |
| 1774 | #define MT6325_DA_CLKSQ_EN_VDIG18_SHIFT 15 |
| 1775 | #define MT6325_TOP_CLKSQ_RTC_SET_MASK 0xFFFF |
| 1776 | #define MT6325_TOP_CLKSQ_RTC_SET_SHIFT 0 |
| 1777 | #define MT6325_TOP_CLKSQ_RTC_CLR_MASK 0xFFFF |
| 1778 | #define MT6325_TOP_CLKSQ_RTC_CLR_SHIFT 0 |
| 1779 | #define MT6325_OSC_75K_TRIM_MASK 0x1F |
| 1780 | #define MT6325_OSC_75K_TRIM_SHIFT 0 |
| 1781 | #define MT6325_RG_OSC_75K_TRIM_EN_MASK 0x1 |
| 1782 | #define MT6325_RG_OSC_75K_TRIM_EN_SHIFT 5 |
| 1783 | #define MT6325_RG_OSC_75K_TRIM_RATE_MASK 0x3 |
| 1784 | #define MT6325_RG_OSC_75K_TRIM_RATE_SHIFT 6 |
| 1785 | #define MT6325_RG_OSC_75K_TRIM_MASK 0x1F |
| 1786 | #define MT6325_RG_OSC_75K_TRIM_SHIFT 8 |
| 1787 | #define MT6325_RG_EFUSE_MAN_RST_MASK 0x1 |
| 1788 | #define MT6325_RG_EFUSE_MAN_RST_SHIFT 0 |
| 1789 | #define MT6325_RG_AUXADC_RST_MASK 0x1 |
| 1790 | #define MT6325_RG_AUXADC_RST_SHIFT 1 |
| 1791 | #define MT6325_RG_AUXADC_REG_RST_MASK 0x1 |
| 1792 | #define MT6325_RG_AUXADC_REG_RST_SHIFT 2 |
| 1793 | #define MT6325_RG_AUDIO_RST_MASK 0x1 |
| 1794 | #define MT6325_RG_AUDIO_RST_SHIFT 3 |
| 1795 | #define MT6325_RG_ACCDET_RST_MASK 0x1 |
| 1796 | #define MT6325_RG_ACCDET_RST_SHIFT 4 |
| 1797 | #define MT6325_RG_BIF_RST_MASK 0x1 |
| 1798 | #define MT6325_RG_BIF_RST_SHIFT 5 |
| 1799 | #define MT6325_RG_DRIVER_RST_MASK 0x1 |
| 1800 | #define MT6325_RG_DRIVER_RST_SHIFT 6 |
| 1801 | #define MT6325_RG_FGADC_RST_MASK 0x1 |
| 1802 | #define MT6325_RG_FGADC_RST_SHIFT 7 |
| 1803 | #define MT6325_RG_FQMTR_RST_MASK 0x1 |
| 1804 | #define MT6325_RG_FQMTR_RST_SHIFT 8 |
| 1805 | #define MT6325_RG_RTC_RST_MASK 0x1 |
| 1806 | #define MT6325_RG_RTC_RST_SHIFT 9 |
| 1807 | #define MT6325_RG_SPK_RST_MASK 0x1 |
| 1808 | #define MT6325_RG_SPK_RST_SHIFT 10 |
| 1809 | #define MT6325_RG_CHRWDT_RST_MASK 0x1 |
| 1810 | #define MT6325_RG_CHRWDT_RST_SHIFT 11 |
| 1811 | #define MT6325_RG_ZCD_RST_MASK 0x1 |
| 1812 | #define MT6325_RG_ZCD_RST_SHIFT 12 |
| 1813 | #define MT6325_RG_AUDNCP_RST_MASK 0x1 |
| 1814 | #define MT6325_RG_AUDNCP_RST_SHIFT 13 |
| 1815 | #define MT6325_RG_CLK_TRIM_RST_MASK 0x1 |
| 1816 | #define MT6325_RG_CLK_TRIM_RST_SHIFT 14 |
| 1817 | #define MT6325_TOP_RST_CON0_RSV_MASK 0x1 |
| 1818 | #define MT6325_TOP_RST_CON0_RSV_SHIFT 15 |
| 1819 | #define MT6325_TOP_RST_CON_SET_MASK 0xFFFF |
| 1820 | #define MT6325_TOP_RST_CON_SET_SHIFT 0 |
| 1821 | #define MT6325_TOP_RST_CON_CLR_MASK 0xFFFF |
| 1822 | #define MT6325_TOP_RST_CON_CLR_SHIFT 0 |
| 1823 | #define MT6325_RG_CHR_LDO_DET_MODE_MASK 0x1 |
| 1824 | #define MT6325_RG_CHR_LDO_DET_MODE_SHIFT 0 |
| 1825 | #define MT6325_RG_CHR_LDO_DET_SW_MASK 0x1 |
| 1826 | #define MT6325_RG_CHR_LDO_DET_SW_SHIFT 1 |
| 1827 | #define MT6325_RG_CHRWDT_FLAG_MODE_MASK 0x1 |
| 1828 | #define MT6325_RG_CHRWDT_FLAG_MODE_SHIFT 2 |
| 1829 | #define MT6325_RG_CHRWDT_FLAG_SW_MASK 0x1 |
| 1830 | #define MT6325_RG_CHRWDT_FLAG_SW_SHIFT 3 |
| 1831 | #define MT6325_TOP_RST_CON1_RSV_MASK 0xF |
| 1832 | #define MT6325_TOP_RST_CON1_RSV_SHIFT 4 |
| 1833 | #define MT6325_RG_WDTRSTB_EN_MASK 0x1 |
| 1834 | #define MT6325_RG_WDTRSTB_EN_SHIFT 0 |
| 1835 | #define MT6325_RG_WDTRSTB_MODE_MASK 0x1 |
| 1836 | #define MT6325_RG_WDTRSTB_MODE_SHIFT 1 |
| 1837 | #define MT6325_WDTRSTB_STATUS_MASK 0x1 |
| 1838 | #define MT6325_WDTRSTB_STATUS_SHIFT 2 |
| 1839 | #define MT6325_WDTRSTB_STATUS_CLR_MASK 0x1 |
| 1840 | #define MT6325_WDTRSTB_STATUS_CLR_SHIFT 3 |
| 1841 | #define MT6325_RG_WDTRSTB_FB_EN_MASK 0x1 |
| 1842 | #define MT6325_RG_WDTRSTB_FB_EN_SHIFT 4 |
| 1843 | #define MT6325_RG_HOMEKEY_RST_EN_MASK 0x1 |
| 1844 | #define MT6325_RG_HOMEKEY_RST_EN_SHIFT 8 |
| 1845 | #define MT6325_RG_PWRKEY_RST_EN_MASK 0x1 |
| 1846 | #define MT6325_RG_PWRKEY_RST_EN_SHIFT 9 |
| 1847 | #define MT6325_RG_PWRRST_TMR_DIS_MASK 0x1 |
| 1848 | #define MT6325_RG_PWRRST_TMR_DIS_SHIFT 10 |
| 1849 | #define MT6325_RG_PWRKEY_RST_TD_MASK 0x3 |
| 1850 | #define MT6325_RG_PWRKEY_RST_TD_SHIFT 12 |
| 1851 | #define MT6325_TOP_RST_MISC_SET_MASK 0xFFFF |
| 1852 | #define MT6325_TOP_RST_MISC_SET_SHIFT 0 |
| 1853 | #define MT6325_TOP_RST_MISC_CLR_MASK 0xFFFF |
| 1854 | #define MT6325_TOP_RST_MISC_CLR_SHIFT 0 |
| 1855 | #define MT6325_VPWRIN_RSTB_STATUS_MASK 0x1 |
| 1856 | #define MT6325_VPWRIN_RSTB_STATUS_SHIFT 0 |
| 1857 | #define MT6325_DDLO_RSTB_STATUS_MASK 0x1 |
| 1858 | #define MT6325_DDLO_RSTB_STATUS_SHIFT 1 |
| 1859 | #define MT6325_UVLO_RSTB_STATUS_MASK 0x1 |
| 1860 | #define MT6325_UVLO_RSTB_STATUS_SHIFT 2 |
| 1861 | #define MT6325_RTC_DDLO_RSTB_STATUS_MASK 0x1 |
| 1862 | #define MT6325_RTC_DDLO_RSTB_STATUS_SHIFT 3 |
| 1863 | #define MT6325_CHRWDT_REG_RSTB_STATUS_MASK 0x1 |
| 1864 | #define MT6325_CHRWDT_REG_RSTB_STATUS_SHIFT 4 |
| 1865 | #define MT6325_CHRDET_REG_RSTB_STATUS_MASK 0x1 |
| 1866 | #define MT6325_CHRDET_REG_RSTB_STATUS_SHIFT 5 |
| 1867 | #define MT6325_TOP_RST_STATUS_RSV_MASK 0x3 |
| 1868 | #define MT6325_TOP_RST_STATUS_RSV_SHIFT 6 |
| 1869 | #define MT6325_TOP_RST_STATUS_SET_MASK 0xFFFF |
| 1870 | #define MT6325_TOP_RST_STATUS_SET_SHIFT 0 |
| 1871 | #define MT6325_TOP_RST_STATUS_CLR_MASK 0xFFFF |
| 1872 | #define MT6325_TOP_RST_STATUS_CLR_SHIFT 0 |
| 1873 | #define MT6325_RG_INT_EN_PWRKEY_MASK 0x1 |
| 1874 | #define MT6325_RG_INT_EN_PWRKEY_SHIFT 0 |
| 1875 | #define MT6325_RG_INT_EN_HOMEKEY_MASK 0x1 |
| 1876 | #define MT6325_RG_INT_EN_HOMEKEY_SHIFT 1 |
| 1877 | #define MT6325_RG_INT_EN_PWRKEY_R_MASK 0x1 |
| 1878 | #define MT6325_RG_INT_EN_PWRKEY_R_SHIFT 2 |
| 1879 | #define MT6325_RG_INT_EN_HOMEKEY_R_MASK 0x1 |
| 1880 | #define MT6325_RG_INT_EN_HOMEKEY_R_SHIFT 3 |
| 1881 | #define MT6325_RG_INT_EN_THR_H_MASK 0x1 |
| 1882 | #define MT6325_RG_INT_EN_THR_H_SHIFT 4 |
| 1883 | #define MT6325_RG_INT_EN_THR_L_MASK 0x1 |
| 1884 | #define MT6325_RG_INT_EN_THR_L_SHIFT 5 |
| 1885 | #define MT6325_RG_INT_EN_BAT_H_MASK 0x1 |
| 1886 | #define MT6325_RG_INT_EN_BAT_H_SHIFT 6 |
| 1887 | #define MT6325_RG_INT_EN_BAT_L_MASK 0x1 |
| 1888 | #define MT6325_RG_INT_EN_BAT_L_SHIFT 7 |
| 1889 | #define MT6325_RG_INT_EN_BIF_MASK 0x1 |
| 1890 | #define MT6325_RG_INT_EN_BIF_SHIFT 8 |
| 1891 | #define MT6325_RG_INT_EN_RTC_MASK 0x1 |
| 1892 | #define MT6325_RG_INT_EN_RTC_SHIFT 9 |
| 1893 | #define MT6325_RG_INT_EN_AUDIO_MASK 0x1 |
| 1894 | #define MT6325_RG_INT_EN_AUDIO_SHIFT 10 |
| 1895 | #define MT6325_RG_INT_EN_VOW_MASK 0x1 |
| 1896 | #define MT6325_RG_INT_EN_VOW_SHIFT 11 |
| 1897 | #define MT6325_RG_INT_EN_ACCDET_MASK 0x1 |
| 1898 | #define MT6325_RG_INT_EN_ACCDET_SHIFT 12 |
| 1899 | #define MT6325_RG_INT_EN_ACCDET_EINT_MASK 0x1 |
| 1900 | #define MT6325_RG_INT_EN_ACCDET_EINT_SHIFT 13 |
| 1901 | #define MT6325_RG_INT_EN_ACCDET_NEGV_MASK 0x1 |
| 1902 | #define MT6325_RG_INT_EN_ACCDET_NEGV_SHIFT 14 |
| 1903 | #define MT6325_RG_INT_EN_NI_LBAT_INT_MASK 0x1 |
| 1904 | #define MT6325_RG_INT_EN_NI_LBAT_INT_SHIFT 15 |
| 1905 | #define MT6325_INT_CON0_SET_MASK 0xFFFF |
| 1906 | #define MT6325_INT_CON0_SET_SHIFT 0 |
| 1907 | #define MT6325_INT_CON0_CLR_MASK 0xFFFF |
| 1908 | #define MT6325_INT_CON0_CLR_SHIFT 0 |
| 1909 | #define MT6325_RG_INT_EN_VDVFS11_OC_MASK 0x1 |
| 1910 | #define MT6325_RG_INT_EN_VDVFS11_OC_SHIFT 0 |
| 1911 | #define MT6325_RG_INT_EN_VDVFS12_OC_MASK 0x1 |
| 1912 | #define MT6325_RG_INT_EN_VDVFS12_OC_SHIFT 1 |
| 1913 | #define MT6325_RG_INT_EN_VRF18_0_OC_MASK 0x1 |
| 1914 | #define MT6325_RG_INT_EN_VRF18_0_OC_SHIFT 2 |
| 1915 | #define MT6325_RG_INT_EN_VDRAM_OC_MASK 0x1 |
| 1916 | #define MT6325_RG_INT_EN_VDRAM_OC_SHIFT 3 |
| 1917 | #define MT6325_RG_INT_EN_VGPU_OC_MASK 0x1 |
| 1918 | #define MT6325_RG_INT_EN_VGPU_OC_SHIFT 4 |
| 1919 | #define MT6325_RG_INT_EN_VCORE1_OC_MASK 0x1 |
| 1920 | #define MT6325_RG_INT_EN_VCORE1_OC_SHIFT 5 |
| 1921 | #define MT6325_RG_INT_EN_VCORE2_OC_MASK 0x1 |
| 1922 | #define MT6325_RG_INT_EN_VCORE2_OC_SHIFT 6 |
| 1923 | #define MT6325_RG_INT_EN_VIO18_OC_MASK 0x1 |
| 1924 | #define MT6325_RG_INT_EN_VIO18_OC_SHIFT 7 |
| 1925 | #define MT6325_RG_INT_EN_VPA_OC_MASK 0x1 |
| 1926 | #define MT6325_RG_INT_EN_VPA_OC_SHIFT 8 |
| 1927 | #define MT6325_RG_INT_EN_LDO_OC_MASK 0x1 |
| 1928 | #define MT6325_RG_INT_EN_LDO_OC_SHIFT 9 |
| 1929 | #define MT6325_RG_INT_EN_BAT2_H_MASK 0x1 |
| 1930 | #define MT6325_RG_INT_EN_BAT2_H_SHIFT 10 |
| 1931 | #define MT6325_RG_INT_EN_BAT2_L_MASK 0x1 |
| 1932 | #define MT6325_RG_INT_EN_BAT2_L_SHIFT 11 |
| 1933 | #define MT6325_RG_INT_EN_VISMPS0_H_MASK 0x1 |
| 1934 | #define MT6325_RG_INT_EN_VISMPS0_H_SHIFT 12 |
| 1935 | #define MT6325_RG_INT_EN_VISMPS0_L_MASK 0x1 |
| 1936 | #define MT6325_RG_INT_EN_VISMPS0_L_SHIFT 13 |
| 1937 | #define MT6325_RG_INT_EN_AUXADC_IMP_MASK 0x1 |
| 1938 | #define MT6325_RG_INT_EN_AUXADC_IMP_SHIFT 14 |
| 1939 | #define MT6325_INT_CON1_SET_MASK 0xFFFF |
| 1940 | #define MT6325_INT_CON1_SET_SHIFT 0 |
| 1941 | #define MT6325_INT_CON1_CLR_MASK 0xFFFF |
| 1942 | #define MT6325_INT_CON1_CLR_SHIFT 0 |
| 1943 | #define MT6325_RG_INT_EN_OV_MASK 0x1 |
| 1944 | #define MT6325_RG_INT_EN_OV_SHIFT 0 |
| 1945 | #define MT6325_RG_INT_EN_BVALID_DET_MASK 0x1 |
| 1946 | #define MT6325_RG_INT_EN_BVALID_DET_SHIFT 1 |
| 1947 | #define MT6325_RG_INT_EN_VBATON_UNDET_MASK 0x1 |
| 1948 | #define MT6325_RG_INT_EN_VBATON_UNDET_SHIFT 2 |
| 1949 | #define MT6325_RG_INT_EN_WATCHDOG_MASK 0x1 |
| 1950 | #define MT6325_RG_INT_EN_WATCHDOG_SHIFT 3 |
| 1951 | #define MT6325_RG_INT_EN_PCHR_CM_VDEC_MASK 0x1 |
| 1952 | #define MT6325_RG_INT_EN_PCHR_CM_VDEC_SHIFT 4 |
| 1953 | #define MT6325_RG_INT_EN_CHRDET_MASK 0x1 |
| 1954 | #define MT6325_RG_INT_EN_CHRDET_SHIFT 5 |
| 1955 | #define MT6325_RG_INT_EN_PCHR_CM_VINC_MASK 0x1 |
| 1956 | #define MT6325_RG_INT_EN_PCHR_CM_VINC_SHIFT 6 |
| 1957 | #define MT6325_RG_INT_EN_FG_BAT_H_MASK 0x1 |
| 1958 | #define MT6325_RG_INT_EN_FG_BAT_H_SHIFT 7 |
| 1959 | #define MT6325_RG_INT_EN_FG_BAT_L_MASK 0x1 |
| 1960 | #define MT6325_RG_INT_EN_FG_BAT_L_SHIFT 8 |
| 1961 | #define MT6325_RG_INT_EN_FG_CUR_H_MASK 0x1 |
| 1962 | #define MT6325_RG_INT_EN_FG_CUR_H_SHIFT 9 |
| 1963 | #define MT6325_RG_INT_EN_FG_CUR_L_MASK 0x1 |
| 1964 | #define MT6325_RG_INT_EN_FG_CUR_L_SHIFT 10 |
| 1965 | #define MT6325_RG_INT_EN_FG_ZCV_MASK 0x1 |
| 1966 | #define MT6325_RG_INT_EN_FG_ZCV_SHIFT 11 |
| 1967 | #define MT6325_RG_INT_EN_SPKL_D_MASK 0x1 |
| 1968 | #define MT6325_RG_INT_EN_SPKL_D_SHIFT 12 |
| 1969 | #define MT6325_RG_INT_EN_SPKL_AB_MASK 0x1 |
| 1970 | #define MT6325_RG_INT_EN_SPKL_AB_SHIFT 13 |
| 1971 | #define MT6325_INT_CON2_SET_MASK 0xFFFF |
| 1972 | #define MT6325_INT_CON2_SET_SHIFT 0 |
| 1973 | #define MT6325_INT_CON2_CLR_MASK 0xFFFF |
| 1974 | #define MT6325_INT_CON2_CLR_SHIFT 0 |
| 1975 | #define MT6325_POLARITY_MASK 0x1 |
| 1976 | #define MT6325_POLARITY_SHIFT 0 |
| 1977 | #define MT6325_RG_HOMEKEY_INT_SEL_MASK 0x1 |
| 1978 | #define MT6325_RG_HOMEKEY_INT_SEL_SHIFT 1 |
| 1979 | #define MT6325_RG_PWRKEY_INT_SEL_MASK 0x1 |
| 1980 | #define MT6325_RG_PWRKEY_INT_SEL_SHIFT 2 |
| 1981 | #define MT6325_RG_CHRDET_INT_SEL_MASK 0x1 |
| 1982 | #define MT6325_RG_CHRDET_INT_SEL_SHIFT 3 |
| 1983 | #define MT6325_RG_PCHR_CM_VINC_POLARITY_RSV_MASK 0x1 |
| 1984 | #define MT6325_RG_PCHR_CM_VINC_POLARITY_RSV_SHIFT 4 |
| 1985 | #define MT6325_RG_PCHR_CM_VDEC_POLARITY_RSV_MASK 0x1 |
| 1986 | #define MT6325_RG_PCHR_CM_VDEC_POLARITY_RSV_SHIFT 5 |
| 1987 | #define MT6325_INT_MISC_CON_SET_MASK 0xFFFF |
| 1988 | #define MT6325_INT_MISC_CON_SET_SHIFT 0 |
| 1989 | #define MT6325_INT_MISC_CON_CLR_MASK 0xFFFF |
| 1990 | #define MT6325_INT_MISC_CON_CLR_SHIFT 0 |
| 1991 | #define MT6325_RG_INT_STATUS_PWRKEY_MASK 0x1 |
| 1992 | #define MT6325_RG_INT_STATUS_PWRKEY_SHIFT 0 |
| 1993 | #define MT6325_RG_INT_STATUS_HOMEKEY_MASK 0x1 |
| 1994 | #define MT6325_RG_INT_STATUS_HOMEKEY_SHIFT 1 |
| 1995 | #define MT6325_RG_INT_STATUS_PWRKEY_R_MASK 0x1 |
| 1996 | #define MT6325_RG_INT_STATUS_PWRKEY_R_SHIFT 2 |
| 1997 | #define MT6325_RG_INT_STATUS_HOMEKEY_R_MASK 0x1 |
| 1998 | #define MT6325_RG_INT_STATUS_HOMEKEY_R_SHIFT 3 |
| 1999 | #define MT6325_RG_INT_STATUS_THR_H_MASK 0x1 |
| 2000 | #define MT6325_RG_INT_STATUS_THR_H_SHIFT 4 |
| 2001 | #define MT6325_RG_INT_STATUS_THR_L_MASK 0x1 |
| 2002 | #define MT6325_RG_INT_STATUS_THR_L_SHIFT 5 |
| 2003 | #define MT6325_RG_INT_STATUS_BAT_H_MASK 0x1 |
| 2004 | #define MT6325_RG_INT_STATUS_BAT_H_SHIFT 6 |
| 2005 | #define MT6325_RG_INT_STATUS_BAT_L_MASK 0x1 |
| 2006 | #define MT6325_RG_INT_STATUS_BAT_L_SHIFT 7 |
| 2007 | #define MT6325_RG_INT_STATUS_BIF_MASK 0x1 |
| 2008 | #define MT6325_RG_INT_STATUS_BIF_SHIFT 8 |
| 2009 | #define MT6325_RG_INT_STATUS_RTC_MASK 0x1 |
| 2010 | #define MT6325_RG_INT_STATUS_RTC_SHIFT 9 |
| 2011 | #define MT6325_RG_INT_STATUS_AUDIO_MASK 0x1 |
| 2012 | #define MT6325_RG_INT_STATUS_AUDIO_SHIFT 10 |
| 2013 | #define MT6325_RG_INT_STATUS_VOW_MASK 0x1 |
| 2014 | #define MT6325_RG_INT_STATUS_VOW_SHIFT 11 |
| 2015 | #define MT6325_RG_INT_STATUS_ACCDET_MASK 0x1 |
| 2016 | #define MT6325_RG_INT_STATUS_ACCDET_SHIFT 12 |
| 2017 | #define MT6325_RG_INT_STATUS_ACCDET_EINT_MASK 0x1 |
| 2018 | #define MT6325_RG_INT_STATUS_ACCDET_EINT_SHIFT 13 |
| 2019 | #define MT6325_RG_INT_STATUS_ACCDET_NEGV_MASK 0x1 |
| 2020 | #define MT6325_RG_INT_STATUS_ACCDET_NEGV_SHIFT 14 |
| 2021 | #define MT6325_RG_INT_STATUS_NI_LBAT_INT_MASK 0x1 |
| 2022 | #define MT6325_RG_INT_STATUS_NI_LBAT_INT_SHIFT 15 |
| 2023 | #define MT6325_RG_INT_STATUS_VDVFS11_OC_MASK 0x1 |
| 2024 | #define MT6325_RG_INT_STATUS_VDVFS11_OC_SHIFT 0 |
| 2025 | #define MT6325_RG_INT_STATUS_VDVFS12_OC_MASK 0x1 |
| 2026 | #define MT6325_RG_INT_STATUS_VDVFS12_OC_SHIFT 1 |
| 2027 | #define MT6325_RG_INT_STATUS_VRF18_0_OC_MASK 0x1 |
| 2028 | #define MT6325_RG_INT_STATUS_VRF18_0_OC_SHIFT 2 |
| 2029 | #define MT6325_RG_INT_STATUS_VDRAM_OC_MASK 0x1 |
| 2030 | #define MT6325_RG_INT_STATUS_VDRAM_OC_SHIFT 3 |
| 2031 | #define MT6325_RG_INT_STATUS_VGPU_OC_MASK 0x1 |
| 2032 | #define MT6325_RG_INT_STATUS_VGPU_OC_SHIFT 4 |
| 2033 | #define MT6325_RG_INT_STATUS_VCORE1_OC_MASK 0x1 |
| 2034 | #define MT6325_RG_INT_STATUS_VCORE1_OC_SHIFT 5 |
| 2035 | #define MT6325_RG_INT_STATUS_VCORE2_OC_MASK 0x1 |
| 2036 | #define MT6325_RG_INT_STATUS_VCORE2_OC_SHIFT 6 |
| 2037 | #define MT6325_RG_INT_STATUS_VIO18_OC_MASK 0x1 |
| 2038 | #define MT6325_RG_INT_STATUS_VIO18_OC_SHIFT 7 |
| 2039 | #define MT6325_RG_INT_STATUS_VPA_OC_MASK 0x1 |
| 2040 | #define MT6325_RG_INT_STATUS_VPA_OC_SHIFT 8 |
| 2041 | #define MT6325_RG_INT_STATUS_LDO_OC_MASK 0x1 |
| 2042 | #define MT6325_RG_INT_STATUS_LDO_OC_SHIFT 9 |
| 2043 | #define MT6325_RG_INT_STATUS_BAT2_H_MASK 0x1 |
| 2044 | #define MT6325_RG_INT_STATUS_BAT2_H_SHIFT 10 |
| 2045 | #define MT6325_RG_INT_STATUS_BAT2_L_MASK 0x1 |
| 2046 | #define MT6325_RG_INT_STATUS_BAT2_L_SHIFT 11 |
| 2047 | #define MT6325_RG_INT_STATUS_VISMPS0_H_MASK 0x1 |
| 2048 | #define MT6325_RG_INT_STATUS_VISMPS0_H_SHIFT 12 |
| 2049 | #define MT6325_RG_INT_STATUS_VISMPS0_L_MASK 0x1 |
| 2050 | #define MT6325_RG_INT_STATUS_VISMPS0_L_SHIFT 13 |
| 2051 | #define MT6325_RG_INT_STATUS_AUXADC_IMP_MASK 0x1 |
| 2052 | #define MT6325_RG_INT_STATUS_AUXADC_IMP_SHIFT 14 |
| 2053 | #define MT6325_RG_INT_STATUS_OV_MASK 0x1 |
| 2054 | #define MT6325_RG_INT_STATUS_OV_SHIFT 0 |
| 2055 | #define MT6325_RG_INT_STATUS_BVALID_DET_MASK 0x1 |
| 2056 | #define MT6325_RG_INT_STATUS_BVALID_DET_SHIFT 1 |
| 2057 | #define MT6325_RG_INT_STATUS_VBATON_UNDET_MASK 0x1 |
| 2058 | #define MT6325_RG_INT_STATUS_VBATON_UNDET_SHIFT 2 |
| 2059 | #define MT6325_RG_INT_STATUS_WATCHDOG_MASK 0x1 |
| 2060 | #define MT6325_RG_INT_STATUS_WATCHDOG_SHIFT 3 |
| 2061 | #define MT6325_RG_INT_STATUS_PCHR_CM_VDEC_MASK 0x1 |
| 2062 | #define MT6325_RG_INT_STATUS_PCHR_CM_VDEC_SHIFT 4 |
| 2063 | #define MT6325_RG_INT_STATUS_CHRDET_MASK 0x1 |
| 2064 | #define MT6325_RG_INT_STATUS_CHRDET_SHIFT 5 |
| 2065 | #define MT6325_RG_INT_STATUS_PCHR_CM_VINC_MASK 0x1 |
| 2066 | #define MT6325_RG_INT_STATUS_PCHR_CM_VINC_SHIFT 6 |
| 2067 | #define MT6325_RG_INT_STATUS_FG_BAT_H_MASK 0x1 |
| 2068 | #define MT6325_RG_INT_STATUS_FG_BAT_H_SHIFT 7 |
| 2069 | #define MT6325_RG_INT_STATUS_FG_BAT_L_MASK 0x1 |
| 2070 | #define MT6325_RG_INT_STATUS_FG_BAT_L_SHIFT 8 |
| 2071 | #define MT6325_RG_INT_STATUS_FG_CUR_H_MASK 0x1 |
| 2072 | #define MT6325_RG_INT_STATUS_FG_CUR_H_SHIFT 9 |
| 2073 | #define MT6325_RG_INT_STATUS_FG_CUR_L_MASK 0x1 |
| 2074 | #define MT6325_RG_INT_STATUS_FG_CUR_L_SHIFT 10 |
| 2075 | #define MT6325_RG_INT_STATUS_FG_ZCV_MASK 0x1 |
| 2076 | #define MT6325_RG_INT_STATUS_FG_ZCV_SHIFT 11 |
| 2077 | #define MT6325_RG_INT_STATUS_SPKL_D_MASK 0x1 |
| 2078 | #define MT6325_RG_INT_STATUS_SPKL_D_SHIFT 12 |
| 2079 | #define MT6325_RG_INT_STATUS_SPKL_AB_MASK 0x1 |
| 2080 | #define MT6325_RG_INT_STATUS_SPKL_AB_SHIFT 13 |
| 2081 | #define MT6325_OC_GEAR_LDO_MASK 0x3 |
| 2082 | #define MT6325_OC_GEAR_LDO_SHIFT 0 |
| 2083 | #define MT6325_FQMTR_TCKSEL_MASK 0x7 |
| 2084 | #define MT6325_FQMTR_TCKSEL_SHIFT 0 |
| 2085 | #define MT6325_FQMTR_BUSY_MASK 0x1 |
| 2086 | #define MT6325_FQMTR_BUSY_SHIFT 3 |
| 2087 | #define MT6325_FQMTR_EN_MASK 0x1 |
| 2088 | #define MT6325_FQMTR_EN_SHIFT 15 |
| 2089 | #define MT6325_FQMTR_WINSET_MASK 0xFFFF |
| 2090 | #define MT6325_FQMTR_WINSET_SHIFT 0 |
| 2091 | #define MT6325_FQMTR_DATA_MASK 0xFFFF |
| 2092 | #define MT6325_FQMTR_DATA_SHIFT 0 |
| 2093 | #define MT6325_RG_SLP_RW_EN_MASK 0x1 |
| 2094 | #define MT6325_RG_SLP_RW_EN_SHIFT 0 |
| 2095 | #define MT6325_RG_SPI_RSV_MASK 0x7FFF |
| 2096 | #define MT6325_RG_SPI_RSV_SHIFT 1 |
| 2097 | #define MT6325_DEW_DIO_EN_MASK 0x1 |
| 2098 | #define MT6325_DEW_DIO_EN_SHIFT 0 |
| 2099 | #define MT6325_DEW_READ_TEST_MASK 0xFFFF |
| 2100 | #define MT6325_DEW_READ_TEST_SHIFT 0 |
| 2101 | #define MT6325_DEW_WRITE_TEST_MASK 0xFFFF |
| 2102 | #define MT6325_DEW_WRITE_TEST_SHIFT 0 |
| 2103 | #define MT6325_DEW_CRC_SWRST_MASK 0x1 |
| 2104 | #define MT6325_DEW_CRC_SWRST_SHIFT 0 |
| 2105 | #define MT6325_DEW_CRC_EN_MASK 0x1 |
| 2106 | #define MT6325_DEW_CRC_EN_SHIFT 0 |
| 2107 | #define MT6325_DEW_CRC_VAL_MASK 0xFF |
| 2108 | #define MT6325_DEW_CRC_VAL_SHIFT 0 |
| 2109 | #define MT6325_DEW_DBG_MON_SEL_MASK 0xF |
| 2110 | #define MT6325_DEW_DBG_MON_SEL_SHIFT 0 |
| 2111 | #define MT6325_DEW_CIPHER_KEY_SEL_MASK 0x3 |
| 2112 | #define MT6325_DEW_CIPHER_KEY_SEL_SHIFT 0 |
| 2113 | #define MT6325_DEW_CIPHER_IV_SEL_MASK 0x3 |
| 2114 | #define MT6325_DEW_CIPHER_IV_SEL_SHIFT 0 |
| 2115 | #define MT6325_DEW_CIPHER_EN_MASK 0x1 |
| 2116 | #define MT6325_DEW_CIPHER_EN_SHIFT 0 |
| 2117 | #define MT6325_DEW_CIPHER_RDY_MASK 0x1 |
| 2118 | #define MT6325_DEW_CIPHER_RDY_SHIFT 0 |
| 2119 | #define MT6325_DEW_CIPHER_MODE_MASK 0x1 |
| 2120 | #define MT6325_DEW_CIPHER_MODE_SHIFT 0 |
| 2121 | #define MT6325_DEW_CIPHER_SWRST_MASK 0x1 |
| 2122 | #define MT6325_DEW_CIPHER_SWRST_SHIFT 0 |
| 2123 | #define MT6325_DEW_RDDMY_NO_MASK 0xF |
| 2124 | #define MT6325_DEW_RDDMY_NO_SHIFT 0 |
| 2125 | #define MT6325_INT_TYPE_CON0_MASK 0xFFFF |
| 2126 | #define MT6325_INT_TYPE_CON0_SHIFT 0 |
| 2127 | #define MT6325_INT_TYPE_CON0_SET_MASK 0xFFFF |
| 2128 | #define MT6325_INT_TYPE_CON0_SET_SHIFT 0 |
| 2129 | #define MT6325_INT_TYPE_CON0_CLR_MASK 0xFFFF |
| 2130 | #define MT6325_INT_TYPE_CON0_CLR_SHIFT 0 |
| 2131 | #define MT6325_INT_TYPE_CON1_MASK 0x7FFF |
| 2132 | #define MT6325_INT_TYPE_CON1_SHIFT 0 |
| 2133 | #define MT6325_INT_TYPE_CON1_SET_MASK 0x7FFF |
| 2134 | #define MT6325_INT_TYPE_CON1_SET_SHIFT 0 |
| 2135 | #define MT6325_INT_TYPE_CON1_CLR_MASK 0x7FFF |
| 2136 | #define MT6325_INT_TYPE_CON1_CLR_SHIFT 0 |
| 2137 | #define MT6325_INT_TYPE_CON2_MASK 0x3FFF |
| 2138 | #define MT6325_INT_TYPE_CON2_SHIFT 0 |
| 2139 | #define MT6325_INT_TYPE_CON2_SET_MASK 0x3FFF |
| 2140 | #define MT6325_INT_TYPE_CON2_SET_SHIFT 0 |
| 2141 | #define MT6325_INT_TYPE_CON2_CLR_MASK 0x3FFF |
| 2142 | #define MT6325_INT_TYPE_CON2_CLR_SHIFT 0 |
| 2143 | #define MT6325_CPU_INT_STA_MASK 0x1 |
| 2144 | #define MT6325_CPU_INT_STA_SHIFT 0 |
| 2145 | #define MT6325_MD32_INT_STA_MASK 0x1 |
| 2146 | #define MT6325_MD32_INT_STA_SHIFT 1 |
| 2147 | #define MT6325_BUCK_ALL_RSV0_MASK 0xFF |
| 2148 | #define MT6325_BUCK_ALL_RSV0_SHIFT 8 |
| 2149 | #define MT6325_VSLEEP_SRC0_MASK 0x1FF |
| 2150 | #define MT6325_VSLEEP_SRC0_SHIFT 0 |
| 2151 | #define MT6325_VSLEEP_SRC1_MASK 0xF |
| 2152 | #define MT6325_VSLEEP_SRC1_SHIFT 12 |
| 2153 | #define MT6325_R2R_SRC0_MASK 0x1FF |
| 2154 | #define MT6325_R2R_SRC0_SHIFT 0 |
| 2155 | #define MT6325_R2R_SRC1_MASK 0xF |
| 2156 | #define MT6325_R2R_SRC1_SHIFT 12 |
| 2157 | #define MT6325_BUCK_OSC_SEL_SRC0_MASK 0x1FF |
| 2158 | #define MT6325_BUCK_OSC_SEL_SRC0_SHIFT 0 |
| 2159 | #define MT6325_SRCLKEN_DLY_SRC1_MASK 0xF |
| 2160 | #define MT6325_SRCLKEN_DLY_SRC1_SHIFT 12 |
| 2161 | #define MT6325_BUCK_CON5_RSV0_MASK 0xFFFF |
| 2162 | #define MT6325_BUCK_CON5_RSV0_SHIFT 0 |
| 2163 | #define MT6325_QI_VGPU_DIG_MON_MASK 0xF |
| 2164 | #define MT6325_QI_VGPU_DIG_MON_SHIFT 0 |
| 2165 | #define MT6325_QI_VIO18_DIG_MON_MASK 0xF |
| 2166 | #define MT6325_QI_VIO18_DIG_MON_SHIFT 4 |
| 2167 | #define MT6325_QI_VCORE1_DIG_MON_MASK 0xF |
| 2168 | #define MT6325_QI_VCORE1_DIG_MON_SHIFT 0 |
| 2169 | #define MT6325_QI_VCORE2_DIG_MON_MASK 0xF |
| 2170 | #define MT6325_QI_VCORE2_DIG_MON_SHIFT 4 |
| 2171 | #define MT6325_QI_VRF18_0_DIG_MON_MASK 0xF |
| 2172 | #define MT6325_QI_VRF18_0_DIG_MON_SHIFT 0 |
| 2173 | #define MT6325_QI_VPA_DIG_MON_MASK 0xFF |
| 2174 | #define MT6325_QI_VPA_DIG_MON_SHIFT 8 |
| 2175 | #define MT6325_QI_VDVFS11_DIG_MON_MASK 0xFF |
| 2176 | #define MT6325_QI_VDVFS11_DIG_MON_SHIFT 0 |
| 2177 | #define MT6325_QI_VDVFS12_DIG_MON_MASK 0xFF |
| 2178 | #define MT6325_QI_VDVFS12_DIG_MON_SHIFT 8 |
| 2179 | #define MT6325_VDVFS11_OC_EN_MASK 0x1 |
| 2180 | #define MT6325_VDVFS11_OC_EN_SHIFT 0 |
| 2181 | #define MT6325_VDVFS11_OC_DEG_EN_MASK 0x1 |
| 2182 | #define MT6325_VDVFS11_OC_DEG_EN_SHIFT 1 |
| 2183 | #define MT6325_VDVFS11_OC_WND_MASK 0x3 |
| 2184 | #define MT6325_VDVFS11_OC_WND_SHIFT 2 |
| 2185 | #define MT6325_VDVFS11_OC_THD_MASK 0x3 |
| 2186 | #define MT6325_VDVFS11_OC_THD_SHIFT 6 |
| 2187 | #define MT6325_VDVFS12_OC_EN_MASK 0x1 |
| 2188 | #define MT6325_VDVFS12_OC_EN_SHIFT 0 |
| 2189 | #define MT6325_VDVFS12_OC_DEG_EN_MASK 0x1 |
| 2190 | #define MT6325_VDVFS12_OC_DEG_EN_SHIFT 1 |
| 2191 | #define MT6325_VDVFS12_OC_WND_MASK 0x3 |
| 2192 | #define MT6325_VDVFS12_OC_WND_SHIFT 2 |
| 2193 | #define MT6325_VDVFS12_OC_THD_MASK 0x3 |
| 2194 | #define MT6325_VDVFS12_OC_THD_SHIFT 6 |
| 2195 | #define MT6325_VRF18_0_OC_EN_MASK 0x1 |
| 2196 | #define MT6325_VRF18_0_OC_EN_SHIFT 0 |
| 2197 | #define MT6325_VRF18_0_OC_DEG_EN_MASK 0x1 |
| 2198 | #define MT6325_VRF18_0_OC_DEG_EN_SHIFT 1 |
| 2199 | #define MT6325_VRF18_0_OC_WND_MASK 0x3 |
| 2200 | #define MT6325_VRF18_0_OC_WND_SHIFT 2 |
| 2201 | #define MT6325_VRF18_0_OC_THD_MASK 0x3 |
| 2202 | #define MT6325_VRF18_0_OC_THD_SHIFT 6 |
| 2203 | #define MT6325_VPA_OC_EN_MASK 0x1 |
| 2204 | #define MT6325_VPA_OC_EN_SHIFT 0 |
| 2205 | #define MT6325_VPA_OC_DEG_EN_MASK 0x1 |
| 2206 | #define MT6325_VPA_OC_DEG_EN_SHIFT 1 |
| 2207 | #define MT6325_VPA_OC_WND_MASK 0x3 |
| 2208 | #define MT6325_VPA_OC_WND_SHIFT 2 |
| 2209 | #define MT6325_VPA_OC_THD_MASK 0x3 |
| 2210 | #define MT6325_VPA_OC_THD_SHIFT 6 |
| 2211 | #define MT6325_VGPU_OC_EN_MASK 0x1 |
| 2212 | #define MT6325_VGPU_OC_EN_SHIFT 0 |
| 2213 | #define MT6325_VGPU_OC_DEG_EN_MASK 0x1 |
| 2214 | #define MT6325_VGPU_OC_DEG_EN_SHIFT 1 |
| 2215 | #define MT6325_VGPU_OC_WND_MASK 0x3 |
| 2216 | #define MT6325_VGPU_OC_WND_SHIFT 2 |
| 2217 | #define MT6325_VGPU_OC_THD_MASK 0x3 |
| 2218 | #define MT6325_VGPU_OC_THD_SHIFT 6 |
| 2219 | #define MT6325_VCORE1_OC_EN_MASK 0x1 |
| 2220 | #define MT6325_VCORE1_OC_EN_SHIFT 0 |
| 2221 | #define MT6325_VCORE1_OC_DEG_EN_MASK 0x1 |
| 2222 | #define MT6325_VCORE1_OC_DEG_EN_SHIFT 1 |
| 2223 | #define MT6325_VCORE1_OC_WND_MASK 0x3 |
| 2224 | #define MT6325_VCORE1_OC_WND_SHIFT 2 |
| 2225 | #define MT6325_VCORE1_OC_THD_MASK 0x3 |
| 2226 | #define MT6325_VCORE1_OC_THD_SHIFT 6 |
| 2227 | #define MT6325_VCORE2_OC_EN_MASK 0x1 |
| 2228 | #define MT6325_VCORE2_OC_EN_SHIFT 0 |
| 2229 | #define MT6325_VCORE2_OC_DEG_EN_MASK 0x1 |
| 2230 | #define MT6325_VCORE2_OC_DEG_EN_SHIFT 1 |
| 2231 | #define MT6325_VCORE2_OC_WND_MASK 0x3 |
| 2232 | #define MT6325_VCORE2_OC_WND_SHIFT 2 |
| 2233 | #define MT6325_VCORE2_OC_THD_MASK 0x3 |
| 2234 | #define MT6325_VCORE2_OC_THD_SHIFT 6 |
| 2235 | #define MT6325_VIO18_OC_EN_MASK 0x1 |
| 2236 | #define MT6325_VIO18_OC_EN_SHIFT 0 |
| 2237 | #define MT6325_VIO18_OC_DEG_EN_MASK 0x1 |
| 2238 | #define MT6325_VIO18_OC_DEG_EN_SHIFT 1 |
| 2239 | #define MT6325_VIO18_OC_WND_MASK 0x3 |
| 2240 | #define MT6325_VIO18_OC_WND_SHIFT 2 |
| 2241 | #define MT6325_VIO18_OC_THD_MASK 0x3 |
| 2242 | #define MT6325_VIO18_OC_THD_SHIFT 6 |
| 2243 | #define MT6325_VDRAM_OC_EN_MASK 0x1 |
| 2244 | #define MT6325_VDRAM_OC_EN_SHIFT 0 |
| 2245 | #define MT6325_VDRAM_OC_DEG_EN_MASK 0x1 |
| 2246 | #define MT6325_VDRAM_OC_DEG_EN_SHIFT 1 |
| 2247 | #define MT6325_VDRAM_OC_WND_MASK 0x3 |
| 2248 | #define MT6325_VDRAM_OC_WND_SHIFT 2 |
| 2249 | #define MT6325_VDRAM_OC_THD_MASK 0x3 |
| 2250 | #define MT6325_VDRAM_OC_THD_SHIFT 6 |
| 2251 | #define MT6325_VDVFS11_OC_FLAG_CLR_MASK 0x1 |
| 2252 | #define MT6325_VDVFS11_OC_FLAG_CLR_SHIFT 0 |
| 2253 | #define MT6325_VDVFS12_OC_FLAG_CLR_MASK 0x1 |
| 2254 | #define MT6325_VDVFS12_OC_FLAG_CLR_SHIFT 1 |
| 2255 | #define MT6325_VRF18_0_OC_FLAG_CLR_MASK 0x1 |
| 2256 | #define MT6325_VRF18_0_OC_FLAG_CLR_SHIFT 2 |
| 2257 | #define MT6325_VPA_OC_FLAG_CLR_MASK 0x1 |
| 2258 | #define MT6325_VPA_OC_FLAG_CLR_SHIFT 3 |
| 2259 | #define MT6325_VGPU_OC_FLAG_CLR_MASK 0x1 |
| 2260 | #define MT6325_VGPU_OC_FLAG_CLR_SHIFT 4 |
| 2261 | #define MT6325_VCORE1_OC_FLAG_CLR_MASK 0x1 |
| 2262 | #define MT6325_VCORE1_OC_FLAG_CLR_SHIFT 5 |
| 2263 | #define MT6325_VCORE2_OC_FLAG_CLR_MASK 0x1 |
| 2264 | #define MT6325_VCORE2_OC_FLAG_CLR_SHIFT 6 |
| 2265 | #define MT6325_VIO18_OC_FLAG_CLR_MASK 0x1 |
| 2266 | #define MT6325_VIO18_OC_FLAG_CLR_SHIFT 7 |
| 2267 | #define MT6325_VDRAM_OC_FLAG_CLR_MASK 0x1 |
| 2268 | #define MT6325_VDRAM_OC_FLAG_CLR_SHIFT 8 |
| 2269 | #define MT6325_VDVFS11_OC_FLAG_CLR_SEL_MASK 0x1 |
| 2270 | #define MT6325_VDVFS11_OC_FLAG_CLR_SEL_SHIFT 0 |
| 2271 | #define MT6325_VDVFS12_OC_FLAG_CLR_SEL_MASK 0x1 |
| 2272 | #define MT6325_VDVFS12_OC_FLAG_CLR_SEL_SHIFT 1 |
| 2273 | #define MT6325_VRF18_0_OC_FLAG_CLR_SEL_MASK 0x1 |
| 2274 | #define MT6325_VRF18_0_OC_FLAG_CLR_SEL_SHIFT 2 |
| 2275 | #define MT6325_VPA_OC_FLAG_CLR_SEL_MASK 0x1 |
| 2276 | #define MT6325_VPA_OC_FLAG_CLR_SEL_SHIFT 3 |
| 2277 | #define MT6325_VGPU_OC_FLAG_CLR_SEL_MASK 0x1 |
| 2278 | #define MT6325_VGPU_OC_FLAG_CLR_SEL_SHIFT 4 |
| 2279 | #define MT6325_VCORE1_OC_FLAG_CLR_SEL_MASK 0x1 |
| 2280 | #define MT6325_VCORE1_OC_FLAG_CLR_SEL_SHIFT 5 |
| 2281 | #define MT6325_VCORE2_OC_FLAG_CLR_SEL_MASK 0x1 |
| 2282 | #define MT6325_VCORE2_OC_FLAG_CLR_SEL_SHIFT 6 |
| 2283 | #define MT6325_VIO18_OC_FLAG_CLR_SEL_MASK 0x1 |
| 2284 | #define MT6325_VIO18_OC_FLAG_CLR_SEL_SHIFT 7 |
| 2285 | #define MT6325_VDRAM_OC_FLAG_CLR_SEL_MASK 0x1 |
| 2286 | #define MT6325_VDRAM_OC_FLAG_CLR_SEL_SHIFT 8 |
| 2287 | #define MT6325_VDVFS11_OC_STATUS_MASK 0x1 |
| 2288 | #define MT6325_VDVFS11_OC_STATUS_SHIFT 0 |
| 2289 | #define MT6325_VDVFS12_OC_STATUS_MASK 0x1 |
| 2290 | #define MT6325_VDVFS12_OC_STATUS_SHIFT 1 |
| 2291 | #define MT6325_VRF18_0_OC_STATUS_MASK 0x1 |
| 2292 | #define MT6325_VRF18_0_OC_STATUS_SHIFT 2 |
| 2293 | #define MT6325_VPA_OC_STATUS_MASK 0x1 |
| 2294 | #define MT6325_VPA_OC_STATUS_SHIFT 3 |
| 2295 | #define MT6325_VGPU_OC_STATUS_MASK 0x1 |
| 2296 | #define MT6325_VGPU_OC_STATUS_SHIFT 4 |
| 2297 | #define MT6325_VCORE1_OC_STATUS_MASK 0x1 |
| 2298 | #define MT6325_VCORE1_OC_STATUS_SHIFT 5 |
| 2299 | #define MT6325_VCORE2_OC_STATUS_MASK 0x1 |
| 2300 | #define MT6325_VCORE2_OC_STATUS_SHIFT 6 |
| 2301 | #define MT6325_VIO18_OC_STATUS_MASK 0x1 |
| 2302 | #define MT6325_VIO18_OC_STATUS_SHIFT 7 |
| 2303 | #define MT6325_VDRAM_OC_STATUS_MASK 0x1 |
| 2304 | #define MT6325_VDRAM_OC_STATUS_SHIFT 8 |
| 2305 | #define MT6325_VDVFS11_OC_INT_EN_MASK 0x1 |
| 2306 | #define MT6325_VDVFS11_OC_INT_EN_SHIFT 0 |
| 2307 | #define MT6325_VDVFS12_OC_INT_EN_MASK 0x1 |
| 2308 | #define MT6325_VDVFS12_OC_INT_EN_SHIFT 1 |
| 2309 | #define MT6325_VRF18_0_OC_INT_EN_MASK 0x1 |
| 2310 | #define MT6325_VRF18_0_OC_INT_EN_SHIFT 2 |
| 2311 | #define MT6325_VPA_OC_INT_EN_MASK 0x1 |
| 2312 | #define MT6325_VPA_OC_INT_EN_SHIFT 3 |
| 2313 | #define MT6325_VGPU_OC_INT_EN_MASK 0x1 |
| 2314 | #define MT6325_VGPU_OC_INT_EN_SHIFT 4 |
| 2315 | #define MT6325_VCORE1_OC_INT_EN_MASK 0x1 |
| 2316 | #define MT6325_VCORE1_OC_INT_EN_SHIFT 5 |
| 2317 | #define MT6325_VCORE2_OC_INT_EN_MASK 0x1 |
| 2318 | #define MT6325_VCORE2_OC_INT_EN_SHIFT 6 |
| 2319 | #define MT6325_VIO18_OC_INT_EN_MASK 0x1 |
| 2320 | #define MT6325_VIO18_OC_INT_EN_SHIFT 7 |
| 2321 | #define MT6325_VDRAM_OC_INT_EN_MASK 0x1 |
| 2322 | #define MT6325_VDRAM_OC_INT_EN_SHIFT 8 |
| 2323 | #define MT6325_VDVFS11_EN_OC_SDN_SEL_MASK 0x1 |
| 2324 | #define MT6325_VDVFS11_EN_OC_SDN_SEL_SHIFT 0 |
| 2325 | #define MT6325_VDVFS12_EN_OC_SDN_SEL_MASK 0x1 |
| 2326 | #define MT6325_VDVFS12_EN_OC_SDN_SEL_SHIFT 1 |
| 2327 | #define MT6325_VRF18_0_EN_OC_SDN_SEL_MASK 0x1 |
| 2328 | #define MT6325_VRF18_0_EN_OC_SDN_SEL_SHIFT 2 |
| 2329 | #define MT6325_VPA_EN_OC_SDN_SEL_MASK 0x1 |
| 2330 | #define MT6325_VPA_EN_OC_SDN_SEL_SHIFT 3 |
| 2331 | #define MT6325_VGPU_EN_OC_SDN_SEL_MASK 0x1 |
| 2332 | #define MT6325_VGPU_EN_OC_SDN_SEL_SHIFT 4 |
| 2333 | #define MT6325_VCORE1_EN_OC_SDN_SEL_MASK 0x1 |
| 2334 | #define MT6325_VCORE1_EN_OC_SDN_SEL_SHIFT 5 |
| 2335 | #define MT6325_VCORE2_EN_OC_SDN_SEL_MASK 0x1 |
| 2336 | #define MT6325_VCORE2_EN_OC_SDN_SEL_SHIFT 6 |
| 2337 | #define MT6325_VIO18_EN_OC_SDN_SEL_MASK 0x1 |
| 2338 | #define MT6325_VIO18_EN_OC_SDN_SEL_SHIFT 7 |
| 2339 | #define MT6325_VDRAM_EN_OC_SDN_SEL_MASK 0x1 |
| 2340 | #define MT6325_VDRAM_EN_OC_SDN_SEL_SHIFT 8 |
| 2341 | #define MT6325_VSRAM_DVFS1_TRACK_SLEEP_CTRL_MASK 0x1 |
| 2342 | #define MT6325_VSRAM_DVFS1_TRACK_SLEEP_CTRL_SHIFT 0 |
| 2343 | #define MT6325_VSRAM_DVFS1_TRACK_ON_CTRL_MASK 0x1 |
| 2344 | #define MT6325_VSRAM_DVFS1_TRACK_ON_CTRL_SHIFT 1 |
| 2345 | #define MT6325_VDVFS1_TRACK_ON_CTRL_MASK 0x1 |
| 2346 | #define MT6325_VDVFS1_TRACK_ON_CTRL_SHIFT 2 |
| 2347 | #define MT6325_VSRAM_DVFS1_VOSEL_DELTA_MASK 0x7F |
| 2348 | #define MT6325_VSRAM_DVFS1_VOSEL_DELTA_SHIFT 0 |
| 2349 | #define MT6325_VSRAM_DVFS1_VOSEL_OFFSET_MASK 0x7F |
| 2350 | #define MT6325_VSRAM_DVFS1_VOSEL_OFFSET_SHIFT 8 |
| 2351 | #define MT6325_VSRAM_DVFS1_VOSEL_ON_LB_MASK 0x7F |
| 2352 | #define MT6325_VSRAM_DVFS1_VOSEL_ON_LB_SHIFT 0 |
| 2353 | #define MT6325_VSRAM_DVFS1_VOSEL_ON_HB_MASK 0x7F |
| 2354 | #define MT6325_VSRAM_DVFS1_VOSEL_ON_HB_SHIFT 8 |
| 2355 | #define MT6325_VSRAM_DVFS1_VOSEL_SLEEP_LB_MASK 0x7F |
| 2356 | #define MT6325_VSRAM_DVFS1_VOSEL_SLEEP_LB_SHIFT 0 |
| 2357 | #define MT6325_QI_VDVFS11_VSLEEP_MASK 0x3 |
| 2358 | #define MT6325_QI_VDVFS11_VSLEEP_SHIFT 0 |
| 2359 | #define MT6325_QI_VDVFS12_VSLEEP_MASK 0x3 |
| 2360 | #define MT6325_QI_VDVFS12_VSLEEP_SHIFT 2 |
| 2361 | #define MT6325_QI_VGPU_VSLEEP_MASK 0x3 |
| 2362 | #define MT6325_QI_VGPU_VSLEEP_SHIFT 4 |
| 2363 | #define MT6325_QI_VCORE1_VSLEEP_MASK 0x3 |
| 2364 | #define MT6325_QI_VCORE1_VSLEEP_SHIFT 6 |
| 2365 | #define MT6325_QI_VCORE2_VSLEEP_MASK 0x3 |
| 2366 | #define MT6325_QI_VCORE2_VSLEEP_SHIFT 8 |
| 2367 | #define MT6325_QI_VDRAM_VSLEEP_MASK 0x3 |
| 2368 | #define MT6325_QI_VDRAM_VSLEEP_SHIFT 10 |
| 2369 | #define MT6325_QI_VSRAM_DVFS1_VSLEEP_MASK 0x3 |
| 2370 | #define MT6325_QI_VSRAM_DVFS1_VSLEEP_SHIFT 12 |
| 2371 | #define MT6325_QI_VDVFS11_VSLEEP_RSV0_MASK 0x1 |
| 2372 | #define MT6325_QI_VDVFS11_VSLEEP_RSV0_SHIFT 0 |
| 2373 | #define MT6325_QI_VDVFS12_VSLEEP_RSV0_MASK 0x1 |
| 2374 | #define MT6325_QI_VDVFS12_VSLEEP_RSV0_SHIFT 1 |
| 2375 | #define MT6325_QI_VGPU_MODE_MASK 0x1 |
| 2376 | #define MT6325_QI_VGPU_MODE_SHIFT 2 |
| 2377 | #define MT6325_QI_VCORE1_MODE_MASK 0x1 |
| 2378 | #define MT6325_QI_VCORE1_MODE_SHIFT 3 |
| 2379 | #define MT6325_QI_VCORE2_MODE_MASK 0x1 |
| 2380 | #define MT6325_QI_VCORE2_MODE_SHIFT 4 |
| 2381 | #define MT6325_QI_VDRAM_MODE_MASK 0x1 |
| 2382 | #define MT6325_QI_VDRAM_MODE_SHIFT 5 |
| 2383 | #define MT6325_QI_VRF18_0_MODE_MASK 0x1 |
| 2384 | #define MT6325_QI_VRF18_0_MODE_SHIFT 6 |
| 2385 | #define MT6325_QI_VIO18_MODE_MASK 0x1 |
| 2386 | #define MT6325_QI_VIO18_MODE_SHIFT 7 |
| 2387 | #define MT6325_RG_VDRAM_MIN_OFF_MASK 0x3 |
| 2388 | #define MT6325_RG_VDRAM_MIN_OFF_SHIFT 0 |
| 2389 | #define MT6325_RG_VDRAM_NVT_BUFF_OFF_EN_MASK 0x1 |
| 2390 | #define MT6325_RG_VDRAM_NVT_BUFF_OFF_EN_SHIFT 2 |
| 2391 | #define MT6325_RG_VDRAM_VRF18_SSTART_EN_MASK 0x1 |
| 2392 | #define MT6325_RG_VDRAM_VRF18_SSTART_EN_SHIFT 3 |
| 2393 | #define MT6325_RG_VDRAM_1P35UP_SEL_EN_MASK 0x1 |
| 2394 | #define MT6325_RG_VDRAM_1P35UP_SEL_EN_SHIFT 4 |
| 2395 | #define MT6325_RG_VDRAM_RZSEL_MASK 0x7 |
| 2396 | #define MT6325_RG_VDRAM_RZSEL_SHIFT 5 |
| 2397 | #define MT6325_RG_VDRAM_CC_MASK 0x3 |
| 2398 | #define MT6325_RG_VDRAM_CC_SHIFT 8 |
| 2399 | #define MT6325_RG_VDRAM_CSR_MASK 0x7 |
| 2400 | #define MT6325_RG_VDRAM_CSR_SHIFT 10 |
| 2401 | #define MT6325_RG_VDRAM_CSL_MASK 0xF |
| 2402 | #define MT6325_RG_VDRAM_CSL_SHIFT 0 |
| 2403 | #define MT6325_RG_VDRAM_SLP_MASK 0x7 |
| 2404 | #define MT6325_RG_VDRAM_SLP_SHIFT 4 |
| 2405 | #define MT6325_RG_VDRAM_ZX_OS_MASK 0x3 |
| 2406 | #define MT6325_RG_VDRAM_ZX_OS_SHIFT 7 |
| 2407 | #define MT6325_RG_VDRAM_ZXOS_TRIM_MASK 0x3F |
| 2408 | #define MT6325_RG_VDRAM_ZXOS_TRIM_SHIFT 9 |
| 2409 | #define MT6325_RG_VDRAM_MODESET_MASK 0x1 |
| 2410 | #define MT6325_RG_VDRAM_MODESET_SHIFT 15 |
| 2411 | #define MT6325_RG_VDRAM_NDIS_EN_MASK 0x1 |
| 2412 | #define MT6325_RG_VDRAM_NDIS_EN_SHIFT 0 |
| 2413 | #define MT6325_RG_VDRAM_CSM_MASK 0x3F |
| 2414 | #define MT6325_RG_VDRAM_CSM_SHIFT 1 |
| 2415 | #define MT6325_RG_VDRAM_RSV_MASK 0xFF |
| 2416 | #define MT6325_RG_VDRAM_RSV_SHIFT 7 |
| 2417 | #define MT6325_RG_VDRAM_PFM_RIP_MASK 0x7 |
| 2418 | #define MT6325_RG_VDRAM_PFM_RIP_SHIFT 0 |
| 2419 | #define MT6325_RG_VDRAM_TRAN_BST_MASK 0x3F |
| 2420 | #define MT6325_RG_VDRAM_TRAN_BST_SHIFT 3 |
| 2421 | #define MT6325_RG_VDRAM_DTS_ENB_MASK 0x1 |
| 2422 | #define MT6325_RG_VDRAM_DTS_ENB_SHIFT 9 |
| 2423 | #define MT6325_RG_VDRAM_RCL_TRIM_MASK 0x1F |
| 2424 | #define MT6325_RG_VDRAM_RCL_TRIM_SHIFT 10 |
| 2425 | #define MT6325_RG_VDRAM_RCL_TRIM_EN_MASK 0x1 |
| 2426 | #define MT6325_RG_VDRAM_RCL_TRIM_EN_SHIFT 15 |
| 2427 | #define MT6325_RG_VDRAM_C2_RSV_MASK 0x1 |
| 2428 | #define MT6325_RG_VDRAM_C2_RSV_SHIFT 0 |
| 2429 | #define MT6325_RG_VCORE1_MIN_OFF_MASK 0x3 |
| 2430 | #define MT6325_RG_VCORE1_MIN_OFF_SHIFT 0 |
| 2431 | #define MT6325_RG_VCORE1_NVT_BUFF_OFF_EN_MASK 0x1 |
| 2432 | #define MT6325_RG_VCORE1_NVT_BUFF_OFF_EN_SHIFT 2 |
| 2433 | #define MT6325_RG_VCORE1_VRF18_SSTART_EN_MASK 0x1 |
| 2434 | #define MT6325_RG_VCORE1_VRF18_SSTART_EN_SHIFT 3 |
| 2435 | #define MT6325_RG_VCORE1_1P35UP_SEL_EN_MASK 0x1 |
| 2436 | #define MT6325_RG_VCORE1_1P35UP_SEL_EN_SHIFT 4 |
| 2437 | #define MT6325_RG_VCORE1_RZSEL_MASK 0x7 |
| 2438 | #define MT6325_RG_VCORE1_RZSEL_SHIFT 5 |
| 2439 | #define MT6325_RG_VCORE1_CC_MASK 0x3 |
| 2440 | #define MT6325_RG_VCORE1_CC_SHIFT 8 |
| 2441 | #define MT6325_RG_VCORE1_CSR_MASK 0x7 |
| 2442 | #define MT6325_RG_VCORE1_CSR_SHIFT 10 |
| 2443 | #define MT6325_RG_VCORE1_CSL_MASK 0xF |
| 2444 | #define MT6325_RG_VCORE1_CSL_SHIFT 0 |
| 2445 | #define MT6325_RG_VCORE1_SLP_MASK 0x7 |
| 2446 | #define MT6325_RG_VCORE1_SLP_SHIFT 4 |
| 2447 | #define MT6325_RG_VCORE1_ZX_OS_MASK 0x3 |
| 2448 | #define MT6325_RG_VCORE1_ZX_OS_SHIFT 7 |
| 2449 | #define MT6325_RG_VCORE1_ZXOS_TRIM_MASK 0x3F |
| 2450 | #define MT6325_RG_VCORE1_ZXOS_TRIM_SHIFT 9 |
| 2451 | #define MT6325_RG_VCORE1_MODESET_MASK 0x1 |
| 2452 | #define MT6325_RG_VCORE1_MODESET_SHIFT 15 |
| 2453 | #define MT6325_RG_VCORE1_NDIS_EN_MASK 0x1 |
| 2454 | #define MT6325_RG_VCORE1_NDIS_EN_SHIFT 0 |
| 2455 | #define MT6325_RG_VCORE1_CSM_MASK 0x3F |
| 2456 | #define MT6325_RG_VCORE1_CSM_SHIFT 1 |
| 2457 | #define MT6325_RG_VCORE1_RSV_MASK 0xFF |
| 2458 | #define MT6325_RG_VCORE1_RSV_SHIFT 7 |
| 2459 | #define MT6325_RG_VCORE1_PFM_RIP_MASK 0x7 |
| 2460 | #define MT6325_RG_VCORE1_PFM_RIP_SHIFT 0 |
| 2461 | #define MT6325_RG_VCORE1_TRAN_BST_MASK 0x3F |
| 2462 | #define MT6325_RG_VCORE1_TRAN_BST_SHIFT 3 |
| 2463 | #define MT6325_RG_VCORE1_DTS_ENB_MASK 0x1 |
| 2464 | #define MT6325_RG_VCORE1_DTS_ENB_SHIFT 9 |
| 2465 | #define MT6325_RG_VCORE1_RCL_TRIM_MASK 0x1F |
| 2466 | #define MT6325_RG_VCORE1_RCL_TRIM_SHIFT 10 |
| 2467 | #define MT6325_RG_VCORE1_RCL_TRIM_EN_MASK 0x1 |
| 2468 | #define MT6325_RG_VCORE1_RCL_TRIM_EN_SHIFT 15 |
| 2469 | #define MT6325_RG_VCORE1_C2_RSV_MASK 0x1 |
| 2470 | #define MT6325_RG_VCORE1_C2_RSV_SHIFT 0 |
| 2471 | #define MT6325_RG_SMPS_TESTMODE_B_MASK 0x1FF |
| 2472 | #define MT6325_RG_SMPS_TESTMODE_B_SHIFT 0 |
| 2473 | #define MT6325_RG_VSRAM_DVFS1_TRIMH_MASK 0x1F |
| 2474 | #define MT6325_RG_VSRAM_DVFS1_TRIMH_SHIFT 9 |
| 2475 | #define MT6325_RG_VSRAM_DVFS1_TRIML_MASK 0x1F |
| 2476 | #define MT6325_RG_VSRAM_DVFS1_TRIML_SHIFT 0 |
| 2477 | #define MT6325_RG_VDVFS11_TRIMH_MASK 0x1F |
| 2478 | #define MT6325_RG_VDVFS11_TRIMH_SHIFT 5 |
| 2479 | #define MT6325_RG_VDVFS11_TRIML_MASK 0x1F |
| 2480 | #define MT6325_RG_VDVFS11_TRIML_SHIFT 10 |
| 2481 | #define MT6325_RG_VDVFS12_TRIMH_MASK 0x1F |
| 2482 | #define MT6325_RG_VDVFS12_TRIMH_SHIFT 0 |
| 2483 | #define MT6325_RG_VDVFS12_TRIML_MASK 0x1F |
| 2484 | #define MT6325_RG_VDVFS12_TRIML_SHIFT 5 |
| 2485 | #define MT6325_RG_VGPU_TRIMH_MASK 0x1F |
| 2486 | #define MT6325_RG_VGPU_TRIMH_SHIFT 10 |
| 2487 | #define MT6325_RG_VGPU_TRIML_MASK 0x1F |
| 2488 | #define MT6325_RG_VGPU_TRIML_SHIFT 0 |
| 2489 | #define MT6325_RG_VCORE1_TRIMH_MASK 0x1F |
| 2490 | #define MT6325_RG_VCORE1_TRIMH_SHIFT 5 |
| 2491 | #define MT6325_RG_VCORE1_TRIML_MASK 0x1F |
| 2492 | #define MT6325_RG_VCORE1_TRIML_SHIFT 10 |
| 2493 | #define MT6325_RG_VCORE2_TRIMH_MASK 0x1F |
| 2494 | #define MT6325_RG_VCORE2_TRIMH_SHIFT 0 |
| 2495 | #define MT6325_RG_VCORE2_TRIML_MASK 0x1F |
| 2496 | #define MT6325_RG_VCORE2_TRIML_SHIFT 5 |
| 2497 | #define MT6325_RG_VIO18_TRIMH_MASK 0xF |
| 2498 | #define MT6325_RG_VIO18_TRIMH_SHIFT 10 |
| 2499 | #define MT6325_RG_VIO18_TRIML_MASK 0xF |
| 2500 | #define MT6325_RG_VIO18_TRIML_SHIFT 0 |
| 2501 | #define MT6325_RG_VPA_TRIMH_MASK 0x1F |
| 2502 | #define MT6325_RG_VPA_TRIMH_SHIFT 4 |
| 2503 | #define MT6325_RG_VPA_TRIML_MASK 0x1F |
| 2504 | #define MT6325_RG_VPA_TRIML_SHIFT 9 |
| 2505 | #define MT6325_RG_VPA_TRIM_REF_MASK 0x1F |
| 2506 | #define MT6325_RG_VPA_TRIM_REF_SHIFT 0 |
| 2507 | #define MT6325_RG_VRF18_0_TRIMH_MASK 0xF |
| 2508 | #define MT6325_RG_VRF18_0_TRIMH_SHIFT 5 |
| 2509 | #define MT6325_RG_VRF18_0_TRIML_MASK 0xF |
| 2510 | #define MT6325_RG_VRF18_0_TRIML_SHIFT 9 |
| 2511 | #define MT6325_RG_VDRAM_TRIMH_MASK 0xF |
| 2512 | #define MT6325_RG_VDRAM_TRIMH_SHIFT 0 |
| 2513 | #define MT6325_RG_VDRAM_TRIML_MASK 0xF |
| 2514 | #define MT6325_RG_VDRAM_TRIML_SHIFT 4 |
| 2515 | #define MT6325_RG_VSRAM_DVFS1_VSLEEP_MASK 0x7 |
| 2516 | #define MT6325_RG_VSRAM_DVFS1_VSLEEP_SHIFT 8 |
| 2517 | #define MT6325_RG_VDVFS11_VSLEEP_MASK 0x7 |
| 2518 | #define MT6325_RG_VDVFS11_VSLEEP_SHIFT 11 |
| 2519 | #define MT6325_RG_VDVFS12_VSLEEP_MASK 0x7 |
| 2520 | #define MT6325_RG_VDVFS12_VSLEEP_SHIFT 0 |
| 2521 | #define MT6325_RG_VGPU_VSLEEP_MASK 0x7 |
| 2522 | #define MT6325_RG_VGPU_VSLEEP_SHIFT 3 |
| 2523 | #define MT6325_RG_VCORE1_VSLEEP_MASK 0x7 |
| 2524 | #define MT6325_RG_VCORE1_VSLEEP_SHIFT 6 |
| 2525 | #define MT6325_RG_VCORE2_VSLEEP_MASK 0x7 |
| 2526 | #define MT6325_RG_VCORE2_VSLEEP_SHIFT 9 |
| 2527 | #define MT6325_RG_VPA_BURSTH_MASK 0x3 |
| 2528 | #define MT6325_RG_VPA_BURSTH_SHIFT 12 |
| 2529 | #define MT6325_RG_VPA_BURSTL_MASK 0x3 |
| 2530 | #define MT6325_RG_VPA_BURSTL_SHIFT 14 |
| 2531 | #define MT6325_RG_VDRAM_VSLEEP_MASK 0x7 |
| 2532 | #define MT6325_RG_VDRAM_VSLEEP_SHIFT 0 |
| 2533 | #define MT6325_RG_DMY100MA_EN_MASK 0x1 |
| 2534 | #define MT6325_RG_DMY100MA_EN_SHIFT 3 |
| 2535 | #define MT6325_RG_DMY100MA_SEL_MASK 0x3 |
| 2536 | #define MT6325_RG_DMY100MA_SEL_SHIFT 4 |
| 2537 | #define MT6325_RG_VDVFS1_MIN_OFF_MASK 0x3 |
| 2538 | #define MT6325_RG_VDVFS1_MIN_OFF_SHIFT 0 |
| 2539 | #define MT6325_RG_VDVFS1_NVT_BUFF_OFF_EN_MASK 0x1 |
| 2540 | #define MT6325_RG_VDVFS1_NVT_BUFF_OFF_EN_SHIFT 2 |
| 2541 | #define MT6325_RG_VDVFS1_VRF18_SSTART_EN_MASK 0x1 |
| 2542 | #define MT6325_RG_VDVFS1_VRF18_SSTART_EN_SHIFT 3 |
| 2543 | #define MT6325_RG_VDVFS1_1P35UP_SEL_EN_MASK 0x1 |
| 2544 | #define MT6325_RG_VDVFS1_1P35UP_SEL_EN_SHIFT 4 |
| 2545 | #define MT6325_RG_VDVFS11_RZSEL_MASK 0xF |
| 2546 | #define MT6325_RG_VDVFS11_RZSEL_SHIFT 5 |
| 2547 | #define MT6325_RG_VDVFS12_RZSEL_MASK 0xF |
| 2548 | #define MT6325_RG_VDVFS12_RZSEL_SHIFT 9 |
| 2549 | #define MT6325_RG_VDVFS11_PFM_RIP_MASK 0x7 |
| 2550 | #define MT6325_RG_VDVFS11_PFM_RIP_SHIFT 13 |
| 2551 | #define MT6325_RG_VDVFS11_CSR_MASK 0x7 |
| 2552 | #define MT6325_RG_VDVFS11_CSR_SHIFT 0 |
| 2553 | #define MT6325_RG_VDVFS12_CSR_MASK 0x7 |
| 2554 | #define MT6325_RG_VDVFS12_CSR_SHIFT 3 |
| 2555 | #define MT6325_RG_VDVFS11_PFM_CSR_MASK 0x7 |
| 2556 | #define MT6325_RG_VDVFS11_PFM_CSR_SHIFT 6 |
| 2557 | #define MT6325_RG_VDVFS12_PFM_CSR_MASK 0x7 |
| 2558 | #define MT6325_RG_VDVFS12_PFM_CSR_SHIFT 9 |
| 2559 | #define MT6325_RG_VDVFS11_CSL_MASK 0xF |
| 2560 | #define MT6325_RG_VDVFS11_CSL_SHIFT 12 |
| 2561 | #define MT6325_RG_VDVFS12_CSL_MASK 0xF |
| 2562 | #define MT6325_RG_VDVFS12_CSL_SHIFT 0 |
| 2563 | #define MT6325_RG_VDVFS11_SLP_MASK 0x7 |
| 2564 | #define MT6325_RG_VDVFS11_SLP_SHIFT 4 |
| 2565 | #define MT6325_RG_VDVFS12_SLP_MASK 0x7 |
| 2566 | #define MT6325_RG_VDVFS12_SLP_SHIFT 7 |
| 2567 | #define MT6325_RG_VDVFS11_ZX_OS_MASK 0x3 |
| 2568 | #define MT6325_RG_VDVFS11_ZX_OS_SHIFT 10 |
| 2569 | #define MT6325_RG_VDVFS12_ZX_OS_MASK 0x3 |
| 2570 | #define MT6325_RG_VDVFS12_ZX_OS_SHIFT 12 |
| 2571 | #define MT6325_RG_VDVFS11_MODESET_MASK 0x1 |
| 2572 | #define MT6325_RG_VDVFS11_MODESET_SHIFT 14 |
| 2573 | #define MT6325_RG_VDVFS12_MODESET_MASK 0x1 |
| 2574 | #define MT6325_RG_VDVFS12_MODESET_SHIFT 15 |
| 2575 | #define MT6325_RG_VDVFS11_NDIS_EN_MASK 0x1 |
| 2576 | #define MT6325_RG_VDVFS11_NDIS_EN_SHIFT 0 |
| 2577 | #define MT6325_RG_VDVFS12_NDIS_EN_MASK 0x1 |
| 2578 | #define MT6325_RG_VDVFS12_NDIS_EN_SHIFT 1 |
| 2579 | #define MT6325_RG_VDVFS11_TRANS_BST_MASK 0xFF |
| 2580 | #define MT6325_RG_VDVFS11_TRANS_BST_SHIFT 2 |
| 2581 | #define MT6325_RG_VDVFS12_TRANS_BST_MASK 0xFF |
| 2582 | #define MT6325_RG_VDVFS12_TRANS_BST_SHIFT 0 |
| 2583 | #define MT6325_RG_VDVFS11_UVP_EN_MASK 0x1 |
| 2584 | #define MT6325_RG_VDVFS11_UVP_EN_SHIFT 8 |
| 2585 | #define MT6325_RG_VDVFS12_UVP_EN_MASK 0x1 |
| 2586 | #define MT6325_RG_VDVFS12_UVP_EN_SHIFT 9 |
| 2587 | #define MT6325_RG_VDVFS11_CSM_MASK 0x3F |
| 2588 | #define MT6325_RG_VDVFS11_CSM_SHIFT 10 |
| 2589 | #define MT6325_RG_VDVFS12_CSM_MASK 0x3F |
| 2590 | #define MT6325_RG_VDVFS12_CSM_SHIFT 0 |
| 2591 | #define MT6325_RG_VDVFS11_PKMODE_MASK 0x1 |
| 2592 | #define MT6325_RG_VDVFS11_PKMODE_SHIFT 6 |
| 2593 | #define MT6325_RG_VDVFS12_PKMODE_MASK 0x1 |
| 2594 | #define MT6325_RG_VDVFS12_PKMODE_SHIFT 7 |
| 2595 | #define MT6325_RG_VDVFS11_RSV_MASK 0xFF |
| 2596 | #define MT6325_RG_VDVFS11_RSV_SHIFT 8 |
| 2597 | #define MT6325_RG_VDVFS12_RSV_MASK 0xFF |
| 2598 | #define MT6325_RG_VDVFS12_RSV_SHIFT 0 |
| 2599 | #define MT6325_RG_VDVFS11_ZXOS_TRIM_MASK 0xFF |
| 2600 | #define MT6325_RG_VDVFS11_ZXOS_TRIM_SHIFT 8 |
| 2601 | #define MT6325_RG_VDVFS12_ZXOS_TRIM_MASK 0xFF |
| 2602 | #define MT6325_RG_VDVFS12_ZXOS_TRIM_SHIFT 0 |
| 2603 | #define MT6325_RG_VDVFS11_OC_OFF_MASK 0x1 |
| 2604 | #define MT6325_RG_VDVFS11_OC_OFF_SHIFT 8 |
| 2605 | #define MT6325_RG_VDVFS12_OC_OFF_MASK 0x1 |
| 2606 | #define MT6325_RG_VDVFS12_OC_OFF_SHIFT 9 |
| 2607 | #define MT6325_RG_VDVFS11_PHS_SHED_TRIM_MASK 0xF |
| 2608 | #define MT6325_RG_VDVFS11_PHS_SHED_TRIM_SHIFT 10 |
| 2609 | #define MT6325_RG_VGPU_MIN_OFF_MASK 0x3 |
| 2610 | #define MT6325_RG_VGPU_MIN_OFF_SHIFT 0 |
| 2611 | #define MT6325_RG_VGPU_NVT_BUFF_OFF_EN_MASK 0x1 |
| 2612 | #define MT6325_RG_VGPU_NVT_BUFF_OFF_EN_SHIFT 2 |
| 2613 | #define MT6325_RG_VGPU_VRF18_SSTART_EN_MASK 0x1 |
| 2614 | #define MT6325_RG_VGPU_VRF18_SSTART_EN_SHIFT 3 |
| 2615 | #define MT6325_RG_VGPU_1P35UP_SEL_EN_MASK 0x1 |
| 2616 | #define MT6325_RG_VGPU_1P35UP_SEL_EN_SHIFT 4 |
| 2617 | #define MT6325_RG_VGPU_RZSEL_MASK 0x7 |
| 2618 | #define MT6325_RG_VGPU_RZSEL_SHIFT 5 |
| 2619 | #define MT6325_RG_VGPU_CC_MASK 0x3 |
| 2620 | #define MT6325_RG_VGPU_CC_SHIFT 8 |
| 2621 | #define MT6325_RG_VGPU_CSR_MASK 0x7 |
| 2622 | #define MT6325_RG_VGPU_CSR_SHIFT 10 |
| 2623 | #define MT6325_RG_VGPU_CSL_MASK 0xF |
| 2624 | #define MT6325_RG_VGPU_CSL_SHIFT 0 |
| 2625 | #define MT6325_RG_VGPU_SLP_MASK 0x7 |
| 2626 | #define MT6325_RG_VGPU_SLP_SHIFT 4 |
| 2627 | #define MT6325_RG_VGPU_ZX_OS_MASK 0x3 |
| 2628 | #define MT6325_RG_VGPU_ZX_OS_SHIFT 7 |
| 2629 | #define MT6325_RG_VGPU_ZXOS_TRIM_MASK 0x3F |
| 2630 | #define MT6325_RG_VGPU_ZXOS_TRIM_SHIFT 9 |
| 2631 | #define MT6325_RG_VGPU_MODESET_MASK 0x1 |
| 2632 | #define MT6325_RG_VGPU_MODESET_SHIFT 15 |
| 2633 | #define MT6325_RG_VGPU_NDIS_EN_MASK 0x1 |
| 2634 | #define MT6325_RG_VGPU_NDIS_EN_SHIFT 0 |
| 2635 | #define MT6325_RG_VGPU_CSM_MASK 0x3F |
| 2636 | #define MT6325_RG_VGPU_CSM_SHIFT 1 |
| 2637 | #define MT6325_RG_VGPU_RSV_MASK 0xFF |
| 2638 | #define MT6325_RG_VGPU_RSV_SHIFT 7 |
| 2639 | #define MT6325_RG_VGPU_PFM_RIP_MASK 0x7 |
| 2640 | #define MT6325_RG_VGPU_PFM_RIP_SHIFT 0 |
| 2641 | #define MT6325_RG_VGPU_TRAN_BST_MASK 0x3F |
| 2642 | #define MT6325_RG_VGPU_TRAN_BST_SHIFT 3 |
| 2643 | #define MT6325_RG_VGPU_DTS_ENB_MASK 0x1 |
| 2644 | #define MT6325_RG_VGPU_DTS_ENB_SHIFT 9 |
| 2645 | #define MT6325_RG_VGPU_RCL_TRIM_MASK 0x1F |
| 2646 | #define MT6325_RG_VGPU_RCL_TRIM_SHIFT 10 |
| 2647 | #define MT6325_RG_VGPU_RCL_TRIM_EN_MASK 0x1 |
| 2648 | #define MT6325_RG_VGPU_RCL_TRIM_EN_SHIFT 15 |
| 2649 | #define MT6325_RG_VGPU_C2_RSV_MASK 0x1 |
| 2650 | #define MT6325_RG_VGPU_C2_RSV_SHIFT 0 |
| 2651 | #define MT6325_RG_VPA_RZSEL_MASK 0x3 |
| 2652 | #define MT6325_RG_VPA_RZSEL_SHIFT 0 |
| 2653 | #define MT6325_RG_VPA_CC_MASK 0x3 |
| 2654 | #define MT6325_RG_VPA_CC_SHIFT 2 |
| 2655 | #define MT6325_RG_VPA_CSR_MASK 0x3 |
| 2656 | #define MT6325_RG_VPA_CSR_SHIFT 4 |
| 2657 | #define MT6325_RG_VPA_CSMIR_MASK 0x3 |
| 2658 | #define MT6325_RG_VPA_CSMIR_SHIFT 6 |
| 2659 | #define MT6325_RG_VPA_CSL_MASK 0x3 |
| 2660 | #define MT6325_RG_VPA_CSL_SHIFT 8 |
| 2661 | #define MT6325_RG_VPA_SLP_MASK 0x3 |
| 2662 | #define MT6325_RG_VPA_SLP_SHIFT 10 |
| 2663 | #define MT6325_RG_VPA_ZX_OS_TRIM_MASK 0x3F |
| 2664 | #define MT6325_RG_VPA_ZX_OS_TRIM_SHIFT 0 |
| 2665 | #define MT6325_RG_VPA_ZX_OS_MASK 0x3 |
| 2666 | #define MT6325_RG_VPA_ZX_OS_SHIFT 6 |
| 2667 | #define MT6325_RG_VPA_HZP_MASK 0x1 |
| 2668 | #define MT6325_RG_VPA_HZP_SHIFT 8 |
| 2669 | #define MT6325_RG_VPA_BWEX_GAT_MASK 0x1 |
| 2670 | #define MT6325_RG_VPA_BWEX_GAT_SHIFT 9 |
| 2671 | #define MT6325_RG_VPA_MODESET_MASK 0x1 |
| 2672 | #define MT6325_RG_VPA_MODESET_SHIFT 10 |
| 2673 | #define MT6325_RG_VPA_SLEW_MASK 0x3 |
| 2674 | #define MT6325_RG_VPA_SLEW_SHIFT 11 |
| 2675 | #define MT6325_RG_VPA_SLEW_NMOS_MASK 0x3 |
| 2676 | #define MT6325_RG_VPA_SLEW_NMOS_SHIFT 13 |
| 2677 | #define MT6325_RG_VPA_NDIS_EN_MASK 0x1 |
| 2678 | #define MT6325_RG_VPA_NDIS_EN_SHIFT 15 |
| 2679 | #define MT6325_RG_VPA_MIN_ON_MASK 0x3 |
| 2680 | #define MT6325_RG_VPA_MIN_ON_SHIFT 0 |
| 2681 | #define MT6325_RG_VPA_VBAT_DEL_MASK 0x3 |
| 2682 | #define MT6325_RG_VPA_VBAT_DEL_SHIFT 2 |
| 2683 | #define MT6325_RG_VPA_EN_MASK 0x1 |
| 2684 | #define MT6325_RG_VPA_EN_SHIFT 4 |
| 2685 | #define MT6325_RG_VPA_RSV1_MASK 0xFF |
| 2686 | #define MT6325_RG_VPA_RSV1_SHIFT 5 |
| 2687 | #define MT6325_RG_VPA_RSV2_MASK 0xFF |
| 2688 | #define MT6325_RG_VPA_RSV2_SHIFT 0 |
| 2689 | #define MT6325_RG_VCORE2_MIN_OFF_MASK 0x3 |
| 2690 | #define MT6325_RG_VCORE2_MIN_OFF_SHIFT 0 |
| 2691 | #define MT6325_RG_VCORE2_NVT_BUFF_OFF_EN_MASK 0x1 |
| 2692 | #define MT6325_RG_VCORE2_NVT_BUFF_OFF_EN_SHIFT 2 |
| 2693 | #define MT6325_RG_VCORE2_VRF18_SSTART_EN_MASK 0x1 |
| 2694 | #define MT6325_RG_VCORE2_VRF18_SSTART_EN_SHIFT 3 |
| 2695 | #define MT6325_RG_VCORE2_1P35UP_SEL_EN_MASK 0x1 |
| 2696 | #define MT6325_RG_VCORE2_1P35UP_SEL_EN_SHIFT 4 |
| 2697 | #define MT6325_RG_VCORE2_RZSEL_MASK 0x7 |
| 2698 | #define MT6325_RG_VCORE2_RZSEL_SHIFT 5 |
| 2699 | #define MT6325_RG_VCORE2_CC_MASK 0x3 |
| 2700 | #define MT6325_RG_VCORE2_CC_SHIFT 8 |
| 2701 | #define MT6325_RG_VCORE2_CSR_MASK 0x7 |
| 2702 | #define MT6325_RG_VCORE2_CSR_SHIFT 10 |
| 2703 | #define MT6325_RG_VCORE2_CSL_MASK 0xF |
| 2704 | #define MT6325_RG_VCORE2_CSL_SHIFT 0 |
| 2705 | #define MT6325_RG_VCORE2_SLP_MASK 0x7 |
| 2706 | #define MT6325_RG_VCORE2_SLP_SHIFT 4 |
| 2707 | #define MT6325_RG_VCORE2_ZX_OS_MASK 0x3 |
| 2708 | #define MT6325_RG_VCORE2_ZX_OS_SHIFT 7 |
| 2709 | #define MT6325_RG_VCORE2_ZXOS_TRIM_MASK 0x3F |
| 2710 | #define MT6325_RG_VCORE2_ZXOS_TRIM_SHIFT 9 |
| 2711 | #define MT6325_RG_VCORE2_MODESET_MASK 0x1 |
| 2712 | #define MT6325_RG_VCORE2_MODESET_SHIFT 15 |
| 2713 | #define MT6325_RG_VCORE2_NDIS_EN_MASK 0x1 |
| 2714 | #define MT6325_RG_VCORE2_NDIS_EN_SHIFT 0 |
| 2715 | #define MT6325_RG_VCORE2_CSM_MASK 0x3F |
| 2716 | #define MT6325_RG_VCORE2_CSM_SHIFT 1 |
| 2717 | #define MT6325_RG_VCORE2_RSV_MASK 0xFF |
| 2718 | #define MT6325_RG_VCORE2_RSV_SHIFT 7 |
| 2719 | #define MT6325_RG_VCORE2_PFM_RIP_MASK 0x7 |
| 2720 | #define MT6325_RG_VCORE2_PFM_RIP_SHIFT 0 |
| 2721 | #define MT6325_RG_VCORE2_TRAN_BST_MASK 0x3F |
| 2722 | #define MT6325_RG_VCORE2_TRAN_BST_SHIFT 3 |
| 2723 | #define MT6325_RG_VCORE2_DTS_ENB_MASK 0x1 |
| 2724 | #define MT6325_RG_VCORE2_DTS_ENB_SHIFT 9 |
| 2725 | #define MT6325_RG_VCORE2_RCL_TRIM_MASK 0x1F |
| 2726 | #define MT6325_RG_VCORE2_RCL_TRIM_SHIFT 10 |
| 2727 | #define MT6325_RG_VCORE2_RCL_TRIM_EN_MASK 0x1 |
| 2728 | #define MT6325_RG_VCORE2_RCL_TRIM_EN_SHIFT 15 |
| 2729 | #define MT6325_RG_VCORE2_C2_RSV_MASK 0x1 |
| 2730 | #define MT6325_RG_VCORE2_C2_RSV_SHIFT 0 |
| 2731 | #define MT6325_RG_VIO18_MIN_OFF_MASK 0x3 |
| 2732 | #define MT6325_RG_VIO18_MIN_OFF_SHIFT 0 |
| 2733 | #define MT6325_RG_VIO18_NVT_BUFF_OFF_EN_MASK 0x1 |
| 2734 | #define MT6325_RG_VIO18_NVT_BUFF_OFF_EN_SHIFT 2 |
| 2735 | #define MT6325_RG_VIO18_VRF18_SSTART_EN_MASK 0x1 |
| 2736 | #define MT6325_RG_VIO18_VRF18_SSTART_EN_SHIFT 3 |
| 2737 | #define MT6325_RG_VIO18_1P35UP_SEL_EN_MASK 0x1 |
| 2738 | #define MT6325_RG_VIO18_1P35UP_SEL_EN_SHIFT 4 |
| 2739 | #define MT6325_RG_VIO18_RZSEL_MASK 0x7 |
| 2740 | #define MT6325_RG_VIO18_RZSEL_SHIFT 5 |
| 2741 | #define MT6325_RG_VIO18_CC_MASK 0x3 |
| 2742 | #define MT6325_RG_VIO18_CC_SHIFT 8 |
| 2743 | #define MT6325_RG_VIO18_CSR_MASK 0x7 |
| 2744 | #define MT6325_RG_VIO18_CSR_SHIFT 10 |
| 2745 | #define MT6325_RG_VIO18_CSL_MASK 0xF |
| 2746 | #define MT6325_RG_VIO18_CSL_SHIFT 0 |
| 2747 | #define MT6325_RG_VIO18_SLP_MASK 0x7 |
| 2748 | #define MT6325_RG_VIO18_SLP_SHIFT 4 |
| 2749 | #define MT6325_RG_VIO18_ZX_OS_MASK 0x3 |
| 2750 | #define MT6325_RG_VIO18_ZX_OS_SHIFT 7 |
| 2751 | #define MT6325_RG_VIO18_MODESET_MASK 0x1 |
| 2752 | #define MT6325_RG_VIO18_MODESET_SHIFT 9 |
| 2753 | #define MT6325_RG_VIO18_NDIS_EN_MASK 0x1 |
| 2754 | #define MT6325_RG_VIO18_NDIS_EN_SHIFT 10 |
| 2755 | #define MT6325_RG_VIO18_CSM_MASK 0x3F |
| 2756 | #define MT6325_RG_VIO18_CSM_SHIFT 0 |
| 2757 | #define MT6325_RG_VIO18_RSV_MASK 0xFF |
| 2758 | #define MT6325_RG_VIO18_RSV_SHIFT 6 |
| 2759 | #define MT6325_RG_VIO18_ZXOS_TRIM_MASK 0x3F |
| 2760 | #define MT6325_RG_VIO18_ZXOS_TRIM_SHIFT 0 |
| 2761 | #define MT6325_RG_VIO18_PFM_RIP_MASK 0x7 |
| 2762 | #define MT6325_RG_VIO18_PFM_RIP_SHIFT 6 |
| 2763 | #define MT6325_RG_VIO18_TRAN_BST_MASK 0x3F |
| 2764 | #define MT6325_RG_VIO18_TRAN_BST_SHIFT 9 |
| 2765 | #define MT6325_RG_VIO18_DTS_ENB_MASK 0x1 |
| 2766 | #define MT6325_RG_VIO18_DTS_ENB_SHIFT 15 |
| 2767 | #define MT6325_RG_VIO18_RCL_TRIM_MASK 0x1F |
| 2768 | #define MT6325_RG_VIO18_RCL_TRIM_SHIFT 0 |
| 2769 | #define MT6325_RG_VIO18_RCL_TRIM_EN_MASK 0x1 |
| 2770 | #define MT6325_RG_VIO18_RCL_TRIM_EN_SHIFT 5 |
| 2771 | #define MT6325_RG_VIO18_C2_RSV_MASK 0x1 |
| 2772 | #define MT6325_RG_VIO18_C2_RSV_SHIFT 6 |
| 2773 | #define MT6325_RG_VRF1_MIN_OFF_MASK 0x3 |
| 2774 | #define MT6325_RG_VRF1_MIN_OFF_SHIFT 0 |
| 2775 | #define MT6325_RG_VRF18_0_NVT_BUFF_OFF_EN_MASK 0x1 |
| 2776 | #define MT6325_RG_VRF18_0_NVT_BUFF_OFF_EN_SHIFT 2 |
| 2777 | #define MT6325_RG_VRF18_0_SSTART_EN_MASK 0x1 |
| 2778 | #define MT6325_RG_VRF18_0_SSTART_EN_SHIFT 3 |
| 2779 | #define MT6325_RG_VRF18_0_1P35UP_SEL_EN_MASK 0x1 |
| 2780 | #define MT6325_RG_VRF18_0_1P35UP_SEL_EN_SHIFT 4 |
| 2781 | #define MT6325_RG_VRF18_0_RZSEL_MASK 0x7 |
| 2782 | #define MT6325_RG_VRF18_0_RZSEL_SHIFT 5 |
| 2783 | #define MT6325_RG_VRF18_0_CC_MASK 0x3 |
| 2784 | #define MT6325_RG_VRF18_0_CC_SHIFT 8 |
| 2785 | #define MT6325_RG_VRF18_0_CSR_MASK 0x7 |
| 2786 | #define MT6325_RG_VRF18_0_CSR_SHIFT 10 |
| 2787 | #define MT6325_RG_VRF18_0_CSL_MASK 0xF |
| 2788 | #define MT6325_RG_VRF18_0_CSL_SHIFT 0 |
| 2789 | #define MT6325_RG_VRF18_0_SLP_MASK 0x7 |
| 2790 | #define MT6325_RG_VRF18_0_SLP_SHIFT 4 |
| 2791 | #define MT6325_RG_VRF18_0_ZX_OS_MASK 0x3 |
| 2792 | #define MT6325_RG_VRF18_0_ZX_OS_SHIFT 7 |
| 2793 | #define MT6325_RG_VRF18_0_ZXOS_TRIM_MASK 0x3F |
| 2794 | #define MT6325_RG_VRF18_0_ZXOS_TRIM_SHIFT 9 |
| 2795 | #define MT6325_RG_VRF18_0_MODESET_MASK 0x1 |
| 2796 | #define MT6325_RG_VRF18_0_MODESET_SHIFT 15 |
| 2797 | #define MT6325_RG_VRF18_0_NDIS_EN_MASK 0x1 |
| 2798 | #define MT6325_RG_VRF18_0_NDIS_EN_SHIFT 0 |
| 2799 | #define MT6325_RG_VRF18_0_CSM_MASK 0x3F |
| 2800 | #define MT6325_RG_VRF18_0_CSM_SHIFT 1 |
| 2801 | #define MT6325_RG_VRF18_0_RSV_MASK 0xFF |
| 2802 | #define MT6325_RG_VRF18_0_RSV_SHIFT 7 |
| 2803 | #define MT6325_RG_VRF18_0_PFM_RIP_MASK 0x7 |
| 2804 | #define MT6325_RG_VRF18_0_PFM_RIP_SHIFT 0 |
| 2805 | #define MT6325_RG_VRF18_0_TRAN_BST_MASK 0x3F |
| 2806 | #define MT6325_RG_VRF18_0_TRAN_BST_SHIFT 3 |
| 2807 | #define MT6325_RG_VRF18_0_DTS_ENB_MASK 0x1 |
| 2808 | #define MT6325_RG_VRF18_0_DTS_ENB_SHIFT 9 |
| 2809 | #define MT6325_RG_VRF18_0_RCL_TRIM_MASK 0x1F |
| 2810 | #define MT6325_RG_VRF18_0_RCL_TRIM_SHIFT 10 |
| 2811 | #define MT6325_RG_VRF18_0_RCL_TRIM_EN_MASK 0x1 |
| 2812 | #define MT6325_RG_VRF18_0_RCL_TRIM_EN_SHIFT 15 |
| 2813 | #define MT6325_RG_VRF18_0_C2_RSV_MASK 0x1 |
| 2814 | #define MT6325_RG_VRF18_0_C2_RSV_SHIFT 0 |
| 2815 | #define MT6325_VDVFS11_DIG0_RSV0_MASK 0xFF |
| 2816 | #define MT6325_VDVFS11_DIG0_RSV0_SHIFT 8 |
| 2817 | #define MT6325_VDVFS11_EN_CTRL_MASK 0x1 |
| 2818 | #define MT6325_VDVFS11_EN_CTRL_SHIFT 0 |
| 2819 | #define MT6325_VDVFS11_VOSEL_CTRL_MASK 0x1 |
| 2820 | #define MT6325_VDVFS11_VOSEL_CTRL_SHIFT 1 |
| 2821 | #define MT6325_VDVFS11_DIG0_RSV1_MASK 0x1 |
| 2822 | #define MT6325_VDVFS11_DIG0_RSV1_SHIFT 2 |
| 2823 | #define MT6325_VDVFS11_DIG1_RSV1_MASK 0x1 |
| 2824 | #define MT6325_VDVFS11_DIG1_RSV1_SHIFT 3 |
| 2825 | #define MT6325_VDVFS11_EN_SEL_MASK 0x3 |
| 2826 | #define MT6325_VDVFS11_EN_SEL_SHIFT 0 |
| 2827 | #define MT6325_VDVFS11_VOSEL_SEL_MASK 0x3 |
| 2828 | #define MT6325_VDVFS11_VOSEL_SEL_SHIFT 4 |
| 2829 | #define MT6325_VDVFS11_DIG0_RSV2_MASK 0x3 |
| 2830 | #define MT6325_VDVFS11_DIG0_RSV2_SHIFT 8 |
| 2831 | #define MT6325_VDVFS11_DIG1_RSV2_MASK 0x3 |
| 2832 | #define MT6325_VDVFS11_DIG1_RSV2_SHIFT 12 |
| 2833 | #define MT6325_VDVFS11_EN_MASK 0x1 |
| 2834 | #define MT6325_VDVFS11_EN_SHIFT 0 |
| 2835 | #define MT6325_VDVFS11_STBTD_MASK 0x3 |
| 2836 | #define MT6325_VDVFS11_STBTD_SHIFT 4 |
| 2837 | #define MT6325_QI_VDVFS11_STB_MASK 0x1 |
| 2838 | #define MT6325_QI_VDVFS11_STB_SHIFT 12 |
| 2839 | #define MT6325_QI_VDVFS11_EN_MASK 0x1 |
| 2840 | #define MT6325_QI_VDVFS11_EN_SHIFT 13 |
| 2841 | #define MT6325_QI_VDVFS11_OC_STATUS_MASK 0x1 |
| 2842 | #define MT6325_QI_VDVFS11_OC_STATUS_SHIFT 15 |
| 2843 | #define MT6325_VDVFS11_SFCHG_FRATE_MASK 0x7F |
| 2844 | #define MT6325_VDVFS11_SFCHG_FRATE_SHIFT 0 |
| 2845 | #define MT6325_VDVFS11_SFCHG_FEN_MASK 0x1 |
| 2846 | #define MT6325_VDVFS11_SFCHG_FEN_SHIFT 7 |
| 2847 | #define MT6325_VDVFS11_SFCHG_RRATE_MASK 0x7F |
| 2848 | #define MT6325_VDVFS11_SFCHG_RRATE_SHIFT 8 |
| 2849 | #define MT6325_VDVFS11_SFCHG_REN_MASK 0x1 |
| 2850 | #define MT6325_VDVFS11_SFCHG_REN_SHIFT 15 |
| 2851 | #define MT6325_VDVFS11_VOSEL_MASK 0x7F |
| 2852 | #define MT6325_VDVFS11_VOSEL_SHIFT 0 |
| 2853 | #define MT6325_VDVFS11_VOSEL_ON_MASK 0x7F |
| 2854 | #define MT6325_VDVFS11_VOSEL_ON_SHIFT 0 |
| 2855 | #define MT6325_VDVFS11_VOSEL_SLEEP_MASK 0x7F |
| 2856 | #define MT6325_VDVFS11_VOSEL_SLEEP_SHIFT 0 |
| 2857 | #define MT6325_NI_VDVFS11_VOSEL_MASK 0x7F |
| 2858 | #define MT6325_NI_VDVFS11_VOSEL_SHIFT 0 |
| 2859 | #define MT6325_VDVFS11_TRANS_TD_MASK 0x3 |
| 2860 | #define MT6325_VDVFS11_TRANS_TD_SHIFT 0 |
| 2861 | #define MT6325_VDVFS11_TRANS_CTRL_MASK 0x3 |
| 2862 | #define MT6325_VDVFS11_TRANS_CTRL_SHIFT 4 |
| 2863 | #define MT6325_VDVFS11_TRANS_ONCE_MASK 0x1 |
| 2864 | #define MT6325_VDVFS11_TRANS_ONCE_SHIFT 6 |
| 2865 | #define MT6325_NI_VDVFS11_VOSEL_TRANS_MASK 0x1 |
| 2866 | #define MT6325_NI_VDVFS11_VOSEL_TRANS_SHIFT 7 |
| 2867 | #define MT6325_VDVFS11_VSLEEP_EN_MASK 0x1 |
| 2868 | #define MT6325_VDVFS11_VSLEEP_EN_SHIFT 8 |
| 2869 | #define MT6325_VDVFS11_R2R_PDN_MASK 0x1 |
| 2870 | #define MT6325_VDVFS11_R2R_PDN_SHIFT 10 |
| 2871 | #define MT6325_VDVFS11_VSLEEP_SEL_MASK 0x1 |
| 2872 | #define MT6325_VDVFS11_VSLEEP_SEL_SHIFT 11 |
| 2873 | #define MT6325_NI_VDVFS11_R2R_PDN_MASK 0x1 |
| 2874 | #define MT6325_NI_VDVFS11_R2R_PDN_SHIFT 14 |
| 2875 | #define MT6325_NI_VDVFS11_VSLEEP_SEL_MASK 0x1 |
| 2876 | #define MT6325_NI_VDVFS11_VSLEEP_SEL_SHIFT 15 |
| 2877 | #define MT6325_VDVFS12_DIG0_RSV0_MASK 0xFF |
| 2878 | #define MT6325_VDVFS12_DIG0_RSV0_SHIFT 8 |
| 2879 | #define MT6325_VDVFS12_EN_CTRL_MASK 0x1 |
| 2880 | #define MT6325_VDVFS12_EN_CTRL_SHIFT 0 |
| 2881 | #define MT6325_VDVFS12_VOSEL_CTRL_MASK 0x1 |
| 2882 | #define MT6325_VDVFS12_VOSEL_CTRL_SHIFT 1 |
| 2883 | #define MT6325_VDVFS12_DIG0_RSV1_MASK 0x1 |
| 2884 | #define MT6325_VDVFS12_DIG0_RSV1_SHIFT 2 |
| 2885 | #define MT6325_VDVFS12_DIG1_RSV1_MASK 0x1 |
| 2886 | #define MT6325_VDVFS12_DIG1_RSV1_SHIFT 3 |
| 2887 | #define MT6325_VDVFS12_EN_SEL_MASK 0x3 |
| 2888 | #define MT6325_VDVFS12_EN_SEL_SHIFT 0 |
| 2889 | #define MT6325_VDVFS12_VOSEL_SEL_MASK 0x3 |
| 2890 | #define MT6325_VDVFS12_VOSEL_SEL_SHIFT 4 |
| 2891 | #define MT6325_VDVFS12_DIG0_RSV2_MASK 0x3 |
| 2892 | #define MT6325_VDVFS12_DIG0_RSV2_SHIFT 8 |
| 2893 | #define MT6325_VDVFS12_DIG1_RSV2_MASK 0x3 |
| 2894 | #define MT6325_VDVFS12_DIG1_RSV2_SHIFT 12 |
| 2895 | #define MT6325_VDVFS12_EN_MASK 0x1 |
| 2896 | #define MT6325_VDVFS12_EN_SHIFT 0 |
| 2897 | #define MT6325_VDVFS12_STBTD_MASK 0x3 |
| 2898 | #define MT6325_VDVFS12_STBTD_SHIFT 4 |
| 2899 | #define MT6325_QI_VDVFS12_STB_MASK 0x1 |
| 2900 | #define MT6325_QI_VDVFS12_STB_SHIFT 12 |
| 2901 | #define MT6325_QI_VDVFS12_EN_MASK 0x1 |
| 2902 | #define MT6325_QI_VDVFS12_EN_SHIFT 13 |
| 2903 | #define MT6325_QI_VDVFS12_OC_STATUS_MASK 0x1 |
| 2904 | #define MT6325_QI_VDVFS12_OC_STATUS_SHIFT 15 |
| 2905 | #define MT6325_VDVFS12_SFCHG_FRATE_MASK 0x7F |
| 2906 | #define MT6325_VDVFS12_SFCHG_FRATE_SHIFT 0 |
| 2907 | #define MT6325_VDVFS12_SFCHG_FEN_MASK 0x1 |
| 2908 | #define MT6325_VDVFS12_SFCHG_FEN_SHIFT 7 |
| 2909 | #define MT6325_VDVFS12_SFCHG_RRATE_MASK 0x7F |
| 2910 | #define MT6325_VDVFS12_SFCHG_RRATE_SHIFT 8 |
| 2911 | #define MT6325_VDVFS12_SFCHG_REN_MASK 0x1 |
| 2912 | #define MT6325_VDVFS12_SFCHG_REN_SHIFT 15 |
| 2913 | #define MT6325_VDVFS12_VOSEL_MASK 0x7F |
| 2914 | #define MT6325_VDVFS12_VOSEL_SHIFT 0 |
| 2915 | #define MT6325_VDVFS12_VOSEL_ON_MASK 0x7F |
| 2916 | #define MT6325_VDVFS12_VOSEL_ON_SHIFT 0 |
| 2917 | #define MT6325_VDVFS12_VOSEL_SLEEP_MASK 0x7F |
| 2918 | #define MT6325_VDVFS12_VOSEL_SLEEP_SHIFT 0 |
| 2919 | #define MT6325_NI_VDVFS12_VOSEL_MASK 0x7F |
| 2920 | #define MT6325_NI_VDVFS12_VOSEL_SHIFT 0 |
| 2921 | #define MT6325_VDVFS12_TRANS_TD_MASK 0x3 |
| 2922 | #define MT6325_VDVFS12_TRANS_TD_SHIFT 0 |
| 2923 | #define MT6325_VDVFS12_TRANS_CTRL_MASK 0x3 |
| 2924 | #define MT6325_VDVFS12_TRANS_CTRL_SHIFT 4 |
| 2925 | #define MT6325_VDVFS12_TRANS_ONCE_MASK 0x1 |
| 2926 | #define MT6325_VDVFS12_TRANS_ONCE_SHIFT 6 |
| 2927 | #define MT6325_NI_VDVFS12_VOSEL_TRANS_MASK 0x1 |
| 2928 | #define MT6325_NI_VDVFS12_VOSEL_TRANS_SHIFT 7 |
| 2929 | #define MT6325_VDVFS12_VSLEEP_EN_MASK 0x1 |
| 2930 | #define MT6325_VDVFS12_VSLEEP_EN_SHIFT 8 |
| 2931 | #define MT6325_VDVFS12_R2R_PDN_MASK 0x1 |
| 2932 | #define MT6325_VDVFS12_R2R_PDN_SHIFT 10 |
| 2933 | #define MT6325_VDVFS12_VSLEEP_SEL_MASK 0x1 |
| 2934 | #define MT6325_VDVFS12_VSLEEP_SEL_SHIFT 11 |
| 2935 | #define MT6325_NI_VDVFS12_R2R_PDN_MASK 0x1 |
| 2936 | #define MT6325_NI_VDVFS12_R2R_PDN_SHIFT 14 |
| 2937 | #define MT6325_NI_VDVFS12_VSLEEP_SEL_MASK 0x1 |
| 2938 | #define MT6325_NI_VDVFS12_VSLEEP_SEL_SHIFT 15 |
| 2939 | #define MT6325_VSRAM_DVFS1_DIG0_RSV0_MASK 0xFF |
| 2940 | #define MT6325_VSRAM_DVFS1_DIG0_RSV0_SHIFT 8 |
| 2941 | #define MT6325_VSRAM_DVFS1_EN_CTRL_MASK 0x1 |
| 2942 | #define MT6325_VSRAM_DVFS1_EN_CTRL_SHIFT 0 |
| 2943 | #define MT6325_VSRAM_DVFS1_VOSEL_CTRL_MASK 0x1 |
| 2944 | #define MT6325_VSRAM_DVFS1_VOSEL_CTRL_SHIFT 1 |
| 2945 | #define MT6325_VSRAM_DVFS1_DIG0_RSV1_MASK 0x1 |
| 2946 | #define MT6325_VSRAM_DVFS1_DIG0_RSV1_SHIFT 2 |
| 2947 | #define MT6325_VSRAM_DVFS1_DIG1_RSV1_MASK 0x1 |
| 2948 | #define MT6325_VSRAM_DVFS1_DIG1_RSV1_SHIFT 3 |
| 2949 | #define MT6325_VSRAM_DVFS1_EN_SEL_MASK 0x3 |
| 2950 | #define MT6325_VSRAM_DVFS1_EN_SEL_SHIFT 0 |
| 2951 | #define MT6325_VSRAM_DVFS1_VOSEL_SEL_MASK 0x3 |
| 2952 | #define MT6325_VSRAM_DVFS1_VOSEL_SEL_SHIFT 4 |
| 2953 | #define MT6325_VSRAM_DVFS1_DIG0_RSV2_MASK 0x3 |
| 2954 | #define MT6325_VSRAM_DVFS1_DIG0_RSV2_SHIFT 8 |
| 2955 | #define MT6325_VSRAM_DVFS1_DIG1_RSV2_MASK 0x3 |
| 2956 | #define MT6325_VSRAM_DVFS1_DIG1_RSV2_SHIFT 12 |
| 2957 | #define MT6325_VSRAM_DVFS1_EN_MASK 0x1 |
| 2958 | #define MT6325_VSRAM_DVFS1_EN_SHIFT 0 |
| 2959 | #define MT6325_VSRAM_DVFS1_STBTD_MASK 0x3 |
| 2960 | #define MT6325_VSRAM_DVFS1_STBTD_SHIFT 4 |
| 2961 | #define MT6325_VSRAM_DVFS1_DIG0_RSV4_MASK 0x1 |
| 2962 | #define MT6325_VSRAM_DVFS1_DIG0_RSV4_SHIFT 12 |
| 2963 | #define MT6325_VSRAM_DVFS1_DIG0_RSV3_MASK 0x1 |
| 2964 | #define MT6325_VSRAM_DVFS1_DIG0_RSV3_SHIFT 13 |
| 2965 | #define MT6325_QI_VSRAM_DVFS1_OC_STATUS_MASK 0x1 |
| 2966 | #define MT6325_QI_VSRAM_DVFS1_OC_STATUS_SHIFT 15 |
| 2967 | #define MT6325_VSRAM_DVFS1_SFCHG_FRATE_MASK 0x7F |
| 2968 | #define MT6325_VSRAM_DVFS1_SFCHG_FRATE_SHIFT 0 |
| 2969 | #define MT6325_VSRAM_DVFS1_SFCHG_FEN_MASK 0x1 |
| 2970 | #define MT6325_VSRAM_DVFS1_SFCHG_FEN_SHIFT 7 |
| 2971 | #define MT6325_VSRAM_DVFS1_SFCHG_RRATE_MASK 0x7F |
| 2972 | #define MT6325_VSRAM_DVFS1_SFCHG_RRATE_SHIFT 8 |
| 2973 | #define MT6325_VSRAM_DVFS1_SFCHG_REN_MASK 0x1 |
| 2974 | #define MT6325_VSRAM_DVFS1_SFCHG_REN_SHIFT 15 |
| 2975 | #define MT6325_VSRAM_DVFS1_VOSEL_RSV_MASK 0x7F |
| 2976 | #define MT6325_VSRAM_DVFS1_VOSEL_RSV_SHIFT 0 |
| 2977 | #define MT6325_VSRAM_DVFS1_VOSEL_ON_MASK 0x7F |
| 2978 | #define MT6325_VSRAM_DVFS1_VOSEL_ON_SHIFT 0 |
| 2979 | #define MT6325_VSRAM_DVFS1_VOSEL_SLEEP_MASK 0x7F |
| 2980 | #define MT6325_VSRAM_DVFS1_VOSEL_SLEEP_SHIFT 0 |
| 2981 | #define MT6325_NI_VSRAM_DVFS1_VOSEL_MASK 0x7F |
| 2982 | #define MT6325_NI_VSRAM_DVFS1_VOSEL_SHIFT 0 |
| 2983 | #define MT6325_VSRAM_DVFS1_TRANS_TD_MASK 0x3 |
| 2984 | #define MT6325_VSRAM_DVFS1_TRANS_TD_SHIFT 0 |
| 2985 | #define MT6325_VSRAM_DVFS1_TRANS_CTRL_MASK 0x3 |
| 2986 | #define MT6325_VSRAM_DVFS1_TRANS_CTRL_SHIFT 4 |
| 2987 | #define MT6325_VSRAM_DVFS1_TRANS_ONCE_MASK 0x1 |
| 2988 | #define MT6325_VSRAM_DVFS1_TRANS_ONCE_SHIFT 6 |
| 2989 | #define MT6325_NI_VSRAM_DVFS1_VOSEL_TRANS_MASK 0x1 |
| 2990 | #define MT6325_NI_VSRAM_DVFS1_VOSEL_TRANS_SHIFT 7 |
| 2991 | #define MT6325_VSRAM_DVFS1_VSLEEP_EN_MASK 0x1 |
| 2992 | #define MT6325_VSRAM_DVFS1_VSLEEP_EN_SHIFT 8 |
| 2993 | #define MT6325_VSRAM_DVFS1_R2R_PDN_MASK 0x1 |
| 2994 | #define MT6325_VSRAM_DVFS1_R2R_PDN_SHIFT 10 |
| 2995 | #define MT6325_VSRAM_DVFS1_VSLEEP_SEL_MASK 0x1 |
| 2996 | #define MT6325_VSRAM_DVFS1_VSLEEP_SEL_SHIFT 11 |
| 2997 | #define MT6325_NI_VSRAM_DVFS1_R2R_PDN_MASK 0x1 |
| 2998 | #define MT6325_NI_VSRAM_DVFS1_R2R_PDN_SHIFT 14 |
| 2999 | #define MT6325_NI_VSRAM_DVFS1_VSLEEP_SEL_MASK 0x1 |
| 3000 | #define MT6325_NI_VSRAM_DVFS1_VSLEEP_SEL_SHIFT 15 |
| 3001 | #define MT6325_VDRAM_DIG0_RSV0_MASK 0xFF |
| 3002 | #define MT6325_VDRAM_DIG0_RSV0_SHIFT 8 |
| 3003 | #define MT6325_VDRAM_EN_CTRL_MASK 0x1 |
| 3004 | #define MT6325_VDRAM_EN_CTRL_SHIFT 0 |
| 3005 | #define MT6325_VDRAM_VOSEL_CTRL_MASK 0x1 |
| 3006 | #define MT6325_VDRAM_VOSEL_CTRL_SHIFT 1 |
| 3007 | #define MT6325_VDRAM_DIG0_RSV1_MASK 0x1 |
| 3008 | #define MT6325_VDRAM_DIG0_RSV1_SHIFT 2 |
| 3009 | #define MT6325_VDRAM_BURST_CTRL_MASK 0x1 |
| 3010 | #define MT6325_VDRAM_BURST_CTRL_SHIFT 3 |
| 3011 | #define MT6325_VDRAM_EN_SEL_MASK 0x3 |
| 3012 | #define MT6325_VDRAM_EN_SEL_SHIFT 0 |
| 3013 | #define MT6325_VDRAM_VOSEL_SEL_MASK 0x3 |
| 3014 | #define MT6325_VDRAM_VOSEL_SEL_SHIFT 4 |
| 3015 | #define MT6325_VDRAM_DIG0_RSV2_MASK 0x3 |
| 3016 | #define MT6325_VDRAM_DIG0_RSV2_SHIFT 8 |
| 3017 | #define MT6325_VDRAM_BURST_SEL_MASK 0x3 |
| 3018 | #define MT6325_VDRAM_BURST_SEL_SHIFT 12 |
| 3019 | #define MT6325_VDRAM_EN_MASK 0x1 |
| 3020 | #define MT6325_VDRAM_EN_SHIFT 0 |
| 3021 | #define MT6325_VDRAM_STBTD_MASK 0x3 |
| 3022 | #define MT6325_VDRAM_STBTD_SHIFT 4 |
| 3023 | #define MT6325_QI_VDRAM_STB_MASK 0x1 |
| 3024 | #define MT6325_QI_VDRAM_STB_SHIFT 12 |
| 3025 | #define MT6325_QI_VDRAM_EN_MASK 0x1 |
| 3026 | #define MT6325_QI_VDRAM_EN_SHIFT 13 |
| 3027 | #define MT6325_QI_VDRAM_OC_STATUS_MASK 0x1 |
| 3028 | #define MT6325_QI_VDRAM_OC_STATUS_SHIFT 15 |
| 3029 | #define MT6325_VDRAM_SFCHG_FRATE_MASK 0x7F |
| 3030 | #define MT6325_VDRAM_SFCHG_FRATE_SHIFT 0 |
| 3031 | #define MT6325_VDRAM_SFCHG_FEN_MASK 0x1 |
| 3032 | #define MT6325_VDRAM_SFCHG_FEN_SHIFT 7 |
| 3033 | #define MT6325_VDRAM_SFCHG_RRATE_MASK 0x7F |
| 3034 | #define MT6325_VDRAM_SFCHG_RRATE_SHIFT 8 |
| 3035 | #define MT6325_VDRAM_SFCHG_REN_MASK 0x1 |
| 3036 | #define MT6325_VDRAM_SFCHG_REN_SHIFT 15 |
| 3037 | #define MT6325_VDRAM_VOSEL_MASK 0x7F |
| 3038 | #define MT6325_VDRAM_VOSEL_SHIFT 0 |
| 3039 | #define MT6325_VDRAM_VOSEL_ON_MASK 0x7F |
| 3040 | #define MT6325_VDRAM_VOSEL_ON_SHIFT 0 |
| 3041 | #define MT6325_VDRAM_VOSEL_SLEEP_MASK 0x7F |
| 3042 | #define MT6325_VDRAM_VOSEL_SLEEP_SHIFT 0 |
| 3043 | #define MT6325_NI_VDRAM_VOSEL_MASK 0x7F |
| 3044 | #define MT6325_NI_VDRAM_VOSEL_SHIFT 0 |
| 3045 | #define MT6325_VDRAM_BURST_MASK 0x7 |
| 3046 | #define MT6325_VDRAM_BURST_SHIFT 0 |
| 3047 | #define MT6325_VDRAM_BURST_ON_MASK 0x7 |
| 3048 | #define MT6325_VDRAM_BURST_ON_SHIFT 4 |
| 3049 | #define MT6325_VDRAM_BURST_SLEEP_MASK 0x7 |
| 3050 | #define MT6325_VDRAM_BURST_SLEEP_SHIFT 8 |
| 3051 | #define MT6325_QI_VDRAM_BURST_MASK 0x7 |
| 3052 | #define MT6325_QI_VDRAM_BURST_SHIFT 12 |
| 3053 | #define MT6325_VDRAM_TRANS_TD_MASK 0x3 |
| 3054 | #define MT6325_VDRAM_TRANS_TD_SHIFT 0 |
| 3055 | #define MT6325_VDRAM_TRANS_CTRL_MASK 0x3 |
| 3056 | #define MT6325_VDRAM_TRANS_CTRL_SHIFT 4 |
| 3057 | #define MT6325_VDRAM_TRANS_ONCE_MASK 0x1 |
| 3058 | #define MT6325_VDRAM_TRANS_ONCE_SHIFT 6 |
| 3059 | #define MT6325_NI_VDRAM_VOSEL_TRANS_MASK 0x1 |
| 3060 | #define MT6325_NI_VDRAM_VOSEL_TRANS_SHIFT 7 |
| 3061 | #define MT6325_VDRAM_VSLEEP_EN_MASK 0x1 |
| 3062 | #define MT6325_VDRAM_VSLEEP_EN_SHIFT 8 |
| 3063 | #define MT6325_VDRAM_R2R_PDN_MASK 0x1 |
| 3064 | #define MT6325_VDRAM_R2R_PDN_SHIFT 10 |
| 3065 | #define MT6325_VDRAM_VSLEEP_SEL_MASK 0x1 |
| 3066 | #define MT6325_VDRAM_VSLEEP_SEL_SHIFT 11 |
| 3067 | #define MT6325_NI_VDRAM_R2R_PDN_MASK 0x1 |
| 3068 | #define MT6325_NI_VDRAM_R2R_PDN_SHIFT 14 |
| 3069 | #define MT6325_NI_VDRAM_VSLEEP_SEL_MASK 0x1 |
| 3070 | #define MT6325_NI_VDRAM_VSLEEP_SEL_SHIFT 15 |
| 3071 | #define MT6325_VRF18_0_DIG0_RSV0_MASK 0xFF |
| 3072 | #define MT6325_VRF18_0_DIG0_RSV0_SHIFT 8 |
| 3073 | #define MT6325_VRF18_0_EN_CTRL_MASK 0x1 |
| 3074 | #define MT6325_VRF18_0_EN_CTRL_SHIFT 0 |
| 3075 | #define MT6325_VRF18_0_VOSEL_CTRL_MASK 0x1 |
| 3076 | #define MT6325_VRF18_0_VOSEL_CTRL_SHIFT 1 |
| 3077 | #define MT6325_VRF18_0_DIG0_RSV1_MASK 0x1 |
| 3078 | #define MT6325_VRF18_0_DIG0_RSV1_SHIFT 2 |
| 3079 | #define MT6325_VRF18_0_BURST_CTRL_MASK 0x1 |
| 3080 | #define MT6325_VRF18_0_BURST_CTRL_SHIFT 3 |
| 3081 | #define MT6325_VRF18_0_EN_SEL_MASK 0x3 |
| 3082 | #define MT6325_VRF18_0_EN_SEL_SHIFT 0 |
| 3083 | #define MT6325_VRF18_0_VOSEL_SEL_MASK 0x3 |
| 3084 | #define MT6325_VRF18_0_VOSEL_SEL_SHIFT 4 |
| 3085 | #define MT6325_VRF18_0_DIG0_RSV2_MASK 0x3 |
| 3086 | #define MT6325_VRF18_0_DIG0_RSV2_SHIFT 8 |
| 3087 | #define MT6325_VRF18_0_BURST_SEL_MASK 0x3 |
| 3088 | #define MT6325_VRF18_0_BURST_SEL_SHIFT 12 |
| 3089 | #define MT6325_VRF18_0_EN_MASK 0x1 |
| 3090 | #define MT6325_VRF18_0_EN_SHIFT 0 |
| 3091 | #define MT6325_VRF18_0_STBTD_MASK 0x3 |
| 3092 | #define MT6325_VRF18_0_STBTD_SHIFT 4 |
| 3093 | #define MT6325_QI_VRF18_0_STB_MASK 0x1 |
| 3094 | #define MT6325_QI_VRF18_0_STB_SHIFT 12 |
| 3095 | #define MT6325_QI_VRF18_0_EN_MASK 0x1 |
| 3096 | #define MT6325_QI_VRF18_0_EN_SHIFT 13 |
| 3097 | #define MT6325_QI_VRF18_0_OC_STATUS_MASK 0x1 |
| 3098 | #define MT6325_QI_VRF18_0_OC_STATUS_SHIFT 15 |
| 3099 | #define MT6325_VRF18_0_SFCHG_FRATE_MASK 0x7F |
| 3100 | #define MT6325_VRF18_0_SFCHG_FRATE_SHIFT 0 |
| 3101 | #define MT6325_VRF18_0_SFCHG_FEN_MASK 0x1 |
| 3102 | #define MT6325_VRF18_0_SFCHG_FEN_SHIFT 7 |
| 3103 | #define MT6325_VRF18_0_SFCHG_RRATE_MASK 0x7F |
| 3104 | #define MT6325_VRF18_0_SFCHG_RRATE_SHIFT 8 |
| 3105 | #define MT6325_VRF18_0_SFCHG_REN_MASK 0x1 |
| 3106 | #define MT6325_VRF18_0_SFCHG_REN_SHIFT 15 |
| 3107 | #define MT6325_VRF18_0_VOSEL_MASK 0x7F |
| 3108 | #define MT6325_VRF18_0_VOSEL_SHIFT 0 |
| 3109 | #define MT6325_VRF18_0_VOSEL_ON_MASK 0x7F |
| 3110 | #define MT6325_VRF18_0_VOSEL_ON_SHIFT 0 |
| 3111 | #define MT6325_VRF18_0_VOSEL_SLEEP_MASK 0x7F |
| 3112 | #define MT6325_VRF18_0_VOSEL_SLEEP_SHIFT 0 |
| 3113 | #define MT6325_NI_VRF18_0_VOSEL_MASK 0x7F |
| 3114 | #define MT6325_NI_VRF18_0_VOSEL_SHIFT 0 |
| 3115 | #define MT6325_VRF18_0_BURST_MASK 0x7 |
| 3116 | #define MT6325_VRF18_0_BURST_SHIFT 0 |
| 3117 | #define MT6325_VRF18_0_BURST_ON_MASK 0x7 |
| 3118 | #define MT6325_VRF18_0_BURST_ON_SHIFT 4 |
| 3119 | #define MT6325_VRF18_0_BURST_SLEEP_MASK 0x7 |
| 3120 | #define MT6325_VRF18_0_BURST_SLEEP_SHIFT 8 |
| 3121 | #define MT6325_QI_VRF18_0_BURST_MASK 0x7 |
| 3122 | #define MT6325_QI_VRF18_0_BURST_SHIFT 12 |
| 3123 | #define MT6325_VRF18_0_TRANS_TD_MASK 0x3 |
| 3124 | #define MT6325_VRF18_0_TRANS_TD_SHIFT 0 |
| 3125 | #define MT6325_VRF18_0_TRANS_CTRL_MASK 0x3 |
| 3126 | #define MT6325_VRF18_0_TRANS_CTRL_SHIFT 4 |
| 3127 | #define MT6325_VRF18_0_TRANS_ONCE_MASK 0x1 |
| 3128 | #define MT6325_VRF18_0_TRANS_ONCE_SHIFT 6 |
| 3129 | #define MT6325_NI_VRF18_0_VOSEL_TRANS_MASK 0x1 |
| 3130 | #define MT6325_NI_VRF18_0_VOSEL_TRANS_SHIFT 7 |
| 3131 | #define MT6325_VRF18_0_VSLEEP_EN_MASK 0x1 |
| 3132 | #define MT6325_VRF18_0_VSLEEP_EN_SHIFT 8 |
| 3133 | #define MT6325_VRF18_0_R2R_PDN_MASK 0x1 |
| 3134 | #define MT6325_VRF18_0_R2R_PDN_SHIFT 10 |
| 3135 | #define MT6325_VRF18_0_VSLEEP_SEL_MASK 0x1 |
| 3136 | #define MT6325_VRF18_0_VSLEEP_SEL_SHIFT 11 |
| 3137 | #define MT6325_NI_VRF18_0_R2R_PDN_MASK 0x1 |
| 3138 | #define MT6325_NI_VRF18_0_R2R_PDN_SHIFT 14 |
| 3139 | #define MT6325_NI_VRF18_0_VSLEEP_SEL_MASK 0x1 |
| 3140 | #define MT6325_NI_VRF18_0_VSLEEP_SEL_SHIFT 15 |
| 3141 | #define MT6325_VGPU_DIG0_RSV0_MASK 0xFF |
| 3142 | #define MT6325_VGPU_DIG0_RSV0_SHIFT 8 |
| 3143 | #define MT6325_VGPU_EN_CTRL_MASK 0x1 |
| 3144 | #define MT6325_VGPU_EN_CTRL_SHIFT 0 |
| 3145 | #define MT6325_VGPU_VOSEL_CTRL_MASK 0x1 |
| 3146 | #define MT6325_VGPU_VOSEL_CTRL_SHIFT 1 |
| 3147 | #define MT6325_VGPU_DLC_CTRL_MASK 0x1 |
| 3148 | #define MT6325_VGPU_DLC_CTRL_SHIFT 2 |
| 3149 | #define MT6325_VGPU_BURST_CTRL_MASK 0x1 |
| 3150 | #define MT6325_VGPU_BURST_CTRL_SHIFT 3 |
| 3151 | #define MT6325_VGPU_EN_SEL_MASK 0x3 |
| 3152 | #define MT6325_VGPU_EN_SEL_SHIFT 0 |
| 3153 | #define MT6325_VGPU_VOSEL_SEL_MASK 0x3 |
| 3154 | #define MT6325_VGPU_VOSEL_SEL_SHIFT 4 |
| 3155 | #define MT6325_VGPU_DLC_SEL_MASK 0x3 |
| 3156 | #define MT6325_VGPU_DLC_SEL_SHIFT 8 |
| 3157 | #define MT6325_VGPU_BURST_SEL_MASK 0x3 |
| 3158 | #define MT6325_VGPU_BURST_SEL_SHIFT 12 |
| 3159 | #define MT6325_VGPU_EN_MASK 0x1 |
| 3160 | #define MT6325_VGPU_EN_SHIFT 0 |
| 3161 | #define MT6325_VGPU_STBTD_MASK 0x3 |
| 3162 | #define MT6325_VGPU_STBTD_SHIFT 4 |
| 3163 | #define MT6325_QI_VGPU_STB_MASK 0x1 |
| 3164 | #define MT6325_QI_VGPU_STB_SHIFT 12 |
| 3165 | #define MT6325_QI_VGPU_EN_MASK 0x1 |
| 3166 | #define MT6325_QI_VGPU_EN_SHIFT 13 |
| 3167 | #define MT6325_QI_VGPU_OC_STATUS_MASK 0x1 |
| 3168 | #define MT6325_QI_VGPU_OC_STATUS_SHIFT 15 |
| 3169 | #define MT6325_VGPU_SFCHG_FRATE_MASK 0x7F |
| 3170 | #define MT6325_VGPU_SFCHG_FRATE_SHIFT 0 |
| 3171 | #define MT6325_VGPU_SFCHG_FEN_MASK 0x1 |
| 3172 | #define MT6325_VGPU_SFCHG_FEN_SHIFT 7 |
| 3173 | #define MT6325_VGPU_SFCHG_RRATE_MASK 0x7F |
| 3174 | #define MT6325_VGPU_SFCHG_RRATE_SHIFT 8 |
| 3175 | #define MT6325_VGPU_SFCHG_REN_MASK 0x1 |
| 3176 | #define MT6325_VGPU_SFCHG_REN_SHIFT 15 |
| 3177 | #define MT6325_VGPU_VOSEL_MASK 0x7F |
| 3178 | #define MT6325_VGPU_VOSEL_SHIFT 0 |
| 3179 | #define MT6325_VGPU_VOSEL_ON_MASK 0x7F |
| 3180 | #define MT6325_VGPU_VOSEL_ON_SHIFT 0 |
| 3181 | #define MT6325_VGPU_VOSEL_SLEEP_MASK 0x7F |
| 3182 | #define MT6325_VGPU_VOSEL_SLEEP_SHIFT 0 |
| 3183 | #define MT6325_NI_VGPU_VOSEL_MASK 0x7F |
| 3184 | #define MT6325_NI_VGPU_VOSEL_SHIFT 0 |
| 3185 | #define MT6325_VGPU_BURST_MASK 0x7 |
| 3186 | #define MT6325_VGPU_BURST_SHIFT 0 |
| 3187 | #define MT6325_VGPU_BURST_ON_MASK 0x7 |
| 3188 | #define MT6325_VGPU_BURST_ON_SHIFT 4 |
| 3189 | #define MT6325_VGPU_BURST_SLEEP_MASK 0x7 |
| 3190 | #define MT6325_VGPU_BURST_SLEEP_SHIFT 8 |
| 3191 | #define MT6325_QI_VGPU_BURST_MASK 0x7 |
| 3192 | #define MT6325_QI_VGPU_BURST_SHIFT 12 |
| 3193 | #define MT6325_VGPU_DLC_MASK 0x3 |
| 3194 | #define MT6325_VGPU_DLC_SHIFT 0 |
| 3195 | #define MT6325_VGPU_DLC_ON_MASK 0x3 |
| 3196 | #define MT6325_VGPU_DLC_ON_SHIFT 4 |
| 3197 | #define MT6325_VGPU_DLC_SLEEP_MASK 0x3 |
| 3198 | #define MT6325_VGPU_DLC_SLEEP_SHIFT 8 |
| 3199 | #define MT6325_QI_VGPU_DLC_MASK 0x3 |
| 3200 | #define MT6325_QI_VGPU_DLC_SHIFT 12 |
| 3201 | #define MT6325_VGPU_DLC_N_MASK 0x3 |
| 3202 | #define MT6325_VGPU_DLC_N_SHIFT 0 |
| 3203 | #define MT6325_VGPU_DLC_N_ON_MASK 0x3 |
| 3204 | #define MT6325_VGPU_DLC_N_ON_SHIFT 4 |
| 3205 | #define MT6325_VGPU_DLC_N_SLEEP_MASK 0x3 |
| 3206 | #define MT6325_VGPU_DLC_N_SLEEP_SHIFT 8 |
| 3207 | #define MT6325_QI_VGPU_DLC_N_MASK 0x3 |
| 3208 | #define MT6325_QI_VGPU_DLC_N_SHIFT 12 |
| 3209 | #define MT6325_VGPU_TRANS_TD_MASK 0x3 |
| 3210 | #define MT6325_VGPU_TRANS_TD_SHIFT 0 |
| 3211 | #define MT6325_VGPU_TRANS_CTRL_MASK 0x3 |
| 3212 | #define MT6325_VGPU_TRANS_CTRL_SHIFT 4 |
| 3213 | #define MT6325_VGPU_TRANS_ONCE_MASK 0x1 |
| 3214 | #define MT6325_VGPU_TRANS_ONCE_SHIFT 6 |
| 3215 | #define MT6325_NI_VGPU_VOSEL_TRANS_MASK 0x1 |
| 3216 | #define MT6325_NI_VGPU_VOSEL_TRANS_SHIFT 7 |
| 3217 | #define MT6325_VGPU_VSLEEP_EN_MASK 0x1 |
| 3218 | #define MT6325_VGPU_VSLEEP_EN_SHIFT 8 |
| 3219 | #define MT6325_VGPU_R2R_PDN_MASK 0x1 |
| 3220 | #define MT6325_VGPU_R2R_PDN_SHIFT 10 |
| 3221 | #define MT6325_VGPU_VSLEEP_SEL_MASK 0x1 |
| 3222 | #define MT6325_VGPU_VSLEEP_SEL_SHIFT 11 |
| 3223 | #define MT6325_NI_VGPU_R2R_PDN_MASK 0x1 |
| 3224 | #define MT6325_NI_VGPU_R2R_PDN_SHIFT 14 |
| 3225 | #define MT6325_NI_VGPU_VSLEEP_SEL_MASK 0x1 |
| 3226 | #define MT6325_NI_VGPU_VSLEEP_SEL_SHIFT 15 |
| 3227 | #define MT6325_VCORE1_DIG0_RSV0_MASK 0xFF |
| 3228 | #define MT6325_VCORE1_DIG0_RSV0_SHIFT 8 |
| 3229 | #define MT6325_VCORE1_EN_CTRL_MASK 0x1 |
| 3230 | #define MT6325_VCORE1_EN_CTRL_SHIFT 0 |
| 3231 | #define MT6325_VCORE1_VOSEL_CTRL_MASK 0x1 |
| 3232 | #define MT6325_VCORE1_VOSEL_CTRL_SHIFT 1 |
| 3233 | #define MT6325_VCORE1_DLC_CTRL_MASK 0x1 |
| 3234 | #define MT6325_VCORE1_DLC_CTRL_SHIFT 2 |
| 3235 | #define MT6325_VCORE1_BURST_CTRL_MASK 0x1 |
| 3236 | #define MT6325_VCORE1_BURST_CTRL_SHIFT 3 |
| 3237 | #define MT6325_VCORE1_EN_SEL_MASK 0x3 |
| 3238 | #define MT6325_VCORE1_EN_SEL_SHIFT 0 |
| 3239 | #define MT6325_VCORE1_VOSEL_SEL_MASK 0x3 |
| 3240 | #define MT6325_VCORE1_VOSEL_SEL_SHIFT 4 |
| 3241 | #define MT6325_VCORE1_DLC_SEL_MASK 0x3 |
| 3242 | #define MT6325_VCORE1_DLC_SEL_SHIFT 8 |
| 3243 | #define MT6325_VCORE1_BURST_SEL_MASK 0x3 |
| 3244 | #define MT6325_VCORE1_BURST_SEL_SHIFT 12 |
| 3245 | #define MT6325_VCORE1_EN_MASK 0x1 |
| 3246 | #define MT6325_VCORE1_EN_SHIFT 0 |
| 3247 | #define MT6325_VCORE1_STBTD_MASK 0x3 |
| 3248 | #define MT6325_VCORE1_STBTD_SHIFT 4 |
| 3249 | #define MT6325_QI_VCORE1_STB_MASK 0x1 |
| 3250 | #define MT6325_QI_VCORE1_STB_SHIFT 12 |
| 3251 | #define MT6325_QI_VCORE1_EN_MASK 0x1 |
| 3252 | #define MT6325_QI_VCORE1_EN_SHIFT 13 |
| 3253 | #define MT6325_QI_VCORE1_OC_STATUS_MASK 0x1 |
| 3254 | #define MT6325_QI_VCORE1_OC_STATUS_SHIFT 15 |
| 3255 | #define MT6325_VCORE1_SFCHG_FRATE_MASK 0x7F |
| 3256 | #define MT6325_VCORE1_SFCHG_FRATE_SHIFT 0 |
| 3257 | #define MT6325_VCORE1_SFCHG_FEN_MASK 0x1 |
| 3258 | #define MT6325_VCORE1_SFCHG_FEN_SHIFT 7 |
| 3259 | #define MT6325_VCORE1_SFCHG_RRATE_MASK 0x7F |
| 3260 | #define MT6325_VCORE1_SFCHG_RRATE_SHIFT 8 |
| 3261 | #define MT6325_VCORE1_SFCHG_REN_MASK 0x1 |
| 3262 | #define MT6325_VCORE1_SFCHG_REN_SHIFT 15 |
| 3263 | #define MT6325_VCORE1_VOSEL_MASK 0x7F |
| 3264 | #define MT6325_VCORE1_VOSEL_SHIFT 0 |
| 3265 | #define MT6325_VCORE1_VOSEL_ON_MASK 0x7F |
| 3266 | #define MT6325_VCORE1_VOSEL_ON_SHIFT 0 |
| 3267 | #define MT6325_VCORE1_VOSEL_SLEEP_MASK 0x7F |
| 3268 | #define MT6325_VCORE1_VOSEL_SLEEP_SHIFT 0 |
| 3269 | #define MT6325_NI_VCORE1_VOSEL_MASK 0x7F |
| 3270 | #define MT6325_NI_VCORE1_VOSEL_SHIFT 0 |
| 3271 | #define MT6325_VCORE1_BURST_MASK 0x7 |
| 3272 | #define MT6325_VCORE1_BURST_SHIFT 0 |
| 3273 | #define MT6325_VCORE1_BURST_ON_MASK 0x7 |
| 3274 | #define MT6325_VCORE1_BURST_ON_SHIFT 4 |
| 3275 | #define MT6325_VCORE1_BURST_SLEEP_MASK 0x7 |
| 3276 | #define MT6325_VCORE1_BURST_SLEEP_SHIFT 8 |
| 3277 | #define MT6325_QI_VCORE1_BURST_MASK 0x7 |
| 3278 | #define MT6325_QI_VCORE1_BURST_SHIFT 12 |
| 3279 | #define MT6325_VCORE1_DLC_MASK 0x3 |
| 3280 | #define MT6325_VCORE1_DLC_SHIFT 0 |
| 3281 | #define MT6325_VCORE1_DLC_ON_MASK 0x3 |
| 3282 | #define MT6325_VCORE1_DLC_ON_SHIFT 4 |
| 3283 | #define MT6325_VCORE1_DLC_SLEEP_MASK 0x3 |
| 3284 | #define MT6325_VCORE1_DLC_SLEEP_SHIFT 8 |
| 3285 | #define MT6325_QI_VCORE1_DLC_MASK 0x3 |
| 3286 | #define MT6325_QI_VCORE1_DLC_SHIFT 12 |
| 3287 | #define MT6325_VCORE1_DLC_N_MASK 0x3 |
| 3288 | #define MT6325_VCORE1_DLC_N_SHIFT 0 |
| 3289 | #define MT6325_VCORE1_DLC_N_ON_MASK 0x3 |
| 3290 | #define MT6325_VCORE1_DLC_N_ON_SHIFT 4 |
| 3291 | #define MT6325_VCORE1_DLC_N_SLEEP_MASK 0x3 |
| 3292 | #define MT6325_VCORE1_DLC_N_SLEEP_SHIFT 8 |
| 3293 | #define MT6325_QI_VCORE1_DLC_N_MASK 0x3 |
| 3294 | #define MT6325_QI_VCORE1_DLC_N_SHIFT 12 |
| 3295 | #define MT6325_VCORE1_TRANS_TD_MASK 0x3 |
| 3296 | #define MT6325_VCORE1_TRANS_TD_SHIFT 0 |
| 3297 | #define MT6325_VCORE1_TRANS_CTRL_MASK 0x3 |
| 3298 | #define MT6325_VCORE1_TRANS_CTRL_SHIFT 4 |
| 3299 | #define MT6325_VCORE1_TRANS_ONCE_MASK 0x1 |
| 3300 | #define MT6325_VCORE1_TRANS_ONCE_SHIFT 6 |
| 3301 | #define MT6325_NI_VCORE1_VOSEL_TRANS_MASK 0x1 |
| 3302 | #define MT6325_NI_VCORE1_VOSEL_TRANS_SHIFT 7 |
| 3303 | #define MT6325_VCORE1_VSLEEP_EN_MASK 0x1 |
| 3304 | #define MT6325_VCORE1_VSLEEP_EN_SHIFT 8 |
| 3305 | #define MT6325_VCORE1_R2R_PDN_MASK 0x1 |
| 3306 | #define MT6325_VCORE1_R2R_PDN_SHIFT 10 |
| 3307 | #define MT6325_VCORE1_VSLEEP_SEL_MASK 0x1 |
| 3308 | #define MT6325_VCORE1_VSLEEP_SEL_SHIFT 11 |
| 3309 | #define MT6325_NI_VCORE1_R2R_PDN_MASK 0x1 |
| 3310 | #define MT6325_NI_VCORE1_R2R_PDN_SHIFT 14 |
| 3311 | #define MT6325_NI_VCORE1_VSLEEP_SEL_MASK 0x1 |
| 3312 | #define MT6325_NI_VCORE1_VSLEEP_SEL_SHIFT 15 |
| 3313 | #define MT6325_VCORE2_DIG0_RSV0_MASK 0xFF |
| 3314 | #define MT6325_VCORE2_DIG0_RSV0_SHIFT 8 |
| 3315 | #define MT6325_VCORE2_EN_CTRL_MASK 0x1 |
| 3316 | #define MT6325_VCORE2_EN_CTRL_SHIFT 0 |
| 3317 | #define MT6325_VCORE2_VOSEL_CTRL_MASK 0x1 |
| 3318 | #define MT6325_VCORE2_VOSEL_CTRL_SHIFT 1 |
| 3319 | #define MT6325_VCORE2_DLC_CTRL_MASK 0x1 |
| 3320 | #define MT6325_VCORE2_DLC_CTRL_SHIFT 2 |
| 3321 | #define MT6325_VCORE2_BURST_CTRL_MASK 0x1 |
| 3322 | #define MT6325_VCORE2_BURST_CTRL_SHIFT 3 |
| 3323 | #define MT6325_VCORE2_EN_SEL_MASK 0x3 |
| 3324 | #define MT6325_VCORE2_EN_SEL_SHIFT 0 |
| 3325 | #define MT6325_VCORE2_VOSEL_SEL_MASK 0x3 |
| 3326 | #define MT6325_VCORE2_VOSEL_SEL_SHIFT 4 |
| 3327 | #define MT6325_VCORE2_DLC_SEL_MASK 0x3 |
| 3328 | #define MT6325_VCORE2_DLC_SEL_SHIFT 8 |
| 3329 | #define MT6325_VCORE2_BURST_SEL_MASK 0x3 |
| 3330 | #define MT6325_VCORE2_BURST_SEL_SHIFT 12 |
| 3331 | #define MT6325_VCORE2_EN_MASK 0x1 |
| 3332 | #define MT6325_VCORE2_EN_SHIFT 0 |
| 3333 | #define MT6325_VCORE2_STBTD_MASK 0x3 |
| 3334 | #define MT6325_VCORE2_STBTD_SHIFT 4 |
| 3335 | #define MT6325_QI_VCORE2_STB_MASK 0x1 |
| 3336 | #define MT6325_QI_VCORE2_STB_SHIFT 12 |
| 3337 | #define MT6325_QI_VCORE2_EN_MASK 0x1 |
| 3338 | #define MT6325_QI_VCORE2_EN_SHIFT 13 |
| 3339 | #define MT6325_QI_VCORE2_OC_STATUS_MASK 0x1 |
| 3340 | #define MT6325_QI_VCORE2_OC_STATUS_SHIFT 15 |
| 3341 | #define MT6325_VCORE2_SFCHG_FRATE_MASK 0x7F |
| 3342 | #define MT6325_VCORE2_SFCHG_FRATE_SHIFT 0 |
| 3343 | #define MT6325_VCORE2_SFCHG_FEN_MASK 0x1 |
| 3344 | #define MT6325_VCORE2_SFCHG_FEN_SHIFT 7 |
| 3345 | #define MT6325_VCORE2_SFCHG_RRATE_MASK 0x7F |
| 3346 | #define MT6325_VCORE2_SFCHG_RRATE_SHIFT 8 |
| 3347 | #define MT6325_VCORE2_SFCHG_REN_MASK 0x1 |
| 3348 | #define MT6325_VCORE2_SFCHG_REN_SHIFT 15 |
| 3349 | #define MT6325_VCORE2_VOSEL_MASK 0x7F |
| 3350 | #define MT6325_VCORE2_VOSEL_SHIFT 0 |
| 3351 | #define MT6325_VCORE2_VOSEL_ON_MASK 0x7F |
| 3352 | #define MT6325_VCORE2_VOSEL_ON_SHIFT 0 |
| 3353 | #define MT6325_VCORE2_VOSEL_SLEEP_MASK 0x7F |
| 3354 | #define MT6325_VCORE2_VOSEL_SLEEP_SHIFT 0 |
| 3355 | #define MT6325_NI_VCORE2_VOSEL_MASK 0x7F |
| 3356 | #define MT6325_NI_VCORE2_VOSEL_SHIFT 0 |
| 3357 | #define MT6325_VCORE2_BURST_MASK 0x7 |
| 3358 | #define MT6325_VCORE2_BURST_SHIFT 0 |
| 3359 | #define MT6325_VCORE2_BURST_ON_MASK 0x7 |
| 3360 | #define MT6325_VCORE2_BURST_ON_SHIFT 4 |
| 3361 | #define MT6325_VCORE2_BURST_SLEEP_MASK 0x7 |
| 3362 | #define MT6325_VCORE2_BURST_SLEEP_SHIFT 8 |
| 3363 | #define MT6325_QI_VCORE2_BURST_MASK 0x7 |
| 3364 | #define MT6325_QI_VCORE2_BURST_SHIFT 12 |
| 3365 | #define MT6325_VCORE2_DLC_MASK 0x3 |
| 3366 | #define MT6325_VCORE2_DLC_SHIFT 0 |
| 3367 | #define MT6325_VCORE2_DLC_ON_MASK 0x3 |
| 3368 | #define MT6325_VCORE2_DLC_ON_SHIFT 4 |
| 3369 | #define MT6325_VCORE2_DLC_SLEEP_MASK 0x3 |
| 3370 | #define MT6325_VCORE2_DLC_SLEEP_SHIFT 8 |
| 3371 | #define MT6325_QI_VCORE2_DLC_MASK 0x3 |
| 3372 | #define MT6325_QI_VCORE2_DLC_SHIFT 12 |
| 3373 | #define MT6325_VCORE2_DLC_N_MASK 0x3 |
| 3374 | #define MT6325_VCORE2_DLC_N_SHIFT 0 |
| 3375 | #define MT6325_VCORE2_DLC_N_ON_MASK 0x3 |
| 3376 | #define MT6325_VCORE2_DLC_N_ON_SHIFT 4 |
| 3377 | #define MT6325_VCORE2_DLC_N_SLEEP_MASK 0x3 |
| 3378 | #define MT6325_VCORE2_DLC_N_SLEEP_SHIFT 8 |
| 3379 | #define MT6325_QI_VCORE2_DLC_N_MASK 0x3 |
| 3380 | #define MT6325_QI_VCORE2_DLC_N_SHIFT 12 |
| 3381 | #define MT6325_VCORE2_TRANS_TD_MASK 0x3 |
| 3382 | #define MT6325_VCORE2_TRANS_TD_SHIFT 0 |
| 3383 | #define MT6325_VCORE2_TRANS_CTRL_MASK 0x3 |
| 3384 | #define MT6325_VCORE2_TRANS_CTRL_SHIFT 4 |
| 3385 | #define MT6325_VCORE2_TRANS_ONCE_MASK 0x1 |
| 3386 | #define MT6325_VCORE2_TRANS_ONCE_SHIFT 6 |
| 3387 | #define MT6325_NI_VCORE2_VOSEL_TRANS_MASK 0x1 |
| 3388 | #define MT6325_NI_VCORE2_VOSEL_TRANS_SHIFT 7 |
| 3389 | #define MT6325_VCORE2_VSLEEP_EN_MASK 0x1 |
| 3390 | #define MT6325_VCORE2_VSLEEP_EN_SHIFT 8 |
| 3391 | #define MT6325_VCORE2_R2R_PDN_MASK 0x1 |
| 3392 | #define MT6325_VCORE2_R2R_PDN_SHIFT 10 |
| 3393 | #define MT6325_VCORE2_VSLEEP_SEL_MASK 0x1 |
| 3394 | #define MT6325_VCORE2_VSLEEP_SEL_SHIFT 11 |
| 3395 | #define MT6325_NI_VCORE2_R2R_PDN_MASK 0x1 |
| 3396 | #define MT6325_NI_VCORE2_R2R_PDN_SHIFT 14 |
| 3397 | #define MT6325_NI_VCORE2_VSLEEP_SEL_MASK 0x1 |
| 3398 | #define MT6325_NI_VCORE2_VSLEEP_SEL_SHIFT 15 |
| 3399 | #define MT6325_VCORE2_VOSEL_AUD_MASK 0x7F |
| 3400 | #define MT6325_VCORE2_VOSEL_AUD_SHIFT 0 |
| 3401 | #define MT6325_BUCK_DVFS_DONE_MASK 0x1 |
| 3402 | #define MT6325_BUCK_DVFS_DONE_SHIFT 0 |
| 3403 | #define MT6325_BUCK_DVFS_DONE_SW_MASK 0x1 |
| 3404 | #define MT6325_BUCK_DVFS_DONE_SW_SHIFT 1 |
| 3405 | #define MT6325_VCORE_DVFS_DONE_STA_MASK 0x1 |
| 3406 | #define MT6325_VCORE_DVFS_DONE_STA_SHIFT 2 |
| 3407 | #define MT6325_VIO18_DIG0_RSV0_MASK 0xFF |
| 3408 | #define MT6325_VIO18_DIG0_RSV0_SHIFT 8 |
| 3409 | #define MT6325_VIO18_EN_CTRL_MASK 0x1 |
| 3410 | #define MT6325_VIO18_EN_CTRL_SHIFT 0 |
| 3411 | #define MT6325_VIO18_VOSEL_CTRL_MASK 0x1 |
| 3412 | #define MT6325_VIO18_VOSEL_CTRL_SHIFT 1 |
| 3413 | #define MT6325_VIO18_DLC_CTRL_MASK 0x1 |
| 3414 | #define MT6325_VIO18_DLC_CTRL_SHIFT 2 |
| 3415 | #define MT6325_VIO18_BURST_CTRL_MASK 0x1 |
| 3416 | #define MT6325_VIO18_BURST_CTRL_SHIFT 3 |
| 3417 | #define MT6325_VIO18_EN_SEL_MASK 0x3 |
| 3418 | #define MT6325_VIO18_EN_SEL_SHIFT 0 |
| 3419 | #define MT6325_VIO18_VOSEL_SEL_MASK 0x3 |
| 3420 | #define MT6325_VIO18_VOSEL_SEL_SHIFT 4 |
| 3421 | #define MT6325_VIO18_DLC_SEL_MASK 0x3 |
| 3422 | #define MT6325_VIO18_DLC_SEL_SHIFT 8 |
| 3423 | #define MT6325_VIO18_BURST_SEL_MASK 0x3 |
| 3424 | #define MT6325_VIO18_BURST_SEL_SHIFT 12 |
| 3425 | #define MT6325_VIO18_EN_MASK 0x1 |
| 3426 | #define MT6325_VIO18_EN_SHIFT 0 |
| 3427 | #define MT6325_VIO18_STBTD_MASK 0x3 |
| 3428 | #define MT6325_VIO18_STBTD_SHIFT 4 |
| 3429 | #define MT6325_QI_VIO18_STB_MASK 0x1 |
| 3430 | #define MT6325_QI_VIO18_STB_SHIFT 12 |
| 3431 | #define MT6325_QI_VIO18_EN_MASK 0x1 |
| 3432 | #define MT6325_QI_VIO18_EN_SHIFT 13 |
| 3433 | #define MT6325_QI_VIO18_OC_STATUS_MASK 0x1 |
| 3434 | #define MT6325_QI_VIO18_OC_STATUS_SHIFT 15 |
| 3435 | #define MT6325_VIO18_SFCHG_FRATE_MASK 0x7F |
| 3436 | #define MT6325_VIO18_SFCHG_FRATE_SHIFT 0 |
| 3437 | #define MT6325_VIO18_SFCHG_FEN_MASK 0x1 |
| 3438 | #define MT6325_VIO18_SFCHG_FEN_SHIFT 7 |
| 3439 | #define MT6325_VIO18_SFCHG_RRATE_MASK 0x7F |
| 3440 | #define MT6325_VIO18_SFCHG_RRATE_SHIFT 8 |
| 3441 | #define MT6325_VIO18_SFCHG_REN_MASK 0x1 |
| 3442 | #define MT6325_VIO18_SFCHG_REN_SHIFT 15 |
| 3443 | #define MT6325_VIO18_VOSEL_MASK 0x7F |
| 3444 | #define MT6325_VIO18_VOSEL_SHIFT 0 |
| 3445 | #define MT6325_VIO18_VOSEL_ON_MASK 0x7F |
| 3446 | #define MT6325_VIO18_VOSEL_ON_SHIFT 0 |
| 3447 | #define MT6325_VIO18_VOSEL_SLEEP_MASK 0x7F |
| 3448 | #define MT6325_VIO18_VOSEL_SLEEP_SHIFT 0 |
| 3449 | #define MT6325_NI_VIO18_VOSEL_MASK 0x7F |
| 3450 | #define MT6325_NI_VIO18_VOSEL_SHIFT 0 |
| 3451 | #define MT6325_VIO18_BURST_MASK 0x7 |
| 3452 | #define MT6325_VIO18_BURST_SHIFT 0 |
| 3453 | #define MT6325_VIO18_BURST_ON_MASK 0x7 |
| 3454 | #define MT6325_VIO18_BURST_ON_SHIFT 4 |
| 3455 | #define MT6325_VIO18_BURST_SLEEP_MASK 0x7 |
| 3456 | #define MT6325_VIO18_BURST_SLEEP_SHIFT 8 |
| 3457 | #define MT6325_QI_VIO18_BURST_MASK 0x7 |
| 3458 | #define MT6325_QI_VIO18_BURST_SHIFT 12 |
| 3459 | #define MT6325_VIO18_DLC_MASK 0x3 |
| 3460 | #define MT6325_VIO18_DLC_SHIFT 0 |
| 3461 | #define MT6325_VIO18_DLC_ON_MASK 0x3 |
| 3462 | #define MT6325_VIO18_DLC_ON_SHIFT 4 |
| 3463 | #define MT6325_VIO18_DLC_SLEEP_MASK 0x3 |
| 3464 | #define MT6325_VIO18_DLC_SLEEP_SHIFT 8 |
| 3465 | #define MT6325_QI_VIO18_DLC_MASK 0x3 |
| 3466 | #define MT6325_QI_VIO18_DLC_SHIFT 12 |
| 3467 | #define MT6325_VIO18_DLC_N_MASK 0x3 |
| 3468 | #define MT6325_VIO18_DLC_N_SHIFT 0 |
| 3469 | #define MT6325_VIO18_DLC_N_ON_MASK 0x3 |
| 3470 | #define MT6325_VIO18_DLC_N_ON_SHIFT 4 |
| 3471 | #define MT6325_VIO18_DLC_N_SLEEP_MASK 0x3 |
| 3472 | #define MT6325_VIO18_DLC_N_SLEEP_SHIFT 8 |
| 3473 | #define MT6325_QI_VIO18_DLC_N_MASK 0x3 |
| 3474 | #define MT6325_QI_VIO18_DLC_N_SHIFT 12 |
| 3475 | #define MT6325_VIO18_TRANS_TD_MASK 0x3 |
| 3476 | #define MT6325_VIO18_TRANS_TD_SHIFT 0 |
| 3477 | #define MT6325_VIO18_TRANS_CTRL_MASK 0x3 |
| 3478 | #define MT6325_VIO18_TRANS_CTRL_SHIFT 4 |
| 3479 | #define MT6325_VIO18_TRANS_ONCE_MASK 0x1 |
| 3480 | #define MT6325_VIO18_TRANS_ONCE_SHIFT 6 |
| 3481 | #define MT6325_NI_VIO18_VOSEL_TRANS_MASK 0x1 |
| 3482 | #define MT6325_NI_VIO18_VOSEL_TRANS_SHIFT 7 |
| 3483 | #define MT6325_VIO18_VSLEEP_EN_MASK 0x1 |
| 3484 | #define MT6325_VIO18_VSLEEP_EN_SHIFT 8 |
| 3485 | #define MT6325_VIO18_R2R_PDN_MASK 0x1 |
| 3486 | #define MT6325_VIO18_R2R_PDN_SHIFT 10 |
| 3487 | #define MT6325_VIO18_VSLEEP_SEL_MASK 0x1 |
| 3488 | #define MT6325_VIO18_VSLEEP_SEL_SHIFT 11 |
| 3489 | #define MT6325_NI_VIO18_R2R_PDN_MASK 0x1 |
| 3490 | #define MT6325_NI_VIO18_R2R_PDN_SHIFT 14 |
| 3491 | #define MT6325_NI_VIO18_VSLEEP_SEL_MASK 0x1 |
| 3492 | #define MT6325_NI_VIO18_VSLEEP_SEL_SHIFT 15 |
| 3493 | #define MT6325_VPA_DIG0_RSV0_MASK 0xFF |
| 3494 | #define MT6325_VPA_DIG0_RSV0_SHIFT 8 |
| 3495 | #define MT6325_VPA_EN_CTRL_MASK 0x1 |
| 3496 | #define MT6325_VPA_EN_CTRL_SHIFT 0 |
| 3497 | #define MT6325_VPA_VOSEL_CTRL_MASK 0x1 |
| 3498 | #define MT6325_VPA_VOSEL_CTRL_SHIFT 1 |
| 3499 | #define MT6325_VPA_DLC_CTRL_MASK 0x1 |
| 3500 | #define MT6325_VPA_DLC_CTRL_SHIFT 2 |
| 3501 | #define MT6325_VPA_BURST_CTRL_MASK 0x1 |
| 3502 | #define MT6325_VPA_BURST_CTRL_SHIFT 3 |
| 3503 | #define MT6325_VPA_EN_SEL_MASK 0x3 |
| 3504 | #define MT6325_VPA_EN_SEL_SHIFT 0 |
| 3505 | #define MT6325_VPA_VOSEL_SEL_MASK 0x3 |
| 3506 | #define MT6325_VPA_VOSEL_SEL_SHIFT 4 |
| 3507 | #define MT6325_VPA_DLC_SEL_MASK 0x3 |
| 3508 | #define MT6325_VPA_DLC_SEL_SHIFT 8 |
| 3509 | #define MT6325_VPA_BURST_SEL_MASK 0x3 |
| 3510 | #define MT6325_VPA_BURST_SEL_SHIFT 12 |
| 3511 | #define MT6325_VPA_EN_MASK 0x1 |
| 3512 | #define MT6325_VPA_EN_SHIFT 0 |
| 3513 | #define MT6325_VPA_STBTD_MASK 0x3 |
| 3514 | #define MT6325_VPA_STBTD_SHIFT 4 |
| 3515 | #define MT6325_QI_VPA_STB_MASK 0x1 |
| 3516 | #define MT6325_QI_VPA_STB_SHIFT 12 |
| 3517 | #define MT6325_QI_VPA_EN_MASK 0x1 |
| 3518 | #define MT6325_QI_VPA_EN_SHIFT 13 |
| 3519 | #define MT6325_QI_VPA_OC_STATUS_MASK 0x1 |
| 3520 | #define MT6325_QI_VPA_OC_STATUS_SHIFT 15 |
| 3521 | #define MT6325_VPA_SFCHG_FRATE_MASK 0x7F |
| 3522 | #define MT6325_VPA_SFCHG_FRATE_SHIFT 0 |
| 3523 | #define MT6325_VPA_SFCHG_FEN_MASK 0x1 |
| 3524 | #define MT6325_VPA_SFCHG_FEN_SHIFT 7 |
| 3525 | #define MT6325_VPA_SFCHG_RRATE_MASK 0x7F |
| 3526 | #define MT6325_VPA_SFCHG_RRATE_SHIFT 8 |
| 3527 | #define MT6325_VPA_SFCHG_REN_MASK 0x1 |
| 3528 | #define MT6325_VPA_SFCHG_REN_SHIFT 15 |
| 3529 | #define MT6325_VPA_VOSEL_MASK 0x3F |
| 3530 | #define MT6325_VPA_VOSEL_SHIFT 0 |
| 3531 | #define MT6325_VPA_VOSEL_ON_MASK 0x3F |
| 3532 | #define MT6325_VPA_VOSEL_ON_SHIFT 0 |
| 3533 | #define MT6325_VPA_VOSEL_SLEEP_MASK 0x3F |
| 3534 | #define MT6325_VPA_VOSEL_SLEEP_SHIFT 0 |
| 3535 | #define MT6325_NI_VPA_VOSEL_MASK 0x3F |
| 3536 | #define MT6325_NI_VPA_VOSEL_SHIFT 0 |
| 3537 | #define MT6325_VPA_DIG0_RSV3_MASK 0x7 |
| 3538 | #define MT6325_VPA_DIG0_RSV3_SHIFT 11 |
| 3539 | #define MT6325_VPA_DLC_MASK 0x7 |
| 3540 | #define MT6325_VPA_DLC_SHIFT 0 |
| 3541 | #define MT6325_VPA_DLC_ON_MASK 0x7 |
| 3542 | #define MT6325_VPA_DLC_ON_SHIFT 4 |
| 3543 | #define MT6325_VPA_DLC_SLEEP_MASK 0x7 |
| 3544 | #define MT6325_VPA_DLC_SLEEP_SHIFT 8 |
| 3545 | #define MT6325_QI_VPA_DLC_MASK 0x7 |
| 3546 | #define MT6325_QI_VPA_DLC_SHIFT 12 |
| 3547 | #define MT6325_VPA_DIG0_RSV1_MASK 0xFF |
| 3548 | #define MT6325_VPA_DIG0_RSV1_SHIFT 0 |
| 3549 | #define MT6325_VPA_DIG1_RSV1_MASK 0xFF |
| 3550 | #define MT6325_VPA_DIG1_RSV1_SHIFT 8 |
| 3551 | #define MT6325_VPA_TRANS_TD_MASK 0x3 |
| 3552 | #define MT6325_VPA_TRANS_TD_SHIFT 0 |
| 3553 | #define MT6325_VPA_TRANS_CTRL_MASK 0x3 |
| 3554 | #define MT6325_VPA_TRANS_CTRL_SHIFT 4 |
| 3555 | #define MT6325_VPA_TRANS_ONCE_MASK 0x1 |
| 3556 | #define MT6325_VPA_TRANS_ONCE_SHIFT 6 |
| 3557 | #define MT6325_NI_VPA_DVS_BW_MASK 0x1 |
| 3558 | #define MT6325_NI_VPA_DVS_BW_SHIFT 7 |
| 3559 | #define MT6325_VPA_DIG1_RSV4_MASK 0x3 |
| 3560 | #define MT6325_VPA_DIG1_RSV4_SHIFT 10 |
| 3561 | #define MT6325_VPA_DIG1_RSV3_MASK 0x3 |
| 3562 | #define MT6325_VPA_DIG1_RSV3_SHIFT 14 |
| 3563 | #define MT6325_VPA_BURSTH_MASK 0x3 |
| 3564 | #define MT6325_VPA_BURSTH_SHIFT 0 |
| 3565 | #define MT6325_VPA_BURSTH_ON_MASK 0x3 |
| 3566 | #define MT6325_VPA_BURSTH_ON_SHIFT 4 |
| 3567 | #define MT6325_VPA_BURSTH_SLEEP_MASK 0x3 |
| 3568 | #define MT6325_VPA_BURSTH_SLEEP_SHIFT 8 |
| 3569 | #define MT6325_QI_VPA_BURSTH_MASK 0x3 |
| 3570 | #define MT6325_QI_VPA_BURSTH_SHIFT 12 |
| 3571 | #define MT6325_VPA_BURSTL_MASK 0x3 |
| 3572 | #define MT6325_VPA_BURSTL_SHIFT 0 |
| 3573 | #define MT6325_VPA_BURSTL_ON_MASK 0x3 |
| 3574 | #define MT6325_VPA_BURSTL_ON_SHIFT 4 |
| 3575 | #define MT6325_VPA_BURSTL_SLEEP_MASK 0x3 |
| 3576 | #define MT6325_VPA_BURSTL_SLEEP_SHIFT 8 |
| 3577 | #define MT6325_QI_VPA_BURSTL_MASK 0x3 |
| 3578 | #define MT6325_QI_VPA_BURSTL_SHIFT 12 |
| 3579 | #define MT6325_VPA_VOSEL_DLC011_MASK 0x3F |
| 3580 | #define MT6325_VPA_VOSEL_DLC011_SHIFT 0 |
| 3581 | #define MT6325_VPA_VOSEL_DLC111_MASK 0x3F |
| 3582 | #define MT6325_VPA_VOSEL_DLC111_SHIFT 8 |
| 3583 | #define MT6325_VPA_DLC_MAP_EN_MASK 0x1 |
| 3584 | #define MT6325_VPA_DLC_MAP_EN_SHIFT 0 |
| 3585 | #define MT6325_VPA_VOSEL_DLC001_MASK 0x3F |
| 3586 | #define MT6325_VPA_VOSEL_DLC001_SHIFT 8 |
| 3587 | #define MT6325_VPA_DVS_TRANS_TD_MASK 0x3 |
| 3588 | #define MT6325_VPA_DVS_TRANS_TD_SHIFT 0 |
| 3589 | #define MT6325_VPA_DVS_TRANS_CTRL_MASK 0x3 |
| 3590 | #define MT6325_VPA_DVS_TRANS_CTRL_SHIFT 4 |
| 3591 | #define MT6325_VPA_DVS_TRANS_ONCE_MASK 0x1 |
| 3592 | #define MT6325_VPA_DVS_TRANS_ONCE_SHIFT 6 |
| 3593 | #define MT6325_NI_VPA_DVS_TRANST_MASK 0x1 |
| 3594 | #define MT6325_NI_VPA_DVS_TRANST_SHIFT 7 |
| 3595 | #define MT6325_VPA_DIG0_RSV4_MASK 0xF |
| 3596 | #define MT6325_VPA_DIG0_RSV4_SHIFT 8 |
| 3597 | #define MT6325_VPA_DIG1_RSV2_MASK 0xF |
| 3598 | #define MT6325_VPA_DIG1_RSV2_SHIFT 12 |
| 3599 | #define MT6325_K_RST_DONE_MASK 0x1 |
| 3600 | #define MT6325_K_RST_DONE_SHIFT 0 |
| 3601 | #define MT6325_K_MAP_SEL_MASK 0x1 |
| 3602 | #define MT6325_K_MAP_SEL_SHIFT 1 |
| 3603 | #define MT6325_K_ONCE_EN_MASK 0x1 |
| 3604 | #define MT6325_K_ONCE_EN_SHIFT 2 |
| 3605 | #define MT6325_K_ONCE_MASK 0x1 |
| 3606 | #define MT6325_K_ONCE_SHIFT 3 |
| 3607 | #define MT6325_K_START_MANUAL_MASK 0x1 |
| 3608 | #define MT6325_K_START_MANUAL_SHIFT 4 |
| 3609 | #define MT6325_K_SRC_SEL_MASK 0x1 |
| 3610 | #define MT6325_K_SRC_SEL_SHIFT 5 |
| 3611 | #define MT6325_K_AUTO_EN_MASK 0x1 |
| 3612 | #define MT6325_K_AUTO_EN_SHIFT 6 |
| 3613 | #define MT6325_K_INV_MASK 0x1 |
| 3614 | #define MT6325_K_INV_SHIFT 7 |
| 3615 | #define MT6325_K_CONTROL_SMPS_MASK 0x3F |
| 3616 | #define MT6325_K_CONTROL_SMPS_SHIFT 8 |
| 3617 | #define MT6325_K_RESULT_MASK 0x1 |
| 3618 | #define MT6325_K_RESULT_SHIFT 0 |
| 3619 | #define MT6325_K_DONE_MASK 0x1 |
| 3620 | #define MT6325_K_DONE_SHIFT 1 |
| 3621 | #define MT6325_K_CONTROL_MASK 0x3F |
| 3622 | #define MT6325_K_CONTROL_SHIFT 2 |
| 3623 | #define MT6325_QI_SMPS_OSC_CAL_MASK 0x3F |
| 3624 | #define MT6325_QI_SMPS_OSC_CAL_SHIFT 8 |
| 3625 | #define MT6325_K_BUCK_CK_CNT_MASK 0x3FF |
| 3626 | #define MT6325_K_BUCK_CK_CNT_SHIFT 0 |
| 3627 | #define MT6325_RG_AUDZCDENABLE_MASK 0x1 |
| 3628 | #define MT6325_RG_AUDZCDENABLE_SHIFT 0 |
| 3629 | #define MT6325_RG_AUDZCDGAINSTEPTIME_MASK 0x7 |
| 3630 | #define MT6325_RG_AUDZCDGAINSTEPTIME_SHIFT 1 |
| 3631 | #define MT6325_RG_AUDZCDGAINSTEPSIZE_MASK 0x3 |
| 3632 | #define MT6325_RG_AUDZCDGAINSTEPSIZE_SHIFT 4 |
| 3633 | #define MT6325_RG_AUDZCDTIMEOUTMODESEL_MASK 0x1 |
| 3634 | #define MT6325_RG_AUDZCDTIMEOUTMODESEL_SHIFT 6 |
| 3635 | #define MT6325_RG_AUDZCDCLKSEL_VAUDP15_MASK 0x1 |
| 3636 | #define MT6325_RG_AUDZCDCLKSEL_VAUDP15_SHIFT 7 |
| 3637 | #define MT6325_RG_AUDZCDMUXSEL_VAUDP15_MASK 0x7 |
| 3638 | #define MT6325_RG_AUDZCDMUXSEL_VAUDP15_SHIFT 8 |
| 3639 | #define MT6325_RG_AUDLOLGAIN_MASK 0x1F |
| 3640 | #define MT6325_RG_AUDLOLGAIN_SHIFT 0 |
| 3641 | #define MT6325_RG_AUDLORGAIN_MASK 0x1F |
| 3642 | #define MT6325_RG_AUDLORGAIN_SHIFT 7 |
| 3643 | #define MT6325_RG_AUDHPLGAIN_MASK 0x1F |
| 3644 | #define MT6325_RG_AUDHPLGAIN_SHIFT 0 |
| 3645 | #define MT6325_RG_AUDHPRGAIN_MASK 0x1F |
| 3646 | #define MT6325_RG_AUDHPRGAIN_SHIFT 7 |
| 3647 | #define MT6325_RG_AUDHSGAIN_MASK 0x1F |
| 3648 | #define MT6325_RG_AUDHSGAIN_SHIFT 0 |
| 3649 | #define MT6325_RG_AUDIVLGAIN_MASK 0x7 |
| 3650 | #define MT6325_RG_AUDIVLGAIN_SHIFT 0 |
| 3651 | #define MT6325_RG_AUDIVRGAIN_MASK 0x7 |
| 3652 | #define MT6325_RG_AUDIVRGAIN_SHIFT 8 |
| 3653 | #define MT6325_RG_AUDINTGAIN1_MASK 0x3F |
| 3654 | #define MT6325_RG_AUDINTGAIN1_SHIFT 0 |
| 3655 | #define MT6325_RG_AUDINTGAIN2_MASK 0x3F |
| 3656 | #define MT6325_RG_AUDINTGAIN2_SHIFT 8 |
| 3657 | #define MT6325_ISINK_DIM0_FSEL_MASK 0xFFFF |
| 3658 | #define MT6325_ISINK_DIM0_FSEL_SHIFT 0 |
| 3659 | #define MT6325_ISINK0_RSV1_MASK 0xF |
| 3660 | #define MT6325_ISINK0_RSV1_SHIFT 0 |
| 3661 | #define MT6325_ISINK0_RSV0_MASK 0x7 |
| 3662 | #define MT6325_ISINK0_RSV0_SHIFT 4 |
| 3663 | #define MT6325_ISINK_DIM0_DUTY_MASK 0x1F |
| 3664 | #define MT6325_ISINK_DIM0_DUTY_SHIFT 7 |
| 3665 | #define MT6325_ISINK_CH0_STEP_MASK 0x7 |
| 3666 | #define MT6325_ISINK_CH0_STEP_SHIFT 12 |
| 3667 | #define MT6325_ISINK_BREATH0_TF2_SEL_MASK 0xF |
| 3668 | #define MT6325_ISINK_BREATH0_TF2_SEL_SHIFT 0 |
| 3669 | #define MT6325_ISINK_BREATH0_TF1_SEL_MASK 0xF |
| 3670 | #define MT6325_ISINK_BREATH0_TF1_SEL_SHIFT 4 |
| 3671 | #define MT6325_ISINK_BREATH0_TR2_SEL_MASK 0xF |
| 3672 | #define MT6325_ISINK_BREATH0_TR2_SEL_SHIFT 8 |
| 3673 | #define MT6325_ISINK_BREATH0_TR1_SEL_MASK 0xF |
| 3674 | #define MT6325_ISINK_BREATH0_TR1_SEL_SHIFT 12 |
| 3675 | #define MT6325_ISINK_BREATH0_TOFF_SEL_MASK 0xF |
| 3676 | #define MT6325_ISINK_BREATH0_TOFF_SEL_SHIFT 0 |
| 3677 | #define MT6325_ISINK_BREATH0_TON_SEL_MASK 0xF |
| 3678 | #define MT6325_ISINK_BREATH0_TON_SEL_SHIFT 8 |
| 3679 | #define MT6325_ISINK_DIM1_FSEL_MASK 0xFFFF |
| 3680 | #define MT6325_ISINK_DIM1_FSEL_SHIFT 0 |
| 3681 | #define MT6325_ISINK1_RSV1_MASK 0xF |
| 3682 | #define MT6325_ISINK1_RSV1_SHIFT 0 |
| 3683 | #define MT6325_ISINK1_RSV0_MASK 0x7 |
| 3684 | #define MT6325_ISINK1_RSV0_SHIFT 4 |
| 3685 | #define MT6325_ISINK_DIM1_DUTY_MASK 0x1F |
| 3686 | #define MT6325_ISINK_DIM1_DUTY_SHIFT 7 |
| 3687 | #define MT6325_ISINK_CH1_STEP_MASK 0x7 |
| 3688 | #define MT6325_ISINK_CH1_STEP_SHIFT 12 |
| 3689 | #define MT6325_ISINK_BREATH1_TF2_SEL_MASK 0xF |
| 3690 | #define MT6325_ISINK_BREATH1_TF2_SEL_SHIFT 0 |
| 3691 | #define MT6325_ISINK_BREATH1_TF1_SEL_MASK 0xF |
| 3692 | #define MT6325_ISINK_BREATH1_TF1_SEL_SHIFT 4 |
| 3693 | #define MT6325_ISINK_BREATH1_TR2_SEL_MASK 0xF |
| 3694 | #define MT6325_ISINK_BREATH1_TR2_SEL_SHIFT 8 |
| 3695 | #define MT6325_ISINK_BREATH1_TR1_SEL_MASK 0xF |
| 3696 | #define MT6325_ISINK_BREATH1_TR1_SEL_SHIFT 12 |
| 3697 | #define MT6325_ISINK_BREATH1_TOFF_SEL_MASK 0xF |
| 3698 | #define MT6325_ISINK_BREATH1_TOFF_SEL_SHIFT 0 |
| 3699 | #define MT6325_ISINK_BREATH1_TON_SEL_MASK 0xF |
| 3700 | #define MT6325_ISINK_BREATH1_TON_SEL_SHIFT 8 |
| 3701 | #define MT6325_ISINK_DIM2_FSEL_MASK 0xFFFF |
| 3702 | #define MT6325_ISINK_DIM2_FSEL_SHIFT 0 |
| 3703 | #define MT6325_ISINK2_RSV1_MASK 0xF |
| 3704 | #define MT6325_ISINK2_RSV1_SHIFT 0 |
| 3705 | #define MT6325_ISINK2_RSV0_MASK 0x7 |
| 3706 | #define MT6325_ISINK2_RSV0_SHIFT 4 |
| 3707 | #define MT6325_ISINK_DIM2_DUTY_MASK 0x1F |
| 3708 | #define MT6325_ISINK_DIM2_DUTY_SHIFT 7 |
| 3709 | #define MT6325_ISINK_CH2_STEP_MASK 0x7 |
| 3710 | #define MT6325_ISINK_CH2_STEP_SHIFT 12 |
| 3711 | #define MT6325_ISINK_BREATH2_TF2_SEL_MASK 0xF |
| 3712 | #define MT6325_ISINK_BREATH2_TF2_SEL_SHIFT 0 |
| 3713 | #define MT6325_ISINK_BREATH2_TF1_SEL_MASK 0xF |
| 3714 | #define MT6325_ISINK_BREATH2_TF1_SEL_SHIFT 4 |
| 3715 | #define MT6325_ISINK_BREATH2_TR2_SEL_MASK 0xF |
| 3716 | #define MT6325_ISINK_BREATH2_TR2_SEL_SHIFT 8 |
| 3717 | #define MT6325_ISINK_BREATH2_TR1_SEL_MASK 0xF |
| 3718 | #define MT6325_ISINK_BREATH2_TR1_SEL_SHIFT 12 |
| 3719 | #define MT6325_ISINK_BREATH2_TOFF_SEL_MASK 0xF |
| 3720 | #define MT6325_ISINK_BREATH2_TOFF_SEL_SHIFT 0 |
| 3721 | #define MT6325_ISINK_BREATH2_TON_SEL_MASK 0xF |
| 3722 | #define MT6325_ISINK_BREATH2_TON_SEL_SHIFT 8 |
| 3723 | #define MT6325_ISINK_DIM3_FSEL_MASK 0xFFFF |
| 3724 | #define MT6325_ISINK_DIM3_FSEL_SHIFT 0 |
| 3725 | #define MT6325_ISINK3_RSV1_MASK 0xF |
| 3726 | #define MT6325_ISINK3_RSV1_SHIFT 0 |
| 3727 | #define MT6325_ISINK3_RSV0_MASK 0x7 |
| 3728 | #define MT6325_ISINK3_RSV0_SHIFT 4 |
| 3729 | #define MT6325_ISINK_DIM3_DUTY_MASK 0x1F |
| 3730 | #define MT6325_ISINK_DIM3_DUTY_SHIFT 7 |
| 3731 | #define MT6325_ISINK_CH3_STEP_MASK 0x7 |
| 3732 | #define MT6325_ISINK_CH3_STEP_SHIFT 12 |
| 3733 | #define MT6325_ISINK_BREATH3_TF2_SEL_MASK 0xF |
| 3734 | #define MT6325_ISINK_BREATH3_TF2_SEL_SHIFT 0 |
| 3735 | #define MT6325_ISINK_BREATH3_TF1_SEL_MASK 0xF |
| 3736 | #define MT6325_ISINK_BREATH3_TF1_SEL_SHIFT 4 |
| 3737 | #define MT6325_ISINK_BREATH3_TR2_SEL_MASK 0xF |
| 3738 | #define MT6325_ISINK_BREATH3_TR2_SEL_SHIFT 8 |
| 3739 | #define MT6325_ISINK_BREATH3_TR1_SEL_MASK 0xF |
| 3740 | #define MT6325_ISINK_BREATH3_TR1_SEL_SHIFT 12 |
| 3741 | #define MT6325_ISINK_BREATH3_TOFF_SEL_MASK 0xF |
| 3742 | #define MT6325_ISINK_BREATH3_TOFF_SEL_SHIFT 0 |
| 3743 | #define MT6325_ISINK_BREATH3_TON_SEL_MASK 0xF |
| 3744 | #define MT6325_ISINK_BREATH3_TON_SEL_SHIFT 8 |
| 3745 | #define MT6325_RG_ISINKS_RSV_MASK 0xFF |
| 3746 | #define MT6325_RG_ISINKS_RSV_SHIFT 0 |
| 3747 | #define MT6325_RG_ISINK3_DOUBLE_EN_MASK 0x1 |
| 3748 | #define MT6325_RG_ISINK3_DOUBLE_EN_SHIFT 8 |
| 3749 | #define MT6325_RG_ISINK2_DOUBLE_EN_MASK 0x1 |
| 3750 | #define MT6325_RG_ISINK2_DOUBLE_EN_SHIFT 9 |
| 3751 | #define MT6325_RG_ISINK1_DOUBLE_EN_MASK 0x1 |
| 3752 | #define MT6325_RG_ISINK1_DOUBLE_EN_SHIFT 10 |
| 3753 | #define MT6325_RG_ISINK0_DOUBLE_EN_MASK 0x1 |
| 3754 | #define MT6325_RG_ISINK0_DOUBLE_EN_SHIFT 11 |
| 3755 | #define MT6325_RG_TRIM_SEL_MASK 0x7 |
| 3756 | #define MT6325_RG_TRIM_SEL_SHIFT 12 |
| 3757 | #define MT6325_RG_TRIM_EN_MASK 0x1 |
| 3758 | #define MT6325_RG_TRIM_EN_SHIFT 15 |
| 3759 | #define MT6325_NI_ISINK3_STATUS_MASK 0x1 |
| 3760 | #define MT6325_NI_ISINK3_STATUS_SHIFT 0 |
| 3761 | #define MT6325_NI_ISINK2_STATUS_MASK 0x1 |
| 3762 | #define MT6325_NI_ISINK2_STATUS_SHIFT 1 |
| 3763 | #define MT6325_NI_ISINK1_STATUS_MASK 0x1 |
| 3764 | #define MT6325_NI_ISINK1_STATUS_SHIFT 2 |
| 3765 | #define MT6325_NI_ISINK0_STATUS_MASK 0x1 |
| 3766 | #define MT6325_NI_ISINK0_STATUS_SHIFT 3 |
| 3767 | #define MT6325_ISINK_PHASE0_DLY_EN_MASK 0x1 |
| 3768 | #define MT6325_ISINK_PHASE0_DLY_EN_SHIFT 0 |
| 3769 | #define MT6325_ISINK_PHASE1_DLY_EN_MASK 0x1 |
| 3770 | #define MT6325_ISINK_PHASE1_DLY_EN_SHIFT 1 |
| 3771 | #define MT6325_ISINK_PHASE2_DLY_EN_MASK 0x1 |
| 3772 | #define MT6325_ISINK_PHASE2_DLY_EN_SHIFT 2 |
| 3773 | #define MT6325_ISINK_PHASE3_DLY_EN_MASK 0x1 |
| 3774 | #define MT6325_ISINK_PHASE3_DLY_EN_SHIFT 3 |
| 3775 | #define MT6325_ISINK_PHASE_DLY_TC_MASK 0x3 |
| 3776 | #define MT6325_ISINK_PHASE_DLY_TC_SHIFT 4 |
| 3777 | #define MT6325_ISINK_CHOP0_SW_MASK 0x1 |
| 3778 | #define MT6325_ISINK_CHOP0_SW_SHIFT 12 |
| 3779 | #define MT6325_ISINK_CHOP1_SW_MASK 0x1 |
| 3780 | #define MT6325_ISINK_CHOP1_SW_SHIFT 13 |
| 3781 | #define MT6325_ISINK_CHOP2_SW_MASK 0x1 |
| 3782 | #define MT6325_ISINK_CHOP2_SW_SHIFT 14 |
| 3783 | #define MT6325_ISINK_CHOP3_SW_MASK 0x1 |
| 3784 | #define MT6325_ISINK_CHOP3_SW_SHIFT 15 |
| 3785 | #define MT6325_ISINK_SFSTR3_EN_MASK 0x1 |
| 3786 | #define MT6325_ISINK_SFSTR3_EN_SHIFT 0 |
| 3787 | #define MT6325_ISINK_SFSTR3_TC_MASK 0x3 |
| 3788 | #define MT6325_ISINK_SFSTR3_TC_SHIFT 1 |
| 3789 | #define MT6325_ISINK_SFSTR2_EN_MASK 0x1 |
| 3790 | #define MT6325_ISINK_SFSTR2_EN_SHIFT 4 |
| 3791 | #define MT6325_ISINK_SFSTR2_TC_MASK 0x3 |
| 3792 | #define MT6325_ISINK_SFSTR2_TC_SHIFT 5 |
| 3793 | #define MT6325_ISINK_SFSTR1_EN_MASK 0x1 |
| 3794 | #define MT6325_ISINK_SFSTR1_EN_SHIFT 8 |
| 3795 | #define MT6325_ISINK_SFSTR1_TC_MASK 0x3 |
| 3796 | #define MT6325_ISINK_SFSTR1_TC_SHIFT 9 |
| 3797 | #define MT6325_ISINK_SFSTR0_EN_MASK 0x1 |
| 3798 | #define MT6325_ISINK_SFSTR0_EN_SHIFT 12 |
| 3799 | #define MT6325_ISINK_SFSTR0_TC_MASK 0x3 |
| 3800 | #define MT6325_ISINK_SFSTR0_TC_SHIFT 13 |
| 3801 | #define MT6325_ISINK_CH0_EN_MASK 0x1 |
| 3802 | #define MT6325_ISINK_CH0_EN_SHIFT 0 |
| 3803 | #define MT6325_ISINK_CH1_EN_MASK 0x1 |
| 3804 | #define MT6325_ISINK_CH1_EN_SHIFT 1 |
| 3805 | #define MT6325_ISINK_CH2_EN_MASK 0x1 |
| 3806 | #define MT6325_ISINK_CH2_EN_SHIFT 2 |
| 3807 | #define MT6325_ISINK_CH3_EN_MASK 0x1 |
| 3808 | #define MT6325_ISINK_CH3_EN_SHIFT 3 |
| 3809 | #define MT6325_ISINK_CHOP0_EN_MASK 0x1 |
| 3810 | #define MT6325_ISINK_CHOP0_EN_SHIFT 4 |
| 3811 | #define MT6325_ISINK_CHOP1_EN_MASK 0x1 |
| 3812 | #define MT6325_ISINK_CHOP1_EN_SHIFT 5 |
| 3813 | #define MT6325_ISINK_CHOP2_EN_MASK 0x1 |
| 3814 | #define MT6325_ISINK_CHOP2_EN_SHIFT 6 |
| 3815 | #define MT6325_ISINK_CHOP3_EN_MASK 0x1 |
| 3816 | #define MT6325_ISINK_CHOP3_EN_SHIFT 7 |
| 3817 | #define MT6325_ISINK_CH0_BIAS_EN_MASK 0x1 |
| 3818 | #define MT6325_ISINK_CH0_BIAS_EN_SHIFT 8 |
| 3819 | #define MT6325_ISINK_CH1_BIAS_EN_MASK 0x1 |
| 3820 | #define MT6325_ISINK_CH1_BIAS_EN_SHIFT 9 |
| 3821 | #define MT6325_ISINK_CH2_BIAS_EN_MASK 0x1 |
| 3822 | #define MT6325_ISINK_CH2_BIAS_EN_SHIFT 10 |
| 3823 | #define MT6325_ISINK_CH3_BIAS_EN_MASK 0x1 |
| 3824 | #define MT6325_ISINK_CH3_BIAS_EN_SHIFT 11 |
| 3825 | #define MT6325_ISINK_RSV_MASK 0xF |
| 3826 | #define MT6325_ISINK_RSV_SHIFT 0 |
| 3827 | #define MT6325_ISINK_CH3_MODE_MASK 0x3 |
| 3828 | #define MT6325_ISINK_CH3_MODE_SHIFT 8 |
| 3829 | #define MT6325_ISINK_CH2_MODE_MASK 0x3 |
| 3830 | #define MT6325_ISINK_CH2_MODE_SHIFT 10 |
| 3831 | #define MT6325_ISINK_CH1_MODE_MASK 0x3 |
| 3832 | #define MT6325_ISINK_CH1_MODE_SHIFT 12 |
| 3833 | #define MT6325_ISINK_CH0_MODE_MASK 0x3 |
| 3834 | #define MT6325_ISINK_CH0_MODE_SHIFT 14 |
| 3835 | #define MT6325_RG_ISINKS_CH0_STEP_MASK 0x7 |
| 3836 | #define MT6325_RG_ISINKS_CH0_STEP_SHIFT 0 |
| 3837 | #define MT6325_RG_ISINKS_CH1_STEP_MASK 0x7 |
| 3838 | #define MT6325_RG_ISINKS_CH1_STEP_SHIFT 3 |
| 3839 | #define MT6325_RG_ISINKS_CH2_STEP_MASK 0x7 |
| 3840 | #define MT6325_RG_ISINKS_CH2_STEP_SHIFT 6 |
| 3841 | #define MT6325_RG_ISINKS_CH3_STEP_MASK 0x7 |
| 3842 | #define MT6325_RG_ISINKS_CH3_STEP_SHIFT 9 |
| 3843 | #define MT6325_RG_VTCXO0_MODE_SET_MASK 0x1 |
| 3844 | #define MT6325_RG_VTCXO0_MODE_SET_SHIFT 0 |
| 3845 | #define MT6325_RG_VTCXO0_EN_MASK 0x1 |
| 3846 | #define MT6325_RG_VTCXO0_EN_SHIFT 1 |
| 3847 | #define MT6325_RG_VTCXO0_MODE_CTRL_MASK 0x1 |
| 3848 | #define MT6325_RG_VTCXO0_MODE_CTRL_SHIFT 2 |
| 3849 | #define MT6325_RG_VTCXO0_ON_CTRL_MASK 0x1 |
| 3850 | #define MT6325_RG_VTCXO0_ON_CTRL_SHIFT 3 |
| 3851 | #define MT6325_RG_VTCXO0_SRCLK_MODE_SEL_MASK 0x3 |
| 3852 | #define MT6325_RG_VTCXO0_SRCLK_MODE_SEL_SHIFT 4 |
| 3853 | #define MT6325_QI_VTCXO0_MODE_MASK 0x1 |
| 3854 | #define MT6325_QI_VTCXO0_MODE_SHIFT 7 |
| 3855 | #define MT6325_RG_VTCXO0_STBTD_MASK 0x3 |
| 3856 | #define MT6325_RG_VTCXO0_STBTD_SHIFT 8 |
| 3857 | #define MT6325_RG_VTCXO0_SRCLK_EN_SEL_MASK 0x3 |
| 3858 | #define MT6325_RG_VTCXO0_SRCLK_EN_SEL_SHIFT 12 |
| 3859 | #define MT6325_QI_VTCXO0_STB_MASK 0x1 |
| 3860 | #define MT6325_QI_VTCXO0_STB_SHIFT 14 |
| 3861 | #define MT6325_QI_VTCXO0_EN_MASK 0x1 |
| 3862 | #define MT6325_QI_VTCXO0_EN_SHIFT 15 |
| 3863 | #define MT6325_RG_VTCXO1_MODE_SET_MASK 0x1 |
| 3864 | #define MT6325_RG_VTCXO1_MODE_SET_SHIFT 0 |
| 3865 | #define MT6325_RG_VTCXO1_EN_MASK 0x1 |
| 3866 | #define MT6325_RG_VTCXO1_EN_SHIFT 1 |
| 3867 | #define MT6325_RG_VTCXO1_MODE_CTRL_MASK 0x1 |
| 3868 | #define MT6325_RG_VTCXO1_MODE_CTRL_SHIFT 2 |
| 3869 | #define MT6325_RG_VTCXO1_ON_CTRL_MASK 0x1 |
| 3870 | #define MT6325_RG_VTCXO1_ON_CTRL_SHIFT 3 |
| 3871 | #define MT6325_RG_VTCXO1_SRCLK_MODE_SEL_MASK 0x3 |
| 3872 | #define MT6325_RG_VTCXO1_SRCLK_MODE_SEL_SHIFT 4 |
| 3873 | #define MT6325_QI_VTCXO1_MODE_MASK 0x1 |
| 3874 | #define MT6325_QI_VTCXO1_MODE_SHIFT 7 |
| 3875 | #define MT6325_RG_VTCXO1_STBTD_MASK 0x3 |
| 3876 | #define MT6325_RG_VTCXO1_STBTD_SHIFT 8 |
| 3877 | #define MT6325_RG_VTCXO1_SRCLK_EN_SEL_MASK 0x3 |
| 3878 | #define MT6325_RG_VTCXO1_SRCLK_EN_SEL_SHIFT 12 |
| 3879 | #define MT6325_QI_VTCXO1_STB_MASK 0x1 |
| 3880 | #define MT6325_QI_VTCXO1_STB_SHIFT 14 |
| 3881 | #define MT6325_QI_VTCXO1_EN_MASK 0x1 |
| 3882 | #define MT6325_QI_VTCXO1_EN_SHIFT 15 |
| 3883 | #define MT6325_RG_VAUD28_MODE_SET_MASK 0x1 |
| 3884 | #define MT6325_RG_VAUD28_MODE_SET_SHIFT 0 |
| 3885 | #define MT6325_RG_VAUD28_EN_MASK 0x1 |
| 3886 | #define MT6325_RG_VAUD28_EN_SHIFT 1 |
| 3887 | #define MT6325_RG_VAUD28_MODE_CTRL_MASK 0x1 |
| 3888 | #define MT6325_RG_VAUD28_MODE_CTRL_SHIFT 2 |
| 3889 | #define MT6325_RG_VAUD28_ON_CTRL_MASK 0x1 |
| 3890 | #define MT6325_RG_VAUD28_ON_CTRL_SHIFT 3 |
| 3891 | #define MT6325_RG_VAUD28_SRCLK_MODE_SEL_MASK 0x3 |
| 3892 | #define MT6325_RG_VAUD28_SRCLK_MODE_SEL_SHIFT 4 |
| 3893 | #define MT6325_QI_VAUD28_MODE_MASK 0x1 |
| 3894 | #define MT6325_QI_VAUD28_MODE_SHIFT 7 |
| 3895 | #define MT6325_RG_VAUD28_STBTD_MASK 0x3 |
| 3896 | #define MT6325_RG_VAUD28_STBTD_SHIFT 8 |
| 3897 | #define MT6325_RG_VAUD28_SRCLK_EN_SEL_MASK 0x3 |
| 3898 | #define MT6325_RG_VAUD28_SRCLK_EN_SEL_SHIFT 12 |
| 3899 | #define MT6325_QI_VAUD28_STB_MASK 0x1 |
| 3900 | #define MT6325_QI_VAUD28_STB_SHIFT 14 |
| 3901 | #define MT6325_QI_VAUD28_EN_MASK 0x1 |
| 3902 | #define MT6325_QI_VAUD28_EN_SHIFT 15 |
| 3903 | #define MT6325_RG_VAUXA28_MODE_SET_MASK 0x1 |
| 3904 | #define MT6325_RG_VAUXA28_MODE_SET_SHIFT 0 |
| 3905 | #define MT6325_RG_VAUXA28_EN_MASK 0x1 |
| 3906 | #define MT6325_RG_VAUXA28_EN_SHIFT 1 |
| 3907 | #define MT6325_RG_VAUXA28_MODE_CTRL_MASK 0x1 |
| 3908 | #define MT6325_RG_VAUXA28_MODE_CTRL_SHIFT 2 |
| 3909 | #define MT6325_RG_VAUXA28_ON_CTRL_MASK 0x1 |
| 3910 | #define MT6325_RG_VAUXA28_ON_CTRL_SHIFT 3 |
| 3911 | #define MT6325_RG_VAUXA28_SRCLK_MODE_SEL_MASK 0x3 |
| 3912 | #define MT6325_RG_VAUXA28_SRCLK_MODE_SEL_SHIFT 4 |
| 3913 | #define MT6325_QI_VAUXA28_MODE_MASK 0x1 |
| 3914 | #define MT6325_QI_VAUXA28_MODE_SHIFT 7 |
| 3915 | #define MT6325_RG_VAUXA28_STBTD_MASK 0x3 |
| 3916 | #define MT6325_RG_VAUXA28_STBTD_SHIFT 8 |
| 3917 | #define MT6325_RG_VAUXA28_AUXADC_PWDB_EN_MASK 0x1 |
| 3918 | #define MT6325_RG_VAUXA28_AUXADC_PWDB_EN_SHIFT 11 |
| 3919 | #define MT6325_RG_VAUXA28_SRCLK_EN_SEL_MASK 0x3 |
| 3920 | #define MT6325_RG_VAUXA28_SRCLK_EN_SEL_SHIFT 12 |
| 3921 | #define MT6325_QI_VAUXA28_STB_MASK 0x1 |
| 3922 | #define MT6325_QI_VAUXA28_STB_SHIFT 14 |
| 3923 | #define MT6325_QI_VAUXA28_EN_MASK 0x1 |
| 3924 | #define MT6325_QI_VAUXA28_EN_SHIFT 15 |
| 3925 | #define MT6325_RG_VBIF28_MODE_SET_MASK 0x1 |
| 3926 | #define MT6325_RG_VBIF28_MODE_SET_SHIFT 0 |
| 3927 | #define MT6325_RG_VBIF28_EN_MASK 0x1 |
| 3928 | #define MT6325_RG_VBIF28_EN_SHIFT 1 |
| 3929 | #define MT6325_RG_VBIF28_MODE_CTRL_MASK 0x1 |
| 3930 | #define MT6325_RG_VBIF28_MODE_CTRL_SHIFT 2 |
| 3931 | #define MT6325_RG_VBIF28_ON_CTRL_MASK 0x1 |
| 3932 | #define MT6325_RG_VBIF28_ON_CTRL_SHIFT 3 |
| 3933 | #define MT6325_RG_VBIF28_SRCLK_MODE_SEL_MASK 0x3 |
| 3934 | #define MT6325_RG_VBIF28_SRCLK_MODE_SEL_SHIFT 4 |
| 3935 | #define MT6325_QI_VBIF28_MODE_MASK 0x1 |
| 3936 | #define MT6325_QI_VBIF28_MODE_SHIFT 7 |
| 3937 | #define MT6325_RG_VBIF28_STBTD_MASK 0x3 |
| 3938 | #define MT6325_RG_VBIF28_STBTD_SHIFT 8 |
| 3939 | #define MT6325_RG_VBIF28_SRCLK_EN_SEL_MASK 0x3 |
| 3940 | #define MT6325_RG_VBIF28_SRCLK_EN_SEL_SHIFT 12 |
| 3941 | #define MT6325_QI_VBIF28_STB_MASK 0x1 |
| 3942 | #define MT6325_QI_VBIF28_STB_SHIFT 14 |
| 3943 | #define MT6325_QI_VBIF28_EN_MASK 0x1 |
| 3944 | #define MT6325_QI_VBIF28_EN_SHIFT 15 |
| 3945 | #define MT6325_RG_VCAMA_EN_MASK 0x1 |
| 3946 | #define MT6325_RG_VCAMA_EN_SHIFT 1 |
| 3947 | #define MT6325_RG_VCAMA_STBTD_MASK 0x3 |
| 3948 | #define MT6325_RG_VCAMA_STBTD_SHIFT 8 |
| 3949 | #define MT6325_QI_VCAMA_STB_MASK 0x1 |
| 3950 | #define MT6325_QI_VCAMA_STB_SHIFT 14 |
| 3951 | #define MT6325_QI_VCAMA_EN_MASK 0x1 |
| 3952 | #define MT6325_QI_VCAMA_EN_SHIFT 15 |
| 3953 | #define MT6325_RG_VCN28_MODE_SET_MASK 0x1 |
| 3954 | #define MT6325_RG_VCN28_MODE_SET_SHIFT 0 |
| 3955 | #define MT6325_RG_VCN28_EN_MASK 0x1 |
| 3956 | #define MT6325_RG_VCN28_EN_SHIFT 1 |
| 3957 | #define MT6325_RG_VCN28_MODE_CTRL_MASK 0x1 |
| 3958 | #define MT6325_RG_VCN28_MODE_CTRL_SHIFT 2 |
| 3959 | #define MT6325_RG_VCN28_ON_CTRL_MASK 0x1 |
| 3960 | #define MT6325_RG_VCN28_ON_CTRL_SHIFT 3 |
| 3961 | #define MT6325_RG_VCN28_SRCLK_MODE_SEL_MASK 0x3 |
| 3962 | #define MT6325_RG_VCN28_SRCLK_MODE_SEL_SHIFT 4 |
| 3963 | #define MT6325_QI_VCN28_MODE_MASK 0x1 |
| 3964 | #define MT6325_QI_VCN28_MODE_SHIFT 7 |
| 3965 | #define MT6325_RG_VCN28_STBTD_MASK 0x3 |
| 3966 | #define MT6325_RG_VCN28_STBTD_SHIFT 8 |
| 3967 | #define MT6325_RG_VCN28_SRCLK_EN_SEL_MASK 0x3 |
| 3968 | #define MT6325_RG_VCN28_SRCLK_EN_SEL_SHIFT 12 |
| 3969 | #define MT6325_QI_VCN28_STB_MASK 0x1 |
| 3970 | #define MT6325_QI_VCN28_STB_SHIFT 14 |
| 3971 | #define MT6325_QI_VCN28_EN_MASK 0x1 |
| 3972 | #define MT6325_QI_VCN28_EN_SHIFT 15 |
| 3973 | #define MT6325_RG_VCN33_MODE_SET_MASK 0x1 |
| 3974 | #define MT6325_RG_VCN33_MODE_SET_SHIFT 0 |
| 3975 | #define MT6325_RG_VCN33_EN_MASK 0x1 |
| 3976 | #define MT6325_RG_VCN33_EN_SHIFT 1 |
| 3977 | #define MT6325_RG_VCN33_MODE_CTRL_MASK 0x1 |
| 3978 | #define MT6325_RG_VCN33_MODE_CTRL_SHIFT 2 |
| 3979 | #define MT6325_RG_VCN33_ON_CTRL_MASK 0x1 |
| 3980 | #define MT6325_RG_VCN33_ON_CTRL_SHIFT 3 |
| 3981 | #define MT6325_RG_VCN33_SRCLK_MODE_SEL_MASK 0x3 |
| 3982 | #define MT6325_RG_VCN33_SRCLK_MODE_SEL_SHIFT 4 |
| 3983 | #define MT6325_QI_VCN33_MODE_MASK 0x1 |
| 3984 | #define MT6325_QI_VCN33_MODE_SHIFT 7 |
| 3985 | #define MT6325_RG_VCN33_STBTD_MASK 0x3 |
| 3986 | #define MT6325_RG_VCN33_STBTD_SHIFT 8 |
| 3987 | #define MT6325_RG_VCN33_SRCLK_EN_SEL_MASK 0x3 |
| 3988 | #define MT6325_RG_VCN33_SRCLK_EN_SEL_SHIFT 12 |
| 3989 | #define MT6325_QI_VCN33_STB_MASK 0x1 |
| 3990 | #define MT6325_QI_VCN33_STB_SHIFT 14 |
| 3991 | #define MT6325_QI_VCN33_EN_MASK 0x1 |
| 3992 | #define MT6325_QI_VCN33_EN_SHIFT 15 |
| 3993 | #define MT6325_RG_VRF18_1_MODE_SET_MASK 0x1 |
| 3994 | #define MT6325_RG_VRF18_1_MODE_SET_SHIFT 0 |
| 3995 | #define MT6325_RG_VRF18_1_EN_MASK 0x1 |
| 3996 | #define MT6325_RG_VRF18_1_EN_SHIFT 1 |
| 3997 | #define MT6325_RG_VRF18_1_MODE_CTRL_MASK 0x1 |
| 3998 | #define MT6325_RG_VRF18_1_MODE_CTRL_SHIFT 2 |
| 3999 | #define MT6325_RG_VRF18_1_ON_CTRL_MASK 0x1 |
| 4000 | #define MT6325_RG_VRF18_1_ON_CTRL_SHIFT 3 |
| 4001 | #define MT6325_RG_VRF18_1_SRCLK_MODE_SEL_MASK 0x3 |
| 4002 | #define MT6325_RG_VRF18_1_SRCLK_MODE_SEL_SHIFT 4 |
| 4003 | #define MT6325_QI_VRF18_1_MODE_MASK 0x1 |
| 4004 | #define MT6325_QI_VRF18_1_MODE_SHIFT 7 |
| 4005 | #define MT6325_RG_VRF18_1_STBTD_MASK 0x3 |
| 4006 | #define MT6325_RG_VRF18_1_STBTD_SHIFT 8 |
| 4007 | #define MT6325_RG_VRF18_1_SRCLK_EN_SEL_MASK 0x3 |
| 4008 | #define MT6325_RG_VRF18_1_SRCLK_EN_SEL_SHIFT 12 |
| 4009 | #define MT6325_QI_VRF18_1_STB_MASK 0x1 |
| 4010 | #define MT6325_QI_VRF18_1_STB_SHIFT 14 |
| 4011 | #define MT6325_QI_VRF18_1_EN_MASK 0x1 |
| 4012 | #define MT6325_QI_VRF18_1_EN_SHIFT 15 |
| 4013 | #define MT6325_RG_VUSB33_MODE_SET_MASK 0x1 |
| 4014 | #define MT6325_RG_VUSB33_MODE_SET_SHIFT 0 |
| 4015 | #define MT6325_RG_VUSB33_EN_MASK 0x1 |
| 4016 | #define MT6325_RG_VUSB33_EN_SHIFT 1 |
| 4017 | #define MT6325_RG_VUSB33_MODE_CTRL_MASK 0x1 |
| 4018 | #define MT6325_RG_VUSB33_MODE_CTRL_SHIFT 2 |
| 4019 | #define MT6325_RG_VUSB33_ON_CTRL_MASK 0x1 |
| 4020 | #define MT6325_RG_VUSB33_ON_CTRL_SHIFT 3 |
| 4021 | #define MT6325_RG_VUSB33_SRCLK_MODE_SEL_MASK 0x3 |
| 4022 | #define MT6325_RG_VUSB33_SRCLK_MODE_SEL_SHIFT 4 |
| 4023 | #define MT6325_QI_VUSB33_MODE_MASK 0x1 |
| 4024 | #define MT6325_QI_VUSB33_MODE_SHIFT 7 |
| 4025 | #define MT6325_RG_VUSB33_STBTD_MASK 0x3 |
| 4026 | #define MT6325_RG_VUSB33_STBTD_SHIFT 8 |
| 4027 | #define MT6325_RG_VUSB33_SRCLK_EN_SEL_MASK 0x3 |
| 4028 | #define MT6325_RG_VUSB33_SRCLK_EN_SEL_SHIFT 12 |
| 4029 | #define MT6325_QI_VUSB33_STB_MASK 0x1 |
| 4030 | #define MT6325_QI_VUSB33_STB_SHIFT 14 |
| 4031 | #define MT6325_QI_VUSB33_EN_MASK 0x1 |
| 4032 | #define MT6325_QI_VUSB33_EN_SHIFT 15 |
| 4033 | #define MT6325_RG_VMCH_MODE_SET_MASK 0x1 |
| 4034 | #define MT6325_RG_VMCH_MODE_SET_SHIFT 0 |
| 4035 | #define MT6325_RG_VMCH_EN_MASK 0x1 |
| 4036 | #define MT6325_RG_VMCH_EN_SHIFT 1 |
| 4037 | #define MT6325_RG_VMCH_MODE_CTRL_MASK 0x1 |
| 4038 | #define MT6325_RG_VMCH_MODE_CTRL_SHIFT 2 |
| 4039 | #define MT6325_RG_VMCH_ON_CTRL_MASK 0x1 |
| 4040 | #define MT6325_RG_VMCH_ON_CTRL_SHIFT 3 |
| 4041 | #define MT6325_RG_VMCH_SRCLK_MODE_SEL_MASK 0x3 |
| 4042 | #define MT6325_RG_VMCH_SRCLK_MODE_SEL_SHIFT 4 |
| 4043 | #define MT6325_QI_VMCH_MODE_MASK 0x1 |
| 4044 | #define MT6325_QI_VMCH_MODE_SHIFT 7 |
| 4045 | #define MT6325_RG_VMCH_STBTD_MASK 0x3 |
| 4046 | #define MT6325_RG_VMCH_STBTD_SHIFT 8 |
| 4047 | #define MT6325_RG_VMCH_SRCLK_EN_SEL_MASK 0x3 |
| 4048 | #define MT6325_RG_VMCH_SRCLK_EN_SEL_SHIFT 12 |
| 4049 | #define MT6325_QI_VMCH_STB_MASK 0x1 |
| 4050 | #define MT6325_QI_VMCH_STB_SHIFT 14 |
| 4051 | #define MT6325_QI_VMCH_EN_MASK 0x1 |
| 4052 | #define MT6325_QI_VMCH_EN_SHIFT 15 |
| 4053 | #define MT6325_RG_VMC_MODE_SET_MASK 0x1 |
| 4054 | #define MT6325_RG_VMC_MODE_SET_SHIFT 0 |
| 4055 | #define MT6325_RG_VMC_EN_MASK 0x1 |
| 4056 | #define MT6325_RG_VMC_EN_SHIFT 1 |
| 4057 | #define MT6325_RG_VMC_MODE_CTRL_MASK 0x1 |
| 4058 | #define MT6325_RG_VMC_MODE_CTRL_SHIFT 2 |
| 4059 | #define MT6325_RG_VMC_ON_CTRL_MASK 0x1 |
| 4060 | #define MT6325_RG_VMC_ON_CTRL_SHIFT 3 |
| 4061 | #define MT6325_RG_VMC_SRCLK_MODE_SEL_MASK 0x3 |
| 4062 | #define MT6325_RG_VMC_SRCLK_MODE_SEL_SHIFT 4 |
| 4063 | #define MT6325_QI_VMC_INT_DIS_MASK 0x1 |
| 4064 | #define MT6325_QI_VMC_INT_DIS_SHIFT 6 |
| 4065 | #define MT6325_QI_VMC_MODE_MASK 0x1 |
| 4066 | #define MT6325_QI_VMC_MODE_SHIFT 7 |
| 4067 | #define MT6325_RG_VMC_STBTD_MASK 0x3 |
| 4068 | #define MT6325_RG_VMC_STBTD_SHIFT 8 |
| 4069 | #define MT6325_RG_VMC_INT_DIS_SEL_MASK 0x3 |
| 4070 | #define MT6325_RG_VMC_INT_DIS_SEL_SHIFT 10 |
| 4071 | #define MT6325_RG_VMC_SRCLK_EN_SEL_MASK 0x3 |
| 4072 | #define MT6325_RG_VMC_SRCLK_EN_SEL_SHIFT 12 |
| 4073 | #define MT6325_QI_VMC_STB_MASK 0x1 |
| 4074 | #define MT6325_QI_VMC_STB_SHIFT 14 |
| 4075 | #define MT6325_QI_VMC_EN_MASK 0x1 |
| 4076 | #define MT6325_QI_VMC_EN_SHIFT 15 |
| 4077 | #define MT6325_RG_VEMC33_MODE_SET_MASK 0x1 |
| 4078 | #define MT6325_RG_VEMC33_MODE_SET_SHIFT 0 |
| 4079 | #define MT6325_RG_VEMC33_EN_MASK 0x1 |
| 4080 | #define MT6325_RG_VEMC33_EN_SHIFT 1 |
| 4081 | #define MT6325_RG_VEMC33_MODE_CTRL_MASK 0x1 |
| 4082 | #define MT6325_RG_VEMC33_MODE_CTRL_SHIFT 2 |
| 4083 | #define MT6325_RG_VEMC33_ON_CTRL_MASK 0x1 |
| 4084 | #define MT6325_RG_VEMC33_ON_CTRL_SHIFT 3 |
| 4085 | #define MT6325_RG_VEMC33_SRCLK_MODE_SEL_MASK 0x3 |
| 4086 | #define MT6325_RG_VEMC33_SRCLK_MODE_SEL_SHIFT 4 |
| 4087 | #define MT6325_QI_VEMC_3V3_MODE_MASK 0x1 |
| 4088 | #define MT6325_QI_VEMC_3V3_MODE_SHIFT 7 |
| 4089 | #define MT6325_RG_VEMC33_STBTD_MASK 0x3 |
| 4090 | #define MT6325_RG_VEMC33_STBTD_SHIFT 8 |
| 4091 | #define MT6325_RG_VEMC33_SRCLK_EN_SEL_MASK 0x3 |
| 4092 | #define MT6325_RG_VEMC33_SRCLK_EN_SEL_SHIFT 12 |
| 4093 | #define MT6325_QI_VEMC_3V3_STB_MASK 0x1 |
| 4094 | #define MT6325_QI_VEMC_3V3_STB_SHIFT 14 |
| 4095 | #define MT6325_QI_VEMC_3V3_EN_MASK 0x1 |
| 4096 | #define MT6325_QI_VEMC_3V3_EN_SHIFT 15 |
| 4097 | #define MT6325_RG_VIO28_MODE_SET_MASK 0x1 |
| 4098 | #define MT6325_RG_VIO28_MODE_SET_SHIFT 0 |
| 4099 | #define MT6325_RG_VIO28_EN_MASK 0x1 |
| 4100 | #define MT6325_RG_VIO28_EN_SHIFT 1 |
| 4101 | #define MT6325_RG_VIO28_MODE_CTRL_MASK 0x1 |
| 4102 | #define MT6325_RG_VIO28_MODE_CTRL_SHIFT 2 |
| 4103 | #define MT6325_RG_VIO28_ON_CTRL_MASK 0x1 |
| 4104 | #define MT6325_RG_VIO28_ON_CTRL_SHIFT 3 |
| 4105 | #define MT6325_RG_VIO28_SRCLK_MODE_SEL_MASK 0x3 |
| 4106 | #define MT6325_RG_VIO28_SRCLK_MODE_SEL_SHIFT 4 |
| 4107 | #define MT6325_QI_VIO28_MODE_MASK 0x1 |
| 4108 | #define MT6325_QI_VIO28_MODE_SHIFT 7 |
| 4109 | #define MT6325_RG_VIO28_STBTD_MASK 0x3 |
| 4110 | #define MT6325_RG_VIO28_STBTD_SHIFT 8 |
| 4111 | #define MT6325_RG_VIO28_SRCLK_EN_SEL_MASK 0x3 |
| 4112 | #define MT6325_RG_VIO28_SRCLK_EN_SEL_SHIFT 12 |
| 4113 | #define MT6325_QI_VIO28_STB_MASK 0x1 |
| 4114 | #define MT6325_QI_VIO28_STB_SHIFT 14 |
| 4115 | #define MT6325_QI_VIO28_EN_MASK 0x1 |
| 4116 | #define MT6325_QI_VIO28_EN_SHIFT 15 |
| 4117 | #define MT6325_RG_VCAM_AF_MODE_SET_MASK 0x1 |
| 4118 | #define MT6325_RG_VCAM_AF_MODE_SET_SHIFT 0 |
| 4119 | #define MT6325_RG_VCAM_AF_EN_MASK 0x1 |
| 4120 | #define MT6325_RG_VCAM_AF_EN_SHIFT 1 |
| 4121 | #define MT6325_RG_VCAM_AF_MODE_CTRL_MASK 0x1 |
| 4122 | #define MT6325_RG_VCAM_AF_MODE_CTRL_SHIFT 2 |
| 4123 | #define MT6325_RG_VCAM_AF_ON_CTRL_MASK 0x1 |
| 4124 | #define MT6325_RG_VCAM_AF_ON_CTRL_SHIFT 3 |
| 4125 | #define MT6325_RG_VCAM_AF_SRCLK_MODE_SEL_MASK 0x3 |
| 4126 | #define MT6325_RG_VCAM_AF_SRCLK_MODE_SEL_SHIFT 4 |
| 4127 | #define MT6325_QI_VCAMAF_MODE_MASK 0x1 |
| 4128 | #define MT6325_QI_VCAMAF_MODE_SHIFT 7 |
| 4129 | #define MT6325_RG_VCAM_AF_STBTD_MASK 0x3 |
| 4130 | #define MT6325_RG_VCAM_AF_STBTD_SHIFT 8 |
| 4131 | #define MT6325_RG_VCAM_AF_SRCLK_EN_SEL_MASK 0x3 |
| 4132 | #define MT6325_RG_VCAM_AF_SRCLK_EN_SEL_SHIFT 12 |
| 4133 | #define MT6325_QI_VCAMAF_STB_MASK 0x1 |
| 4134 | #define MT6325_QI_VCAMAF_STB_SHIFT 14 |
| 4135 | #define MT6325_QI_VCAMAF_EN_MASK 0x1 |
| 4136 | #define MT6325_QI_VCAMAF_EN_SHIFT 15 |
| 4137 | #define MT6325_RG_VGP1_MODE_SET_MASK 0x1 |
| 4138 | #define MT6325_RG_VGP1_MODE_SET_SHIFT 0 |
| 4139 | #define MT6325_RG_VGP1_EN_MASK 0x1 |
| 4140 | #define MT6325_RG_VGP1_EN_SHIFT 1 |
| 4141 | #define MT6325_RG_VGP1_MODE_CTRL_MASK 0x1 |
| 4142 | #define MT6325_RG_VGP1_MODE_CTRL_SHIFT 2 |
| 4143 | #define MT6325_RG_VGP1_ON_CTRL_MASK 0x1 |
| 4144 | #define MT6325_RG_VGP1_ON_CTRL_SHIFT 3 |
| 4145 | #define MT6325_RG_VGP1_SRCLK_MODE_SEL_MASK 0x3 |
| 4146 | #define MT6325_RG_VGP1_SRCLK_MODE_SEL_SHIFT 4 |
| 4147 | #define MT6325_QI_VGP1_MODE_MASK 0x1 |
| 4148 | #define MT6325_QI_VGP1_MODE_SHIFT 7 |
| 4149 | #define MT6325_RG_VGP1_STBTD_MASK 0x3 |
| 4150 | #define MT6325_RG_VGP1_STBTD_SHIFT 8 |
| 4151 | #define MT6325_RG_VGP1_SRCLK_EN_SEL_MASK 0x3 |
| 4152 | #define MT6325_RG_VGP1_SRCLK_EN_SEL_SHIFT 12 |
| 4153 | #define MT6325_QI_VGP1_STB_MASK 0x1 |
| 4154 | #define MT6325_QI_VGP1_STB_SHIFT 14 |
| 4155 | #define MT6325_QI_VGP1_EN_MASK 0x1 |
| 4156 | #define MT6325_QI_VGP1_EN_SHIFT 15 |
| 4157 | #define MT6325_RG_VEFUSE_MODE_SET_MASK 0x1 |
| 4158 | #define MT6325_RG_VEFUSE_MODE_SET_SHIFT 0 |
| 4159 | #define MT6325_RG_VEFUSE_EN_MASK 0x1 |
| 4160 | #define MT6325_RG_VEFUSE_EN_SHIFT 1 |
| 4161 | #define MT6325_RG_VEFUSE_MODE_CTRL_MASK 0x1 |
| 4162 | #define MT6325_RG_VEFUSE_MODE_CTRL_SHIFT 2 |
| 4163 | #define MT6325_RG_VEFUSE_ON_CTRL_MASK 0x1 |
| 4164 | #define MT6325_RG_VEFUSE_ON_CTRL_SHIFT 3 |
| 4165 | #define MT6325_RG_VEFUSE_SRCLK_MODE_SEL_MASK 0x3 |
| 4166 | #define MT6325_RG_VEFUSE_SRCLK_MODE_SEL_SHIFT 4 |
| 4167 | #define MT6325_QI_VEFUSE_MODE_MASK 0x1 |
| 4168 | #define MT6325_QI_VEFUSE_MODE_SHIFT 7 |
| 4169 | #define MT6325_RG_VEFUSE_STBTD_MASK 0x3 |
| 4170 | #define MT6325_RG_VEFUSE_STBTD_SHIFT 8 |
| 4171 | #define MT6325_RG_VEFUSE_SRCLK_EN_SEL_MASK 0x3 |
| 4172 | #define MT6325_RG_VEFUSE_SRCLK_EN_SEL_SHIFT 12 |
| 4173 | #define MT6325_QI_VEFUSE_STB_MASK 0x1 |
| 4174 | #define MT6325_QI_VEFUSE_STB_SHIFT 14 |
| 4175 | #define MT6325_QI_VEFUSE_EN_MASK 0x1 |
| 4176 | #define MT6325_QI_VEFUSE_EN_SHIFT 15 |
| 4177 | #define MT6325_RG_VSIM1_MODE_SET_MASK 0x1 |
| 4178 | #define MT6325_RG_VSIM1_MODE_SET_SHIFT 0 |
| 4179 | #define MT6325_RG_VSIM1_EN_MASK 0x1 |
| 4180 | #define MT6325_RG_VSIM1_EN_SHIFT 1 |
| 4181 | #define MT6325_RG_VSIM1_MODE_CTRL_MASK 0x1 |
| 4182 | #define MT6325_RG_VSIM1_MODE_CTRL_SHIFT 2 |
| 4183 | #define MT6325_RG_VSIM1_ON_CTRL_MASK 0x1 |
| 4184 | #define MT6325_RG_VSIM1_ON_CTRL_SHIFT 3 |
| 4185 | #define MT6325_RG_VSIM1_SRCLK_MODE_SEL_MASK 0x3 |
| 4186 | #define MT6325_RG_VSIM1_SRCLK_MODE_SEL_SHIFT 4 |
| 4187 | #define MT6325_QI_VSIM1_MODE_MASK 0x1 |
| 4188 | #define MT6325_QI_VSIM1_MODE_SHIFT 7 |
| 4189 | #define MT6325_RG_VSIM1_STBTD_MASK 0x3 |
| 4190 | #define MT6325_RG_VSIM1_STBTD_SHIFT 8 |
| 4191 | #define MT6325_RG_VSIM1_SRCLK_EN_SEL_MASK 0x3 |
| 4192 | #define MT6325_RG_VSIM1_SRCLK_EN_SEL_SHIFT 12 |
| 4193 | #define MT6325_QI_VSIM1_STB_MASK 0x1 |
| 4194 | #define MT6325_QI_VSIM1_STB_SHIFT 14 |
| 4195 | #define MT6325_QI_VSIM1_EN_MASK 0x1 |
| 4196 | #define MT6325_QI_VSIM1_EN_SHIFT 15 |
| 4197 | #define MT6325_RG_VSIM2_MODE_SET_MASK 0x1 |
| 4198 | #define MT6325_RG_VSIM2_MODE_SET_SHIFT 0 |
| 4199 | #define MT6325_RG_VSIM2_EN_MASK 0x1 |
| 4200 | #define MT6325_RG_VSIM2_EN_SHIFT 1 |
| 4201 | #define MT6325_RG_VSIM2_MODE_CTRL_MASK 0x1 |
| 4202 | #define MT6325_RG_VSIM2_MODE_CTRL_SHIFT 2 |
| 4203 | #define MT6325_RG_VSIM2_ON_CTRL_MASK 0x1 |
| 4204 | #define MT6325_RG_VSIM2_ON_CTRL_SHIFT 3 |
| 4205 | #define MT6325_RG_VSIM2_SRCLK_MODE_SEL_MASK 0x3 |
| 4206 | #define MT6325_RG_VSIM2_SRCLK_MODE_SEL_SHIFT 4 |
| 4207 | #define MT6325_QI_VSIM2_MODE_MASK 0x1 |
| 4208 | #define MT6325_QI_VSIM2_MODE_SHIFT 7 |
| 4209 | #define MT6325_RG_VSIM2_STBTD_MASK 0x3 |
| 4210 | #define MT6325_RG_VSIM2_STBTD_SHIFT 8 |
| 4211 | #define MT6325_RG_VSIM2_SRCLK_EN_SEL_MASK 0x3 |
| 4212 | #define MT6325_RG_VSIM2_SRCLK_EN_SEL_SHIFT 12 |
| 4213 | #define MT6325_QI_VSIM2_STB_MASK 0x1 |
| 4214 | #define MT6325_QI_VSIM2_STB_SHIFT 14 |
| 4215 | #define MT6325_QI_VSIM2_EN_MASK 0x1 |
| 4216 | #define MT6325_QI_VSIM2_EN_SHIFT 15 |
| 4217 | #define MT6325_RG_VMIPI_MODE_SET_MASK 0x1 |
| 4218 | #define MT6325_RG_VMIPI_MODE_SET_SHIFT 0 |
| 4219 | #define MT6325_RG_VMIPI_EN_MASK 0x1 |
| 4220 | #define MT6325_RG_VMIPI_EN_SHIFT 1 |
| 4221 | #define MT6325_RG_VMIPI_MODE_CTRL_MASK 0x1 |
| 4222 | #define MT6325_RG_VMIPI_MODE_CTRL_SHIFT 2 |
| 4223 | #define MT6325_RG_VMIPI_ON_CTRL_MASK 0x1 |
| 4224 | #define MT6325_RG_VMIPI_ON_CTRL_SHIFT 3 |
| 4225 | #define MT6325_RG_VMIPI_SRCLK_MODE_SEL_MASK 0x3 |
| 4226 | #define MT6325_RG_VMIPI_SRCLK_MODE_SEL_SHIFT 4 |
| 4227 | #define MT6325_QI_VMIPI_MODE_MASK 0x1 |
| 4228 | #define MT6325_QI_VMIPI_MODE_SHIFT 7 |
| 4229 | #define MT6325_RG_VMIPI_STBTD_MASK 0x3 |
| 4230 | #define MT6325_RG_VMIPI_STBTD_SHIFT 8 |
| 4231 | #define MT6325_RG_VMIPI_SRCLK_EN_SEL_MASK 0x3 |
| 4232 | #define MT6325_RG_VMIPI_SRCLK_EN_SEL_SHIFT 12 |
| 4233 | #define MT6325_QI_VMIPI_STB_MASK 0x1 |
| 4234 | #define MT6325_QI_VMIPI_STB_SHIFT 14 |
| 4235 | #define MT6325_QI_VMIPI_EN_MASK 0x1 |
| 4236 | #define MT6325_QI_VMIPI_EN_SHIFT 15 |
| 4237 | #define MT6325_RG_VIBR_THER_SHEN_EN_MASK 0x1 |
| 4238 | #define MT6325_RG_VIBR_THER_SHEN_EN_SHIFT 0 |
| 4239 | #define MT6325_RG_VIBR_EN_MASK 0x1 |
| 4240 | #define MT6325_RG_VIBR_EN_SHIFT 1 |
| 4241 | #define MT6325_RG_VIBR_SW_MODE_MASK 0x1 |
| 4242 | #define MT6325_RG_VIBR_SW_MODE_SHIFT 3 |
| 4243 | #define MT6325_RG_VIBR_FR_ORI_MASK 0x3 |
| 4244 | #define MT6325_RG_VIBR_FR_ORI_SHIFT 4 |
| 4245 | #define MT6325_RG_VIBR_MST_TIME_MASK 0x3 |
| 4246 | #define MT6325_RG_VIBR_MST_TIME_SHIFT 8 |
| 4247 | #define MT6325_RG_VIBR_MID_STATE_MASK 0x3 |
| 4248 | #define MT6325_RG_VIBR_MID_STATE_SHIFT 10 |
| 4249 | #define MT6325_QI_VIBR_FR_MASK 0x3 |
| 4250 | #define MT6325_QI_VIBR_FR_SHIFT 12 |
| 4251 | #define MT6325_RG_VIBR_PWDB_MASK 0x1 |
| 4252 | #define MT6325_RG_VIBR_PWDB_SHIFT 15 |
| 4253 | #define MT6325_RG_VCN18_MODE_SET_MASK 0x1 |
| 4254 | #define MT6325_RG_VCN18_MODE_SET_SHIFT 0 |
| 4255 | #define MT6325_RG_VCN18_EN_MASK 0x1 |
| 4256 | #define MT6325_RG_VCN18_EN_SHIFT 1 |
| 4257 | #define MT6325_RG_VCN18_MODE_CTRL_MASK 0x1 |
| 4258 | #define MT6325_RG_VCN18_MODE_CTRL_SHIFT 2 |
| 4259 | #define MT6325_RG_VCN18_ON_CTRL_MASK 0x1 |
| 4260 | #define MT6325_RG_VCN18_ON_CTRL_SHIFT 3 |
| 4261 | #define MT6325_RG_VCN18_SRCLK_MODE_SEL_MASK 0x3 |
| 4262 | #define MT6325_RG_VCN18_SRCLK_MODE_SEL_SHIFT 4 |
| 4263 | #define MT6325_QI_VCN18_MODE_MASK 0x1 |
| 4264 | #define MT6325_QI_VCN18_MODE_SHIFT 7 |
| 4265 | #define MT6325_RG_VCN18_STBTD_MASK 0x3 |
| 4266 | #define MT6325_RG_VCN18_STBTD_SHIFT 8 |
| 4267 | #define MT6325_RG_VCN18_SRCLK_EN_SEL_MASK 0x3 |
| 4268 | #define MT6325_RG_VCN18_SRCLK_EN_SEL_SHIFT 12 |
| 4269 | #define MT6325_QI_VCN18_STB_MASK 0x1 |
| 4270 | #define MT6325_QI_VCN18_STB_SHIFT 14 |
| 4271 | #define MT6325_QI_VCN18_EN_MASK 0x1 |
| 4272 | #define MT6325_QI_VCN18_EN_SHIFT 15 |
| 4273 | #define MT6325_NI_VDIG18_VOSEL_MASK 0x7 |
| 4274 | #define MT6325_NI_VDIG18_VOSEL_SHIFT 0 |
| 4275 | #define MT6325_RG_VDIG18_SRCLKEN_SEL_MASK 0x3 |
| 4276 | #define MT6325_RG_VDIG18_SRCLKEN_SEL_SHIFT 7 |
| 4277 | #define MT6325_RG_VDIG18_SLEEP_VOSEL_MASK 0x7 |
| 4278 | #define MT6325_RG_VDIG18_SLEEP_VOSEL_SHIFT 9 |
| 4279 | #define MT6325_RG_VDIG18_VOSEL_MASK 0x7 |
| 4280 | #define MT6325_RG_VDIG18_VOSEL_SHIFT 12 |
| 4281 | #define MT6325_RG_VDIG18_VOSEL_CTRL_MASK 0x1 |
| 4282 | #define MT6325_RG_VDIG18_VOSEL_CTRL_SHIFT 15 |
| 4283 | #define MT6325_RG_VGP2_MODE_SET_MASK 0x1 |
| 4284 | #define MT6325_RG_VGP2_MODE_SET_SHIFT 0 |
| 4285 | #define MT6325_RG_VGP2_EN_MASK 0x1 |
| 4286 | #define MT6325_RG_VGP2_EN_SHIFT 1 |
| 4287 | #define MT6325_RG_VGP2_MODE_CTRL_MASK 0x1 |
| 4288 | #define MT6325_RG_VGP2_MODE_CTRL_SHIFT 2 |
| 4289 | #define MT6325_RG_VGP2_ON_CTRL_MASK 0x1 |
| 4290 | #define MT6325_RG_VGP2_ON_CTRL_SHIFT 3 |
| 4291 | #define MT6325_RG_VGP2_SRCLK_MODE_SEL_MASK 0x3 |
| 4292 | #define MT6325_RG_VGP2_SRCLK_MODE_SEL_SHIFT 4 |
| 4293 | #define MT6325_QI_VGP2_MODE_MASK 0x1 |
| 4294 | #define MT6325_QI_VGP2_MODE_SHIFT 7 |
| 4295 | #define MT6325_RG_VGP2_STBTD_MASK 0x3 |
| 4296 | #define MT6325_RG_VGP2_STBTD_SHIFT 8 |
| 4297 | #define MT6325_RG_VGP2_SRCLK_EN_SEL_MASK 0x3 |
| 4298 | #define MT6325_RG_VGP2_SRCLK_EN_SEL_SHIFT 12 |
| 4299 | #define MT6325_QI_VGP2_STB_MASK 0x1 |
| 4300 | #define MT6325_QI_VGP2_STB_SHIFT 14 |
| 4301 | #define MT6325_QI_VGP2_EN_MASK 0x1 |
| 4302 | #define MT6325_QI_VGP2_EN_SHIFT 15 |
| 4303 | #define MT6325_RG_VCAMD_MODE_SET_MASK 0x1 |
| 4304 | #define MT6325_RG_VCAMD_MODE_SET_SHIFT 0 |
| 4305 | #define MT6325_RG_VCAMD_EN_MASK 0x1 |
| 4306 | #define MT6325_RG_VCAMD_EN_SHIFT 1 |
| 4307 | #define MT6325_RG_VCAMD_MODE_CTRL_MASK 0x1 |
| 4308 | #define MT6325_RG_VCAMD_MODE_CTRL_SHIFT 2 |
| 4309 | #define MT6325_RG_VCAMD_ON_CTRL_MASK 0x1 |
| 4310 | #define MT6325_RG_VCAMD_ON_CTRL_SHIFT 3 |
| 4311 | #define MT6325_RG_VCAMD_SRCLK_MODE_SEL_MASK 0x3 |
| 4312 | #define MT6325_RG_VCAMD_SRCLK_MODE_SEL_SHIFT 4 |
| 4313 | #define MT6325_QI_VCAMD_MODE_MASK 0x1 |
| 4314 | #define MT6325_QI_VCAMD_MODE_SHIFT 7 |
| 4315 | #define MT6325_RG_VCAMD_STBTD_MASK 0x3 |
| 4316 | #define MT6325_RG_VCAMD_STBTD_SHIFT 8 |
| 4317 | #define MT6325_RG_VCAMD_SRCLK_EN_SEL_MASK 0x3 |
| 4318 | #define MT6325_RG_VCAMD_SRCLK_EN_SEL_SHIFT 12 |
| 4319 | #define MT6325_QI_VCAMD_STB_MASK 0x1 |
| 4320 | #define MT6325_QI_VCAMD_STB_SHIFT 14 |
| 4321 | #define MT6325_QI_VCAMD_EN_MASK 0x1 |
| 4322 | #define MT6325_QI_VCAMD_EN_SHIFT 15 |
| 4323 | #define MT6325_RG_VCAM_IO_MODE_SET_MASK 0x1 |
| 4324 | #define MT6325_RG_VCAM_IO_MODE_SET_SHIFT 0 |
| 4325 | #define MT6325_RG_VCAM_IO_EN_MASK 0x1 |
| 4326 | #define MT6325_RG_VCAM_IO_EN_SHIFT 1 |
| 4327 | #define MT6325_RG_VCAM_IO_MODE_CTRL_MASK 0x1 |
| 4328 | #define MT6325_RG_VCAM_IO_MODE_CTRL_SHIFT 2 |
| 4329 | #define MT6325_RG_VCAM_IO_ON_CTRL_MASK 0x1 |
| 4330 | #define MT6325_RG_VCAM_IO_ON_CTRL_SHIFT 3 |
| 4331 | #define MT6325_RG_VCAM_IO_SRCLK_MODE_SEL_MASK 0x3 |
| 4332 | #define MT6325_RG_VCAM_IO_SRCLK_MODE_SEL_SHIFT 4 |
| 4333 | #define MT6325_QI_VCAMIO_MODE_MASK 0x1 |
| 4334 | #define MT6325_QI_VCAMIO_MODE_SHIFT 7 |
| 4335 | #define MT6325_RG_VCAM_IO_STBTD_MASK 0x3 |
| 4336 | #define MT6325_RG_VCAM_IO_STBTD_SHIFT 8 |
| 4337 | #define MT6325_RG_VCAM_IO_SRCLK_EN_SEL_MASK 0x3 |
| 4338 | #define MT6325_RG_VCAM_IO_SRCLK_EN_SEL_SHIFT 12 |
| 4339 | #define MT6325_QI_VCAMIO_STB_MASK 0x1 |
| 4340 | #define MT6325_QI_VCAMIO_STB_SHIFT 14 |
| 4341 | #define MT6325_QI_VCAMIO_EN_MASK 0x1 |
| 4342 | #define MT6325_QI_VCAMIO_EN_SHIFT 15 |
| 4343 | #define MT6325_RG_VSRAM_DVFS1_MODE_SET_MASK 0x1 |
| 4344 | #define MT6325_RG_VSRAM_DVFS1_MODE_SET_SHIFT 0 |
| 4345 | #define MT6325_RG_VSRAM_DVFS1_EN_MASK 0x1 |
| 4346 | #define MT6325_RG_VSRAM_DVFS1_EN_SHIFT 1 |
| 4347 | #define MT6325_RG_VSRAM_DVFS1_MODE_CTRL_MASK 0x1 |
| 4348 | #define MT6325_RG_VSRAM_DVFS1_MODE_CTRL_SHIFT 2 |
| 4349 | #define MT6325_RG_VSRAM_DVFS1_ON_CTRL_MASK 0x1 |
| 4350 | #define MT6325_RG_VSRAM_DVFS1_ON_CTRL_SHIFT 3 |
| 4351 | #define MT6325_RG_VSRAM_DVFS1_SRCLK_MODE_SEL_MASK 0x3 |
| 4352 | #define MT6325_RG_VSRAM_DVFS1_SRCLK_MODE_SEL_SHIFT 4 |
| 4353 | #define MT6325_QI_VSRAM_DVFS1_MODE_MASK 0x1 |
| 4354 | #define MT6325_QI_VSRAM_DVFS1_MODE_SHIFT 7 |
| 4355 | #define MT6325_RG_VSRAM_DVFS1_STBTD_MASK 0x3 |
| 4356 | #define MT6325_RG_VSRAM_DVFS1_STBTD_SHIFT 8 |
| 4357 | #define MT6325_RG_VSRAM_DVFS1_SRCLK_EN_SEL_MASK 0x3 |
| 4358 | #define MT6325_RG_VSRAM_DVFS1_SRCLK_EN_SEL_SHIFT 12 |
| 4359 | #define MT6325_QI_VSRAM_DVFS1_STB_MASK 0x1 |
| 4360 | #define MT6325_QI_VSRAM_DVFS1_STB_SHIFT 14 |
| 4361 | #define MT6325_QI_VSRAM_DVFS1_EN_MASK 0x1 |
| 4362 | #define MT6325_QI_VSRAM_DVFS1_EN_SHIFT 15 |
| 4363 | #define MT6325_RG_VGP3_MODE_SET_MASK 0x1 |
| 4364 | #define MT6325_RG_VGP3_MODE_SET_SHIFT 0 |
| 4365 | #define MT6325_RG_VGP3_EN_MASK 0x1 |
| 4366 | #define MT6325_RG_VGP3_EN_SHIFT 1 |
| 4367 | #define MT6325_RG_VGP3_MODE_CTRL_MASK 0x1 |
| 4368 | #define MT6325_RG_VGP3_MODE_CTRL_SHIFT 2 |
| 4369 | #define MT6325_RG_VGP3_ON_CTRL_MASK 0x1 |
| 4370 | #define MT6325_RG_VGP3_ON_CTRL_SHIFT 3 |
| 4371 | #define MT6325_RG_VGP3_SRCLK_MODE_SEL_MASK 0x3 |
| 4372 | #define MT6325_RG_VGP3_SRCLK_MODE_SEL_SHIFT 4 |
| 4373 | #define MT6325_QI_VGP3_MODE_MASK 0x1 |
| 4374 | #define MT6325_QI_VGP3_MODE_SHIFT 7 |
| 4375 | #define MT6325_RG_VGP3_STBTD_MASK 0x3 |
| 4376 | #define MT6325_RG_VGP3_STBTD_SHIFT 8 |
| 4377 | #define MT6325_RG_VGP3_SRCLK_EN_SEL_MASK 0x3 |
| 4378 | #define MT6325_RG_VGP3_SRCLK_EN_SEL_SHIFT 12 |
| 4379 | #define MT6325_QI_VGP3_STB_MASK 0x1 |
| 4380 | #define MT6325_QI_VGP3_STB_SHIFT 14 |
| 4381 | #define MT6325_QI_VGP3_EN_MASK 0x1 |
| 4382 | #define MT6325_QI_VGP3_EN_SHIFT 15 |
| 4383 | #define MT6325_RG_VBIASN_MODE_SET_MASK 0x1 |
| 4384 | #define MT6325_RG_VBIASN_MODE_SET_SHIFT 0 |
| 4385 | #define MT6325_RG_VBIASN_EN_MASK 0x1 |
| 4386 | #define MT6325_RG_VBIASN_EN_SHIFT 1 |
| 4387 | #define MT6325_RG_VBIASN_MODE_CTRL_MASK 0x1 |
| 4388 | #define MT6325_RG_VBIASN_MODE_CTRL_SHIFT 2 |
| 4389 | #define MT6325_RG_VBIASN_ON_CTRL_MASK 0x1 |
| 4390 | #define MT6325_RG_VBIASN_ON_CTRL_SHIFT 3 |
| 4391 | #define MT6325_RG_VBIASN_SRCLK_MODE_SEL_MASK 0x3 |
| 4392 | #define MT6325_RG_VBIASN_SRCLK_MODE_SEL_SHIFT 4 |
| 4393 | #define MT6325_QI_VBIASN_MODE_MASK 0x1 |
| 4394 | #define MT6325_QI_VBIASN_MODE_SHIFT 7 |
| 4395 | #define MT6325_RG_VBIASN_STBTD_MASK 0x3 |
| 4396 | #define MT6325_RG_VBIASN_STBTD_SHIFT 8 |
| 4397 | #define MT6325_RG_VBIASN_SRCLK_EN_SEL_MASK 0x3 |
| 4398 | #define MT6325_RG_VBIASN_SRCLK_EN_SEL_SHIFT 12 |
| 4399 | #define MT6325_QI_VBIASN_STB_MASK 0x1 |
| 4400 | #define MT6325_QI_VBIASN_STB_SHIFT 14 |
| 4401 | #define MT6325_QI_VBIASN_EN_MASK 0x1 |
| 4402 | #define MT6325_QI_VBIASN_EN_SHIFT 15 |
| 4403 | #define MT6325_RG_VRTC_EN_MASK 0x1 |
| 4404 | #define MT6325_RG_VRTC_EN_SHIFT 1 |
| 4405 | #define MT6325_QI_VRTC_EN_MASK 0x1 |
| 4406 | #define MT6325_QI_VRTC_EN_SHIFT 15 |
| 4407 | #define MT6325_RG_VBIASN_DIS_SEL_MASK 0x3 |
| 4408 | #define MT6325_RG_VBIASN_DIS_SEL_SHIFT 0 |
| 4409 | #define MT6325_RG_VBIASN_TRANS_EN_MASK 0x1 |
| 4410 | #define MT6325_RG_VBIASN_TRANS_EN_SHIFT 2 |
| 4411 | #define MT6325_RG_VBIASN_TRANS_CTRL_MASK 0x3 |
| 4412 | #define MT6325_RG_VBIASN_TRANS_CTRL_SHIFT 4 |
| 4413 | #define MT6325_RG_VBIASN_TRANS_ONCE_MASK 0x1 |
| 4414 | #define MT6325_RG_VBIASN_TRANS_ONCE_SHIFT 6 |
| 4415 | #define MT6325_QI_VBIASN_CHR_MASK 0x1 |
| 4416 | #define MT6325_QI_VBIASN_CHR_SHIFT 7 |
| 4417 | #define MT6325_RG_VTCXO1_NDIS_EN_MASK 0x1 |
| 4418 | #define MT6325_RG_VTCXO1_NDIS_EN_SHIFT 0 |
| 4419 | #define MT6325_RG_VTCXO1_CAL_MASK 0xF |
| 4420 | #define MT6325_RG_VTCXO1_CAL_SHIFT 4 |
| 4421 | #define MT6325_RG_VTCXO0_NDIS_EN_MASK 0x1 |
| 4422 | #define MT6325_RG_VTCXO0_NDIS_EN_SHIFT 8 |
| 4423 | #define MT6325_RG_VTCXO0_CAL_MASK 0xF |
| 4424 | #define MT6325_RG_VTCXO0_CAL_SHIFT 12 |
| 4425 | #define MT6325_RG_VBIF28_NDIS_EN_MASK 0x1 |
| 4426 | #define MT6325_RG_VBIF28_NDIS_EN_SHIFT 0 |
| 4427 | #define MT6325_RG_VBIF28_CAL_MASK 0xF |
| 4428 | #define MT6325_RG_VBIF28_CAL_SHIFT 4 |
| 4429 | #define MT6325_RG_VAUD28_NDIS_EN_MASK 0x1 |
| 4430 | #define MT6325_RG_VAUD28_NDIS_EN_SHIFT 8 |
| 4431 | #define MT6325_RG_VAUD28_SENSE_SEL_MASK 0x1 |
| 4432 | #define MT6325_RG_VAUD28_SENSE_SEL_SHIFT 9 |
| 4433 | #define MT6325_RG_VAUD28_CAL_MASK 0xF |
| 4434 | #define MT6325_RG_VAUD28_CAL_SHIFT 12 |
| 4435 | #define MT6325_RG_VCAMA_NDIS_EN_MASK 0x1 |
| 4436 | #define MT6325_RG_VCAMA_NDIS_EN_SHIFT 0 |
| 4437 | #define MT6325_RG_VCAMA_VOSEL_MASK 0x3 |
| 4438 | #define MT6325_RG_VCAMA_VOSEL_SHIFT 1 |
| 4439 | #define MT6325_RG_VCAMA_CAL_MASK 0xF |
| 4440 | #define MT6325_RG_VCAMA_CAL_SHIFT 4 |
| 4441 | #define MT6325_RG_VAUXA28_NDIS_EN_MASK 0x1 |
| 4442 | #define MT6325_RG_VAUXA28_NDIS_EN_SHIFT 8 |
| 4443 | #define MT6325_RG_VAUXA28_SENSE_SEL_MASK 0x1 |
| 4444 | #define MT6325_RG_VAUXA28_SENSE_SEL_SHIFT 9 |
| 4445 | #define MT6325_RG_VAUXA28_CAL_MASK 0xF |
| 4446 | #define MT6325_RG_VAUXA28_CAL_SHIFT 12 |
| 4447 | #define MT6325_RG_VCN33_NDIS_EN_MASK 0x1 |
| 4448 | #define MT6325_RG_VCN33_NDIS_EN_SHIFT 0 |
| 4449 | #define MT6325_RG_VCN33_VOSEL_MASK 0x3 |
| 4450 | #define MT6325_RG_VCN33_VOSEL_SHIFT 1 |
| 4451 | #define MT6325_RG_VCN33_CAL_MASK 0xF |
| 4452 | #define MT6325_RG_VCN33_CAL_SHIFT 4 |
| 4453 | #define MT6325_RG_VCN28_NDIS_EN_MASK 0x1 |
| 4454 | #define MT6325_RG_VCN28_NDIS_EN_SHIFT 8 |
| 4455 | #define MT6325_RG_VCN28_CAL_MASK 0xF |
| 4456 | #define MT6325_RG_VCN28_CAL_SHIFT 12 |
| 4457 | #define MT6325_RG_VUSB33_NDIS_EN_MASK 0x1 |
| 4458 | #define MT6325_RG_VUSB33_NDIS_EN_SHIFT 0 |
| 4459 | #define MT6325_RG_VUSB33_CAL_MASK 0xF |
| 4460 | #define MT6325_RG_VUSB33_CAL_SHIFT 4 |
| 4461 | #define MT6325_RG_VRF18_1_NDIS_EN_MASK 0x1 |
| 4462 | #define MT6325_RG_VRF18_1_NDIS_EN_SHIFT 8 |
| 4463 | #define MT6325_RG_VRF18_1_VOSEL_MASK 0x3 |
| 4464 | #define MT6325_RG_VRF18_1_VOSEL_SHIFT 9 |
| 4465 | #define MT6325_RG_VRF18_1_CAL_MASK 0xF |
| 4466 | #define MT6325_RG_VRF18_1_CAL_SHIFT 12 |
| 4467 | #define MT6325_RG_VMC_NDIS_EN_MASK 0x1 |
| 4468 | #define MT6325_RG_VMC_NDIS_EN_SHIFT 0 |
| 4469 | #define MT6325_RG_VMC_VOSEL_MASK 0x1 |
| 4470 | #define MT6325_RG_VMC_VOSEL_SHIFT 1 |
| 4471 | #define MT6325_RG_VMC_STB_CAL_MASK 0x1 |
| 4472 | #define MT6325_RG_VMC_STB_CAL_SHIFT 2 |
| 4473 | #define MT6325_RG_VMC_CAL_MASK 0xF |
| 4474 | #define MT6325_RG_VMC_CAL_SHIFT 4 |
| 4475 | #define MT6325_RG_VMCH_NDIS_EN_MASK 0x1 |
| 4476 | #define MT6325_RG_VMCH_NDIS_EN_SHIFT 8 |
| 4477 | #define MT6325_RG_VMCH_VOSEL_MASK 0x1 |
| 4478 | #define MT6325_RG_VMCH_VOSEL_SHIFT 9 |
| 4479 | #define MT6325_RG_VMCH_DB_EN_MASK 0x1 |
| 4480 | #define MT6325_RG_VMCH_DB_EN_SHIFT 10 |
| 4481 | #define MT6325_RG_VMCH_STB_SEL_MASK 0x1 |
| 4482 | #define MT6325_RG_VMCH_STB_SEL_SHIFT 11 |
| 4483 | #define MT6325_RG_VMCH_CAL_MASK 0xF |
| 4484 | #define MT6325_RG_VMCH_CAL_SHIFT 12 |
| 4485 | #define MT6325_RG_VEMC_3V3_STB_CAL_MASK 0x3 |
| 4486 | #define MT6325_RG_VEMC_3V3_STB_CAL_SHIFT 4 |
| 4487 | #define MT6325_RG_VEMC_3V3_NDIS_EN_MASK 0x1 |
| 4488 | #define MT6325_RG_VEMC_3V3_NDIS_EN_SHIFT 8 |
| 4489 | #define MT6325_RG_VEMC_3V3_VOSEL_MASK 0x1 |
| 4490 | #define MT6325_RG_VEMC_3V3_VOSEL_SHIFT 9 |
| 4491 | #define MT6325_RG_VEMC_3V3_DL_EN_MASK 0x1 |
| 4492 | #define MT6325_RG_VEMC_3V3_DL_EN_SHIFT 10 |
| 4493 | #define MT6325_RG_VEMC_3V3_CAL_MASK 0xF |
| 4494 | #define MT6325_RG_VEMC_3V3_CAL_SHIFT 12 |
| 4495 | #define MT6325_RG_VCAMAF_NDIS_EN_MASK 0x1 |
| 4496 | #define MT6325_RG_VCAMAF_NDIS_EN_SHIFT 0 |
| 4497 | #define MT6325_RG_VCAMAF_VOSEL_MASK 0x7 |
| 4498 | #define MT6325_RG_VCAMAF_VOSEL_SHIFT 1 |
| 4499 | #define MT6325_RG_VCAMAF_CAL_MASK 0xF |
| 4500 | #define MT6325_RG_VCAMAF_CAL_SHIFT 4 |
| 4501 | #define MT6325_RG_VIO28_NDIS_EN_MASK 0x1 |
| 4502 | #define MT6325_RG_VIO28_NDIS_EN_SHIFT 8 |
| 4503 | #define MT6325_RG_VIO28_CAL_MASK 0xF |
| 4504 | #define MT6325_RG_VIO28_CAL_SHIFT 12 |
| 4505 | #define MT6325_RG_VGP2_NDIS_EN_MASK 0x1 |
| 4506 | #define MT6325_RG_VGP2_NDIS_EN_SHIFT 0 |
| 4507 | #define MT6325_RG_VGP2_VOSEL_MASK 0x3 |
| 4508 | #define MT6325_RG_VGP2_VOSEL_SHIFT 1 |
| 4509 | #define MT6325_RG_VGP2_CAL_MASK 0xF |
| 4510 | #define MT6325_RG_VGP2_CAL_SHIFT 4 |
| 4511 | #define MT6325_RG_VGP1_NDIS_EN_MASK 0x1 |
| 4512 | #define MT6325_RG_VGP1_NDIS_EN_SHIFT 8 |
| 4513 | #define MT6325_RG_VGP1_VOSEL_MASK 0x7 |
| 4514 | #define MT6325_RG_VGP1_VOSEL_SHIFT 9 |
| 4515 | #define MT6325_RG_VGP1_CAL_MASK 0xF |
| 4516 | #define MT6325_RG_VGP1_CAL_SHIFT 12 |
| 4517 | #define MT6325_RG_VSIM2_NDIS_EN_MASK 0x1 |
| 4518 | #define MT6325_RG_VSIM2_NDIS_EN_SHIFT 0 |
| 4519 | #define MT6325_RG_VSIM2_VOSEL_MASK 0x7 |
| 4520 | #define MT6325_RG_VSIM2_VOSEL_SHIFT 1 |
| 4521 | #define MT6325_RG_VSIM2_CAL_MASK 0xF |
| 4522 | #define MT6325_RG_VSIM2_CAL_SHIFT 4 |
| 4523 | #define MT6325_RG_VSIM1_NDIS_EN_MASK 0x1 |
| 4524 | #define MT6325_RG_VSIM1_NDIS_EN_SHIFT 8 |
| 4525 | #define MT6325_RG_VSIM1_VOSEL_MASK 0x7 |
| 4526 | #define MT6325_RG_VSIM1_VOSEL_SHIFT 9 |
| 4527 | #define MT6325_RG_VSIM1_CAL_MASK 0xF |
| 4528 | #define MT6325_RG_VSIM1_CAL_SHIFT 12 |
| 4529 | #define MT6325_RG_VIBR_VOSEL_MASK 0x7 |
| 4530 | #define MT6325_RG_VIBR_VOSEL_SHIFT 1 |
| 4531 | #define MT6325_RG_VIBR_VOCAL_MASK 0xF |
| 4532 | #define MT6325_RG_VIBR_VOCAL_SHIFT 4 |
| 4533 | #define MT6325_RG_VMIPI_NDIS_EN_MASK 0x1 |
| 4534 | #define MT6325_RG_VMIPI_NDIS_EN_SHIFT 8 |
| 4535 | #define MT6325_RG_VMIPI_VOSEL_MASK 0x3 |
| 4536 | #define MT6325_RG_VMIPI_VOSEL_SHIFT 9 |
| 4537 | #define MT6325_RG_VMIPI_CAL_MASK 0xF |
| 4538 | #define MT6325_RG_VMIPI_CAL_SHIFT 12 |
| 4539 | #define MT6325_RG_VEFUSE_NDIS_EN_MASK 0x1 |
| 4540 | #define MT6325_RG_VEFUSE_NDIS_EN_SHIFT 0 |
| 4541 | #define MT6325_RG_VEFUSE_VOSEL_MASK 0x7 |
| 4542 | #define MT6325_RG_VEFUSE_VOSEL_SHIFT 1 |
| 4543 | #define MT6325_RG_VEFUSE_CAL_MASK 0xF |
| 4544 | #define MT6325_RG_VEFUSE_CAL_SHIFT 4 |
| 4545 | #define MT6325_RG_VCN18_NDIS_EN_MASK 0x1 |
| 4546 | #define MT6325_RG_VCN18_NDIS_EN_SHIFT 8 |
| 4547 | #define MT6325_RG_VCN18_VOSEL_MASK 0x7 |
| 4548 | #define MT6325_RG_VCN18_VOSEL_SHIFT 9 |
| 4549 | #define MT6325_RG_VCN18_CAL_MASK 0xF |
| 4550 | #define MT6325_RG_VCN18_CAL_SHIFT 12 |
| 4551 | #define MT6325_RG_VCAMD_NDIS_EN_MASK 0x1 |
| 4552 | #define MT6325_RG_VCAMD_NDIS_EN_SHIFT 0 |
| 4553 | #define MT6325_RG_VCAMD_VOSEL_MASK 0x7 |
| 4554 | #define MT6325_RG_VCAMD_VOSEL_SHIFT 1 |
| 4555 | #define MT6325_RG_VCAMD_CAL_MASK 0xF |
| 4556 | #define MT6325_RG_VCAMD_CAL_SHIFT 4 |
| 4557 | #define MT6325_RG_VCAMIO_NDIS_EN_MASK 0x1 |
| 4558 | #define MT6325_RG_VCAMIO_NDIS_EN_SHIFT 8 |
| 4559 | #define MT6325_RG_VCAMIO_VOSEL_MASK 0x7 |
| 4560 | #define MT6325_RG_VCAMIO_VOSEL_SHIFT 9 |
| 4561 | #define MT6325_RG_VCAMIO_CAL_MASK 0xF |
| 4562 | #define MT6325_RG_VCAMIO_CAL_SHIFT 12 |
| 4563 | #define MT6325_RG_VSRAM_DVFS1_NDIS_EN_MASK 0x1 |
| 4564 | #define MT6325_RG_VSRAM_DVFS1_NDIS_EN_SHIFT 0 |
| 4565 | #define MT6325_RG_VSRAM_DVFS1_NDIS_PLCUR_MASK 0x3 |
| 4566 | #define MT6325_RG_VSRAM_DVFS1_NDIS_PLCUR_SHIFT 4 |
| 4567 | #define MT6325_RG_VSRAM_DVFS1_VOSEL_MASK 0x7F |
| 4568 | #define MT6325_RG_VSRAM_DVFS1_VOSEL_SHIFT 9 |
| 4569 | #define MT6325_RG_VBIASN_NDIS_EN_MASK 0x1 |
| 4570 | #define MT6325_RG_VBIASN_NDIS_EN_SHIFT 0 |
| 4571 | #define MT6325_RG_VBIASN_CAL_MASK 0xF |
| 4572 | #define MT6325_RG_VBIASN_CAL_SHIFT 4 |
| 4573 | #define MT6325_RG_VGP3_NDIS_EN_MASK 0x1 |
| 4574 | #define MT6325_RG_VGP3_NDIS_EN_SHIFT 8 |
| 4575 | #define MT6325_RG_VGP3_VOSEL_MASK 0x7 |
| 4576 | #define MT6325_RG_VGP3_VOSEL_SHIFT 9 |
| 4577 | #define MT6325_RG_VGP3_CAL_MASK 0xF |
| 4578 | #define MT6325_RG_VGP3_CAL_SHIFT 12 |
| 4579 | #define MT6325_RG_VBIASN_VOSEL_MASK 0x1F |
| 4580 | #define MT6325_RG_VBIASN_VOSEL_SHIFT 11 |
| 4581 | #define MT6325_RG_DLDO_1_RSV_L_MASK 0x1F |
| 4582 | #define MT6325_RG_DLDO_1_RSV_L_SHIFT 0 |
| 4583 | #define MT6325_RG_LDO_RSV0_MASK 0x3F |
| 4584 | #define MT6325_RG_LDO_RSV0_SHIFT 5 |
| 4585 | #define MT6325_RG_DLDO_1_RSV_H_MASK 0x1F |
| 4586 | #define MT6325_RG_DLDO_1_RSV_H_SHIFT 11 |
| 4587 | #define MT6325_RG_DLDO_2_RSV_L_MASK 0x1F |
| 4588 | #define MT6325_RG_DLDO_2_RSV_L_SHIFT 0 |
| 4589 | #define MT6325_RG_LDO_RSV1_MASK 0x3F |
| 4590 | #define MT6325_RG_LDO_RSV1_SHIFT 5 |
| 4591 | #define MT6325_RG_DLDO_2_RSV_H_MASK 0x1F |
| 4592 | #define MT6325_RG_DLDO_2_RSV_H_SHIFT 11 |
| 4593 | #define MT6325_RG_LDO_RSV3_MASK 0xFF |
| 4594 | #define MT6325_RG_LDO_RSV3_SHIFT 0 |
| 4595 | #define MT6325_RG_SYSLDO_RSVL_MASK 0x7 |
| 4596 | #define MT6325_RG_SYSLDO_RSVL_SHIFT 8 |
| 4597 | #define MT6325_RG_SYSLDO_RSV_H_MASK 0x7 |
| 4598 | #define MT6325_RG_SYSLDO_RSV_H_SHIFT 12 |
| 4599 | #define MT6325_RG_ADLDO_RSV_L_MASK 0x1F |
| 4600 | #define MT6325_RG_ADLDO_RSV_L_SHIFT 0 |
| 4601 | #define MT6325_RG_LDO_RSV2_MASK 0x3F |
| 4602 | #define MT6325_RG_LDO_RSV2_SHIFT 5 |
| 4603 | #define MT6325_RG_ADLDO_RSV_H_MASK 0x1F |
| 4604 | #define MT6325_RG_ADLDO_RSV_H_SHIFT 11 |
| 4605 | #define MT6325_RG_VMC_OCFB_EN_MASK 0x1 |
| 4606 | #define MT6325_RG_VMC_OCFB_EN_SHIFT 0 |
| 4607 | #define MT6325_RG_VIO28_OCFB_EN_MASK 0x1 |
| 4608 | #define MT6325_RG_VIO28_OCFB_EN_SHIFT 1 |
| 4609 | #define MT6325_RG_VEMC33_OCFB_EN_MASK 0x1 |
| 4610 | #define MT6325_RG_VEMC33_OCFB_EN_SHIFT 2 |
| 4611 | #define MT6325_RG_VMCH_OCFB_EN_MASK 0x1 |
| 4612 | #define MT6325_RG_VMCH_OCFB_EN_SHIFT 3 |
| 4613 | #define MT6325_RG_VUSB33_OCFB_EN_MASK 0x1 |
| 4614 | #define MT6325_RG_VUSB33_OCFB_EN_SHIFT 4 |
| 4615 | #define MT6325_RG_VRF18_1_OCFB_EN_MASK 0x1 |
| 4616 | #define MT6325_RG_VRF18_1_OCFB_EN_SHIFT 5 |
| 4617 | #define MT6325_RG_VCN33_OCFB_EN_MASK 0x1 |
| 4618 | #define MT6325_RG_VCN33_OCFB_EN_SHIFT 6 |
| 4619 | #define MT6325_RG_VCN28_OCFB_EN_MASK 0x1 |
| 4620 | #define MT6325_RG_VCN28_OCFB_EN_SHIFT 7 |
| 4621 | #define MT6325_RG_VCAMA_OCFB_EN_MASK 0x1 |
| 4622 | #define MT6325_RG_VCAMA_OCFB_EN_SHIFT 8 |
| 4623 | #define MT6325_RG_VAUXA28_OCFB_EN_MASK 0x1 |
| 4624 | #define MT6325_RG_VAUXA28_OCFB_EN_SHIFT 9 |
| 4625 | #define MT6325_RG_VBIF28_OCFB_EN_MASK 0x1 |
| 4626 | #define MT6325_RG_VBIF28_OCFB_EN_SHIFT 10 |
| 4627 | #define MT6325_RG_VAUD28_OCFB_EN_MASK 0x1 |
| 4628 | #define MT6325_RG_VAUD28_OCFB_EN_SHIFT 11 |
| 4629 | #define MT6325_RG_VTCXO1_OCFB_EN_MASK 0x1 |
| 4630 | #define MT6325_RG_VTCXO1_OCFB_EN_SHIFT 12 |
| 4631 | #define MT6325_RG_VTCXO0_OCFB_EN_MASK 0x1 |
| 4632 | #define MT6325_RG_VTCXO0_OCFB_EN_SHIFT 13 |
| 4633 | #define MT6325_LDO_DEGTD_SEL_MASK 0x3 |
| 4634 | #define MT6325_LDO_DEGTD_SEL_SHIFT 14 |
| 4635 | #define MT6325_RG_VBIASN_OCFB_EN_MASK 0x1 |
| 4636 | #define MT6325_RG_VBIASN_OCFB_EN_SHIFT 1 |
| 4637 | #define MT6325_RG_VGP3_OCFB_EN_MASK 0x1 |
| 4638 | #define MT6325_RG_VGP3_OCFB_EN_SHIFT 2 |
| 4639 | #define MT6325_RG_VSRAM_DVFS1_OCFB_EN_MASK 0x1 |
| 4640 | #define MT6325_RG_VSRAM_DVFS1_OCFB_EN_SHIFT 3 |
| 4641 | #define MT6325_RG_VCAM_IO_OCFB_EN_MASK 0x1 |
| 4642 | #define MT6325_RG_VCAM_IO_OCFB_EN_SHIFT 4 |
| 4643 | #define MT6325_RG_VCAMD_OCFB_EN_MASK 0x1 |
| 4644 | #define MT6325_RG_VCAMD_OCFB_EN_SHIFT 5 |
| 4645 | #define MT6325_RG_VGP2_OCFB_EN_MASK 0x1 |
| 4646 | #define MT6325_RG_VGP2_OCFB_EN_SHIFT 6 |
| 4647 | #define MT6325_RG_VCN18_OCFB_EN_MASK 0x1 |
| 4648 | #define MT6325_RG_VCN18_OCFB_EN_SHIFT 7 |
| 4649 | #define MT6325_RG_VMIPI_OCFB_EN_MASK 0x1 |
| 4650 | #define MT6325_RG_VMIPI_OCFB_EN_SHIFT 8 |
| 4651 | #define MT6325_RG_VSIM2_OCFB_EN_MASK 0x1 |
| 4652 | #define MT6325_RG_VSIM2_OCFB_EN_SHIFT 9 |
| 4653 | #define MT6325_RG_VSIM1_OCFB_EN_MASK 0x1 |
| 4654 | #define MT6325_RG_VSIM1_OCFB_EN_SHIFT 10 |
| 4655 | #define MT6325_RG_VEFUSE_OCFB_EN_MASK 0x1 |
| 4656 | #define MT6325_RG_VEFUSE_OCFB_EN_SHIFT 11 |
| 4657 | #define MT6325_RG_VGP1_OCFB_EN_MASK 0x1 |
| 4658 | #define MT6325_RG_VGP1_OCFB_EN_SHIFT 12 |
| 4659 | #define MT6325_RG_VCAM_AF_OCFB_EN_MASK 0x1 |
| 4660 | #define MT6325_RG_VCAM_AF_OCFB_EN_SHIFT 13 |
| 4661 | #define MT6325_QI_VMC_OCFB_EN_MASK 0x1 |
| 4662 | #define MT6325_QI_VMC_OCFB_EN_SHIFT 0 |
| 4663 | #define MT6325_QI_VIO28_OCFB_EN_MASK 0x1 |
| 4664 | #define MT6325_QI_VIO28_OCFB_EN_SHIFT 1 |
| 4665 | #define MT6325_QI_VEMC_3V3_OCFB_EN_MASK 0x1 |
| 4666 | #define MT6325_QI_VEMC_3V3_OCFB_EN_SHIFT 2 |
| 4667 | #define MT6325_QI_VMCH_OCFB_EN_MASK 0x1 |
| 4668 | #define MT6325_QI_VMCH_OCFB_EN_SHIFT 3 |
| 4669 | #define MT6325_QI_VUSB33_OCFB_EN_MASK 0x1 |
| 4670 | #define MT6325_QI_VUSB33_OCFB_EN_SHIFT 4 |
| 4671 | #define MT6325_QI_VRF18_1_OCFB_EN_MASK 0x1 |
| 4672 | #define MT6325_QI_VRF18_1_OCFB_EN_SHIFT 5 |
| 4673 | #define MT6325_QI_VCN33_OCFB_EN_MASK 0x1 |
| 4674 | #define MT6325_QI_VCN33_OCFB_EN_SHIFT 6 |
| 4675 | #define MT6325_QI_VCN28_OCFB_EN_MASK 0x1 |
| 4676 | #define MT6325_QI_VCN28_OCFB_EN_SHIFT 7 |
| 4677 | #define MT6325_QI_VCAMA_OCFB_EN_MASK 0x1 |
| 4678 | #define MT6325_QI_VCAMA_OCFB_EN_SHIFT 8 |
| 4679 | #define MT6325_QI_VAUXA28_OCFB_EN_MASK 0x1 |
| 4680 | #define MT6325_QI_VAUXA28_OCFB_EN_SHIFT 9 |
| 4681 | #define MT6325_QI_VBIF28_OCFB_EN_MASK 0x1 |
| 4682 | #define MT6325_QI_VBIF28_OCFB_EN_SHIFT 10 |
| 4683 | #define MT6325_QI_VAUD28_OCFB_EN_MASK 0x1 |
| 4684 | #define MT6325_QI_VAUD28_OCFB_EN_SHIFT 11 |
| 4685 | #define MT6325_QI_VTCXO1_OCFB_EN_MASK 0x1 |
| 4686 | #define MT6325_QI_VTCXO1_OCFB_EN_SHIFT 12 |
| 4687 | #define MT6325_QI_VTCXO0_OCFB_EN_MASK 0x1 |
| 4688 | #define MT6325_QI_VTCXO0_OCFB_EN_SHIFT 13 |
| 4689 | #define MT6325_QI_VBIASN_OCFB_EN_MASK 0x1 |
| 4690 | #define MT6325_QI_VBIASN_OCFB_EN_SHIFT 1 |
| 4691 | #define MT6325_QI_VGP3_OCFB_EN_MASK 0x1 |
| 4692 | #define MT6325_QI_VGP3_OCFB_EN_SHIFT 2 |
| 4693 | #define MT6325_QI_VSRAM_DVFS1_OCFB_EN_MASK 0x1 |
| 4694 | #define MT6325_QI_VSRAM_DVFS1_OCFB_EN_SHIFT 3 |
| 4695 | #define MT6325_QI_VCAMIO_OCFB_EN_MASK 0x1 |
| 4696 | #define MT6325_QI_VCAMIO_OCFB_EN_SHIFT 4 |
| 4697 | #define MT6325_QI_VCAMD_OCFB_EN_MASK 0x1 |
| 4698 | #define MT6325_QI_VCAMD_OCFB_EN_SHIFT 5 |
| 4699 | #define MT6325_QI_VGP2_OCFB_EN_MASK 0x1 |
| 4700 | #define MT6325_QI_VGP2_OCFB_EN_SHIFT 6 |
| 4701 | #define MT6325_QI_VCN18_OCFB_EN_MASK 0x1 |
| 4702 | #define MT6325_QI_VCN18_OCFB_EN_SHIFT 7 |
| 4703 | #define MT6325_QI_VMIPI_OCFB_EN_MASK 0x1 |
| 4704 | #define MT6325_QI_VMIPI_OCFB_EN_SHIFT 8 |
| 4705 | #define MT6325_QI_VSIM2_OCFB_EN_MASK 0x1 |
| 4706 | #define MT6325_QI_VSIM2_OCFB_EN_SHIFT 9 |
| 4707 | #define MT6325_QI_VSIM1_OCFB_EN_MASK 0x1 |
| 4708 | #define MT6325_QI_VSIM1_OCFB_EN_SHIFT 10 |
| 4709 | #define MT6325_QI_VEFUSE_OCFB_EN_MASK 0x1 |
| 4710 | #define MT6325_QI_VEFUSE_OCFB_EN_SHIFT 11 |
| 4711 | #define MT6325_QI_VGP1_OCFB_EN_MASK 0x1 |
| 4712 | #define MT6325_QI_VGP1_OCFB_EN_SHIFT 12 |
| 4713 | #define MT6325_QI_VCAMAF_OCFB_EN_MASK 0x1 |
| 4714 | #define MT6325_QI_VCAMAF_OCFB_EN_SHIFT 13 |
| 4715 | #define MT6325_RG_VCAMIO_EN_MASK 0x1 |
| 4716 | #define MT6325_RG_VCAMIO_EN_SHIFT 0 |
| 4717 | #define MT6325_RG_VCAMAF_EN_MASK 0x1 |
| 4718 | #define MT6325_RG_VCAMAF_EN_SHIFT 1 |
| 4719 | #define MT6325_BIF_COMMAND_0_MASK 0x7FF |
| 4720 | #define MT6325_BIF_COMMAND_0_SHIFT 0 |
| 4721 | #define MT6325_BIF_COMMAND_1_MASK 0x7FF |
| 4722 | #define MT6325_BIF_COMMAND_1_SHIFT 0 |
| 4723 | #define MT6325_BIF_COMMAND_2_MASK 0x7FF |
| 4724 | #define MT6325_BIF_COMMAND_2_SHIFT 0 |
| 4725 | #define MT6325_BIF_COMMAND_3_MASK 0x7FF |
| 4726 | #define MT6325_BIF_COMMAND_3_SHIFT 0 |
| 4727 | #define MT6325_BIF_COMMAND_4_MASK 0x7FF |
| 4728 | #define MT6325_BIF_COMMAND_4_SHIFT 0 |
| 4729 | #define MT6325_BIF_COMMAND_5_MASK 0x7FF |
| 4730 | #define MT6325_BIF_COMMAND_5_SHIFT 0 |
| 4731 | #define MT6325_BIF_COMMAND_6_MASK 0x7FF |
| 4732 | #define MT6325_BIF_COMMAND_6_SHIFT 0 |
| 4733 | #define MT6325_BIF_COMMAND_7_MASK 0x7FF |
| 4734 | #define MT6325_BIF_COMMAND_7_SHIFT 0 |
| 4735 | #define MT6325_BIF_COMMAND_8_MASK 0x7FF |
| 4736 | #define MT6325_BIF_COMMAND_8_SHIFT 0 |
| 4737 | #define MT6325_BIF_COMMAND_9_MASK 0x7FF |
| 4738 | #define MT6325_BIF_COMMAND_9_SHIFT 0 |
| 4739 | #define MT6325_BIF_COMMAND_10_MASK 0x7FF |
| 4740 | #define MT6325_BIF_COMMAND_10_SHIFT 0 |
| 4741 | #define MT6325_BIF_COMMAND_11_MASK 0x7FF |
| 4742 | #define MT6325_BIF_COMMAND_11_SHIFT 0 |
| 4743 | #define MT6325_BIF_COMMAND_12_MASK 0x7FF |
| 4744 | #define MT6325_BIF_COMMAND_12_SHIFT 0 |
| 4745 | #define MT6325_BIF_COMMAND_13_MASK 0x7FF |
| 4746 | #define MT6325_BIF_COMMAND_13_SHIFT 0 |
| 4747 | #define MT6325_BIF_COMMAND_14_MASK 0x7FF |
| 4748 | #define MT6325_BIF_COMMAND_14_SHIFT 0 |
| 4749 | #define MT6325_BIF_RSV_MASK 0x7F |
| 4750 | #define MT6325_BIF_RSV_SHIFT 0 |
| 4751 | #define MT6325_BIF_COMMAND_TYPE_MASK 0x3 |
| 4752 | #define MT6325_BIF_COMMAND_TYPE_SHIFT 8 |
| 4753 | #define MT6325_BIF_TRASFER_NUM_MASK 0xF |
| 4754 | #define MT6325_BIF_TRASFER_NUM_SHIFT 12 |
| 4755 | #define MT6325_BIF_LOGIC_0_SET_MASK 0xF |
| 4756 | #define MT6325_BIF_LOGIC_0_SET_SHIFT 0 |
| 4757 | #define MT6325_BIF_LOGIC_1_SET_MASK 0x1F |
| 4758 | #define MT6325_BIF_LOGIC_1_SET_SHIFT 4 |
| 4759 | #define MT6325_BIF_STOP_SET_MASK 0x3F |
| 4760 | #define MT6325_BIF_STOP_SET_SHIFT 10 |
| 4761 | #define MT6325_BIF_DEBOUNCE_WND_MASK 0x3 |
| 4762 | #define MT6325_BIF_DEBOUNCE_WND_SHIFT 0 |
| 4763 | #define MT6325_BIF_DEBOUNCE_THD_MASK 0x3 |
| 4764 | #define MT6325_BIF_DEBOUNCE_THD_SHIFT 2 |
| 4765 | #define MT6325_BIF_DEBOUNCE_EN_MASK 0x1 |
| 4766 | #define MT6325_BIF_DEBOUNCE_EN_SHIFT 4 |
| 4767 | #define MT6325_BIF_READ_EXPECT_NUM_MASK 0xF |
| 4768 | #define MT6325_BIF_READ_EXPECT_NUM_SHIFT 12 |
| 4769 | #define MT6325_BIF_TRASACT_TRIGGER_MASK 0x1 |
| 4770 | #define MT6325_BIF_TRASACT_TRIGGER_SHIFT 0 |
| 4771 | #define MT6325_BIF_DATA_NUM_MASK 0xF |
| 4772 | #define MT6325_BIF_DATA_NUM_SHIFT 0 |
| 4773 | #define MT6325_BIF_RESPONSE_MASK 0x1 |
| 4774 | #define MT6325_BIF_RESPONSE_SHIFT 12 |
| 4775 | #define MT6325_BIF_DATA_0_MASK 0xFF |
| 4776 | #define MT6325_BIF_DATA_0_SHIFT 0 |
| 4777 | #define MT6325_BIF_ACK_0_MASK 0x1 |
| 4778 | #define MT6325_BIF_ACK_0_SHIFT 8 |
| 4779 | #define MT6325_BIF_ERROR_0_MASK 0x1 |
| 4780 | #define MT6325_BIF_ERROR_0_SHIFT 15 |
| 4781 | #define MT6325_BIF_DATA_1_MASK 0xFF |
| 4782 | #define MT6325_BIF_DATA_1_SHIFT 0 |
| 4783 | #define MT6325_BIF_ACK_1_MASK 0x1 |
| 4784 | #define MT6325_BIF_ACK_1_SHIFT 8 |
| 4785 | #define MT6325_BIF_ERROR_1_MASK 0x1 |
| 4786 | #define MT6325_BIF_ERROR_1_SHIFT 15 |
| 4787 | #define MT6325_BIF_DATA_2_MASK 0xFF |
| 4788 | #define MT6325_BIF_DATA_2_SHIFT 0 |
| 4789 | #define MT6325_BIF_ACK_2_MASK 0x1 |
| 4790 | #define MT6325_BIF_ACK_2_SHIFT 8 |
| 4791 | #define MT6325_BIF_ERROR_2_MASK 0x1 |
| 4792 | #define MT6325_BIF_ERROR_2_SHIFT 15 |
| 4793 | #define MT6325_BIF_DATA_3_MASK 0xFF |
| 4794 | #define MT6325_BIF_DATA_3_SHIFT 0 |
| 4795 | #define MT6325_BIF_ACK_3_MASK 0x1 |
| 4796 | #define MT6325_BIF_ACK_3_SHIFT 8 |
| 4797 | #define MT6325_BIF_ERROR_3_MASK 0x1 |
| 4798 | #define MT6325_BIF_ERROR_3_SHIFT 15 |
| 4799 | #define MT6325_BIF_DATA_4_MASK 0xFF |
| 4800 | #define MT6325_BIF_DATA_4_SHIFT 0 |
| 4801 | #define MT6325_BIF_ACK_4_MASK 0x1 |
| 4802 | #define MT6325_BIF_ACK_4_SHIFT 8 |
| 4803 | #define MT6325_BIF_ERROR_4_MASK 0x1 |
| 4804 | #define MT6325_BIF_ERROR_4_SHIFT 15 |
| 4805 | #define MT6325_BIF_DATA_5_MASK 0xFF |
| 4806 | #define MT6325_BIF_DATA_5_SHIFT 0 |
| 4807 | #define MT6325_BIF_ACK_5_MASK 0x1 |
| 4808 | #define MT6325_BIF_ACK_5_SHIFT 8 |
| 4809 | #define MT6325_BIF_ERROR_5_MASK 0x1 |
| 4810 | #define MT6325_BIF_ERROR_5_SHIFT 15 |
| 4811 | #define MT6325_BIF_DATA_6_MASK 0xFF |
| 4812 | #define MT6325_BIF_DATA_6_SHIFT 0 |
| 4813 | #define MT6325_BIF_ACK_6_MASK 0x1 |
| 4814 | #define MT6325_BIF_ACK_6_SHIFT 8 |
| 4815 | #define MT6325_BIF_ERROR_6_MASK 0x1 |
| 4816 | #define MT6325_BIF_ERROR_6_SHIFT 15 |
| 4817 | #define MT6325_BIF_DATA_7_MASK 0xFF |
| 4818 | #define MT6325_BIF_DATA_7_SHIFT 0 |
| 4819 | #define MT6325_BIF_ACK_7_MASK 0x1 |
| 4820 | #define MT6325_BIF_ACK_7_SHIFT 8 |
| 4821 | #define MT6325_BIF_ERROR_7_MASK 0x1 |
| 4822 | #define MT6325_BIF_ERROR_7_SHIFT 15 |
| 4823 | #define MT6325_BIF_DATA_8_MASK 0xFF |
| 4824 | #define MT6325_BIF_DATA_8_SHIFT 0 |
| 4825 | #define MT6325_BIF_ACK_8_MASK 0x1 |
| 4826 | #define MT6325_BIF_ACK_8_SHIFT 8 |
| 4827 | #define MT6325_BIF_ERROR_8_MASK 0x1 |
| 4828 | #define MT6325_BIF_ERROR_8_SHIFT 15 |
| 4829 | #define MT6325_BIF_DATA_9_MASK 0xFF |
| 4830 | #define MT6325_BIF_DATA_9_SHIFT 0 |
| 4831 | #define MT6325_BIF_ACK_9_MASK 0x1 |
| 4832 | #define MT6325_BIF_ACK_9_SHIFT 8 |
| 4833 | #define MT6325_BIF_ERROR_9_MASK 0x1 |
| 4834 | #define MT6325_BIF_ERROR_9_SHIFT 15 |
| 4835 | #define MT6325_BIF_TEST_MODE0_MASK 0x1 |
| 4836 | #define MT6325_BIF_TEST_MODE0_SHIFT 0 |
| 4837 | #define MT6325_BIF_TEST_MODE1_MASK 0x1 |
| 4838 | #define MT6325_BIF_TEST_MODE1_SHIFT 1 |
| 4839 | #define MT6325_BIF_TEST_MODE2_MASK 0x1 |
| 4840 | #define MT6325_BIF_TEST_MODE2_SHIFT 2 |
| 4841 | #define MT6325_BIF_TEST_MODE3_MASK 0x1 |
| 4842 | #define MT6325_BIF_TEST_MODE3_SHIFT 3 |
| 4843 | #define MT6325_BIF_TEST_MODE4_MASK 0x1 |
| 4844 | #define MT6325_BIF_TEST_MODE4_SHIFT 4 |
| 4845 | #define MT6325_BIF_TEST_MODE5_MASK 0x1 |
| 4846 | #define MT6325_BIF_TEST_MODE5_SHIFT 5 |
| 4847 | #define MT6325_BIF_TEST_MODE6_MASK 0x1 |
| 4848 | #define MT6325_BIF_TEST_MODE6_SHIFT 6 |
| 4849 | #define MT6325_BIF_TEST_MODE7_MASK 0x1 |
| 4850 | #define MT6325_BIF_TEST_MODE7_SHIFT 7 |
| 4851 | #define MT6325_BIF_TEST_MODE8_MASK 0x1 |
| 4852 | #define MT6325_BIF_TEST_MODE8_SHIFT 8 |
| 4853 | #define MT6325_BIF_BAT_LOST_SW_MASK 0x1 |
| 4854 | #define MT6325_BIF_BAT_LOST_SW_SHIFT 11 |
| 4855 | #define MT6325_BIF_RX_DATA_SW_MASK 0x1 |
| 4856 | #define MT6325_BIF_RX_DATA_SW_SHIFT 12 |
| 4857 | #define MT6325_BIF_TX_DATA_SW_MASK 0x1 |
| 4858 | #define MT6325_BIF_TX_DATA_SW_SHIFT 13 |
| 4859 | #define MT6325_BIF_RX_EN_SW_MASK 0x1 |
| 4860 | #define MT6325_BIF_RX_EN_SW_SHIFT 14 |
| 4861 | #define MT6325_BIF_TX_EN_SW_MASK 0x1 |
| 4862 | #define MT6325_BIF_TX_EN_SW_SHIFT 15 |
| 4863 | #define MT6325_BIF_BACK_NORMAL_MASK 0x1 |
| 4864 | #define MT6325_BIF_BACK_NORMAL_SHIFT 0 |
| 4865 | #define MT6325_BIF_IRQ_CLR_MASK 0x1 |
| 4866 | #define MT6325_BIF_IRQ_CLR_SHIFT 1 |
| 4867 | #define MT6325_BIF_BAT_LOST_GATED_MASK 0x1 |
| 4868 | #define MT6325_BIF_BAT_LOST_GATED_SHIFT 10 |
| 4869 | #define MT6325_BIF_IRQ_MASK 0x1 |
| 4870 | #define MT6325_BIF_IRQ_SHIFT 11 |
| 4871 | #define MT6325_BIF_TIMEOUT_MASK 0x1 |
| 4872 | #define MT6325_BIF_TIMEOUT_SHIFT 12 |
| 4873 | #define MT6325_BIF_BAT_LOST_MASK 0x1 |
| 4874 | #define MT6325_BIF_BAT_LOST_SHIFT 13 |
| 4875 | #define MT6325_BIF_TOTAL_VALID_MASK 0x1 |
| 4876 | #define MT6325_BIF_TOTAL_VALID_SHIFT 14 |
| 4877 | #define MT6325_BIF_BUS_STATUS_MASK 0x1 |
| 4878 | #define MT6325_BIF_BUS_STATUS_SHIFT 15 |
| 4879 | #define MT6325_BIF_POWER_UP_COUNT_MASK 0x1F |
| 4880 | #define MT6325_BIF_POWER_UP_COUNT_SHIFT 0 |
| 4881 | #define MT6325_BIF_POWER_UP_MASK 0x1 |
| 4882 | #define MT6325_BIF_POWER_UP_SHIFT 15 |
| 4883 | #define MT6325_BIF_RX_ERROR_UNKNOW_MASK 0x1 |
| 4884 | #define MT6325_BIF_RX_ERROR_UNKNOW_SHIFT 2 |
| 4885 | #define MT6325_BIF_RX_ERROR_INSUFF_MASK 0x1 |
| 4886 | #define MT6325_BIF_RX_ERROR_INSUFF_SHIFT 3 |
| 4887 | #define MT6325_BIF_RX_ERROR_LOWPHASE_MASK 0x1 |
| 4888 | #define MT6325_BIF_RX_ERROR_LOWPHASE_SHIFT 4 |
| 4889 | #define MT6325_BIF_RX_STATE_MASK 0x7 |
| 4890 | #define MT6325_BIF_RX_STATE_SHIFT 5 |
| 4891 | #define MT6325_BIF_FLOW_CTL_STATE_MASK 0x3 |
| 4892 | #define MT6325_BIF_FLOW_CTL_STATE_SHIFT 8 |
| 4893 | #define MT6325_BIF_TX_STATE_MASK 0x3 |
| 4894 | #define MT6325_BIF_TX_STATE_SHIFT 10 |
| 4895 | #define MT6325_QI_BIF_RX_DATA_MASK 0x1 |
| 4896 | #define MT6325_QI_BIF_RX_DATA_SHIFT 12 |
| 4897 | #define MT6325_QI_BIF_RX_EN_MASK 0x1 |
| 4898 | #define MT6325_QI_BIF_RX_EN_SHIFT 13 |
| 4899 | #define MT6325_QI_BIF_TX_DATA_MASK 0x1 |
| 4900 | #define MT6325_QI_BIF_TX_DATA_SHIFT 14 |
| 4901 | #define MT6325_QI_BIF_TX_EN_MASK 0x1 |
| 4902 | #define MT6325_QI_BIF_TX_EN_SHIFT 15 |
| 4903 | #define MT6325_BIF_TX_DATA_FIANL_MASK 0xFFFF |
| 4904 | #define MT6325_BIF_TX_DATA_FIANL_SHIFT 0 |
| 4905 | #define MT6325_BIF_RX_DATA_SAMPLING_MASK 0xFFFF |
| 4906 | #define MT6325_BIF_RX_DATA_SAMPLING_SHIFT 0 |
| 4907 | #define MT6325_BIF_RX_DATA_RECOVERY_MASK 0x3FFF |
| 4908 | #define MT6325_BIF_RX_DATA_RECOVERY_SHIFT 0 |
| 4909 | #define MT6325_RG_BATON_HT_EN_MASK 0x1 |
| 4910 | #define MT6325_RG_BATON_HT_EN_SHIFT 0 |
| 4911 | #define MT6325_RG_BATON_TDET_EN_MASK 0x1 |
| 4912 | #define MT6325_RG_BATON_TDET_EN_SHIFT 2 |
| 4913 | #define MT6325_RG_VBIF28_AUXADC_EN_MASK 0x1 |
| 4914 | #define MT6325_RG_VBIF28_AUXADC_EN_SHIFT 3 |
| 4915 | #define MT6325_RG_BATON_HT_EN_DLY_TIME_MASK 0x1 |
| 4916 | #define MT6325_RG_BATON_HT_EN_DLY_TIME_SHIFT 4 |
| 4917 | #define MT6325_QI_BATON_HT_EN_MASK 0x1 |
| 4918 | #define MT6325_QI_BATON_HT_EN_SHIFT 5 |
| 4919 | #define MT6325_RGS_BATON_HV_MASK 0x1 |
| 4920 | #define MT6325_RGS_BATON_HV_SHIFT 6 |
| 4921 | #define MT6325_RG_BATON_HT_TRIM_RSV0_MASK 0x7 |
| 4922 | #define MT6325_RG_BATON_HT_TRIM_RSV0_SHIFT 8 |
| 4923 | #define MT6325_RG_HW_VTH_CTRL_MASK 0x1 |
| 4924 | #define MT6325_RG_HW_VTH_CTRL_SHIFT 11 |
| 4925 | #define MT6325_RG_HW_VTH2_MASK 0x3 |
| 4926 | #define MT6325_RG_HW_VTH2_SHIFT 12 |
| 4927 | #define MT6325_RG_HW_VTH1_MASK 0x3 |
| 4928 | #define MT6325_RG_HW_VTH1_SHIFT 14 |
| 4929 | #define MT6325_BIF_TIMEOUT_SET_MASK 0xFFFF |
| 4930 | #define MT6325_BIF_TIMEOUT_SET_SHIFT 0 |
| 4931 | #define MT6325_BIF_RX_DEG_WND_MASK 0x3FF |
| 4932 | #define MT6325_BIF_RX_DEG_WND_SHIFT 0 |
| 4933 | #define MT6325_BIF_RX_DEG_EN_MASK 0x1 |
| 4934 | #define MT6325_BIF_RX_DEG_EN_SHIFT 15 |
| 4935 | #define MT6325_BIF_RSV1_MASK 0xFF |
| 4936 | #define MT6325_BIF_RSV1_SHIFT 0 |
| 4937 | #define MT6325_BIF_RSV0_MASK 0xFF |
| 4938 | #define MT6325_BIF_RSV0_SHIFT 8 |
| 4939 | #define MT6325_SPK_EN_L_MASK 0x1 |
| 4940 | #define MT6325_SPK_EN_L_SHIFT 0 |
| 4941 | #define MT6325_SPKMODE_L_MASK 0x1 |
| 4942 | #define MT6325_SPKMODE_L_SHIFT 2 |
| 4943 | #define MT6325_SPK_TRIM_EN_L_MASK 0x1 |
| 4944 | #define MT6325_SPK_TRIM_EN_L_SHIFT 3 |
| 4945 | #define MT6325_SPK_OC_SHDN_DL_MASK 0x1 |
| 4946 | #define MT6325_SPK_OC_SHDN_DL_SHIFT 8 |
| 4947 | #define MT6325_SPK_THER_SHDN_L_EN_MASK 0x1 |
| 4948 | #define MT6325_SPK_THER_SHDN_L_EN_SHIFT 9 |
| 4949 | #define MT6325_SPK_OUT_STAGE_SEL_MASK 0x1 |
| 4950 | #define MT6325_SPK_OUT_STAGE_SEL_SHIFT 10 |
| 4951 | #define MT6325_RG_SPK_GAINL_MASK 0x3 |
| 4952 | #define MT6325_RG_SPK_GAINL_SHIFT 12 |
| 4953 | #define MT6325_DA_SPK_OFFSET_L_MASK 0x1F |
| 4954 | #define MT6325_DA_SPK_OFFSET_L_SHIFT 0 |
| 4955 | #define MT6325_DA_SPK_LEAD_DGLH_L_MASK 0x1 |
| 4956 | #define MT6325_DA_SPK_LEAD_DGLH_L_SHIFT 5 |
| 4957 | #define MT6325_NI_SPK_LEAD_L_MASK 0x1 |
| 4958 | #define MT6325_NI_SPK_LEAD_L_SHIFT 6 |
| 4959 | #define MT6325_SPK_OFFSET_L_OV_MASK 0x1 |
| 4960 | #define MT6325_SPK_OFFSET_L_OV_SHIFT 7 |
| 4961 | #define MT6325_SPK_OFFSET_L_SW_MASK 0x1F |
| 4962 | #define MT6325_SPK_OFFSET_L_SW_SHIFT 8 |
| 4963 | #define MT6325_SPK_LEAD_L_SW_MASK 0x1 |
| 4964 | #define MT6325_SPK_LEAD_L_SW_SHIFT 13 |
| 4965 | #define MT6325_SPK_OFFSET_L_MODE_MASK 0x1 |
| 4966 | #define MT6325_SPK_OFFSET_L_MODE_SHIFT 14 |
| 4967 | #define MT6325_SPK_TRIM_DONE_L_MASK 0x1 |
| 4968 | #define MT6325_SPK_TRIM_DONE_L_SHIFT 15 |
| 4969 | #define MT6325_RG_SPK_INTG_RST_L_MASK 0x1 |
| 4970 | #define MT6325_RG_SPK_INTG_RST_L_SHIFT 0 |
| 4971 | #define MT6325_RG_SPK_FORCE_EN_L_MASK 0x1 |
| 4972 | #define MT6325_RG_SPK_FORCE_EN_L_SHIFT 1 |
| 4973 | #define MT6325_RG_SPK_SLEW_L_MASK 0x3 |
| 4974 | #define MT6325_RG_SPK_SLEW_L_SHIFT 2 |
| 4975 | #define MT6325_RG_SPKAB_OBIAS_L_MASK 0x3 |
| 4976 | #define MT6325_RG_SPKAB_OBIAS_L_SHIFT 4 |
| 4977 | #define MT6325_RG_SPKRCV_EN_L_MASK 0x1 |
| 4978 | #define MT6325_RG_SPKRCV_EN_L_SHIFT 6 |
| 4979 | #define MT6325_RG_SPK_DRC_EN_L_MASK 0x1 |
| 4980 | #define MT6325_RG_SPK_DRC_EN_L_SHIFT 7 |
| 4981 | #define MT6325_RG_SPK_TEST_EN_L_MASK 0x1 |
| 4982 | #define MT6325_RG_SPK_TEST_EN_L_SHIFT 8 |
| 4983 | #define MT6325_RG_SPKAB_OC_EN_L_MASK 0x1 |
| 4984 | #define MT6325_RG_SPKAB_OC_EN_L_SHIFT 9 |
| 4985 | #define MT6325_RG_SPK_OC_EN_L_MASK 0x1 |
| 4986 | #define MT6325_RG_SPK_OC_EN_L_SHIFT 10 |
| 4987 | #define MT6325_SPK_EN_R_MASK 0x1 |
| 4988 | #define MT6325_SPK_EN_R_SHIFT 0 |
| 4989 | #define MT6325_SPKMODE_R_MASK 0x1 |
| 4990 | #define MT6325_SPKMODE_R_SHIFT 2 |
| 4991 | #define MT6325_SPK_TRIM_EN_R_MASK 0x1 |
| 4992 | #define MT6325_SPK_TRIM_EN_R_SHIFT 3 |
| 4993 | #define MT6325_SPK_OC_SHDN_DR_MASK 0x1 |
| 4994 | #define MT6325_SPK_OC_SHDN_DR_SHIFT 8 |
| 4995 | #define MT6325_SPK_THER_SHDN_R_EN_MASK 0x1 |
| 4996 | #define MT6325_SPK_THER_SHDN_R_EN_SHIFT 9 |
| 4997 | #define MT6325_RG_SPK_GAINR_MASK 0x3 |
| 4998 | #define MT6325_RG_SPK_GAINR_SHIFT 12 |
| 4999 | #define MT6325_DA_SPK_OFFSET_R_MASK 0x1F |
| 5000 | #define MT6325_DA_SPK_OFFSET_R_SHIFT 0 |
| 5001 | #define MT6325_DA_SPK_LEAD_DGLH_R_MASK 0x1 |
| 5002 | #define MT6325_DA_SPK_LEAD_DGLH_R_SHIFT 5 |
| 5003 | #define MT6325_NI_SPK_LEAD_R_MASK 0x1 |
| 5004 | #define MT6325_NI_SPK_LEAD_R_SHIFT 6 |
| 5005 | #define MT6325_SPK_OFFSET_R_OV_MASK 0x1 |
| 5006 | #define MT6325_SPK_OFFSET_R_OV_SHIFT 7 |
| 5007 | #define MT6325_SPK_OFFSET_R_SW_MASK 0x1F |
| 5008 | #define MT6325_SPK_OFFSET_R_SW_SHIFT 8 |
| 5009 | #define MT6325_SPK_LEAD_R_SW_MASK 0x1 |
| 5010 | #define MT6325_SPK_LEAD_R_SW_SHIFT 13 |
| 5011 | #define MT6325_SPK_OFFSET_R_MODE_MASK 0x1 |
| 5012 | #define MT6325_SPK_OFFSET_R_MODE_SHIFT 14 |
| 5013 | #define MT6325_SPK_TRIM_DONE_R_MASK 0x1 |
| 5014 | #define MT6325_SPK_TRIM_DONE_R_SHIFT 15 |
| 5015 | #define MT6325_RG_SPK_INTG_RST_R_MASK 0x1 |
| 5016 | #define MT6325_RG_SPK_INTG_RST_R_SHIFT 0 |
| 5017 | #define MT6325_RG_SPK_FORCE_EN_R_MASK 0x1 |
| 5018 | #define MT6325_RG_SPK_FORCE_EN_R_SHIFT 1 |
| 5019 | #define MT6325_RG_SPK_SLEW_R_MASK 0x3 |
| 5020 | #define MT6325_RG_SPK_SLEW_R_SHIFT 2 |
| 5021 | #define MT6325_RG_SPKAB_OBIAS_R_MASK 0x3 |
| 5022 | #define MT6325_RG_SPKAB_OBIAS_R_SHIFT 4 |
| 5023 | #define MT6325_RG_SPKRCV_EN_R_MASK 0x1 |
| 5024 | #define MT6325_RG_SPKRCV_EN_R_SHIFT 6 |
| 5025 | #define MT6325_RG_SPK_DRC_EN_R_MASK 0x1 |
| 5026 | #define MT6325_RG_SPK_DRC_EN_R_SHIFT 7 |
| 5027 | #define MT6325_RG_SPK_TEST_EN_R_MASK 0x1 |
| 5028 | #define MT6325_RG_SPK_TEST_EN_R_SHIFT 8 |
| 5029 | #define MT6325_RG_SPKAB_OC_EN_R_MASK 0x1 |
| 5030 | #define MT6325_RG_SPKAB_OC_EN_R_SHIFT 9 |
| 5031 | #define MT6325_RG_SPK_OC_EN_R_MASK 0x1 |
| 5032 | #define MT6325_RG_SPK_OC_EN_R_SHIFT 10 |
| 5033 | #define MT6325_RG_SPKPGA_GAINR_MASK 0xF |
| 5034 | #define MT6325_RG_SPKPGA_GAINR_SHIFT 11 |
| 5035 | #define MT6325_SPK_TRIM_WND_MASK 0x7 |
| 5036 | #define MT6325_SPK_TRIM_WND_SHIFT 0 |
| 5037 | #define MT6325_SPK_TRIM_THD_MASK 0x3 |
| 5038 | #define MT6325_SPK_TRIM_THD_SHIFT 4 |
| 5039 | #define MT6325_SPK_OC_WND_MASK 0x3 |
| 5040 | #define MT6325_SPK_OC_WND_SHIFT 8 |
| 5041 | #define MT6325_SPK_OC_THD_MASK 0x3 |
| 5042 | #define MT6325_SPK_OC_THD_SHIFT 10 |
| 5043 | #define MT6325_SPK_D_OC_R_DEG_MASK 0x1 |
| 5044 | #define MT6325_SPK_D_OC_R_DEG_SHIFT 12 |
| 5045 | #define MT6325_SPK_AB_OC_R_DEG_MASK 0x1 |
| 5046 | #define MT6325_SPK_AB_OC_R_DEG_SHIFT 13 |
| 5047 | #define MT6325_SPK_D_OC_L_DEG_MASK 0x1 |
| 5048 | #define MT6325_SPK_D_OC_L_DEG_SHIFT 14 |
| 5049 | #define MT6325_SPK_AB_OC_L_DEG_MASK 0x1 |
| 5050 | #define MT6325_SPK_AB_OC_L_DEG_SHIFT 15 |
| 5051 | #define MT6325_SPK_TD1_MASK 0xF |
| 5052 | #define MT6325_SPK_TD1_SHIFT 0 |
| 5053 | #define MT6325_SPK_TD2_MASK 0xF |
| 5054 | #define MT6325_SPK_TD2_SHIFT 4 |
| 5055 | #define MT6325_SPK_TD3_MASK 0xF |
| 5056 | #define MT6325_SPK_TD3_SHIFT 8 |
| 5057 | #define MT6325_SPK_TRIM_DIV_MASK 0x7 |
| 5058 | #define MT6325_SPK_TRIM_DIV_SHIFT 12 |
| 5059 | #define MT6325_RG_BTL_SET_MASK 0x3 |
| 5060 | #define MT6325_RG_BTL_SET_SHIFT 0 |
| 5061 | #define MT6325_RG_SPK_IBIAS_SEL_MASK 0x3 |
| 5062 | #define MT6325_RG_SPK_IBIAS_SEL_SHIFT 2 |
| 5063 | #define MT6325_RG_SPK_CCODE_MASK 0xF |
| 5064 | #define MT6325_RG_SPK_CCODE_SHIFT 4 |
| 5065 | #define MT6325_RG_SPK_EN_VIEW_VCM_MASK 0x1 |
| 5066 | #define MT6325_RG_SPK_EN_VIEW_VCM_SHIFT 8 |
| 5067 | #define MT6325_RG_SPK_EN_VIEW_CLK_MASK 0x1 |
| 5068 | #define MT6325_RG_SPK_EN_VIEW_CLK_SHIFT 9 |
| 5069 | #define MT6325_RG_SPK_VCM_SEL_MASK 0x1 |
| 5070 | #define MT6325_RG_SPK_VCM_SEL_SHIFT 10 |
| 5071 | #define MT6325_RG_SPK_VCM_IBSEL_MASK 0x1 |
| 5072 | #define MT6325_RG_SPK_VCM_IBSEL_SHIFT 11 |
| 5073 | #define MT6325_RG_SPK_FBRC_EN_MASK 0x1 |
| 5074 | #define MT6325_RG_SPK_FBRC_EN_SHIFT 12 |
| 5075 | #define MT6325_RG_SPKAB_OVDRV_MASK 0x1 |
| 5076 | #define MT6325_RG_SPKAB_OVDRV_SHIFT 13 |
| 5077 | #define MT6325_RG_SPK_OCTH_D_MASK 0x1 |
| 5078 | #define MT6325_RG_SPK_OCTH_D_SHIFT 14 |
| 5079 | #define MT6325_RG_SPKPGA_GAINL_MASK 0xF |
| 5080 | #define MT6325_RG_SPKPGA_GAINL_SHIFT 8 |
| 5081 | #define MT6325_SPK_RSV0_MASK 0x1 |
| 5082 | #define MT6325_SPK_RSV0_SHIFT 12 |
| 5083 | #define MT6325_SPK_VCM_FAST_EN_MASK 0x1 |
| 5084 | #define MT6325_SPK_VCM_FAST_EN_SHIFT 13 |
| 5085 | #define MT6325_SPK_TEST_MODE0_MASK 0x1 |
| 5086 | #define MT6325_SPK_TEST_MODE0_SHIFT 14 |
| 5087 | #define MT6325_SPK_TEST_MODE1_MASK 0x1 |
| 5088 | #define MT6325_SPK_TEST_MODE1_SHIFT 15 |
| 5089 | #define MT6325_SPK_TD_WAIT_MASK 0x7 |
| 5090 | #define MT6325_SPK_TD_WAIT_SHIFT 0 |
| 5091 | #define MT6325_SPK_TD_DONE_MASK 0x7 |
| 5092 | #define MT6325_SPK_TD_DONE_SHIFT 4 |
| 5093 | #define MT6325_SPK_EN_MODE_MASK 0x1 |
| 5094 | #define MT6325_SPK_EN_MODE_SHIFT 0 |
| 5095 | #define MT6325_SPK_VCM_FAST_SW_MASK 0x1 |
| 5096 | #define MT6325_SPK_VCM_FAST_SW_SHIFT 1 |
| 5097 | #define MT6325_SPK_RST_R_SW_MASK 0x1 |
| 5098 | #define MT6325_SPK_RST_R_SW_SHIFT 2 |
| 5099 | #define MT6325_SPK_RST_L_SW_MASK 0x1 |
| 5100 | #define MT6325_SPK_RST_L_SW_SHIFT 3 |
| 5101 | #define MT6325_SPKMODE_R_SW_MASK 0x1 |
| 5102 | #define MT6325_SPKMODE_R_SW_SHIFT 4 |
| 5103 | #define MT6325_SPKMODE_L_SW_MASK 0x1 |
| 5104 | #define MT6325_SPKMODE_L_SW_SHIFT 5 |
| 5105 | #define MT6325_SPK_DEPOP_EN_R_SW_MASK 0x1 |
| 5106 | #define MT6325_SPK_DEPOP_EN_R_SW_SHIFT 6 |
| 5107 | #define MT6325_SPK_DEPOP_EN_L_SW_MASK 0x1 |
| 5108 | #define MT6325_SPK_DEPOP_EN_L_SW_SHIFT 7 |
| 5109 | #define MT6325_SPK_EN_R_SW_MASK 0x1 |
| 5110 | #define MT6325_SPK_EN_R_SW_SHIFT 8 |
| 5111 | #define MT6325_SPK_EN_L_SW_MASK 0x1 |
| 5112 | #define MT6325_SPK_EN_L_SW_SHIFT 9 |
| 5113 | #define MT6325_SPK_OUTSTG_EN_R_SW_MASK 0x1 |
| 5114 | #define MT6325_SPK_OUTSTG_EN_R_SW_SHIFT 10 |
| 5115 | #define MT6325_SPK_OUTSTG_EN_L_SW_MASK 0x1 |
| 5116 | #define MT6325_SPK_OUTSTG_EN_L_SW_SHIFT 11 |
| 5117 | #define MT6325_SPK_TRIM_EN_R_SW_MASK 0x1 |
| 5118 | #define MT6325_SPK_TRIM_EN_R_SW_SHIFT 12 |
| 5119 | #define MT6325_SPK_TRIM_EN_L_SW_MASK 0x1 |
| 5120 | #define MT6325_SPK_TRIM_EN_L_SW_SHIFT 13 |
| 5121 | #define MT6325_SPK_TRIM_STOP_R_SW_MASK 0x1 |
| 5122 | #define MT6325_SPK_TRIM_STOP_R_SW_SHIFT 14 |
| 5123 | #define MT6325_SPK_TRIM_STOP_L_SW_MASK 0x1 |
| 5124 | #define MT6325_SPK_TRIM_STOP_L_SW_SHIFT 15 |
| 5125 | #define MT6325_RG_SPK_ISENSE_TEST_EN_MASK 0x1 |
| 5126 | #define MT6325_RG_SPK_ISENSE_TEST_EN_SHIFT 7 |
| 5127 | #define MT6325_RG_SPK_ISENSE_REFSEL_MASK 0x7 |
| 5128 | #define MT6325_RG_SPK_ISENSE_REFSEL_SHIFT 8 |
| 5129 | #define MT6325_RG_SPK_ISENSE_GAINSEL_MASK 0x7 |
| 5130 | #define MT6325_RG_SPK_ISENSE_GAINSEL_SHIFT 11 |
| 5131 | #define MT6325_RG_SPK_ISENSE_PDRESET_MASK 0x1 |
| 5132 | #define MT6325_RG_SPK_ISENSE_PDRESET_SHIFT 14 |
| 5133 | #define MT6325_RG_SPK_ISENSE_EN_MASK 0x1 |
| 5134 | #define MT6325_RG_SPK_ISENSE_EN_SHIFT 15 |
| 5135 | #define MT6325_RG_SPK_RSV1_MASK 0xFF |
| 5136 | #define MT6325_RG_SPK_RSV1_SHIFT 0 |
| 5137 | #define MT6325_RG_SPK_RSV0_MASK 0xFF |
| 5138 | #define MT6325_RG_SPK_RSV0_SHIFT 8 |
| 5139 | #define MT6325_RG_SPK_ABD_VOLSEN_GAIN_MASK 0x3 |
| 5140 | #define MT6325_RG_SPK_ABD_VOLSEN_GAIN_SHIFT 4 |
| 5141 | #define MT6325_RG_SPK_ABD_VOLSEN_EN_MASK 0x1 |
| 5142 | #define MT6325_RG_SPK_ABD_VOLSEN_EN_SHIFT 6 |
| 5143 | #define MT6325_RG_SPK_ABD_CURSEN_SEL_MASK 0x1 |
| 5144 | #define MT6325_RG_SPK_ABD_CURSEN_SEL_SHIFT 7 |
| 5145 | #define MT6325_RG_SPK_RSV2_MASK 0xFF |
| 5146 | #define MT6325_RG_SPK_RSV2_SHIFT 8 |
| 5147 | #define MT6325_RG_SPK_TRIM2_MASK 0xFF |
| 5148 | #define MT6325_RG_SPK_TRIM2_SHIFT 0 |
| 5149 | #define MT6325_RG_SPK_TRIM1_MASK 0xFF |
| 5150 | #define MT6325_RG_SPK_TRIM1_SHIFT 8 |
| 5151 | #define MT6325_RG_SPK_D_CURSEN_RSETSEL_MASK 0x1F |
| 5152 | #define MT6325_RG_SPK_D_CURSEN_RSETSEL_SHIFT 0 |
| 5153 | #define MT6325_RG_SPK_D_CURSEN_GAIN_MASK 0x3 |
| 5154 | #define MT6325_RG_SPK_D_CURSEN_GAIN_SHIFT 5 |
| 5155 | #define MT6325_RG_SPK_D_CURSEN_EN_MASK 0x1 |
| 5156 | #define MT6325_RG_SPK_D_CURSEN_EN_SHIFT 7 |
| 5157 | #define MT6325_RG_SPK_AB_CURSEN_RSETSEL_MASK 0x1F |
| 5158 | #define MT6325_RG_SPK_AB_CURSEN_RSETSEL_SHIFT 8 |
| 5159 | #define MT6325_RG_SPK_AB_CURSEN_GAIN_MASK 0x3 |
| 5160 | #define MT6325_RG_SPK_AB_CURSEN_GAIN_SHIFT 13 |
| 5161 | #define MT6325_RG_SPK_AB_CURSEN_EN_MASK 0x1 |
| 5162 | #define MT6325_RG_SPK_AB_CURSEN_EN_SHIFT 15 |
| 5163 | #define MT6325_RG_SPKPGA_GAIN_MASK 0xF |
| 5164 | #define MT6325_RG_SPKPGA_GAIN_SHIFT 11 |
| 5165 | #define MT6325_RG_SPK_RSV_MASK 0xFF |
| 5166 | #define MT6325_RG_SPK_RSV_SHIFT 0 |
| 5167 | #define MT6325_RG_ISENSE_PD_RESET_MASK 0x1 |
| 5168 | #define MT6325_RG_ISENSE_PD_RESET_SHIFT 11 |
| 5169 | #define MT6325_RG_AUDIVLPWRUP_VAUDP12_MASK 0x1 |
| 5170 | #define MT6325_RG_AUDIVLPWRUP_VAUDP12_SHIFT 4 |
| 5171 | #define MT6325_RG_AUDIVLSTARTUP_VAUDP12_MASK 0x1 |
| 5172 | #define MT6325_RG_AUDIVLSTARTUP_VAUDP12_SHIFT 5 |
| 5173 | #define MT6325_RG_AUDIVLMUXSEL_VAUDP12_MASK 0x7 |
| 5174 | #define MT6325_RG_AUDIVLMUXSEL_VAUDP12_SHIFT 6 |
| 5175 | #define MT6325_RG_AUDIVLMUTE_VAUDP12_MASK 0x1 |
| 5176 | #define MT6325_RG_AUDIVLMUTE_VAUDP12_SHIFT 9 |
| 5177 | #define MT6325_RG_OTP_PA_MASK 0x3F |
| 5178 | #define MT6325_RG_OTP_PA_SHIFT 0 |
| 5179 | #define MT6325_RG_OTP_PDIN_MASK 0xFF |
| 5180 | #define MT6325_RG_OTP_PDIN_SHIFT 0 |
| 5181 | #define MT6325_RG_OTP_PTM_MASK 0x3 |
| 5182 | #define MT6325_RG_OTP_PTM_SHIFT 0 |
| 5183 | #define MT6325_RG_OTP_PWE_MASK 0x3 |
| 5184 | #define MT6325_RG_OTP_PWE_SHIFT 0 |
| 5185 | #define MT6325_RG_OTP_PPROG_MASK 0x1 |
| 5186 | #define MT6325_RG_OTP_PPROG_SHIFT 0 |
| 5187 | #define MT6325_RG_OTP_PWE_SRC_MASK 0x1 |
| 5188 | #define MT6325_RG_OTP_PWE_SRC_SHIFT 0 |
| 5189 | #define MT6325_RG_OTP_PROG_PKEY_MASK 0xFFFF |
| 5190 | #define MT6325_RG_OTP_PROG_PKEY_SHIFT 0 |
| 5191 | #define MT6325_RG_OTP_RD_PKEY_MASK 0xFFFF |
| 5192 | #define MT6325_RG_OTP_RD_PKEY_SHIFT 0 |
| 5193 | #define MT6325_RG_OTP_RD_TRIG_MASK 0x1 |
| 5194 | #define MT6325_RG_OTP_RD_TRIG_SHIFT 0 |
| 5195 | #define MT6325_RG_RD_RDY_BYPASS_MASK 0x1 |
| 5196 | #define MT6325_RG_RD_RDY_BYPASS_SHIFT 0 |
| 5197 | #define MT6325_RG_SKIP_OTP_OUT_MASK 0x1 |
| 5198 | #define MT6325_RG_SKIP_OTP_OUT_SHIFT 0 |
| 5199 | #define MT6325_RG_OTP_RD_SW_MASK 0x1 |
| 5200 | #define MT6325_RG_OTP_RD_SW_SHIFT 0 |
| 5201 | #define MT6325_RG_OTP_DOUT_SW_MASK 0xFFFF |
| 5202 | #define MT6325_RG_OTP_DOUT_SW_SHIFT 0 |
| 5203 | #define MT6325_RG_OTP_RD_BUSY_MASK 0x1 |
| 5204 | #define MT6325_RG_OTP_RD_BUSY_SHIFT 0 |
| 5205 | #define MT6325_RG_OTP_RD_ACK_MASK 0x1 |
| 5206 | #define MT6325_RG_OTP_RD_ACK_SHIFT 2 |
| 5207 | #define MT6325_RG_OTP_PA_SW_MASK 0x1F |
| 5208 | #define MT6325_RG_OTP_PA_SW_SHIFT 0 |
| 5209 | #define MT6325_RG_OTP_DOUT_0_15_MASK 0xFFFF |
| 5210 | #define MT6325_RG_OTP_DOUT_0_15_SHIFT 0 |
| 5211 | #define MT6325_RG_OTP_DOUT_16_31_MASK 0xFFFF |
| 5212 | #define MT6325_RG_OTP_DOUT_16_31_SHIFT 0 |
| 5213 | #define MT6325_RG_OTP_DOUT_32_47_MASK 0xFFFF |
| 5214 | #define MT6325_RG_OTP_DOUT_32_47_SHIFT 0 |
| 5215 | #define MT6325_RG_OTP_DOUT_48_63_MASK 0xFFFF |
| 5216 | #define MT6325_RG_OTP_DOUT_48_63_SHIFT 0 |
| 5217 | #define MT6325_RG_OTP_DOUT_64_79_MASK 0xFFFF |
| 5218 | #define MT6325_RG_OTP_DOUT_64_79_SHIFT 0 |
| 5219 | #define MT6325_RG_OTP_DOUT_80_95_MASK 0xFFFF |
| 5220 | #define MT6325_RG_OTP_DOUT_80_95_SHIFT 0 |
| 5221 | #define MT6325_RG_OTP_DOUT_96_111_MASK 0xFFFF |
| 5222 | #define MT6325_RG_OTP_DOUT_96_111_SHIFT 0 |
| 5223 | #define MT6325_RG_OTP_DOUT_112_127_MASK 0xFFFF |
| 5224 | #define MT6325_RG_OTP_DOUT_112_127_SHIFT 0 |
| 5225 | #define MT6325_RG_OTP_DOUT_128_143_MASK 0xFFFF |
| 5226 | #define MT6325_RG_OTP_DOUT_128_143_SHIFT 0 |
| 5227 | #define MT6325_RG_OTP_DOUT_144_159_MASK 0xFFFF |
| 5228 | #define MT6325_RG_OTP_DOUT_144_159_SHIFT 0 |
| 5229 | #define MT6325_RG_OTP_DOUT_160_175_MASK 0xFFFF |
| 5230 | #define MT6325_RG_OTP_DOUT_160_175_SHIFT 0 |
| 5231 | #define MT6325_RG_OTP_DOUT_176_191_MASK 0xFFFF |
| 5232 | #define MT6325_RG_OTP_DOUT_176_191_SHIFT 0 |
| 5233 | #define MT6325_RG_OTP_DOUT_192_207_MASK 0xFFFF |
| 5234 | #define MT6325_RG_OTP_DOUT_192_207_SHIFT 0 |
| 5235 | #define MT6325_RG_OTP_DOUT_208_223_MASK 0xFFFF |
| 5236 | #define MT6325_RG_OTP_DOUT_208_223_SHIFT 0 |
| 5237 | #define MT6325_RG_OTP_DOUT_224_239_MASK 0xFFFF |
| 5238 | #define MT6325_RG_OTP_DOUT_224_239_SHIFT 0 |
| 5239 | #define MT6325_RG_OTP_DOUT_240_255_MASK 0xFFFF |
| 5240 | #define MT6325_RG_OTP_DOUT_240_255_SHIFT 0 |
| 5241 | #define MT6325_RG_OTP_DOUT_256_271_MASK 0xFFFF |
| 5242 | #define MT6325_RG_OTP_DOUT_256_271_SHIFT 0 |
| 5243 | #define MT6325_RG_OTP_DOUT_272_287_MASK 0xFFFF |
| 5244 | #define MT6325_RG_OTP_DOUT_272_287_SHIFT 0 |
| 5245 | #define MT6325_RG_OTP_DOUT_288_303_MASK 0xFFFF |
| 5246 | #define MT6325_RG_OTP_DOUT_288_303_SHIFT 0 |
| 5247 | #define MT6325_RG_OTP_DOUT_304_319_MASK 0xFFFF |
| 5248 | #define MT6325_RG_OTP_DOUT_304_319_SHIFT 0 |
| 5249 | #define MT6325_RG_OTP_DOUT_320_335_MASK 0xFFFF |
| 5250 | #define MT6325_RG_OTP_DOUT_320_335_SHIFT 0 |
| 5251 | #define MT6325_RG_OTP_DOUT_336_351_MASK 0xFFFF |
| 5252 | #define MT6325_RG_OTP_DOUT_336_351_SHIFT 0 |
| 5253 | #define MT6325_RG_OTP_DOUT_352_367_MASK 0xFFFF |
| 5254 | #define MT6325_RG_OTP_DOUT_352_367_SHIFT 0 |
| 5255 | #define MT6325_RG_OTP_DOUT_368_383_MASK 0xFFFF |
| 5256 | #define MT6325_RG_OTP_DOUT_368_383_SHIFT 0 |
| 5257 | #define MT6325_RG_OTP_DOUT_384_399_MASK 0xFFFF |
| 5258 | #define MT6325_RG_OTP_DOUT_384_399_SHIFT 0 |
| 5259 | #define MT6325_RG_OTP_DOUT_400_415_MASK 0xFFFF |
| 5260 | #define MT6325_RG_OTP_DOUT_400_415_SHIFT 0 |
| 5261 | #define MT6325_RG_OTP_DOUT_416_431_MASK 0xFFFF |
| 5262 | #define MT6325_RG_OTP_DOUT_416_431_SHIFT 0 |
| 5263 | #define MT6325_RG_OTP_DOUT_432_447_MASK 0xFFFF |
| 5264 | #define MT6325_RG_OTP_DOUT_432_447_SHIFT 0 |
| 5265 | #define MT6325_RG_OTP_DOUT_448_463_MASK 0xFFFF |
| 5266 | #define MT6325_RG_OTP_DOUT_448_463_SHIFT 0 |
| 5267 | #define MT6325_RG_OTP_DOUT_464_479_MASK 0xFFFF |
| 5268 | #define MT6325_RG_OTP_DOUT_464_479_SHIFT 0 |
| 5269 | #define MT6325_RG_OTP_DOUT_480_495_MASK 0xFFFF |
| 5270 | #define MT6325_RG_OTP_DOUT_480_495_SHIFT 0 |
| 5271 | #define MT6325_RG_OTP_DOUT_496_511_MASK 0xFFFF |
| 5272 | #define MT6325_RG_OTP_DOUT_496_511_SHIFT 0 |
| 5273 | #define MT6325_RG_OTP_VAL_0_15_MASK 0xFFFF |
| 5274 | #define MT6325_RG_OTP_VAL_0_15_SHIFT 0 |
| 5275 | #define MT6325_RG_OTP_VAL_16_31_MASK 0xFFFF |
| 5276 | #define MT6325_RG_OTP_VAL_16_31_SHIFT 0 |
| 5277 | #define MT6325_RG_OTP_VAL_32_47_MASK 0xFFFF |
| 5278 | #define MT6325_RG_OTP_VAL_32_47_SHIFT 0 |
| 5279 | #define MT6325_RG_OTP_VAL_48_63_MASK 0xFFFF |
| 5280 | #define MT6325_RG_OTP_VAL_48_63_SHIFT 0 |
| 5281 | #define MT6325_RG_OTP_VAL_64_79_MASK 0xFFFF |
| 5282 | #define MT6325_RG_OTP_VAL_64_79_SHIFT 0 |
| 5283 | #define MT6325_RG_OTP_VAL_80_95_MASK 0xFFFF |
| 5284 | #define MT6325_RG_OTP_VAL_80_95_SHIFT 0 |
| 5285 | #define MT6325_RG_OTP_VAL_96_111_MASK 0xFFFF |
| 5286 | #define MT6325_RG_OTP_VAL_96_111_SHIFT 0 |
| 5287 | #define MT6325_RG_OTP_VAL_112_127_MASK 0xFFFF |
| 5288 | #define MT6325_RG_OTP_VAL_112_127_SHIFT 0 |
| 5289 | #define MT6325_RG_OTP_VAL_128_143_MASK 0xFFFF |
| 5290 | #define MT6325_RG_OTP_VAL_128_143_SHIFT 0 |
| 5291 | #define MT6325_RG_OTP_VAL_144_159_MASK 0xFFFF |
| 5292 | #define MT6325_RG_OTP_VAL_144_159_SHIFT 0 |
| 5293 | #define MT6325_RG_OTP_VAL_160_175_MASK 0xFFFF |
| 5294 | #define MT6325_RG_OTP_VAL_160_175_SHIFT 0 |
| 5295 | #define MT6325_RG_OTP_VAL_176_191_MASK 0xFFFF |
| 5296 | #define MT6325_RG_OTP_VAL_176_191_SHIFT 0 |
| 5297 | #define MT6325_RG_OTP_VAL_192_207_MASK 0xFFFF |
| 5298 | #define MT6325_RG_OTP_VAL_192_207_SHIFT 0 |
| 5299 | #define MT6325_RG_OTP_VAL_208_223_MASK 0xFFFF |
| 5300 | #define MT6325_RG_OTP_VAL_208_223_SHIFT 0 |
| 5301 | #define MT6325_RG_OTP_VAL_224_239_MASK 0xFFFF |
| 5302 | #define MT6325_RG_OTP_VAL_224_239_SHIFT 0 |
| 5303 | #define MT6325_RG_OTP_VAL_240_255_MASK 0xFFFF |
| 5304 | #define MT6325_RG_OTP_VAL_240_255_SHIFT 0 |
| 5305 | #define MT6325_RG_OTP_VAL_256_271_MASK 0xFFFF |
| 5306 | #define MT6325_RG_OTP_VAL_256_271_SHIFT 0 |
| 5307 | #define MT6325_RG_OTP_VAL_272_287_MASK 0xFFFF |
| 5308 | #define MT6325_RG_OTP_VAL_272_287_SHIFT 0 |
| 5309 | #define MT6325_RG_OTP_VAL_288_303_MASK 0xFFFF |
| 5310 | #define MT6325_RG_OTP_VAL_288_303_SHIFT 0 |
| 5311 | #define MT6325_RG_OTP_VAL_304_319_MASK 0xFFFF |
| 5312 | #define MT6325_RG_OTP_VAL_304_319_SHIFT 0 |
| 5313 | #define MT6325_RG_OTP_VAL_320_335_MASK 0xFFFF |
| 5314 | #define MT6325_RG_OTP_VAL_320_335_SHIFT 0 |
| 5315 | #define MT6325_RG_OTP_VAL_336_351_MASK 0xFFFF |
| 5316 | #define MT6325_RG_OTP_VAL_336_351_SHIFT 0 |
| 5317 | #define MT6325_RG_OTP_VAL_352_367_MASK 0xFFFF |
| 5318 | #define MT6325_RG_OTP_VAL_352_367_SHIFT 0 |
| 5319 | #define MT6325_RG_OTP_VAL_368_383_MASK 0xFFFF |
| 5320 | #define MT6325_RG_OTP_VAL_368_383_SHIFT 0 |
| 5321 | #define MT6325_RG_OTP_VAL_384_399_MASK 0xFFFF |
| 5322 | #define MT6325_RG_OTP_VAL_384_399_SHIFT 0 |
| 5323 | #define MT6325_RG_OTP_VAL_400_415_MASK 0xFFFF |
| 5324 | #define MT6325_RG_OTP_VAL_400_415_SHIFT 0 |
| 5325 | #define MT6325_RG_OTP_VAL_416_431_MASK 0xFFFF |
| 5326 | #define MT6325_RG_OTP_VAL_416_431_SHIFT 0 |
| 5327 | #define MT6325_RG_OTP_VAL_432_447_MASK 0xFFFF |
| 5328 | #define MT6325_RG_OTP_VAL_432_447_SHIFT 0 |
| 5329 | #define MT6325_RG_OTP_VAL_448_463_MASK 0xFFFF |
| 5330 | #define MT6325_RG_OTP_VAL_448_463_SHIFT 0 |
| 5331 | #define MT6325_RG_OTP_VAL_464_479_MASK 0xFFFF |
| 5332 | #define MT6325_RG_OTP_VAL_464_479_SHIFT 0 |
| 5333 | #define MT6325_RG_OTP_VAL_480_495_MASK 0xFFFF |
| 5334 | #define MT6325_RG_OTP_VAL_480_495_SHIFT 0 |
| 5335 | #define MT6325_RG_OTP_VAL_496_511_MASK 0xFFFF |
| 5336 | #define MT6325_RG_OTP_VAL_496_511_SHIFT 0 |
| 5337 | #define MT6325_MIX_EOSC32_STP_LPDTB_MASK 0x1 |
| 5338 | #define MT6325_MIX_EOSC32_STP_LPDTB_SHIFT 1 |
| 5339 | #define MT6325_MIX_EOSC32_STP_LPDEN_MASK 0x1 |
| 5340 | #define MT6325_MIX_EOSC32_STP_LPDEN_SHIFT 2 |
| 5341 | #define MT6325_MIX_XOSC32_STP_PWDB_MASK 0x1 |
| 5342 | #define MT6325_MIX_XOSC32_STP_PWDB_SHIFT 3 |
| 5343 | #define MT6325_MIX_XOSC32_STP_LPDTB_MASK 0x1 |
| 5344 | #define MT6325_MIX_XOSC32_STP_LPDTB_SHIFT 4 |
| 5345 | #define MT6325_MIX_XOSC32_STP_LPDEN_MASK 0x1 |
| 5346 | #define MT6325_MIX_XOSC32_STP_LPDEN_SHIFT 5 |
| 5347 | #define MT6325_MIX_XOSC32_STP_LPDRST_MASK 0x1 |
| 5348 | #define MT6325_MIX_XOSC32_STP_LPDRST_SHIFT 6 |
| 5349 | #define MT6325_MIX_XOSC32_STP_CALI_MASK 0x1F |
| 5350 | #define MT6325_MIX_XOSC32_STP_CALI_SHIFT 7 |
| 5351 | #define MT6325_STMP_MODE_MASK 0x1 |
| 5352 | #define MT6325_STMP_MODE_SHIFT 12 |
| 5353 | #define MT6325_MIX_EOSC32_STP_CHOP_EN_MASK 0x1 |
| 5354 | #define MT6325_MIX_EOSC32_STP_CHOP_EN_SHIFT 0 |
| 5355 | #define MT6325_MIX_DCXO_STP_LVSH_EN_MASK 0x1 |
| 5356 | #define MT6325_MIX_DCXO_STP_LVSH_EN_SHIFT 1 |
| 5357 | #define MT6325_MIX_PMU_STP_DDLO_VRTC_MASK 0x1 |
| 5358 | #define MT6325_MIX_PMU_STP_DDLO_VRTC_SHIFT 2 |
| 5359 | #define MT6325_MIX_PMU_STP_DDLO_VRTC_EN_MASK 0x1 |
| 5360 | #define MT6325_MIX_PMU_STP_DDLO_VRTC_EN_SHIFT 3 |
| 5361 | #define MT6325_MIX_RTC_STP_XOSC32_ENB_MASK 0x1 |
| 5362 | #define MT6325_MIX_RTC_STP_XOSC32_ENB_SHIFT 4 |
| 5363 | #define MT6325_MIX_DCXO_STP_TEST_DEGLITCH_MODE_MASK 0x1 |
| 5364 | #define MT6325_MIX_DCXO_STP_TEST_DEGLITCH_MODE_SHIFT 5 |
| 5365 | #define MT6325_MIX_EOSC32_STP_RSV_MASK 0x3 |
| 5366 | #define MT6325_MIX_EOSC32_STP_RSV_SHIFT 6 |
| 5367 | #define MT6325_MIX_EOSC32_VCT_EN_MASK 0x1 |
| 5368 | #define MT6325_MIX_EOSC32_VCT_EN_SHIFT 8 |
| 5369 | #define MT6325_MIX_EOSC32_OPT_MASK 0x3 |
| 5370 | #define MT6325_MIX_EOSC32_OPT_SHIFT 9 |
| 5371 | #define MT6325_MIX_RTC_STP_DEBUG_OUT_MASK 0x3 |
| 5372 | #define MT6325_MIX_RTC_STP_DEBUG_OUT_SHIFT 0 |
| 5373 | #define MT6325_MIX_RTC_STP_DEBUG_SEL_MASK 0x3 |
| 5374 | #define MT6325_MIX_RTC_STP_DEBUG_SEL_SHIFT 4 |
| 5375 | #define MT6325_MIX_RTC_STP_K_EOSC32_EN_MASK 0x1 |
| 5376 | #define MT6325_MIX_RTC_STP_K_EOSC32_EN_SHIFT 7 |
| 5377 | #define MT6325_MIX_RTC_STP_EMBCK_SEL_MASK 0x1 |
| 5378 | #define MT6325_MIX_RTC_STP_EMBCK_SEL_SHIFT 8 |
| 5379 | #define MT6325_MIX_STP_BBWAKEUP_MASK 0x1 |
| 5380 | #define MT6325_MIX_STP_BBWAKEUP_SHIFT 9 |
| 5381 | #define MT6325_MIX_STP_RTC_DDLO_MASK 0x1 |
| 5382 | #define MT6325_MIX_STP_RTC_DDLO_SHIFT 10 |
| 5383 | #define MT6325_MIX_RTC_XOSC32_ENB_MASK 0x1 |
| 5384 | #define MT6325_MIX_RTC_XOSC32_ENB_SHIFT 11 |
| 5385 | #define MT6325_MIX_EFUSE_XOSC32_ENB_OPT_MASK 0x1 |
| 5386 | #define MT6325_MIX_EFUSE_XOSC32_ENB_OPT_SHIFT 12 |
| 5387 | #define MT6325_FG_ON_MASK 0x1 |
| 5388 | #define MT6325_FG_ON_SHIFT 0 |
| 5389 | #define MT6325_FG_CAL_MASK 0x3 |
| 5390 | #define MT6325_FG_CAL_SHIFT 2 |
| 5391 | #define MT6325_FG_AUTOCALRATE_MASK 0x7 |
| 5392 | #define MT6325_FG_AUTOCALRATE_SHIFT 4 |
| 5393 | #define MT6325_FG_SW_CR_MASK 0x1 |
| 5394 | #define MT6325_FG_SW_CR_SHIFT 8 |
| 5395 | #define MT6325_FG_SW_READ_PRE_MASK 0x1 |
| 5396 | #define MT6325_FG_SW_READ_PRE_SHIFT 9 |
| 5397 | #define MT6325_FG_LATCHDATA_ST_MASK 0x1 |
| 5398 | #define MT6325_FG_LATCHDATA_ST_SHIFT 10 |
| 5399 | #define MT6325_FG_SW_CLEAR_MASK 0x1 |
| 5400 | #define MT6325_FG_SW_CLEAR_SHIFT 11 |
| 5401 | #define MT6325_FG_OFFSET_RST_MASK 0x1 |
| 5402 | #define MT6325_FG_OFFSET_RST_SHIFT 12 |
| 5403 | #define MT6325_FG_TIME_RST_MASK 0x1 |
| 5404 | #define MT6325_FG_TIME_RST_SHIFT 13 |
| 5405 | #define MT6325_FG_CHARGE_RST_MASK 0x1 |
| 5406 | #define MT6325_FG_CHARGE_RST_SHIFT 14 |
| 5407 | #define MT6325_FG_SW_RSTCLR_MASK 0x1 |
| 5408 | #define MT6325_FG_SW_RSTCLR_SHIFT 15 |
| 5409 | #define MT6325_FG_CAR_31_16_MASK 0xFFFF |
| 5410 | #define MT6325_FG_CAR_31_16_SHIFT 0 |
| 5411 | #define MT6325_FG_CAR_15_00_MASK 0xFFFF |
| 5412 | #define MT6325_FG_CAR_15_00_SHIFT 0 |
| 5413 | #define MT6325_FG_NTER_29_16_MASK 0x3FFF |
| 5414 | #define MT6325_FG_NTER_29_16_SHIFT 0 |
| 5415 | #define MT6325_FG_NTER_15_00_MASK 0xFFFF |
| 5416 | #define MT6325_FG_NTER_15_00_SHIFT 0 |
| 5417 | #define MT6325_FG_BLTR_MASK 0xFFFF |
| 5418 | #define MT6325_FG_BLTR_SHIFT 0 |
| 5419 | #define MT6325_FG_BFTR_MASK 0xFFFF |
| 5420 | #define MT6325_FG_BFTR_SHIFT 0 |
| 5421 | #define MT6325_FG_CURRENT_OUT_MASK 0xFFFF |
| 5422 | #define MT6325_FG_CURRENT_OUT_SHIFT 0 |
| 5423 | #define MT6325_FG_ADJUST_OFFSET_VALUE_MASK 0xFFFF |
| 5424 | #define MT6325_FG_ADJUST_OFFSET_VALUE_SHIFT 0 |
| 5425 | #define MT6325_FG_OFFSET_MASK 0xFFFF |
| 5426 | #define MT6325_FG_OFFSET_SHIFT 0 |
| 5427 | #define MT6325_RG_FGRINTMODE_MASK 0x1 |
| 5428 | #define MT6325_RG_FGRINTMODE_SHIFT 0 |
| 5429 | #define MT6325_RG_FGANALOGTEST_MASK 0xF |
| 5430 | #define MT6325_RG_FGANALOGTEST_SHIFT 4 |
| 5431 | #define MT6325_RG_SPARE_MASK 0xFF |
| 5432 | #define MT6325_RG_SPARE_SHIFT 8 |
| 5433 | #define MT6325_FG_OSR_MASK 0xF |
| 5434 | #define MT6325_FG_OSR_SHIFT 0 |
| 5435 | #define MT6325_FG_ADJ_OFFSET_EN_MASK 0x1 |
| 5436 | #define MT6325_FG_ADJ_OFFSET_EN_SHIFT 8 |
| 5437 | #define MT6325_FG_ADC_AUTORST_MASK 0x1 |
| 5438 | #define MT6325_FG_ADC_AUTORST_SHIFT 9 |
| 5439 | #define MT6325_FG_FIR1BYPASS_MASK 0x1 |
| 5440 | #define MT6325_FG_FIR1BYPASS_SHIFT 0 |
| 5441 | #define MT6325_FG_FIR2BYPASS_MASK 0x1 |
| 5442 | #define MT6325_FG_FIR2BYPASS_SHIFT 1 |
| 5443 | #define MT6325_FG_L_CUR_INT_STS_MASK 0x1 |
| 5444 | #define MT6325_FG_L_CUR_INT_STS_SHIFT 2 |
| 5445 | #define MT6325_FG_H_CUR_INT_STS_MASK 0x1 |
| 5446 | #define MT6325_FG_H_CUR_INT_STS_SHIFT 3 |
| 5447 | #define MT6325_FG_L_INT_STS_MASK 0x1 |
| 5448 | #define MT6325_FG_L_INT_STS_SHIFT 4 |
| 5449 | #define MT6325_FG_H_INT_STS_MASK 0x1 |
| 5450 | #define MT6325_FG_H_INT_STS_SHIFT 5 |
| 5451 | #define MT6325_FG_ADC_RSTDETECT_MASK 0x1 |
| 5452 | #define MT6325_FG_ADC_RSTDETECT_SHIFT 7 |
| 5453 | #define MT6325_FG_SLP_EN_MASK 0x1 |
| 5454 | #define MT6325_FG_SLP_EN_SHIFT 8 |
| 5455 | #define MT6325_FG_ZCV_DET_EN_MASK 0x1 |
| 5456 | #define MT6325_FG_ZCV_DET_EN_SHIFT 9 |
| 5457 | #define MT6325_RG_FG_AUXADC_R_MASK 0x1 |
| 5458 | #define MT6325_RG_FG_AUXADC_R_SHIFT 10 |
| 5459 | #define MT6325_FGADC_EN_MASK 0x1 |
| 5460 | #define MT6325_FGADC_EN_SHIFT 12 |
| 5461 | #define MT6325_FGCAL_EN_MASK 0x1 |
| 5462 | #define MT6325_FGCAL_EN_SHIFT 13 |
| 5463 | #define MT6325_FG_RST_MASK 0x1 |
| 5464 | #define MT6325_FG_RST_SHIFT 14 |
| 5465 | #define MT6325_FG_CIC2_MASK 0xFFFF |
| 5466 | #define MT6325_FG_CIC2_SHIFT 0 |
| 5467 | #define MT6325_FG_SLP_CUR_TH_MASK 0xFFFF |
| 5468 | #define MT6325_FG_SLP_CUR_TH_SHIFT 0 |
| 5469 | #define MT6325_FG_SLP_TIME_MASK 0xFF |
| 5470 | #define MT6325_FG_SLP_TIME_SHIFT 0 |
| 5471 | #define MT6325_FG_SRCVOLTEN_FTIME_MASK 0xFF |
| 5472 | #define MT6325_FG_SRCVOLTEN_FTIME_SHIFT 0 |
| 5473 | #define MT6325_FG_DET_TIME_MASK 0xFF |
| 5474 | #define MT6325_FG_DET_TIME_SHIFT 8 |
| 5475 | #define MT6325_FG_ZCV_CAR_31_16_MASK 0xFFFF |
| 5476 | #define MT6325_FG_ZCV_CAR_31_16_SHIFT 0 |
| 5477 | #define MT6325_FG_ZCV_CAR_15_00_MASK 0xFFFF |
| 5478 | #define MT6325_FG_ZCV_CAR_15_00_SHIFT 0 |
| 5479 | #define MT6325_FG_ZCV_CURR_MASK 0xFFFF |
| 5480 | #define MT6325_FG_ZCV_CURR_SHIFT 0 |
| 5481 | #define MT6325_FG_R_CURR_MASK 0xFFFF |
| 5482 | #define MT6325_FG_R_CURR_SHIFT 0 |
| 5483 | #define MT6325_FG_MODE_MASK 0x1 |
| 5484 | #define MT6325_FG_MODE_SHIFT 0 |
| 5485 | #define MT6325_FG_RST_SW_MASK 0x1 |
| 5486 | #define MT6325_FG_RST_SW_SHIFT 1 |
| 5487 | #define MT6325_FG_FGCAL_EN_SW_MASK 0x1 |
| 5488 | #define MT6325_FG_FGCAL_EN_SW_SHIFT 2 |
| 5489 | #define MT6325_FG_FGADC_EN_SW_MASK 0x1 |
| 5490 | #define MT6325_FG_FGADC_EN_SW_SHIFT 3 |
| 5491 | #define MT6325_FG_RSV1_MASK 0xF |
| 5492 | #define MT6325_FG_RSV1_SHIFT 4 |
| 5493 | #define MT6325_FG_TEST_MODE0_MASK 0x1 |
| 5494 | #define MT6325_FG_TEST_MODE0_SHIFT 14 |
| 5495 | #define MT6325_FG_TEST_MODE1_MASK 0x1 |
| 5496 | #define MT6325_FG_TEST_MODE1_SHIFT 15 |
| 5497 | #define MT6325_FG_GAIN_MASK 0x1FFF |
| 5498 | #define MT6325_FG_GAIN_SHIFT 0 |
| 5499 | #define MT6325_FG_CUR_HTH_MASK 0xFFFF |
| 5500 | #define MT6325_FG_CUR_HTH_SHIFT 0 |
| 5501 | #define MT6325_FG_CUR_LTH_MASK 0xFFFF |
| 5502 | #define MT6325_FG_CUR_LTH_SHIFT 0 |
| 5503 | #define MT6325_FG_ZCV_DET_TIME_MASK 0x3F |
| 5504 | #define MT6325_FG_ZCV_DET_TIME_SHIFT 0 |
| 5505 | #define MT6325_FG_ZCV_CAR_TH_30_16_MASK 0x7FFF |
| 5506 | #define MT6325_FG_ZCV_CAR_TH_30_16_SHIFT 0 |
| 5507 | #define MT6325_FG_ZCV_CAR_TH_15_00_MASK 0xFFFF |
| 5508 | #define MT6325_FG_ZCV_CAR_TH_15_00_SHIFT 0 |
| 5509 | #define MT6325_RG_FGINTMODE_MASK 0x1 |
| 5510 | #define MT6325_RG_FGINTMODE_SHIFT 4 |
| 5511 | #define MT6325_RG_AUDDACLPWRUP_VAUDP15_MASK 0x1 |
| 5512 | #define MT6325_RG_AUDDACLPWRUP_VAUDP15_SHIFT 0 |
| 5513 | #define MT6325_RG_AUDDACRPWRUP_VAUDP15_MASK 0x1 |
| 5514 | #define MT6325_RG_AUDDACRPWRUP_VAUDP15_SHIFT 1 |
| 5515 | #define MT6325_RG_AUD_DAC_PWR_UP_VA28_MASK 0x1 |
| 5516 | #define MT6325_RG_AUD_DAC_PWR_UP_VA28_SHIFT 2 |
| 5517 | #define MT6325_RG_AUD_DAC_PWL_UP_VA28_MASK 0x1 |
| 5518 | #define MT6325_RG_AUD_DAC_PWL_UP_VA28_SHIFT 3 |
| 5519 | #define MT6325_RG_AUDHSPWRUP_VAUDP15_MASK 0x1 |
| 5520 | #define MT6325_RG_AUDHSPWRUP_VAUDP15_SHIFT 4 |
| 5521 | #define MT6325_RG_AUDHPLPWRUP_VAUDP15_MASK 0x1 |
| 5522 | #define MT6325_RG_AUDHPLPWRUP_VAUDP15_SHIFT 5 |
| 5523 | #define MT6325_RG_AUDHPRPWRUP_VAUDP15_MASK 0x1 |
| 5524 | #define MT6325_RG_AUDHPRPWRUP_VAUDP15_SHIFT 6 |
| 5525 | #define MT6325_RG_AUDHSMUXINPUTSEL_VAUDP15_MASK 0x3 |
| 5526 | #define MT6325_RG_AUDHSMUXINPUTSEL_VAUDP15_SHIFT 7 |
| 5527 | #define MT6325_RG_AUDHPLMUXINPUTSEL_VAUDP15_MASK 0x3 |
| 5528 | #define MT6325_RG_AUDHPLMUXINPUTSEL_VAUDP15_SHIFT 9 |
| 5529 | #define MT6325_RG_AUDHPRMUXINPUTSEL_VAUDP15_MASK 0x3 |
| 5530 | #define MT6325_RG_AUDHPRMUXINPUTSEL_VAUDP15_SHIFT 11 |
| 5531 | #define MT6325_RG_AUDHSSCDISABLE_VAUDP15_MASK 0x1 |
| 5532 | #define MT6325_RG_AUDHSSCDISABLE_VAUDP15_SHIFT 13 |
| 5533 | #define MT6325_RG_AUDHPLSCDISABLE_VAUDP15_MASK 0x1 |
| 5534 | #define MT6325_RG_AUDHPLSCDISABLE_VAUDP15_SHIFT 14 |
| 5535 | #define MT6325_RG_AUDHPRSCDISABLE_VAUDP15_MASK 0x1 |
| 5536 | #define MT6325_RG_AUDHPRSCDISABLE_VAUDP15_SHIFT 15 |
| 5537 | #define MT6325_RG_AUDHPLBSCCURRENT_VAUDP15_MASK 0x1 |
| 5538 | #define MT6325_RG_AUDHPLBSCCURRENT_VAUDP15_SHIFT 0 |
| 5539 | #define MT6325_RG_AUDHPRBSCCURRENT_VAUDP15_MASK 0x1 |
| 5540 | #define MT6325_RG_AUDHPRBSCCURRENT_VAUDP15_SHIFT 1 |
| 5541 | #define MT6325_RG_AUDHSBSCCURRENT_VAUDP15_MASK 0x1 |
| 5542 | #define MT6325_RG_AUDHSBSCCURRENT_VAUDP15_SHIFT 2 |
| 5543 | #define MT6325_RG_AUDHPSTARTUP_VAUDP15_MASK 0x1 |
| 5544 | #define MT6325_RG_AUDHPSTARTUP_VAUDP15_SHIFT 3 |
| 5545 | #define MT6325_RG_AUDHSSTARTUP_VAUDP15_MASK 0x1 |
| 5546 | #define MT6325_RG_AUDHSSTARTUP_VAUDP15_SHIFT 4 |
| 5547 | #define MT6325_RG_PRECHARGEBUF_EN_VAUDP15_MASK 0x1 |
| 5548 | #define MT6325_RG_PRECHARGEBUF_EN_VAUDP15_SHIFT 5 |
| 5549 | #define MT6325_RG_HPINPUTSTBENH_VAUDP15_MASK 0x1 |
| 5550 | #define MT6325_RG_HPINPUTSTBENH_VAUDP15_SHIFT 6 |
| 5551 | #define MT6325_RG_HPOUTPUTSTBENH_VAUDP15_MASK 0x1 |
| 5552 | #define MT6325_RG_HPOUTPUTSTBENH_VAUDP15_SHIFT 7 |
| 5553 | #define MT6325_RG_HPINPUTRESET0_VAUDP15_MASK 0x1 |
| 5554 | #define MT6325_RG_HPINPUTRESET0_VAUDP15_SHIFT 8 |
| 5555 | #define MT6325_RG_HPOUTPUTRESET0_VAUDP15_MASK 0x1 |
| 5556 | #define MT6325_RG_HPOUTPUTRESET0_VAUDP15_SHIFT 9 |
| 5557 | #define MT6325_RG_HPOUT_SHORTVCM_VAUDP15_MASK 0x1 |
| 5558 | #define MT6325_RG_HPOUT_SHORTVCM_VAUDP15_SHIFT 10 |
| 5559 | #define MT6325_RG_HSINPUTSTBENH_VAUDP15_MASK 0x1 |
| 5560 | #define MT6325_RG_HSINPUTSTBENH_VAUDP15_SHIFT 11 |
| 5561 | #define MT6325_RG_HSOUTPUTSTBENH_VAUDP15_MASK 0x1 |
| 5562 | #define MT6325_RG_HSOUTPUTSTBENH_VAUDP15_SHIFT 12 |
| 5563 | #define MT6325_RG_HSINPUTRESET0_VAUDP15_MASK 0x1 |
| 5564 | #define MT6325_RG_HSINPUTRESET0_VAUDP15_SHIFT 13 |
| 5565 | #define MT6325_RG_HSOUTPUTRESET0_VAUDP15_MASK 0x1 |
| 5566 | #define MT6325_RG_HSOUTPUTRESET0_VAUDP15_SHIFT 14 |
| 5567 | #define MT6325_RG_HPOUTSTB_RSEL_VAUDP15_MASK 0x3 |
| 5568 | #define MT6325_RG_HPOUTSTB_RSEL_VAUDP15_SHIFT 0 |
| 5569 | #define MT6325_RG_HSOUT_SHORTVCM_VAUDP15_MASK 0x1 |
| 5570 | #define MT6325_RG_HSOUT_SHORTVCM_VAUDP15_SHIFT 2 |
| 5571 | #define MT6325_RG_AUDHPLTRIM_VAUDP15_MASK 0xF |
| 5572 | #define MT6325_RG_AUDHPLTRIM_VAUDP15_SHIFT 3 |
| 5573 | #define MT6325_RG_AUDHPRTRIM_VAUDP15_MASK 0xF |
| 5574 | #define MT6325_RG_AUDHPRTRIM_VAUDP15_SHIFT 7 |
| 5575 | #define MT6325_RG_AUDHPTRIM_EN_VAUDP15_MASK 0x1 |
| 5576 | #define MT6325_RG_AUDHPTRIM_EN_VAUDP15_SHIFT 11 |
| 5577 | #define MT6325_RG_AUDHPLFINETRIM_VAUDP15_MASK 0x3 |
| 5578 | #define MT6325_RG_AUDHPLFINETRIM_VAUDP15_SHIFT 12 |
| 5579 | #define MT6325_RG_AUDHPRFINETRIM_VAUDP15_MASK 0x3 |
| 5580 | #define MT6325_RG_AUDHPRFINETRIM_VAUDP15_SHIFT 14 |
| 5581 | #define MT6325_RG_AUDTRIMBUF_EN_VAUDP15_MASK 0x1 |
| 5582 | #define MT6325_RG_AUDTRIMBUF_EN_VAUDP15_SHIFT 0 |
| 5583 | #define MT6325_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK 0xF |
| 5584 | #define MT6325_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_SHIFT 1 |
| 5585 | #define MT6325_RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK 0x3 |
| 5586 | #define MT6325_RG_AUDTRIMBUF_GAINSEL_VAUDP15_SHIFT 5 |
| 5587 | #define MT6325_RG_AUDHPSPKDET_EN_VAUDP15_MASK 0x1 |
| 5588 | #define MT6325_RG_AUDHPSPKDET_EN_VAUDP15_SHIFT 7 |
| 5589 | #define MT6325_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK 0x3 |
| 5590 | #define MT6325_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_SHIFT 8 |
| 5591 | #define MT6325_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK 0x3 |
| 5592 | #define MT6325_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_SHIFT 10 |
| 5593 | #define MT6325_RG_ABIDEC_RESERVED_VA28_MASK 0xFF |
| 5594 | #define MT6325_RG_ABIDEC_RESERVED_VA28_SHIFT 0 |
| 5595 | #define MT6325_RG_ABIDEC_RESERVED_VAUDP15_MASK 0xFF |
| 5596 | #define MT6325_RG_ABIDEC_RESERVED_VAUDP15_SHIFT 8 |
| 5597 | #define MT6325_RG_AUDBIASADJ_0_VAUDP15_MASK 0x3F |
| 5598 | #define MT6325_RG_AUDBIASADJ_0_VAUDP15_SHIFT 4 |
| 5599 | #define MT6325_RG_AUDBIASADJ_1_VAUDP15_MASK 0x3F |
| 5600 | #define MT6325_RG_AUDBIASADJ_1_VAUDP15_SHIFT 10 |
| 5601 | #define MT6325_RG_AUDIBIASPWRDN_VAUDP15_MASK 0x1 |
| 5602 | #define MT6325_RG_AUDIBIASPWRDN_VAUDP15_SHIFT 0 |
| 5603 | #define MT6325_RG_RSTB_DECODER_VA28_MASK 0x1 |
| 5604 | #define MT6325_RG_RSTB_DECODER_VA28_SHIFT 1 |
| 5605 | #define MT6325_RG_RSTB_ENCODER_VA28_MASK 0x1 |
| 5606 | #define MT6325_RG_RSTB_ENCODER_VA28_SHIFT 2 |
| 5607 | #define MT6325_RG_SEL_DECODER_96K_VA28_MASK 0x1 |
| 5608 | #define MT6325_RG_SEL_DECODER_96K_VA28_SHIFT 3 |
| 5609 | #define MT6325_RG_SEL_ENCODER_96K_VA28_MASK 0x1 |
| 5610 | #define MT6325_RG_SEL_ENCODER_96K_VA28_SHIFT 4 |
| 5611 | #define MT6325_RG_SEL_DELAY_VCORE_MASK 0x1 |
| 5612 | #define MT6325_RG_SEL_DELAY_VCORE_SHIFT 5 |
| 5613 | #define MT6325_RG_HCLDO_EN_VA18_MASK 0x1 |
| 5614 | #define MT6325_RG_HCLDO_EN_VA18_SHIFT 6 |
| 5615 | #define MT6325_RG_LCLDO_EN_VA18_MASK 0x1 |
| 5616 | #define MT6325_RG_LCLDO_EN_VA18_SHIFT 7 |
| 5617 | #define MT6325_RG_LCLDO_ENC_EN_VA28_MASK 0x1 |
| 5618 | #define MT6325_RG_LCLDO_ENC_EN_VA28_SHIFT 8 |
| 5619 | #define MT6325_RG_VA33REFGEN_EN_VA18_MASK 0x1 |
| 5620 | #define MT6325_RG_VA33REFGEN_EN_VA18_SHIFT 9 |
| 5621 | #define MT6325_RG_HCLDO_PDDIS_EN_VA18_MASK 0x1 |
| 5622 | #define MT6325_RG_HCLDO_PDDIS_EN_VA18_SHIFT 10 |
| 5623 | #define MT6325_RG_HCLDO_REMOTE_SENSE_VA18_MASK 0x1 |
| 5624 | #define MT6325_RG_HCLDO_REMOTE_SENSE_VA18_SHIFT 11 |
| 5625 | #define MT6325_RG_LCLDO_PDDIS_EN_VA18_MASK 0x1 |
| 5626 | #define MT6325_RG_LCLDO_PDDIS_EN_VA18_SHIFT 12 |
| 5627 | #define MT6325_RG_LCLDO_REMOTE_SENSE_VA18_MASK 0x1 |
| 5628 | #define MT6325_RG_LCLDO_REMOTE_SENSE_VA18_SHIFT 13 |
| 5629 | #define MT6325_RG_LCLDO_VOSEL_VA18_MASK 0x1 |
| 5630 | #define MT6325_RG_LCLDO_VOSEL_VA18_SHIFT 14 |
| 5631 | #define MT6325_RG_HCLDO_VOSEL_VA18_MASK 0x1 |
| 5632 | #define MT6325_RG_HCLDO_VOSEL_VA18_SHIFT 15 |
| 5633 | #define MT6325_RG_LCLDO_ENC_PDDIS_EN_VA28_MASK 0x1 |
| 5634 | #define MT6325_RG_LCLDO_ENC_PDDIS_EN_VA28_SHIFT 0 |
| 5635 | #define MT6325_RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK 0x1 |
| 5636 | #define MT6325_RG_LCLDO_ENC_REMOTE_SENSE_VA28_SHIFT 1 |
| 5637 | #define MT6325_RG_VA28REFGEN_EN_VA28_MASK 0x1 |
| 5638 | #define MT6325_RG_VA28REFGEN_EN_VA28_SHIFT 2 |
| 5639 | #define MT6325_RG_AUDPMU_RESERVED_VA28_MASK 0xF |
| 5640 | #define MT6325_RG_AUDPMU_RESERVED_VA28_SHIFT 3 |
| 5641 | #define MT6325_RG_AUDPMU_RESERVED_VA18_MASK 0xF |
| 5642 | #define MT6325_RG_AUDPMU_RESERVED_VA18_SHIFT 7 |
| 5643 | #define MT6325_RG_AUDPMU_RESERVED_VAUDP15_MASK 0xF |
| 5644 | #define MT6325_RG_AUDPMU_RESERVED_VAUDP15_SHIFT 11 |
| 5645 | #define MT6325_RG_NVREG_EN_VAUDP15_MASK 0x1 |
| 5646 | #define MT6325_RG_NVREG_EN_VAUDP15_SHIFT 15 |
| 5647 | #define MT6325_RG_NVREG_PULL0V_VAUDP15_MASK 0x1 |
| 5648 | #define MT6325_RG_NVREG_PULL0V_VAUDP15_SHIFT 0 |
| 5649 | #define MT6325_RG_AUDGLB_PWRDN_VA28_MASK 0x1 |
| 5650 | #define MT6325_RG_AUDGLB_PWRDN_VA28_SHIFT 1 |
| 5651 | #define MT6325_RG_AUDPREAMPLON_MASK 0x1 |
| 5652 | #define MT6325_RG_AUDPREAMPLON_SHIFT 0 |
| 5653 | #define MT6325_RG_AUDPREAMPLDCCEN_MASK 0x1 |
| 5654 | #define MT6325_RG_AUDPREAMPLDCCEN_SHIFT 1 |
| 5655 | #define MT6325_RG_AUDPREAMPLDCRPECHARGE_MASK 0x1 |
| 5656 | #define MT6325_RG_AUDPREAMPLDCRPECHARGE_SHIFT 2 |
| 5657 | #define MT6325_RG_AUDPREAMPLPGATEST_MASK 0x1 |
| 5658 | #define MT6325_RG_AUDPREAMPLPGATEST_SHIFT 3 |
| 5659 | #define MT6325_RG_AUDPREAMPLVSCALE_MASK 0x3 |
| 5660 | #define MT6325_RG_AUDPREAMPLVSCALE_SHIFT 4 |
| 5661 | #define MT6325_RG_AUDPREAMPLINPUTSEL_MASK 0x3 |
| 5662 | #define MT6325_RG_AUDPREAMPLINPUTSEL_SHIFT 6 |
| 5663 | #define MT6325_RG_AUDADCLPWRUP_MASK 0x1 |
| 5664 | #define MT6325_RG_AUDADCLPWRUP_SHIFT 8 |
| 5665 | #define MT6325_RG_AUDADCLINPUTSEL_MASK 0x3 |
| 5666 | #define MT6325_RG_AUDADCLINPUTSEL_SHIFT 9 |
| 5667 | #define MT6325_RG_AUDPREAMPRON_MASK 0x1 |
| 5668 | #define MT6325_RG_AUDPREAMPRON_SHIFT 0 |
| 5669 | #define MT6325_RG_AUDPREAMPRDCCEN_MASK 0x1 |
| 5670 | #define MT6325_RG_AUDPREAMPRDCCEN_SHIFT 1 |
| 5671 | #define MT6325_RG_AUDPREAMPRDCRPECHARGE_MASK 0x1 |
| 5672 | #define MT6325_RG_AUDPREAMPRDCRPECHARGE_SHIFT 2 |
| 5673 | #define MT6325_RG_AUDPREAMPRPGATEST_MASK 0x1 |
| 5674 | #define MT6325_RG_AUDPREAMPRPGATEST_SHIFT 3 |
| 5675 | #define MT6325_RG_AUDPREAMPRVSCALE_MASK 0x3 |
| 5676 | #define MT6325_RG_AUDPREAMPRVSCALE_SHIFT 4 |
| 5677 | #define MT6325_RG_AUDPREAMPRINPUTSEL_MASK 0x3 |
| 5678 | #define MT6325_RG_AUDPREAMPRINPUTSEL_SHIFT 6 |
| 5679 | #define MT6325_RG_AUDADCRPWRUP_MASK 0x1 |
| 5680 | #define MT6325_RG_AUDADCRPWRUP_SHIFT 8 |
| 5681 | #define MT6325_RG_AUDADCRINPUTSEL_MASK 0x3 |
| 5682 | #define MT6325_RG_AUDADCRINPUTSEL_SHIFT 9 |
| 5683 | #define MT6325_RG_AUDULHALFBIAS_MASK 0x1 |
| 5684 | #define MT6325_RG_AUDULHALFBIAS_SHIFT 0 |
| 5685 | #define MT6325_RG_AUDGLBVOWLPWEN_MASK 0x1 |
| 5686 | #define MT6325_RG_AUDGLBVOWLPWEN_SHIFT 1 |
| 5687 | #define MT6325_RG_AUDPREAMPLPEN_MASK 0x1 |
| 5688 | #define MT6325_RG_AUDPREAMPLPEN_SHIFT 2 |
| 5689 | #define MT6325_RG_AUDADC1STSTAGELPEN_MASK 0x1 |
| 5690 | #define MT6325_RG_AUDADC1STSTAGELPEN_SHIFT 3 |
| 5691 | #define MT6325_RG_AUDADC2NDSTAGELPEN_MASK 0x1 |
| 5692 | #define MT6325_RG_AUDADC2NDSTAGELPEN_SHIFT 4 |
| 5693 | #define MT6325_RG_AUDADCFLASHLPEN_MASK 0x1 |
| 5694 | #define MT6325_RG_AUDADCFLASHLPEN_SHIFT 5 |
| 5695 | #define MT6325_RG_AUDPREAMPIDDTEST_MASK 0x3 |
| 5696 | #define MT6325_RG_AUDPREAMPIDDTEST_SHIFT 6 |
| 5697 | #define MT6325_RG_AUDADC1STSTAGEIDDTEST_MASK 0x3 |
| 5698 | #define MT6325_RG_AUDADC1STSTAGEIDDTEST_SHIFT 8 |
| 5699 | #define MT6325_RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3 |
| 5700 | #define MT6325_RG_AUDADC2NDSTAGEIDDTEST_SHIFT 10 |
| 5701 | #define MT6325_RG_AUDADCREFBUFIDDTEST_MASK 0x3 |
| 5702 | #define MT6325_RG_AUDADCREFBUFIDDTEST_SHIFT 12 |
| 5703 | #define MT6325_RG_AUDADCFLASHIDDTEST_MASK 0x3 |
| 5704 | #define MT6325_RG_AUDADCFLASHIDDTEST_SHIFT 14 |
| 5705 | #define MT6325_RG_AUDADCDAC0P25FS_MASK 0x1 |
| 5706 | #define MT6325_RG_AUDADCDAC0P25FS_SHIFT 0 |
| 5707 | #define MT6325_RG_AUDADCCLKSEL_MASK 0x1 |
| 5708 | #define MT6325_RG_AUDADCCLKSEL_SHIFT 1 |
| 5709 | #define MT6325_RG_AUDADCCLKSOURCE_MASK 0x3 |
| 5710 | #define MT6325_RG_AUDADCCLKSOURCE_SHIFT 2 |
| 5711 | #define MT6325_RG_AUDADCCLKGENMODE_MASK 0x3 |
| 5712 | #define MT6325_RG_AUDADCCLKGENMODE_SHIFT 4 |
| 5713 | #define MT6325_RG_AUDPREAMPAAFEN_MASK 0x1 |
| 5714 | #define MT6325_RG_AUDPREAMPAAFEN_SHIFT 8 |
| 5715 | #define MT6325_RG_DCCVCMBUFLPMODSEL_MASK 0x1 |
| 5716 | #define MT6325_RG_DCCVCMBUFLPMODSEL_SHIFT 9 |
| 5717 | #define MT6325_RG_DCCVCMBUFLPSWEN_MASK 0x1 |
| 5718 | #define MT6325_RG_DCCVCMBUFLPSWEN_SHIFT 10 |
| 5719 | #define MT6325_RG_AUDSPAREPGA_MASK 0x1F |
| 5720 | #define MT6325_RG_AUDSPAREPGA_SHIFT 11 |
| 5721 | #define MT6325_RG_AUDADC1STSTAGESDENB_MASK 0x1 |
| 5722 | #define MT6325_RG_AUDADC1STSTAGESDENB_SHIFT 0 |
| 5723 | #define MT6325_RG_AUDADC2NDSTAGERESET_MASK 0x1 |
| 5724 | #define MT6325_RG_AUDADC2NDSTAGERESET_SHIFT 1 |
| 5725 | #define MT6325_RG_AUDADC3RDSTAGERESET_MASK 0x1 |
| 5726 | #define MT6325_RG_AUDADC3RDSTAGERESET_SHIFT 2 |
| 5727 | #define MT6325_RG_AUDADCFSRESET_MASK 0x1 |
| 5728 | #define MT6325_RG_AUDADCFSRESET_SHIFT 3 |
| 5729 | #define MT6325_RG_AUDADCWIDECM_MASK 0x1 |
| 5730 | #define MT6325_RG_AUDADCWIDECM_SHIFT 4 |
| 5731 | #define MT6325_RG_AUDADCNOPATEST_MASK 0x1 |
| 5732 | #define MT6325_RG_AUDADCNOPATEST_SHIFT 5 |
| 5733 | #define MT6325_RG_AUDADCBYPASS_MASK 0x1 |
| 5734 | #define MT6325_RG_AUDADCBYPASS_SHIFT 6 |
| 5735 | #define MT6325_RG_AUDADCFFBYPASS_MASK 0x1 |
| 5736 | #define MT6325_RG_AUDADCFFBYPASS_SHIFT 7 |
| 5737 | #define MT6325_RG_AUDADCDACFBCURRENT_MASK 0x1 |
| 5738 | #define MT6325_RG_AUDADCDACFBCURRENT_SHIFT 8 |
| 5739 | #define MT6325_RG_AUDADCDACIDDTEST_MASK 0x3 |
| 5740 | #define MT6325_RG_AUDADCDACIDDTEST_SHIFT 9 |
| 5741 | #define MT6325_RG_AUDADCDACNRZ_MASK 0x1 |
| 5742 | #define MT6325_RG_AUDADCDACNRZ_SHIFT 11 |
| 5743 | #define MT6325_RG_AUDADCNODEM_MASK 0x1 |
| 5744 | #define MT6325_RG_AUDADCNODEM_SHIFT 12 |
| 5745 | #define MT6325_RG_AUDADCDACTEST_MASK 0x1 |
| 5746 | #define MT6325_RG_AUDADCDACTEST_SHIFT 13 |
| 5747 | #define MT6325_RG_AUDADCTESTDATA_MASK 0xFFFF |
| 5748 | #define MT6325_RG_AUDADCTESTDATA_SHIFT 0 |
| 5749 | #define MT6325_RG_AUDRCTUNEL_MASK 0x1F |
| 5750 | #define MT6325_RG_AUDRCTUNEL_SHIFT 0 |
| 5751 | #define MT6325_RG_AUDRCTUNELSEL_MASK 0x1 |
| 5752 | #define MT6325_RG_AUDRCTUNELSEL_SHIFT 5 |
| 5753 | #define MT6325_RG_AUDRCTUNER_MASK 0x1F |
| 5754 | #define MT6325_RG_AUDRCTUNER_SHIFT 8 |
| 5755 | #define MT6325_RG_AUDRCTUNERSEL_MASK 0x1 |
| 5756 | #define MT6325_RG_AUDRCTUNERSEL_SHIFT 13 |
| 5757 | #define MT6325_RG_AUDSPAREVA28_MASK 0xFF |
| 5758 | #define MT6325_RG_AUDSPAREVA28_SHIFT 0 |
| 5759 | #define MT6325_RG_AUDSPAREVA18_MASK 0xFF |
| 5760 | #define MT6325_RG_AUDSPAREVA18_SHIFT 8 |
| 5761 | #define MT6325_RG_AUDDIGMICEN_MASK 0x1 |
| 5762 | #define MT6325_RG_AUDDIGMICEN_SHIFT 0 |
| 5763 | #define MT6325_RG_AUDDIGMICBIAS_MASK 0x3 |
| 5764 | #define MT6325_RG_AUDDIGMICBIAS_SHIFT 1 |
| 5765 | #define MT6325_RG_DMICHPCLKEN_MASK 0x1 |
| 5766 | #define MT6325_RG_DMICHPCLKEN_SHIFT 3 |
| 5767 | #define MT6325_RG_AUDDIGMICPDUTY_MASK 0x3 |
| 5768 | #define MT6325_RG_AUDDIGMICPDUTY_SHIFT 4 |
| 5769 | #define MT6325_RG_AUDDIGMICNDUTY_MASK 0x3 |
| 5770 | #define MT6325_RG_AUDDIGMICNDUTY_SHIFT 6 |
| 5771 | #define MT6325_RG_DMICMONEN_MASK 0x1 |
| 5772 | #define MT6325_RG_DMICMONEN_SHIFT 8 |
| 5773 | #define MT6325_RG_DMICMONSEL_MASK 0x7 |
| 5774 | #define MT6325_RG_DMICMONSEL_SHIFT 9 |
| 5775 | #define MT6325_RG_AUDSPAREVMIC_MASK 0xF |
| 5776 | #define MT6325_RG_AUDSPAREVMIC_SHIFT 12 |
| 5777 | #define MT6325_RG_AUDPWDBMICBIAS0_MASK 0x1 |
| 5778 | #define MT6325_RG_AUDPWDBMICBIAS0_SHIFT 0 |
| 5779 | #define MT6325_RG_AUDMICBIAS0DCSWPEN_MASK 0x1 |
| 5780 | #define MT6325_RG_AUDMICBIAS0DCSWPEN_SHIFT 1 |
| 5781 | #define MT6325_RG_AUDMICBIAS0DCSWNEN_MASK 0x1 |
| 5782 | #define MT6325_RG_AUDMICBIAS0DCSWNEN_SHIFT 2 |
| 5783 | #define MT6325_RG_AUDMICBIAS0BYPASSEN_MASK 0x1 |
| 5784 | #define MT6325_RG_AUDMICBIAS0BYPASSEN_SHIFT 3 |
| 5785 | #define MT6325_RG_AUDPWDBMICBIAS1_MASK 0x1 |
| 5786 | #define MT6325_RG_AUDPWDBMICBIAS1_SHIFT 4 |
| 5787 | #define MT6325_RG_AUDMICBIAS1DCSWPEN_MASK 0x1 |
| 5788 | #define MT6325_RG_AUDMICBIAS1DCSWPEN_SHIFT 5 |
| 5789 | #define MT6325_RG_AUDMICBIAS1DCSWNEN_MASK 0x1 |
| 5790 | #define MT6325_RG_AUDMICBIAS1DCSWNEN_SHIFT 6 |
| 5791 | #define MT6325_RG_AUDMICBIAS1BYPASSEN_MASK 0x1 |
| 5792 | #define MT6325_RG_AUDMICBIAS1BYPASSEN_SHIFT 7 |
| 5793 | #define MT6325_RG_AUDMICBIASVREF_MASK 0x7 |
| 5794 | #define MT6325_RG_AUDMICBIASVREF_SHIFT 8 |
| 5795 | #define MT6325_RG_AUDMICBIASLOWPEN_MASK 0x1 |
| 5796 | #define MT6325_RG_AUDMICBIASLOWPEN_SHIFT 11 |
| 5797 | #define MT6325_RG_BANDGAPGEN_MASK 0x1 |
| 5798 | #define MT6325_RG_BANDGAPGEN_SHIFT 12 |
| 5799 | #define MT6325_RG_AUDENCSPAREVA28_MASK 0xFF |
| 5800 | #define MT6325_RG_AUDENCSPAREVA28_SHIFT 0 |
| 5801 | #define MT6325_RG_AUDENCSPAREVA18_MASK 0xFF |
| 5802 | #define MT6325_RG_AUDENCSPAREVA18_SHIFT 8 |
| 5803 | #define MT6325_RG_PLL_EN_MASK 0x1 |
| 5804 | #define MT6325_RG_PLL_EN_SHIFT 0 |
| 5805 | #define MT6325_RG_PLLBS_RST_MASK 0x1 |
| 5806 | #define MT6325_RG_PLLBS_RST_SHIFT 1 |
| 5807 | #define MT6325_RG_PLL_DCKO_SEL_MASK 0x3 |
| 5808 | #define MT6325_RG_PLL_DCKO_SEL_SHIFT 2 |
| 5809 | #define MT6325_RG_PLL_DIV1_MASK 0x3F |
| 5810 | #define MT6325_RG_PLL_DIV1_SHIFT 4 |
| 5811 | #define MT6325_RG_PLL_RLATCH_EN_MASK 0x1 |
| 5812 | #define MT6325_RG_PLL_RLATCH_EN_SHIFT 10 |
| 5813 | #define MT6325_RG_PLL_PDIV1_EN_MASK 0x1 |
| 5814 | #define MT6325_RG_PLL_PDIV1_EN_SHIFT 11 |
| 5815 | #define MT6325_RG_PLL_PDIV1_MASK 0xF |
| 5816 | #define MT6325_RG_PLL_PDIV1_SHIFT 12 |
| 5817 | #define MT6325_RG_PLL_BC_MASK 0x3 |
| 5818 | #define MT6325_RG_PLL_BC_SHIFT 0 |
| 5819 | #define MT6325_RG_PLL_BP_MASK 0x3 |
| 5820 | #define MT6325_RG_PLL_BP_SHIFT 2 |
| 5821 | #define MT6325_RG_PLL_BR_MASK 0x3 |
| 5822 | #define MT6325_RG_PLL_BR_SHIFT 4 |
| 5823 | #define MT6325_RG_CKO_SEL_MASK 0x3 |
| 5824 | #define MT6325_RG_CKO_SEL_SHIFT 6 |
| 5825 | #define MT6325_RG_PLL_IBSEL_MASK 0x3 |
| 5826 | #define MT6325_RG_PLL_IBSEL_SHIFT 8 |
| 5827 | #define MT6325_RG_PLL_CKT_SEL_MASK 0x3 |
| 5828 | #define MT6325_RG_PLL_CKT_SEL_SHIFT 10 |
| 5829 | #define MT6325_RG_PLL_VCT_EN_MASK 0x1 |
| 5830 | #define MT6325_RG_PLL_VCT_EN_SHIFT 12 |
| 5831 | #define MT6325_RG_PLL_CKT_EN_MASK 0x1 |
| 5832 | #define MT6325_RG_PLL_CKT_EN_SHIFT 13 |
| 5833 | #define MT6325_RG_PLL_HPM_EN_MASK 0x1 |
| 5834 | #define MT6325_RG_PLL_HPM_EN_SHIFT 14 |
| 5835 | #define MT6325_RG_PLL_DCHP_EN_MASK 0x1 |
| 5836 | #define MT6325_RG_PLL_DCHP_EN_SHIFT 15 |
| 5837 | #define MT6325_RG_PLL_CDIV_MASK 0x7 |
| 5838 | #define MT6325_RG_PLL_CDIV_SHIFT 0 |
| 5839 | #define MT6325_RG_VCOBAND_MASK 0x7 |
| 5840 | #define MT6325_RG_VCOBAND_SHIFT 3 |
| 5841 | #define MT6325_RG_CKDRV_EN_MASK 0x1 |
| 5842 | #define MT6325_RG_CKDRV_EN_SHIFT 6 |
| 5843 | #define MT6325_RG_PLL_DCHP_AEN_MASK 0x1 |
| 5844 | #define MT6325_RG_PLL_DCHP_AEN_SHIFT 7 |
| 5845 | #define MT6325_RG_PLL_RSVA_MASK 0xFF |
| 5846 | #define MT6325_RG_PLL_RSVA_SHIFT 8 |
| 5847 | #define MT6325_RG_AUDPREAMPLGAIN_MASK 0x7 |
| 5848 | #define MT6325_RG_AUDPREAMPLGAIN_SHIFT 0 |
| 5849 | #define MT6325_RG_AUDPREAMPRGAIN_MASK 0x7 |
| 5850 | #define MT6325_RG_AUDPREAMPRGAIN_SHIFT 4 |
| 5851 | #define MT6325_RG_DIVCKS_CHG_MASK 0x1 |
| 5852 | #define MT6325_RG_DIVCKS_CHG_SHIFT 0 |
| 5853 | #define MT6325_RG_DIVCKS_ON_MASK 0x1 |
| 5854 | #define MT6325_RG_DIVCKS_ON_SHIFT 0 |
| 5855 | #define MT6325_RG_DIVCKS_PRG_MASK 0x1FF |
| 5856 | #define MT6325_RG_DIVCKS_PRG_SHIFT 0 |
| 5857 | #define MT6325_RG_DIVCKS_PWD_NCP_MASK 0x1 |
| 5858 | #define MT6325_RG_DIVCKS_PWD_NCP_SHIFT 0 |
| 5859 | #define MT6325_RG_DIVCKS_PWD_NCP_ST_SEL_MASK 0x3 |
| 5860 | #define MT6325_RG_DIVCKS_PWD_NCP_ST_SEL_SHIFT 0 |
| 5861 | #define MT6325_AUXADC_DIG0_RSV0_MASK 0xFFFF |
| 5862 | #define MT6325_AUXADC_DIG0_RSV0_SHIFT 0 |
| 5863 | #define MT6325_AUXADC_ADC_BUSY_IN_MASK 0x1FFF |
| 5864 | #define MT6325_AUXADC_ADC_BUSY_IN_SHIFT 0 |
| 5865 | #define MT6325_AUXADC_ADC_BUSY_IN_WAKEUP_PCHR_MASK 0x1 |
| 5866 | #define MT6325_AUXADC_ADC_BUSY_IN_WAKEUP_PCHR_SHIFT 13 |
| 5867 | #define MT6325_AUXADC_ADC_BUSY_IN_WAKEUP_SWCHR_MASK 0x1 |
| 5868 | #define MT6325_AUXADC_ADC_BUSY_IN_WAKEUP_SWCHR_SHIFT 14 |
| 5869 | #define MT6325_AUXADC_RO_RSV0_MASK 0x1 |
| 5870 | #define MT6325_AUXADC_RO_RSV0_SHIFT 15 |
| 5871 | #define MT6325_AUXADC_ADC_BUSY_IN_VISMPS0_MASK 0x1 |
| 5872 | #define MT6325_AUXADC_ADC_BUSY_IN_VISMPS0_SHIFT 11 |
| 5873 | #define MT6325_AUXADC_ADC_BUSY_IN_LBAT_MASK 0x1 |
| 5874 | #define MT6325_AUXADC_ADC_BUSY_IN_LBAT_SHIFT 12 |
| 5875 | #define MT6325_AUXADC_ADC_BUSY_IN_LBAT2_MASK 0x1 |
| 5876 | #define MT6325_AUXADC_ADC_BUSY_IN_LBAT2_SHIFT 13 |
| 5877 | #define MT6325_AUXADC_ADC_BUSY_IN_THR1_MASK 0x1 |
| 5878 | #define MT6325_AUXADC_ADC_BUSY_IN_THR1_SHIFT 14 |
| 5879 | #define MT6325_AUXADC_ADC_BUSY_IN_THR2_MASK 0x1 |
| 5880 | #define MT6325_AUXADC_ADC_BUSY_IN_THR2_SHIFT 15 |
| 5881 | #define MT6325_AUXADC_RQST0_RSV1_MASK 0xFF |
| 5882 | #define MT6325_AUXADC_RQST0_RSV1_SHIFT 0 |
| 5883 | #define MT6325_AUXADC_RQST0_RSV0_MASK 0xFF |
| 5884 | #define MT6325_AUXADC_RQST0_RSV0_SHIFT 8 |
| 5885 | #define MT6325_AUXADC_RQST0_SET_MASK 0xFFFF |
| 5886 | #define MT6325_AUXADC_RQST0_SET_SHIFT 0 |
| 5887 | #define MT6325_AUXADC_RQST0_CLR_MASK 0xFFFF |
| 5888 | #define MT6325_AUXADC_RQST0_CLR_SHIFT 0 |
| 5889 | #define MT6325_AUXADC_RQST_RSV0_MASK 0xF |
| 5890 | #define MT6325_AUXADC_RQST_RSV0_SHIFT 0 |
| 5891 | #define MT6325_AUXADC_RQST_CH4_BY_MD_MASK 0x1 |
| 5892 | #define MT6325_AUXADC_RQST_CH4_BY_MD_SHIFT 4 |
| 5893 | #define MT6325_AUXADC_RQST_CH7_BY_MD_MASK 0x1 |
| 5894 | #define MT6325_AUXADC_RQST_CH7_BY_MD_SHIFT 7 |
| 5895 | #define MT6325_AUXADC_RQST_CH7_BY_GPS_MASK 0x1 |
| 5896 | #define MT6325_AUXADC_RQST_CH7_BY_GPS_SHIFT 8 |
| 5897 | #define MT6325_AUXADC_RQST_RSV1_MASK 0x7F |
| 5898 | #define MT6325_AUXADC_RQST_RSV1_SHIFT 9 |
| 5899 | #define MT6325_AUXADC_RQST1_SET_MASK 0xFFFF |
| 5900 | #define MT6325_AUXADC_RQST1_SET_SHIFT 0 |
| 5901 | #define MT6325_AUXADC_RQST1_CLR_MASK 0xFFFF |
| 5902 | #define MT6325_AUXADC_RQST1_CLR_SHIFT 0 |
| 5903 | #define MT6325_AUXADC_CK_ON_EXTD_MASK 0x3F |
| 5904 | #define MT6325_AUXADC_CK_ON_EXTD_SHIFT 0 |
| 5905 | #define MT6325_AUXADC_STRUP_CK_ON_ENB_MASK 0x1 |
| 5906 | #define MT6325_AUXADC_STRUP_CK_ON_ENB_SHIFT 10 |
| 5907 | #define MT6325_AUXADC_ADC_RDY_WAKEUP_CLR_MASK 0x1 |
| 5908 | #define MT6325_AUXADC_ADC_RDY_WAKEUP_CLR_SHIFT 11 |
| 5909 | #define MT6325_AUXADC_SRCLKEN_CK_EN_MASK 0x1 |
| 5910 | #define MT6325_AUXADC_SRCLKEN_CK_EN_SHIFT 12 |
| 5911 | #define MT6325_AUXADC_CK_AON_GPS_MASK 0x1 |
| 5912 | #define MT6325_AUXADC_CK_AON_GPS_SHIFT 13 |
| 5913 | #define MT6325_AUXADC_CK_AON_MD_MASK 0x1 |
| 5914 | #define MT6325_AUXADC_CK_AON_MD_SHIFT 14 |
| 5915 | #define MT6325_AUXADC_CK_AON_MASK 0x1 |
| 5916 | #define MT6325_AUXADC_CK_AON_SHIFT 15 |
| 5917 | #define MT6325_AUXADC_PMU_THR_PDN_SW_MASK 0x1 |
| 5918 | #define MT6325_AUXADC_PMU_THR_PDN_SW_SHIFT 0 |
| 5919 | #define MT6325_AUXADC_PMU_THR_PDN_SEL_MASK 0x1 |
| 5920 | #define MT6325_AUXADC_PMU_THR_PDN_SEL_SHIFT 1 |
| 5921 | #define MT6325_AUXADC_PMU_THR_PDN_STATUS_MASK 0x1 |
| 5922 | #define MT6325_AUXADC_PMU_THR_PDN_STATUS_SHIFT 2 |
| 5923 | #define MT6325_AUXADC_RO_RSV1_MASK 0x7F |
| 5924 | #define MT6325_AUXADC_RO_RSV1_SHIFT 3 |
| 5925 | #define MT6325_AUXADC_DIG1_RSV0_MASK 0x3F |
| 5926 | #define MT6325_AUXADC_DIG1_RSV0_SHIFT 10 |
| 5927 | #define MT6325_AUXADC_THR_DEBT_MAX_MASK 0xFF |
| 5928 | #define MT6325_AUXADC_THR_DEBT_MAX_SHIFT 0 |
| 5929 | #define MT6325_AUXADC_THR_DEBT_MIN_MASK 0xFF |
| 5930 | #define MT6325_AUXADC_THR_DEBT_MIN_SHIFT 8 |
| 5931 | #define MT6325_AUXADC_THR_DET_PRD_15_0_MASK 0xFFFF |
| 5932 | #define MT6325_AUXADC_THR_DET_PRD_15_0_SHIFT 0 |
| 5933 | #define MT6325_AUXADC_THR_DET_PRD_19_16_MASK 0xF |
| 5934 | #define MT6325_AUXADC_THR_DET_PRD_19_16_SHIFT 0 |
| 5935 | #define MT6325_AUXADC_THR_VOLT_MAX_MASK 0xFFF |
| 5936 | #define MT6325_AUXADC_THR_VOLT_MAX_SHIFT 0 |
| 5937 | #define MT6325_AUXADC_THR_IRQ_EN_MAX_MASK 0x1 |
| 5938 | #define MT6325_AUXADC_THR_IRQ_EN_MAX_SHIFT 12 |
| 5939 | #define MT6325_AUXADC_THR_EN_MAX_MASK 0x1 |
| 5940 | #define MT6325_AUXADC_THR_EN_MAX_SHIFT 13 |
| 5941 | #define MT6325_AUXADC_THR_MAX_IRQ_B_MASK 0x1 |
| 5942 | #define MT6325_AUXADC_THR_MAX_IRQ_B_SHIFT 15 |
| 5943 | #define MT6325_AUXADC_THR_VOLT_MIN_MASK 0xFFF |
| 5944 | #define MT6325_AUXADC_THR_VOLT_MIN_SHIFT 0 |
| 5945 | #define MT6325_AUXADC_THR_IRQ_EN_MIN_MASK 0x1 |
| 5946 | #define MT6325_AUXADC_THR_IRQ_EN_MIN_SHIFT 12 |
| 5947 | #define MT6325_AUXADC_THR_EN_MIN_MASK 0x1 |
| 5948 | #define MT6325_AUXADC_THR_EN_MIN_SHIFT 13 |
| 5949 | #define MT6325_AUXADC_THR_MIN_IRQ_B_MASK 0x1 |
| 5950 | #define MT6325_AUXADC_THR_MIN_IRQ_B_SHIFT 15 |
| 5951 | #define MT6325_AUXADC_THR_DEBOUNCE_COUNT_MAX_MASK 0x1FF |
| 5952 | #define MT6325_AUXADC_THR_DEBOUNCE_COUNT_MAX_SHIFT 0 |
| 5953 | #define MT6325_AUXADC_THR_DEBOUNCE_COUNT_MIN_MASK 0x1FF |
| 5954 | #define MT6325_AUXADC_THR_DEBOUNCE_COUNT_MIN_SHIFT 0 |
| 5955 | #define MT6325_RG_AUXADC_FGADC_START_SW_MASK 0x1 |
| 5956 | #define MT6325_RG_AUXADC_FGADC_START_SW_SHIFT 0 |
| 5957 | #define MT6325_RG_AUXADC_FGADC_START_SEL_MASK 0x1 |
| 5958 | #define MT6325_RG_AUXADC_FGADC_START_SEL_SHIFT 1 |
| 5959 | #define MT6325_RG_AUXADC_FGADC_R_SW_MASK 0x1 |
| 5960 | #define MT6325_RG_AUXADC_FGADC_R_SW_SHIFT 2 |
| 5961 | #define MT6325_RG_AUXADC_FGADC_R_SEL_MASK 0x1 |
| 5962 | #define MT6325_RG_AUXADC_FGADC_R_SEL_SHIFT 3 |
| 5963 | #define MT6325_AUXADC_DIG0_RSV2_MASK 0x1 |
| 5964 | #define MT6325_AUXADC_DIG0_RSV2_SHIFT 4 |
| 5965 | #define MT6325_AUXADC_DIG1_RSV2_MASK 0xF |
| 5966 | #define MT6325_AUXADC_DIG1_RSV2_SHIFT 5 |
| 5967 | #define MT6325_AUXADC_ACCDET_AUTO_SPL_MASK 0x1 |
| 5968 | #define MT6325_AUXADC_ACCDET_AUTO_SPL_SHIFT 9 |
| 5969 | #define MT6325_AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1 |
| 5970 | #define MT6325_AUXADC_ACCDET_AUTO_RQST_CLR_SHIFT 10 |
| 5971 | #define MT6325_AUXADC_AUTORPT_PRD_MASK 0x3FF |
| 5972 | #define MT6325_AUXADC_AUTORPT_PRD_SHIFT 0 |
| 5973 | #define MT6325_AUXADC_AUTORPT_EN_MASK 0x1 |
| 5974 | #define MT6325_AUXADC_AUTORPT_EN_SHIFT 15 |
| 5975 | #define MT6325_AUXADC_IMPEDANCE_CNT_MASK 0x3F |
| 5976 | #define MT6325_AUXADC_IMPEDANCE_CNT_SHIFT 0 |
| 5977 | #define MT6325_AUXADC_IMPEDANCE_CHSEL_MASK 0x1 |
| 5978 | #define MT6325_AUXADC_IMPEDANCE_CHSEL_SHIFT 6 |
| 5979 | #define MT6325_AUXADC_IMPEDANCE_IRQ_CLR_MASK 0x1 |
| 5980 | #define MT6325_AUXADC_IMPEDANCE_IRQ_CLR_SHIFT 7 |
| 5981 | #define MT6325_AUXADC_IMPEDANCE_IRQ_STATUS_MASK 0x1 |
| 5982 | #define MT6325_AUXADC_IMPEDANCE_IRQ_STATUS_SHIFT 8 |
| 5983 | #define MT6325_AUXADC_CLR_IMP_CNT_STOP_MASK 0x1 |
| 5984 | #define MT6325_AUXADC_CLR_IMP_CNT_STOP_SHIFT 14 |
| 5985 | #define MT6325_AUXADC_IMPEDANCE_MODE_MASK 0x1 |
| 5986 | #define MT6325_AUXADC_IMPEDANCE_MODE_SHIFT 15 |
| 5987 | #define MT6325_AUXADC_VISMPS0_DEBT_MAX_MASK 0xFF |
| 5988 | #define MT6325_AUXADC_VISMPS0_DEBT_MAX_SHIFT 0 |
| 5989 | #define MT6325_AUXADC_VISMPS0_DEBT_MIN_MASK 0xFF |
| 5990 | #define MT6325_AUXADC_VISMPS0_DEBT_MIN_SHIFT 8 |
| 5991 | #define MT6325_AUXADC_VISMPS0_DET_PRD_15_0_MASK 0xFFFF |
| 5992 | #define MT6325_AUXADC_VISMPS0_DET_PRD_15_0_SHIFT 0 |
| 5993 | #define MT6325_AUXADC_VISMPS0_DET_PRD_19_16_MASK 0xF |
| 5994 | #define MT6325_AUXADC_VISMPS0_DET_PRD_19_16_SHIFT 0 |
| 5995 | #define MT6325_AUXADC_VISMPS0_VOLT_MAX_MASK 0xFFF |
| 5996 | #define MT6325_AUXADC_VISMPS0_VOLT_MAX_SHIFT 0 |
| 5997 | #define MT6325_AUXADC_VISMPS0_IRQ_EN_MAX_MASK 0x1 |
| 5998 | #define MT6325_AUXADC_VISMPS0_IRQ_EN_MAX_SHIFT 12 |
| 5999 | #define MT6325_AUXADC_VISMPS0_EN_MAX_MASK 0x1 |
| 6000 | #define MT6325_AUXADC_VISMPS0_EN_MAX_SHIFT 13 |
| 6001 | #define MT6325_AUXADC_VISMPS0_MAX_IRQ_B_MASK 0x1 |
| 6002 | #define MT6325_AUXADC_VISMPS0_MAX_IRQ_B_SHIFT 15 |
| 6003 | #define MT6325_AUXADC_VISMPS0_VOLT_MIN_MASK 0xFFF |
| 6004 | #define MT6325_AUXADC_VISMPS0_VOLT_MIN_SHIFT 0 |
| 6005 | #define MT6325_AUXADC_VISMPS0_IRQ_EN_MIN_MASK 0x1 |
| 6006 | #define MT6325_AUXADC_VISMPS0_IRQ_EN_MIN_SHIFT 12 |
| 6007 | #define MT6325_AUXADC_VISMPS0_EN_MIN_MASK 0x1 |
| 6008 | #define MT6325_AUXADC_VISMPS0_EN_MIN_SHIFT 13 |
| 6009 | #define MT6325_AUXADC_VISMPS0_MIN_IRQ_B_MASK 0x1 |
| 6010 | #define MT6325_AUXADC_VISMPS0_MIN_IRQ_B_SHIFT 15 |
| 6011 | #define MT6325_AUXADC_VISMPS0_DEBOUNCE_COUNT_MAX_MASK 0x1FF |
| 6012 | #define MT6325_AUXADC_VISMPS0_DEBOUNCE_COUNT_MAX_SHIFT 0 |
| 6013 | #define MT6325_AUXADC_VISMPS0_DEBOUNCE_COUNT_MIN_MASK 0x1FF |
| 6014 | #define MT6325_AUXADC_VISMPS0_DEBOUNCE_COUNT_MIN_SHIFT 0 |
| 6015 | #define MT6325_AUXADC_LBAT2_DEBT_MAX_MASK 0xFF |
| 6016 | #define MT6325_AUXADC_LBAT2_DEBT_MAX_SHIFT 0 |
| 6017 | #define MT6325_AUXADC_LBAT2_DEBT_MIN_MASK 0xFF |
| 6018 | #define MT6325_AUXADC_LBAT2_DEBT_MIN_SHIFT 8 |
| 6019 | #define MT6325_AUXADC_LBAT2_DET_PRD_15_0_MASK 0xFFFF |
| 6020 | #define MT6325_AUXADC_LBAT2_DET_PRD_15_0_SHIFT 0 |
| 6021 | #define MT6325_AUXADC_LBAT2_DET_PRD_19_16_MASK 0xF |
| 6022 | #define MT6325_AUXADC_LBAT2_DET_PRD_19_16_SHIFT 0 |
| 6023 | #define MT6325_AUXADC_LBAT2_VOLT_MAX_MASK 0xFFF |
| 6024 | #define MT6325_AUXADC_LBAT2_VOLT_MAX_SHIFT 0 |
| 6025 | #define MT6325_AUXADC_LBAT2_IRQ_EN_MAX_MASK 0x1 |
| 6026 | #define MT6325_AUXADC_LBAT2_IRQ_EN_MAX_SHIFT 12 |
| 6027 | #define MT6325_AUXADC_LBAT2_EN_MAX_MASK 0x1 |
| 6028 | #define MT6325_AUXADC_LBAT2_EN_MAX_SHIFT 13 |
| 6029 | #define MT6325_AUXADC_LBAT2_MAX_IRQ_B_MASK 0x1 |
| 6030 | #define MT6325_AUXADC_LBAT2_MAX_IRQ_B_SHIFT 15 |
| 6031 | #define MT6325_AUXADC_LBAT2_VOLT_MIN_MASK 0xFFF |
| 6032 | #define MT6325_AUXADC_LBAT2_VOLT_MIN_SHIFT 0 |
| 6033 | #define MT6325_AUXADC_LBAT2_IRQ_EN_MIN_MASK 0x1 |
| 6034 | #define MT6325_AUXADC_LBAT2_IRQ_EN_MIN_SHIFT 12 |
| 6035 | #define MT6325_AUXADC_LBAT2_EN_MIN_MASK 0x1 |
| 6036 | #define MT6325_AUXADC_LBAT2_EN_MIN_SHIFT 13 |
| 6037 | #define MT6325_AUXADC_LBAT2_MIN_IRQ_B_MASK 0x1 |
| 6038 | #define MT6325_AUXADC_LBAT2_MIN_IRQ_B_SHIFT 15 |
| 6039 | #define MT6325_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_MASK 0x1FF |
| 6040 | #define MT6325_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_SHIFT 0 |
| 6041 | #define MT6325_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_MASK 0x1FF |
| 6042 | #define MT6325_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_SHIFT 0 |
| 6043 | #define MT6325_RG_ADC_OUT_BATSNS_MASK 0x7FFF |
| 6044 | #define MT6325_RG_ADC_OUT_BATSNS_SHIFT 0 |
| 6045 | #define MT6325_RG_ADC_RDY_BATSNS_MASK 0x1 |
| 6046 | #define MT6325_RG_ADC_RDY_BATSNS_SHIFT 15 |
| 6047 | #define MT6325_RG_ADC_OUT_ISENSE_MASK 0x7FFF |
| 6048 | #define MT6325_RG_ADC_OUT_ISENSE_SHIFT 0 |
| 6049 | #define MT6325_RG_ADC_RDY_ISENSE_MASK 0x1 |
| 6050 | #define MT6325_RG_ADC_RDY_ISENSE_SHIFT 15 |
| 6051 | #define MT6325_RG_ADC_OUT_VCDT_MASK 0x7FFF |
| 6052 | #define MT6325_RG_ADC_OUT_VCDT_SHIFT 0 |
| 6053 | #define MT6325_RG_ADC_RDY_VCDT_MASK 0x1 |
| 6054 | #define MT6325_RG_ADC_RDY_VCDT_SHIFT 15 |
| 6055 | #define MT6325_RG_ADC_OUT_BATON1_MASK 0x7FFF |
| 6056 | #define MT6325_RG_ADC_OUT_BATON1_SHIFT 0 |
| 6057 | #define MT6325_RG_ADC_RDY_BATON1_MASK 0x1 |
| 6058 | #define MT6325_RG_ADC_RDY_BATON1_SHIFT 15 |
| 6059 | #define MT6325_RG_ADC_OUT_THR_SENSE1_MASK 0x7FFF |
| 6060 | #define MT6325_RG_ADC_OUT_THR_SENSE1_SHIFT 0 |
| 6061 | #define MT6325_RG_ADC_RDY_THR_SENSE1_MASK 0x1 |
| 6062 | #define MT6325_RG_ADC_RDY_THR_SENSE1_SHIFT 15 |
| 6063 | #define MT6325_RG_ADC_OUT_THR_MD_MASK 0x7FFF |
| 6064 | #define MT6325_RG_ADC_OUT_THR_MD_SHIFT 0 |
| 6065 | #define MT6325_RG_ADC_RDY_THR_MD_MASK 0x1 |
| 6066 | #define MT6325_RG_ADC_RDY_THR_MD_SHIFT 15 |
| 6067 | #define MT6325_RG_ADC_OUT_BATON2_MASK 0x7FFF |
| 6068 | #define MT6325_RG_ADC_OUT_BATON2_SHIFT 0 |
| 6069 | #define MT6325_RG_ADC_RDY_BATON2_MASK 0x1 |
| 6070 | #define MT6325_RG_ADC_RDY_BATON2_SHIFT 15 |
| 6071 | #define MT6325_RG_ADC_OUT_CH5_MASK 0x7FFF |
| 6072 | #define MT6325_RG_ADC_OUT_CH5_SHIFT 0 |
| 6073 | #define MT6325_RG_ADC_RDY_CH5_MASK 0x1 |
| 6074 | #define MT6325_RG_ADC_RDY_CH5_SHIFT 15 |
| 6075 | #define MT6325_RG_ADC_OUT_WAKEUP_PCHR_MASK 0x7FFF |
| 6076 | #define MT6325_RG_ADC_OUT_WAKEUP_PCHR_SHIFT 0 |
| 6077 | #define MT6325_RG_ADC_RDY_WAKEUP_PCHR_MASK 0x1 |
| 6078 | #define MT6325_RG_ADC_RDY_WAKEUP_PCHR_SHIFT 15 |
| 6079 | #define MT6325_RG_ADC_OUT_WAKEUP_SWCHR_MASK 0x7FFF |
| 6080 | #define MT6325_RG_ADC_OUT_WAKEUP_SWCHR_SHIFT 0 |
| 6081 | #define MT6325_RG_ADC_RDY_WAKEUP_SWCHR_MASK 0x1 |
| 6082 | #define MT6325_RG_ADC_RDY_WAKEUP_SWCHR_SHIFT 15 |
| 6083 | #define MT6325_RG_ADC_OUT_LBAT_MASK 0xFFF |
| 6084 | #define MT6325_RG_ADC_OUT_LBAT_SHIFT 0 |
| 6085 | #define MT6325_RG_ADC_RDY_LBAT_MASK 0x1 |
| 6086 | #define MT6325_RG_ADC_RDY_LBAT_SHIFT 15 |
| 6087 | #define MT6325_RG_ADC_OUT_CH6_MASK 0x7FFF |
| 6088 | #define MT6325_RG_ADC_OUT_CH6_SHIFT 0 |
| 6089 | #define MT6325_RG_ADC_RDY_CH6_MASK 0x1 |
| 6090 | #define MT6325_RG_ADC_RDY_CH6_SHIFT 15 |
| 6091 | #define MT6325_RG_ADC_RDY_GPS_MASK 0x1 |
| 6092 | #define MT6325_RG_ADC_RDY_GPS_SHIFT 15 |
| 6093 | #define MT6325_RG_ADC_OUT_GPS_MASK 0xFFFF |
| 6094 | #define MT6325_RG_ADC_OUT_GPS_SHIFT 0 |
| 6095 | #define MT6325_RG_ADC_OUT_GPS_LSB_MASK 0x1 |
| 6096 | #define MT6325_RG_ADC_OUT_GPS_LSB_SHIFT 15 |
| 6097 | #define MT6325_RG_ADC_OUT_MD_MASK 0xFFFF |
| 6098 | #define MT6325_RG_ADC_OUT_MD_SHIFT 0 |
| 6099 | #define MT6325_RG_ADC_OUT_MD_LSB_MASK 0x1 |
| 6100 | #define MT6325_RG_ADC_OUT_MD_LSB_SHIFT 0 |
| 6101 | #define MT6325_RG_ADC_RDY_MD_MASK 0x1 |
| 6102 | #define MT6325_RG_ADC_RDY_MD_SHIFT 15 |
| 6103 | #define MT6325_RG_ADC_OUT_INT_MASK 0x7FFF |
| 6104 | #define MT6325_RG_ADC_OUT_INT_SHIFT 0 |
| 6105 | #define MT6325_RG_ADC_RDY_INT_MASK 0x1 |
| 6106 | #define MT6325_RG_ADC_RDY_INT_SHIFT 15 |
| 6107 | #define MT6325_RG_ADC_OUT_CIC_RAW_16_1_MASK 0xFFFF |
| 6108 | #define MT6325_RG_ADC_OUT_CIC_RAW_16_1_SHIFT 0 |
| 6109 | #define MT6325_RG_ADC_OUT_CIC_RAW_0_MASK 0x1 |
| 6110 | #define MT6325_RG_ADC_OUT_CIC_RAW_0_SHIFT 0 |
| 6111 | #define MT6325_RG_ADC_BUSY_MASK 0x7FFF |
| 6112 | #define MT6325_RG_ADC_BUSY_SHIFT 1 |
| 6113 | #define MT6325_RG_ADC_OUT_LBAT2_MASK 0xFFF |
| 6114 | #define MT6325_RG_ADC_OUT_LBAT2_SHIFT 0 |
| 6115 | #define MT6325_RG_ADC_RDY_LBAT2_MASK 0x1 |
| 6116 | #define MT6325_RG_ADC_RDY_LBAT2_SHIFT 15 |
| 6117 | #define MT6325_RG_ADC_OUT_THR_HW_MASK 0xFFF |
| 6118 | #define MT6325_RG_ADC_OUT_THR_HW_SHIFT 0 |
| 6119 | #define MT6325_RG_ADC_RDY_THR_HW_MASK 0x1 |
| 6120 | #define MT6325_RG_ADC_RDY_THR_HW_SHIFT 15 |
| 6121 | #define MT6325_RG_ADC_OUT_CH8_MASK 0x7FFF |
| 6122 | #define MT6325_RG_ADC_OUT_CH8_SHIFT 0 |
| 6123 | #define MT6325_RG_ADC_RDY_CH8_MASK 0x1 |
| 6124 | #define MT6325_RG_ADC_RDY_CH8_SHIFT 15 |
| 6125 | #define MT6325_RG_ADC_OUT_CH9_MASK 0x7FFF |
| 6126 | #define MT6325_RG_ADC_OUT_CH9_SHIFT 0 |
| 6127 | #define MT6325_RG_ADC_RDY_CH9_MASK 0x1 |
| 6128 | #define MT6325_RG_ADC_RDY_CH9_SHIFT 15 |
| 6129 | #define MT6325_RG_ADC_OUT_CH10_MASK 0x7FFF |
| 6130 | #define MT6325_RG_ADC_OUT_CH10_SHIFT 0 |
| 6131 | #define MT6325_RG_ADC_RDY_CH10_MASK 0x1 |
| 6132 | #define MT6325_RG_ADC_RDY_CH10_SHIFT 15 |
| 6133 | #define MT6325_RG_ADC_OUT_CH11_MASK 0x7FFF |
| 6134 | #define MT6325_RG_ADC_OUT_CH11_SHIFT 0 |
| 6135 | #define MT6325_RG_ADC_RDY_CH11_MASK 0x1 |
| 6136 | #define MT6325_RG_ADC_RDY_CH11_SHIFT 15 |
| 6137 | #define MT6325_RG_ADC_OUT_VISMPS0_MASK 0xFFF |
| 6138 | #define MT6325_RG_ADC_OUT_VISMPS0_SHIFT 0 |
| 6139 | #define MT6325_RG_ADC_RDY_VISMPS0_MASK 0x1 |
| 6140 | #define MT6325_RG_ADC_RDY_VISMPS0_SHIFT 15 |
| 6141 | #define MT6325_RG_ADC_OUT_FGADC_MASK 0x7FFF |
| 6142 | #define MT6325_RG_ADC_OUT_FGADC_SHIFT 0 |
| 6143 | #define MT6325_RG_ADC_RDY_FGADC_MASK 0x1 |
| 6144 | #define MT6325_RG_ADC_RDY_FGADC_SHIFT 15 |
| 6145 | #define MT6325_RG_ADC_OUT_IMP_MASK 0x7FFF |
| 6146 | #define MT6325_RG_ADC_OUT_IMP_SHIFT 0 |
| 6147 | #define MT6325_RG_ADC_RDY_IMP_MASK 0x1 |
| 6148 | #define MT6325_RG_ADC_RDY_IMP_SHIFT 15 |
| 6149 | #define MT6325_RG_ADC_OUT_IMP_AVG_MASK 0x7FFF |
| 6150 | #define MT6325_RG_ADC_OUT_IMP_AVG_SHIFT 0 |
| 6151 | #define MT6325_RG_ADC_RDY_IMP_AVG_MASK 0x1 |
| 6152 | #define MT6325_RG_ADC_RDY_IMP_AVG_SHIFT 15 |
| 6153 | #define MT6325_RG_ADC_OUT_FGADC2_MASK 0x7FFF |
| 6154 | #define MT6325_RG_ADC_OUT_FGADC2_SHIFT 0 |
| 6155 | #define MT6325_RG_ADC_RDY_FGADC2_MASK 0x1 |
| 6156 | #define MT6325_RG_ADC_RDY_FGADC2_SHIFT 15 |
| 6157 | #define MT6325_RG_SW_GAIN_TRIM_MASK 0xFFFF |
| 6158 | #define MT6325_RG_SW_GAIN_TRIM_SHIFT 0 |
| 6159 | #define MT6325_RG_SW_OFFSET_TRIM_MASK 0xFFFF |
| 6160 | #define MT6325_RG_SW_OFFSET_TRIM_SHIFT 0 |
| 6161 | #define MT6325_RG_ADC_PWDB_MASK 0x1 |
| 6162 | #define MT6325_RG_ADC_PWDB_SHIFT 0 |
| 6163 | #define MT6325_RG_ADC_PWDB_SWCTRL_MASK 0x1 |
| 6164 | #define MT6325_RG_ADC_PWDB_SWCTRL_SHIFT 2 |
| 6165 | #define MT6325_RG_ADC_CALI_RATE_MASK 0x3 |
| 6166 | #define MT6325_RG_ADC_CALI_RATE_SHIFT 4 |
| 6167 | #define MT6325_RG_ADC_CALI_EN_MASK 0x1 |
| 6168 | #define MT6325_RG_ADC_CALI_EN_SHIFT 6 |
| 6169 | #define MT6325_RG_ADC_CALI_FORCE_MASK 0x1 |
| 6170 | #define MT6325_RG_ADC_CALI_FORCE_SHIFT 7 |
| 6171 | #define MT6325_RG_ADC_AUTORST_RANGE_MASK 0x3 |
| 6172 | #define MT6325_RG_ADC_AUTORST_RANGE_SHIFT 8 |
| 6173 | #define MT6325_RG_ADC_AUTORST_EN_MASK 0x1 |
| 6174 | #define MT6325_RG_ADC_AUTORST_EN_SHIFT 10 |
| 6175 | #define MT6325_RG_ADC_LATCH_EDGE_MASK 0x1 |
| 6176 | #define MT6325_RG_ADC_LATCH_EDGE_SHIFT 11 |
| 6177 | #define MT6325_RG_ADC_FILTER_ORDER_MASK 0x1 |
| 6178 | #define MT6325_RG_ADC_FILTER_ORDER_SHIFT 12 |
| 6179 | #define MT6325_RG_ADC_SWCTRL_EN_MASK 0x1 |
| 6180 | #define MT6325_RG_ADC_SWCTRL_EN_SHIFT 0 |
| 6181 | #define MT6325_AUXADC_ADCIN_VSEN_EN_MASK 0x1 |
| 6182 | #define MT6325_AUXADC_ADCIN_VSEN_EN_SHIFT 1 |
| 6183 | #define MT6325_AUXADC_ADCIN_VSEN_MUX_EN_MASK 0x1 |
| 6184 | #define MT6325_AUXADC_ADCIN_VSEN_MUX_EN_SHIFT 2 |
| 6185 | #define MT6325_AUXADC_ADCIN_VBAT_EN_MASK 0x1 |
| 6186 | #define MT6325_AUXADC_ADCIN_VBAT_EN_SHIFT 4 |
| 6187 | #define MT6325_AUXADC_ADCIN_CHR_EN_MASK 0x1 |
| 6188 | #define MT6325_AUXADC_ADCIN_CHR_EN_SHIFT 5 |
| 6189 | #define MT6325_RG_AUXADC_CHSEL_MASK 0xF |
| 6190 | #define MT6325_RG_AUXADC_CHSEL_SHIFT 12 |
| 6191 | #define MT6325_RG_LBAT_DEBT_MAX_MASK 0xFF |
| 6192 | #define MT6325_RG_LBAT_DEBT_MAX_SHIFT 0 |
| 6193 | #define MT6325_RG_LBAT_DEBT_MIN_MASK 0xFF |
| 6194 | #define MT6325_RG_LBAT_DEBT_MIN_SHIFT 8 |
| 6195 | #define MT6325_RG_LBAT_DET_PRD_15_0_MASK 0xFFFF |
| 6196 | #define MT6325_RG_LBAT_DET_PRD_15_0_SHIFT 0 |
| 6197 | #define MT6325_RG_LBAT_DET_PRD_19_16_MASK 0xF |
| 6198 | #define MT6325_RG_LBAT_DET_PRD_19_16_SHIFT 0 |
| 6199 | #define MT6325_RG_LBAT_VOLT_MAX_MASK 0xFFF |
| 6200 | #define MT6325_RG_LBAT_VOLT_MAX_SHIFT 0 |
| 6201 | #define MT6325_RG_LBAT_IRQ_EN_MAX_MASK 0x1 |
| 6202 | #define MT6325_RG_LBAT_IRQ_EN_MAX_SHIFT 12 |
| 6203 | #define MT6325_RG_LBAT_EN_MAX_MASK 0x1 |
| 6204 | #define MT6325_RG_LBAT_EN_MAX_SHIFT 13 |
| 6205 | #define MT6325_RG_LBAT_MAX_IRQ_B_MASK 0x1 |
| 6206 | #define MT6325_RG_LBAT_MAX_IRQ_B_SHIFT 15 |
| 6207 | #define MT6325_RG_LBAT_VOLT_MIN_MASK 0xFFF |
| 6208 | #define MT6325_RG_LBAT_VOLT_MIN_SHIFT 0 |
| 6209 | #define MT6325_RG_LBAT_IRQ_EN_MIN_MASK 0x1 |
| 6210 | #define MT6325_RG_LBAT_IRQ_EN_MIN_SHIFT 12 |
| 6211 | #define MT6325_RG_LBAT_EN_MIN_MASK 0x1 |
| 6212 | #define MT6325_RG_LBAT_EN_MIN_SHIFT 13 |
| 6213 | #define MT6325_RG_LBAT_MIN_IRQ_B_MASK 0x1 |
| 6214 | #define MT6325_RG_LBAT_MIN_IRQ_B_SHIFT 15 |
| 6215 | #define MT6325_RG_LBAT_DEBOUNCE_COUNT_MAX_MASK 0x1FF |
| 6216 | #define MT6325_RG_LBAT_DEBOUNCE_COUNT_MAX_SHIFT 0 |
| 6217 | #define MT6325_RG_LBAT_DEBOUNCE_COUNT_MIN_MASK 0x1FF |
| 6218 | #define MT6325_RG_LBAT_DEBOUNCE_COUNT_MIN_SHIFT 0 |
| 6219 | #define MT6325_RG_DATA_REUSE_SEL_MASK 0x3 |
| 6220 | #define MT6325_RG_DATA_REUSE_SEL_SHIFT 3 |
| 6221 | #define MT6325_RG_AUXADC_BIST_ENB_MASK 0x1 |
| 6222 | #define MT6325_RG_AUXADC_BIST_ENB_SHIFT 5 |
| 6223 | #define MT6325_RG_OSR_MASK 0x7 |
| 6224 | #define MT6325_RG_OSR_SHIFT 10 |
| 6225 | #define MT6325_RG_OSR_GPS_MASK 0x7 |
| 6226 | #define MT6325_RG_OSR_GPS_SHIFT 13 |
| 6227 | #define MT6325_RG_ADC_TRIM_CH7_SEL_MASK 0x3 |
| 6228 | #define MT6325_RG_ADC_TRIM_CH7_SEL_SHIFT 0 |
| 6229 | #define MT6325_RG_ADC_TRIM_CH6_SEL_MASK 0x3 |
| 6230 | #define MT6325_RG_ADC_TRIM_CH6_SEL_SHIFT 2 |
| 6231 | #define MT6325_RG_ADC_TRIM_CH5_SEL_MASK 0x3 |
| 6232 | #define MT6325_RG_ADC_TRIM_CH5_SEL_SHIFT 4 |
| 6233 | #define MT6325_RG_ADC_TRIM_CH4_SEL_MASK 0x3 |
| 6234 | #define MT6325_RG_ADC_TRIM_CH4_SEL_SHIFT 6 |
| 6235 | #define MT6325_RG_ADC_TRIM_CH3_SEL_MASK 0x3 |
| 6236 | #define MT6325_RG_ADC_TRIM_CH3_SEL_SHIFT 8 |
| 6237 | #define MT6325_RG_ADC_TRIM_CH2_SEL_MASK 0x3 |
| 6238 | #define MT6325_RG_ADC_TRIM_CH2_SEL_SHIFT 10 |
| 6239 | #define MT6325_RG_ADC_TRIM_CH0_SEL_MASK 0x3 |
| 6240 | #define MT6325_RG_ADC_TRIM_CH0_SEL_SHIFT 14 |
| 6241 | #define MT6325_RG_VBUF_CALEN_MASK 0x1 |
| 6242 | #define MT6325_RG_VBUF_CALEN_SHIFT 0 |
| 6243 | #define MT6325_RG_VBUF_EXTEN_MASK 0x1 |
| 6244 | #define MT6325_RG_VBUF_EXTEN_SHIFT 1 |
| 6245 | #define MT6325_RG_VBUF_BYP_MASK 0x1 |
| 6246 | #define MT6325_RG_VBUF_BYP_SHIFT 2 |
| 6247 | #define MT6325_RG_VBUF_EN_MASK 0x1 |
| 6248 | #define MT6325_RG_VBUF_EN_SHIFT 4 |
| 6249 | #define MT6325_RG_SOURCE_LBAT_SEL_MASK 0x1 |
| 6250 | #define MT6325_RG_SOURCE_LBAT_SEL_SHIFT 15 |
| 6251 | #define MT6325_EFUSE_GAIN_CH0_TRIM_MASK 0x1FF |
| 6252 | #define MT6325_EFUSE_GAIN_CH0_TRIM_SHIFT 0 |
| 6253 | #define MT6325_EFUSE_OFFSET_CH0_TRIM_MASK 0xFF |
| 6254 | #define MT6325_EFUSE_OFFSET_CH0_TRIM_SHIFT 0 |
| 6255 | #define MT6325_EFUSE_GAIN_CH4_TRIM_MASK 0x1FF |
| 6256 | #define MT6325_EFUSE_GAIN_CH4_TRIM_SHIFT 0 |
| 6257 | #define MT6325_EFUSE_OFFSET_CH4_TRIM_MASK 0xFF |
| 6258 | #define MT6325_EFUSE_OFFSET_CH4_TRIM_SHIFT 0 |
| 6259 | #define MT6325_EFUSE_GAIN_CH7_TRIM_MASK 0xFFFF |
| 6260 | #define MT6325_EFUSE_GAIN_CH7_TRIM_SHIFT 0 |
| 6261 | #define MT6325_EFUSE_OFFSET_CH7_TRIM_MASK 0xFFFF |
| 6262 | #define MT6325_EFUSE_OFFSET_CH7_TRIM_SHIFT 0 |
| 6263 | #define MT6325_RG_ADC_IBIAS_MASK 0x3 |
| 6264 | #define MT6325_RG_ADC_IBIAS_SHIFT 0 |
| 6265 | #define MT6325_RG_ADC_RST_MASK 0x1 |
| 6266 | #define MT6325_RG_ADC_RST_SHIFT 2 |
| 6267 | #define MT6325_RG_ADC_LP_EN_MASK 0x1 |
| 6268 | #define MT6325_RG_ADC_LP_EN_SHIFT 3 |
| 6269 | #define MT6325_RG_ADC_INPUT_SHORT_MASK 0x1 |
| 6270 | #define MT6325_RG_ADC_INPUT_SHORT_SHIFT 4 |
| 6271 | #define MT6325_RG_ADC_CHOPPER_EN_MASK 0x1 |
| 6272 | #define MT6325_RG_ADC_CHOPPER_EN_SHIFT 5 |
| 6273 | #define MT6325_RG_VPWDB_ADC_MASK 0x1 |
| 6274 | #define MT6325_RG_VPWDB_ADC_SHIFT 6 |
| 6275 | #define MT6325_RG_VREF18_EN_MASK 0x1 |
| 6276 | #define MT6325_RG_VREF18_EN_SHIFT 7 |
| 6277 | #define MT6325_RG_ADC_CHS_SEL_MASK 0x3 |
| 6278 | #define MT6325_RG_ADC_CHS_SEL_SHIFT 8 |
| 6279 | #define MT6325_RG_ADC_DVREF_CAL_MASK 0x1 |
| 6280 | #define MT6325_RG_ADC_DVREF_CAL_SHIFT 14 |
| 6281 | #define MT6325_RG_ADC_DENB_MASK 0x1 |
| 6282 | #define MT6325_RG_ADC_DENB_SHIFT 15 |
| 6283 | #define MT6325_RG_ADC_SLEEP_MODE_EN_MASK 0x1 |
| 6284 | #define MT6325_RG_ADC_SLEEP_MODE_EN_SHIFT 0 |
| 6285 | #define MT6325_RG_ADC_GPS_STATUS_MASK 0x1 |
| 6286 | #define MT6325_RG_ADC_GPS_STATUS_SHIFT 1 |
| 6287 | #define MT6325_RG_ADC_RSV_BIT_MASK 0x1 |
| 6288 | #define MT6325_RG_ADC_RSV_BIT_SHIFT 2 |
| 6289 | #define MT6325_RG_ADC_TEST_MODE_EN_MASK 0x1 |
| 6290 | #define MT6325_RG_ADC_TEST_MODE_EN_SHIFT 3 |
| 6291 | #define MT6325_RG_ADC_TEST_OUT_SEL_MASK 0x1 |
| 6292 | #define MT6325_RG_ADC_TEST_OUT_SEL_SHIFT 4 |
| 6293 | #define MT6325_RG_DECI_BYPASS_EN_MASK 0x1 |
| 6294 | #define MT6325_RG_DECI_BYPASS_EN_SHIFT 5 |
| 6295 | #define MT6325_RG_ADC_CLK_AON_MASK 0x1 |
| 6296 | #define MT6325_RG_ADC_CLK_AON_SHIFT 7 |
| 6297 | #define MT6325_RG_ADC_DECI_FORCE_MASK 0x1 |
| 6298 | #define MT6325_RG_ADC_DECI_FORCE_SHIFT 12 |
| 6299 | #define MT6325_RG_ADC_DECI_GDLY_MASK 0x3 |
| 6300 | #define MT6325_RG_ADC_DECI_GDLY_SHIFT 14 |
| 6301 | #define MT6325_RG_MD_RQST_MASK 0x1 |
| 6302 | #define MT6325_RG_MD_RQST_SHIFT 15 |
| 6303 | #define MT6325_RG_GPS_RQST_MASK 0x1 |
| 6304 | #define MT6325_RG_GPS_RQST_SHIFT 15 |
| 6305 | #define MT6325_RG_AP_RQST_LIST_MASK 0x1FF |
| 6306 | #define MT6325_RG_AP_RQST_LIST_SHIFT 0 |
| 6307 | #define MT6325_RG_AP_RQST_MASK 0x1 |
| 6308 | #define MT6325_RG_AP_RQST_SHIFT 15 |
| 6309 | #define MT6325_RG_AP_RQST_LIST_RSV_MASK 0xFF |
| 6310 | #define MT6325_RG_AP_RQST_LIST_RSV_SHIFT 0 |
| 6311 | #define MT6325_RG_ADC_OUT_TRIM_ENB_MASK 0x1 |
| 6312 | #define MT6325_RG_ADC_OUT_TRIM_ENB_SHIFT 1 |
| 6313 | #define MT6325_RG_ADC_TRIM_COMP_MASK 0x1 |
| 6314 | #define MT6325_RG_ADC_TRIM_COMP_SHIFT 2 |
| 6315 | #define MT6325_RG_ADC_2S_COMP_ENB_MASK 0x1 |
| 6316 | #define MT6325_RG_ADC_2S_COMP_ENB_SHIFT 3 |
| 6317 | #define MT6325_RG_CIC_OUT_RAW_MASK 0x1 |
| 6318 | #define MT6325_RG_CIC_OUT_RAW_SHIFT 4 |
| 6319 | #define MT6325_RG_DATA_SKIP_ENB_MASK 0x1 |
| 6320 | #define MT6325_RG_DATA_SKIP_ENB_SHIFT 5 |
| 6321 | #define MT6325_RG_DATA_SKIP_NUM_MASK 0x3 |
| 6322 | #define MT6325_RG_DATA_SKIP_NUM_SHIFT 6 |
| 6323 | #define MT6325_RG_ADC_REV_MASK 0xFF |
| 6324 | #define MT6325_RG_ADC_REV_SHIFT 0 |
| 6325 | #define MT6325_RG_DECI_GDLY_SEL_MODE_MASK 0x1 |
| 6326 | #define MT6325_RG_DECI_GDLY_SEL_MODE_SHIFT 0 |
| 6327 | #define MT6325_RG_DECI_GDLY_VREF18_SELB_MASK 0x1 |
| 6328 | #define MT6325_RG_DECI_GDLY_VREF18_SELB_SHIFT 1 |
| 6329 | #define MT6325_RG_ADC_RSV1_MASK 0x1FFF |
| 6330 | #define MT6325_RG_ADC_RSV1_SHIFT 2 |
| 6331 | #define MT6325_RG_VREF18_ENB_MASK 0x1 |
| 6332 | #define MT6325_RG_VREF18_ENB_SHIFT 15 |
| 6333 | #define MT6325_RG_ADC_MD_STATUS_MASK 0x1 |
| 6334 | #define MT6325_RG_ADC_MD_STATUS_SHIFT 0 |
| 6335 | #define MT6325_RG_ADC_RSV2_MASK 0x3FFF |
| 6336 | #define MT6325_RG_ADC_RSV2_SHIFT 1 |
| 6337 | #define MT6325_RG_VREF18_ENB_MD_MASK 0x1 |
| 6338 | #define MT6325_RG_VREF18_ENB_MD_SHIFT 15 |
| 6339 | #define MT6325_RG_AUDACCDETVTHBCAL_MASK 0x1 |
| 6340 | #define MT6325_RG_AUDACCDETVTHBCAL_SHIFT 0 |
| 6341 | #define MT6325_RG_AUDACCDETVTHACAL_MASK 0x1 |
| 6342 | #define MT6325_RG_AUDACCDETVTHACAL_SHIFT 1 |
| 6343 | #define MT6325_RG_AUDACCDETANASWCTRLENB_MASK 0x1 |
| 6344 | #define MT6325_RG_AUDACCDETANASWCTRLENB_SHIFT 2 |
| 6345 | #define MT6325_RG_ACCDETSEL_MASK 0x1 |
| 6346 | #define MT6325_RG_ACCDETSEL_SHIFT 3 |
| 6347 | #define MT6325_RG_AUDACCDETSWCTRL_MASK 0x7 |
| 6348 | #define MT6325_RG_AUDACCDETSWCTRL_SHIFT 4 |
| 6349 | #define MT6325_RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1 |
| 6350 | #define MT6325_RG_AUDACCDETMICBIAS1PULLLOW_SHIFT 7 |
| 6351 | #define MT6325_RG_AUDACCDETTVDET_MASK 0x1 |
| 6352 | #define MT6325_RG_AUDACCDETTVDET_SHIFT 8 |
| 6353 | #define MT6325_RG_AUDACCDETVIN1PULLLOW_MASK 0x1 |
| 6354 | #define MT6325_RG_AUDACCDETVIN1PULLLOW_SHIFT 9 |
| 6355 | #define MT6325_AUDACCDETAUXADCSWCTRL_MASK 0x1 |
| 6356 | #define MT6325_AUDACCDETAUXADCSWCTRL_SHIFT 10 |
| 6357 | #define MT6325_AUDACCDETAUXADCSWCTRL_SEL_MASK 0x1 |
| 6358 | #define MT6325_AUDACCDETAUXADCSWCTRL_SEL_SHIFT 11 |
| 6359 | #define MT6325_RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1 |
| 6360 | #define MT6325_RG_AUDACCDETMICBIAS0PULLLOW_SHIFT 12 |
| 6361 | #define MT6325_RG_AUDACCDETRSV_MASK 0x3 |
| 6362 | #define MT6325_RG_AUDACCDETRSV_SHIFT 13 |
| 6363 | #define MT6325_ACCDET_EN_MASK 0x1 |
| 6364 | #define MT6325_ACCDET_EN_SHIFT 0 |
| 6365 | #define MT6325_ACCDET_SEQ_INIT_MASK 0x1 |
| 6366 | #define MT6325_ACCDET_SEQ_INIT_SHIFT 1 |
| 6367 | #define MT6325_ACCDET_EINTDET_EN_MASK 0x1 |
| 6368 | #define MT6325_ACCDET_EINTDET_EN_SHIFT 2 |
| 6369 | #define MT6325_ACCDET_EINT_SEQ_INIT_MASK 0x1 |
| 6370 | #define MT6325_ACCDET_EINT_SEQ_INIT_SHIFT 3 |
| 6371 | #define MT6325_ACCDET_NEGVDET_EN_MASK 0x1 |
| 6372 | #define MT6325_ACCDET_NEGVDET_EN_SHIFT 4 |
| 6373 | #define MT6325_ACCDET_NEGVDET_EN_CTRL_MASK 0x1 |
| 6374 | #define MT6325_ACCDET_NEGVDET_EN_CTRL_SHIFT 5 |
| 6375 | #define MT6325_ACCDET_CMP_PWM_EN_MASK 0x1 |
| 6376 | #define MT6325_ACCDET_CMP_PWM_EN_SHIFT 0 |
| 6377 | #define MT6325_ACCDET_VTH_PWM_EN_MASK 0x1 |
| 6378 | #define MT6325_ACCDET_VTH_PWM_EN_SHIFT 1 |
| 6379 | #define MT6325_ACCDET_MBIAS_PWM_EN_MASK 0x1 |
| 6380 | #define MT6325_ACCDET_MBIAS_PWM_EN_SHIFT 2 |
| 6381 | #define MT6325_ACCDET_EINT_PWM_EN_MASK 0x1 |
| 6382 | #define MT6325_ACCDET_EINT_PWM_EN_SHIFT 3 |
| 6383 | #define MT6325_ACCDET_CMP_PWM_IDLE_MASK 0x1 |
| 6384 | #define MT6325_ACCDET_CMP_PWM_IDLE_SHIFT 4 |
| 6385 | #define MT6325_ACCDET_VTH_PWM_IDLE_MASK 0x1 |
| 6386 | #define MT6325_ACCDET_VTH_PWM_IDLE_SHIFT 5 |
| 6387 | #define MT6325_ACCDET_MBIAS_PWM_IDLE_MASK 0x1 |
| 6388 | #define MT6325_ACCDET_MBIAS_PWM_IDLE_SHIFT 6 |
| 6389 | #define MT6325_ACCDET_EINT_PWM_IDLE_MASK 0x1 |
| 6390 | #define MT6325_ACCDET_EINT_PWM_IDLE_SHIFT 7 |
| 6391 | #define MT6325_ACCDET_PWM_WIDTH_MASK 0xFFFF |
| 6392 | #define MT6325_ACCDET_PWM_WIDTH_SHIFT 0 |
| 6393 | #define MT6325_ACCDET_PWM_THRESH_MASK 0xFFFF |
| 6394 | #define MT6325_ACCDET_PWM_THRESH_SHIFT 0 |
| 6395 | #define MT6325_ACCDET_RISE_DELAY_MASK 0x7FFF |
| 6396 | #define MT6325_ACCDET_RISE_DELAY_SHIFT 0 |
| 6397 | #define MT6325_ACCDET_FALL_DELAY_MASK 0x1 |
| 6398 | #define MT6325_ACCDET_FALL_DELAY_SHIFT 15 |
| 6399 | #define MT6325_ACCDET_DEBOUNCE0_MASK 0xFFFF |
| 6400 | #define MT6325_ACCDET_DEBOUNCE0_SHIFT 0 |
| 6401 | #define MT6325_ACCDET_DEBOUNCE1_MASK 0xFFFF |
| 6402 | #define MT6325_ACCDET_DEBOUNCE1_SHIFT 0 |
| 6403 | #define MT6325_ACCDET_DEBOUNCE2_MASK 0xFFFF |
| 6404 | #define MT6325_ACCDET_DEBOUNCE2_SHIFT 0 |
| 6405 | #define MT6325_ACCDET_DEBOUNCE3_MASK 0xFFFF |
| 6406 | #define MT6325_ACCDET_DEBOUNCE3_SHIFT 0 |
| 6407 | #define MT6325_ACCDET_DEBOUNCE4_MASK 0xFFFF |
| 6408 | #define MT6325_ACCDET_DEBOUNCE4_SHIFT 0 |
| 6409 | #define MT6325_ACCDET_IVAL_CUR_IN_MASK 0x3 |
| 6410 | #define MT6325_ACCDET_IVAL_CUR_IN_SHIFT 0 |
| 6411 | #define MT6325_ACCDET_EINT_IVAL_CUR_IN_MASK 0x1 |
| 6412 | #define MT6325_ACCDET_EINT_IVAL_CUR_IN_SHIFT 2 |
| 6413 | #define MT6325_ACCDET_IVAL_SAM_IN_MASK 0x3 |
| 6414 | #define MT6325_ACCDET_IVAL_SAM_IN_SHIFT 4 |
| 6415 | #define MT6325_ACCDET_EINT_IVAL_SAM_IN_MASK 0x1 |
| 6416 | #define MT6325_ACCDET_EINT_IVAL_SAM_IN_SHIFT 6 |
| 6417 | #define MT6325_ACCDET_IVAL_MEM_IN_MASK 0x3 |
| 6418 | #define MT6325_ACCDET_IVAL_MEM_IN_SHIFT 8 |
| 6419 | #define MT6325_ACCDET_EINT_IVAL_MEM_IN_MASK 0x1 |
| 6420 | #define MT6325_ACCDET_EINT_IVAL_MEM_IN_SHIFT 10 |
| 6421 | #define MT6325_ACCDET_EINT_IVAL_SEL_MASK 0x1 |
| 6422 | #define MT6325_ACCDET_EINT_IVAL_SEL_SHIFT 14 |
| 6423 | #define MT6325_ACCDET_IVAL_SEL_MASK 0x1 |
| 6424 | #define MT6325_ACCDET_IVAL_SEL_SHIFT 15 |
| 6425 | #define MT6325_ACCDET_IRQ_MASK 0x1 |
| 6426 | #define MT6325_ACCDET_IRQ_SHIFT 0 |
| 6427 | #define MT6325_ACCDET_NEGV_IRQ_MASK 0x1 |
| 6428 | #define MT6325_ACCDET_NEGV_IRQ_SHIFT 1 |
| 6429 | #define MT6325_ACCDET_EINT_IRQ_MASK 0x1 |
| 6430 | #define MT6325_ACCDET_EINT_IRQ_SHIFT 2 |
| 6431 | #define MT6325_ACCDET_IRQ_CLR_MASK 0x1 |
| 6432 | #define MT6325_ACCDET_IRQ_CLR_SHIFT 8 |
| 6433 | #define MT6325_ACCDET_NEGV_IRQ_CLR_MASK 0x1 |
| 6434 | #define MT6325_ACCDET_NEGV_IRQ_CLR_SHIFT 9 |
| 6435 | #define MT6325_ACCDET_EINT_IRQ_CLR_MASK 0x1 |
| 6436 | #define MT6325_ACCDET_EINT_IRQ_CLR_SHIFT 10 |
| 6437 | #define MT6325_ACCDET_EINT_IRQ_POLARITY_MASK 0x1 |
| 6438 | #define MT6325_ACCDET_EINT_IRQ_POLARITY_SHIFT 15 |
| 6439 | #define MT6325_ACCDET_TEST_MODE0_MASK 0x1 |
| 6440 | #define MT6325_ACCDET_TEST_MODE0_SHIFT 0 |
| 6441 | #define MT6325_ACCDET_TEST_MODE1_MASK 0x1 |
| 6442 | #define MT6325_ACCDET_TEST_MODE1_SHIFT 1 |
| 6443 | #define MT6325_ACCDET_TEST_MODE2_MASK 0x1 |
| 6444 | #define MT6325_ACCDET_TEST_MODE2_SHIFT 2 |
| 6445 | #define MT6325_ACCDET_TEST_MODE3_MASK 0x1 |
| 6446 | #define MT6325_ACCDET_TEST_MODE3_SHIFT 3 |
| 6447 | #define MT6325_ACCDET_TEST_MODE4_MASK 0x1 |
| 6448 | #define MT6325_ACCDET_TEST_MODE4_SHIFT 4 |
| 6449 | #define MT6325_ACCDET_TEST_MODE5_MASK 0x1 |
| 6450 | #define MT6325_ACCDET_TEST_MODE5_SHIFT 5 |
| 6451 | #define MT6325_ACCDET_PWM_SEL_MASK 0x3 |
| 6452 | #define MT6325_ACCDET_PWM_SEL_SHIFT 6 |
| 6453 | #define MT6325_ACCDET_IN_SW_MASK 0x3 |
| 6454 | #define MT6325_ACCDET_IN_SW_SHIFT 8 |
| 6455 | #define MT6325_ACCDET_CMP_EN_SW_MASK 0x1 |
| 6456 | #define MT6325_ACCDET_CMP_EN_SW_SHIFT 12 |
| 6457 | #define MT6325_ACCDET_VTH_EN_SW_MASK 0x1 |
| 6458 | #define MT6325_ACCDET_VTH_EN_SW_SHIFT 13 |
| 6459 | #define MT6325_ACCDET_MBIAS_EN_SW_MASK 0x1 |
| 6460 | #define MT6325_ACCDET_MBIAS_EN_SW_SHIFT 14 |
| 6461 | #define MT6325_ACCDET_PWM_EN_SW_MASK 0x1 |
| 6462 | #define MT6325_ACCDET_PWM_EN_SW_SHIFT 15 |
| 6463 | #define MT6325_ACCDET_IN_MASK 0x3 |
| 6464 | #define MT6325_ACCDET_IN_SHIFT 0 |
| 6465 | #define MT6325_ACCDET_CUR_IN_MASK 0x3 |
| 6466 | #define MT6325_ACCDET_CUR_IN_SHIFT 2 |
| 6467 | #define MT6325_ACCDET_SAM_IN_MASK 0x3 |
| 6468 | #define MT6325_ACCDET_SAM_IN_SHIFT 4 |
| 6469 | #define MT6325_ACCDET_MEM_IN_MASK 0x3 |
| 6470 | #define MT6325_ACCDET_MEM_IN_SHIFT 6 |
| 6471 | #define MT6325_ACCDET_STATE_MASK 0x7 |
| 6472 | #define MT6325_ACCDET_STATE_SHIFT 8 |
| 6473 | #define MT6325_ACCDET_MBIAS_CLK_MASK 0x1 |
| 6474 | #define MT6325_ACCDET_MBIAS_CLK_SHIFT 12 |
| 6475 | #define MT6325_ACCDET_VTH_CLK_MASK 0x1 |
| 6476 | #define MT6325_ACCDET_VTH_CLK_SHIFT 13 |
| 6477 | #define MT6325_ACCDET_CMP_CLK_MASK 0x1 |
| 6478 | #define MT6325_ACCDET_CMP_CLK_SHIFT 14 |
| 6479 | #define MT6325_DA_AUDACCDETAUXADCSWCTRL_MASK 0x1 |
| 6480 | #define MT6325_DA_AUDACCDETAUXADCSWCTRL_SHIFT 15 |
| 6481 | #define MT6325_ACCDET_EINT_DEB_SEL_MASK 0x1 |
| 6482 | #define MT6325_ACCDET_EINT_DEB_SEL_SHIFT 0 |
| 6483 | #define MT6325_ACCDET_EINT_DEBOUNCE_MASK 0x7 |
| 6484 | #define MT6325_ACCDET_EINT_DEBOUNCE_SHIFT 4 |
| 6485 | #define MT6325_ACCDET_EINT_PWM_THRESH_MASK 0x7 |
| 6486 | #define MT6325_ACCDET_EINT_PWM_THRESH_SHIFT 8 |
| 6487 | #define MT6325_ACCDET_EINT_PWM_WIDTH_MASK 0x3 |
| 6488 | #define MT6325_ACCDET_EINT_PWM_WIDTH_SHIFT 12 |
| 6489 | #define MT6325_ACCDET_NEGV_THRESH_MASK 0x1F |
| 6490 | #define MT6325_ACCDET_NEGV_THRESH_SHIFT 0 |
| 6491 | #define MT6325_ACCDET_EINT_PWM_FALL_DELAY_MASK 0x1 |
| 6492 | #define MT6325_ACCDET_EINT_PWM_FALL_DELAY_SHIFT 5 |
| 6493 | #define MT6325_ACCDET_EINT_PWM_RISE_DELAY_MASK 0x3FF |
| 6494 | #define MT6325_ACCDET_EINT_PWM_RISE_DELAY_SHIFT 6 |
| 6495 | #define MT6325_ACCDET_TEST_MODE13_MASK 0x1 |
| 6496 | #define MT6325_ACCDET_TEST_MODE13_SHIFT 1 |
| 6497 | #define MT6325_ACCDET_TEST_MODE12_MASK 0x1 |
| 6498 | #define MT6325_ACCDET_TEST_MODE12_SHIFT 2 |
| 6499 | #define MT6325_ACCDET_NVDETECTOUT_SW_MASK 0x1 |
| 6500 | #define MT6325_ACCDET_NVDETECTOUT_SW_SHIFT 3 |
| 6501 | #define MT6325_ACCDET_TEST_MODE11_MASK 0x1 |
| 6502 | #define MT6325_ACCDET_TEST_MODE11_SHIFT 5 |
| 6503 | #define MT6325_ACCDET_TEST_MODE10_MASK 0x1 |
| 6504 | #define MT6325_ACCDET_TEST_MODE10_SHIFT 6 |
| 6505 | #define MT6325_ACCDET_EINTCMPOUT_SW_MASK 0x1 |
| 6506 | #define MT6325_ACCDET_EINTCMPOUT_SW_SHIFT 7 |
| 6507 | #define MT6325_ACCDET_TEST_MODE9_MASK 0x1 |
| 6508 | #define MT6325_ACCDET_TEST_MODE9_SHIFT 9 |
| 6509 | #define MT6325_ACCDET_TEST_MODE8_MASK 0x1 |
| 6510 | #define MT6325_ACCDET_TEST_MODE8_SHIFT 10 |
| 6511 | #define MT6325_ACCDET_AUXADC_CTRL_SW_MASK 0x1 |
| 6512 | #define MT6325_ACCDET_AUXADC_CTRL_SW_SHIFT 11 |
| 6513 | #define MT6325_ACCDET_TEST_MODE7_MASK 0x1 |
| 6514 | #define MT6325_ACCDET_TEST_MODE7_SHIFT 13 |
| 6515 | #define MT6325_ACCDET_TEST_MODE6_MASK 0x1 |
| 6516 | #define MT6325_ACCDET_TEST_MODE6_SHIFT 14 |
| 6517 | #define MT6325_ACCDET_EINTCMP_EN_SW_MASK 0x1 |
| 6518 | #define MT6325_ACCDET_EINTCMP_EN_SW_SHIFT 15 |
| 6519 | #define MT6325_RG_NVCMPSWEN_MASK 0x1 |
| 6520 | #define MT6325_RG_NVCMPSWEN_SHIFT 8 |
| 6521 | #define MT6325_RG_NVMODSEL_MASK 0x1 |
| 6522 | #define MT6325_RG_NVMODSEL_SHIFT 9 |
| 6523 | #define MT6325_RG_SWBUFSWEN_MASK 0x1 |
| 6524 | #define MT6325_RG_SWBUFSWEN_SHIFT 10 |
| 6525 | #define MT6325_RG_SWBUFMODSEL_MASK 0x1 |
| 6526 | #define MT6325_RG_SWBUFMODSEL_SHIFT 11 |
| 6527 | #define MT6325_RG_NVDETVTH_MASK 0x1 |
| 6528 | #define MT6325_RG_NVDETVTH_SHIFT 12 |
| 6529 | #define MT6325_RG_NVDETCMPEN_MASK 0x1 |
| 6530 | #define MT6325_RG_NVDETCMPEN_SHIFT 13 |
| 6531 | #define MT6325_RG_EINTCONFIGACCDET_MASK 0x1 |
| 6532 | #define MT6325_RG_EINTCONFIGACCDET_SHIFT 14 |
| 6533 | #define MT6325_RG_EINTCOMPVTH_MASK 0x1 |
| 6534 | #define MT6325_RG_EINTCOMPVTH_SHIFT 15 |
| 6535 | #define MT6325_ACCDET_EINT_STATE_MASK 0x7 |
| 6536 | #define MT6325_ACCDET_EINT_STATE_SHIFT 0 |
| 6537 | #define MT6325_ACCDET_EINT_CUR_IN_MASK 0x1 |
| 6538 | #define MT6325_ACCDET_EINT_CUR_IN_SHIFT 8 |
| 6539 | #define MT6325_ACCDET_EINT_SAM_IN_MASK 0x1 |
| 6540 | #define MT6325_ACCDET_EINT_SAM_IN_SHIFT 9 |
| 6541 | #define MT6325_ACCDET_EINT_MEM_IN_MASK 0x1 |
| 6542 | #define MT6325_ACCDET_EINT_MEM_IN_SHIFT 10 |
| 6543 | #define MT6325_NVDETECTOUT_MASK 0x1 |
| 6544 | #define MT6325_NVDETECTOUT_SHIFT 13 |
| 6545 | #define MT6325_EINTCMPOUT_MASK 0x1 |
| 6546 | #define MT6325_EINTCMPOUT_SHIFT 14 |
| 6547 | #define MT6325_NI_EINTCMPEN_MASK 0x1 |
| 6548 | #define MT6325_NI_EINTCMPEN_SHIFT 15 |
| 6549 | #define MT6325_ACCDET_NEGV_COUNT_IN_MASK 0x3F |
| 6550 | #define MT6325_ACCDET_NEGV_COUNT_IN_SHIFT 0 |
| 6551 | #define MT6325_ACCDET_NEGV_EN_FINAL_MASK 0x1 |
| 6552 | #define MT6325_ACCDET_NEGV_EN_FINAL_SHIFT 6 |
| 6553 | #define MT6325_ACCDET_NEGV_COUNT_END_MASK 0x1 |
| 6554 | #define MT6325_ACCDET_NEGV_COUNT_END_SHIFT 12 |
| 6555 | #define MT6325_ACCDET_NEGV_MINU_MASK 0x1 |
| 6556 | #define MT6325_ACCDET_NEGV_MINU_SHIFT 13 |
| 6557 | #define MT6325_ACCDET_NEGV_ADD_MASK 0x1 |
| 6558 | #define MT6325_ACCDET_NEGV_ADD_SHIFT 14 |
| 6559 | #define MT6325_ACCDET_NEGV_CMP_MASK 0x1 |
| 6560 | #define MT6325_ACCDET_NEGV_CMP_SHIFT 15 |
| 6561 | #define MT6325_ACCDET_CUR_DEB_MASK 0xFFFF |
| 6562 | #define MT6325_ACCDET_CUR_DEB_SHIFT 0 |
| 6563 | #define MT6325_ACCDET_EINT_CUR_DEB_MASK 0x7FFF |
| 6564 | #define MT6325_ACCDET_EINT_CUR_DEB_SHIFT 0 |
| 6565 | #define MT6325_ACCDET_RSV_CON0_MASK 0xFFFF |
| 6566 | #define MT6325_ACCDET_RSV_CON0_SHIFT 0 |
| 6567 | #define MT6325_ACCDET_RSV_CON1_MASK 0xFFFF |
| 6568 | #define MT6325_ACCDET_RSV_CON1_SHIFT 0 |
| 6569 | #define MT6325_RG_VCDT_HV_EN_MASK 0x1 |
| 6570 | #define MT6325_RG_VCDT_HV_EN_SHIFT 0 |
| 6571 | #define MT6325_RGS_CHR_LDO_DET_MASK 0x1 |
| 6572 | #define MT6325_RGS_CHR_LDO_DET_SHIFT 1 |
| 6573 | #define MT6325_RG_PCHR_AUTOMODE_MASK 0x1 |
| 6574 | #define MT6325_RG_PCHR_AUTOMODE_SHIFT 2 |
| 6575 | #define MT6325_RG_CSDAC_EN_MASK 0x1 |
| 6576 | #define MT6325_RG_CSDAC_EN_SHIFT 3 |
| 6577 | #define MT6325_RG_CHR_EN_MASK 0x1 |
| 6578 | #define MT6325_RG_CHR_EN_SHIFT 4 |
| 6579 | #define MT6325_RGS_CHRDET_MASK 0x1 |
| 6580 | #define MT6325_RGS_CHRDET_SHIFT 5 |
| 6581 | #define MT6325_RGS_VCDT_LV_DET_MASK 0x1 |
| 6582 | #define MT6325_RGS_VCDT_LV_DET_SHIFT 6 |
| 6583 | #define MT6325_RGS_VCDT_HV_DET_MASK 0x1 |
| 6584 | #define MT6325_RGS_VCDT_HV_DET_SHIFT 7 |
| 6585 | #define MT6325_RG_VCDT_LV_VTH_MASK 0xF |
| 6586 | #define MT6325_RG_VCDT_LV_VTH_SHIFT 0 |
| 6587 | #define MT6325_RG_VCDT_HV_VTH_MASK 0xF |
| 6588 | #define MT6325_RG_VCDT_HV_VTH_SHIFT 4 |
| 6589 | #define MT6325_RG_VBAT_CV_EN_MASK 0x1 |
| 6590 | #define MT6325_RG_VBAT_CV_EN_SHIFT 1 |
| 6591 | #define MT6325_RG_VBAT_CC_EN_MASK 0x1 |
| 6592 | #define MT6325_RG_VBAT_CC_EN_SHIFT 2 |
| 6593 | #define MT6325_RG_CS_EN_MASK 0x1 |
| 6594 | #define MT6325_RG_CS_EN_SHIFT 3 |
| 6595 | #define MT6325_RGS_CS_DET_MASK 0x1 |
| 6596 | #define MT6325_RGS_CS_DET_SHIFT 5 |
| 6597 | #define MT6325_RGS_VBAT_CV_DET_MASK 0x1 |
| 6598 | #define MT6325_RGS_VBAT_CV_DET_SHIFT 6 |
| 6599 | #define MT6325_RGS_VBAT_CC_DET_MASK 0x1 |
| 6600 | #define MT6325_RGS_VBAT_CC_DET_SHIFT 7 |
| 6601 | #define MT6325_RG_VBAT_CV_VTH_MASK 0x3F |
| 6602 | #define MT6325_RG_VBAT_CV_VTH_SHIFT 0 |
| 6603 | #define MT6325_RG_VBAT_CC_VTH_MASK 0x3 |
| 6604 | #define MT6325_RG_VBAT_CC_VTH_SHIFT 6 |
| 6605 | #define MT6325_RG_CS_VTH_MASK 0xF |
| 6606 | #define MT6325_RG_CS_VTH_SHIFT 0 |
| 6607 | #define MT6325_RG_PCHR_TOHTC_MASK 0x7 |
| 6608 | #define MT6325_RG_PCHR_TOHTC_SHIFT 0 |
| 6609 | #define MT6325_RG_PCHR_TOLTC_MASK 0x7 |
| 6610 | #define MT6325_RG_PCHR_TOLTC_SHIFT 4 |
| 6611 | #define MT6325_RG_VBAT_OV_EN_MASK 0x1 |
| 6612 | #define MT6325_RG_VBAT_OV_EN_SHIFT 0 |
| 6613 | #define MT6325_RG_VBAT_OV_VTH_MASK 0xF |
| 6614 | #define MT6325_RG_VBAT_OV_VTH_SHIFT 1 |
| 6615 | #define MT6325_RG_VBAT_OV_DEG_MASK 0x1 |
| 6616 | #define MT6325_RG_VBAT_OV_DEG_SHIFT 5 |
| 6617 | #define MT6325_RGS_VBAT_OV_DET_MASK 0x1 |
| 6618 | #define MT6325_RGS_VBAT_OV_DET_SHIFT 6 |
| 6619 | #define MT6325_RG_BATON_EN_MASK 0x1 |
| 6620 | #define MT6325_RG_BATON_EN_SHIFT 0 |
| 6621 | #define MT6325_RG_BATON_HT_EN_RSV0_MASK 0x1 |
| 6622 | #define MT6325_RG_BATON_HT_EN_RSV0_SHIFT 1 |
| 6623 | #define MT6325_BATON_TDET_EN_MASK 0x1 |
| 6624 | #define MT6325_BATON_TDET_EN_SHIFT 2 |
| 6625 | #define MT6325_RG_BATON_HT_TRIM_MASK 0x7 |
| 6626 | #define MT6325_RG_BATON_HT_TRIM_SHIFT 4 |
| 6627 | #define MT6325_RG_BATON_HT_TRIM_SET_MASK 0x1 |
| 6628 | #define MT6325_RG_BATON_HT_TRIM_SET_SHIFT 7 |
| 6629 | #define MT6325_RGS_BATON_UNDET_MASK 0x1 |
| 6630 | #define MT6325_RGS_BATON_UNDET_SHIFT 12 |
| 6631 | #define MT6325_RG_CSDAC_DATA_MASK 0x3FF |
| 6632 | #define MT6325_RG_CSDAC_DATA_SHIFT 0 |
| 6633 | #define MT6325_RG_FRC_CSVTH_USBDL_MASK 0x1 |
| 6634 | #define MT6325_RG_FRC_CSVTH_USBDL_SHIFT 0 |
| 6635 | #define MT6325_RGS_PCHR_FLAG_OUT_MASK 0xF |
| 6636 | #define MT6325_RGS_PCHR_FLAG_OUT_SHIFT 0 |
| 6637 | #define MT6325_RG_PCHR_FLAG_EN_MASK 0x1 |
| 6638 | #define MT6325_RG_PCHR_FLAG_EN_SHIFT 4 |
| 6639 | #define MT6325_RG_OTG_BVALID_EN_MASK 0x1 |
| 6640 | #define MT6325_RG_OTG_BVALID_EN_SHIFT 5 |
| 6641 | #define MT6325_RGS_OTG_BVALID_DET_MASK 0x1 |
| 6642 | #define MT6325_RGS_OTG_BVALID_DET_SHIFT 6 |
| 6643 | #define MT6325_RG_PCHR_FLAG_SEL_MASK 0x3F |
| 6644 | #define MT6325_RG_PCHR_FLAG_SEL_SHIFT 0 |
| 6645 | #define MT6325_RG_PCHR_TESTMODE_MASK 0x1 |
| 6646 | #define MT6325_RG_PCHR_TESTMODE_SHIFT 0 |
| 6647 | #define MT6325_RG_CSDAC_TESTMODE_MASK 0x1 |
| 6648 | #define MT6325_RG_CSDAC_TESTMODE_SHIFT 1 |
| 6649 | #define MT6325_RG_PCHR_RST_MASK 0x1 |
| 6650 | #define MT6325_RG_PCHR_RST_SHIFT 2 |
| 6651 | #define MT6325_RG_PCHR_FT_CTRL_MASK 0x7 |
| 6652 | #define MT6325_RG_PCHR_FT_CTRL_SHIFT 4 |
| 6653 | #define MT6325_RG_CHRWDT_TD_MASK 0xF |
| 6654 | #define MT6325_RG_CHRWDT_TD_SHIFT 0 |
| 6655 | #define MT6325_RG_CHRWDT_EN_MASK 0x1 |
| 6656 | #define MT6325_RG_CHRWDT_EN_SHIFT 4 |
| 6657 | #define MT6325_RG_CHRWDT_WR_MASK 0x1 |
| 6658 | #define MT6325_RG_CHRWDT_WR_SHIFT 8 |
| 6659 | #define MT6325_RG_PCHR_RV_MASK 0xFF |
| 6660 | #define MT6325_RG_PCHR_RV_SHIFT 0 |
| 6661 | #define MT6325_RG_CHRWDT_INT_EN_MASK 0x1 |
| 6662 | #define MT6325_RG_CHRWDT_INT_EN_SHIFT 0 |
| 6663 | #define MT6325_RG_CHRWDT_FLAG_WR_MASK 0x1 |
| 6664 | #define MT6325_RG_CHRWDT_FLAG_WR_SHIFT 1 |
| 6665 | #define MT6325_RGS_CHRWDT_OUT_MASK 0x1 |
| 6666 | #define MT6325_RGS_CHRWDT_OUT_SHIFT 2 |
| 6667 | #define MT6325_RG_USBDL_RST_MASK 0x1 |
| 6668 | #define MT6325_RG_USBDL_RST_SHIFT 2 |
| 6669 | #define MT6325_RG_USBDL_SET_MASK 0x1 |
| 6670 | #define MT6325_RG_USBDL_SET_SHIFT 3 |
| 6671 | #define MT6325_RG_ADCIN_VSEN_MUX_EN_MASK 0x1 |
| 6672 | #define MT6325_RG_ADCIN_VSEN_MUX_EN_SHIFT 8 |
| 6673 | #define MT6325_RG_ADCIN_VSEN_EXT_BATON_EN_MASK 0x1 |
| 6674 | #define MT6325_RG_ADCIN_VSEN_EXT_BATON_EN_SHIFT 9 |
| 6675 | #define MT6325_RG_ADCIN_VBAT_EN_MASK 0x1 |
| 6676 | #define MT6325_RG_ADCIN_VBAT_EN_SHIFT 10 |
| 6677 | #define MT6325_RG_ADCIN_VSEN_EN_MASK 0x1 |
| 6678 | #define MT6325_RG_ADCIN_VSEN_EN_SHIFT 11 |
| 6679 | #define MT6325_RG_ADCIN_CHR_EN_MASK 0x1 |
| 6680 | #define MT6325_RG_ADCIN_CHR_EN_SHIFT 12 |
| 6681 | #define MT6325_RG_UVLO_VTHL_MASK 0x1F |
| 6682 | #define MT6325_RG_UVLO_VTHL_SHIFT 0 |
| 6683 | #define MT6325_RG_UVLO_VH_LAT_MASK 0x1 |
| 6684 | #define MT6325_RG_UVLO_VH_LAT_SHIFT 7 |
| 6685 | #define MT6325_RG_LBAT_INT_VTH_MASK 0x1F |
| 6686 | #define MT6325_RG_LBAT_INT_VTH_SHIFT 0 |
| 6687 | #define MT6325_RG_BGR_RSEL_MASK 0x7 |
| 6688 | #define MT6325_RG_BGR_RSEL_SHIFT 0 |
| 6689 | #define MT6325_RG_BGR_UNCHOP_PH_MASK 0x1 |
| 6690 | #define MT6325_RG_BGR_UNCHOP_PH_SHIFT 4 |
| 6691 | #define MT6325_RG_BGR_UNCHOP_MASK 0x1 |
| 6692 | #define MT6325_RG_BGR_UNCHOP_SHIFT 5 |
| 6693 | #define MT6325_RG_BC11_BB_CTRL_MASK 0x1 |
| 6694 | #define MT6325_RG_BC11_BB_CTRL_SHIFT 0 |
| 6695 | #define MT6325_RG_BC11_RST_MASK 0x1 |
| 6696 | #define MT6325_RG_BC11_RST_SHIFT 1 |
| 6697 | #define MT6325_RG_BC11_VSRC_EN_MASK 0x3 |
| 6698 | #define MT6325_RG_BC11_VSRC_EN_SHIFT 2 |
| 6699 | #define MT6325_RG_BC11_ACA_EN_MASK 0x1 |
| 6700 | #define MT6325_RG_BC11_ACA_EN_SHIFT 4 |
| 6701 | #define MT6325_RGS_BC11_CMP_OUT_MASK 0x1 |
| 6702 | #define MT6325_RGS_BC11_CMP_OUT_SHIFT 7 |
| 6703 | #define MT6325_RG_BC11_VREF_VTH_MASK 0x3 |
| 6704 | #define MT6325_RG_BC11_VREF_VTH_SHIFT 0 |
| 6705 | #define MT6325_RG_BC11_CMP_EN_MASK 0x3 |
| 6706 | #define MT6325_RG_BC11_CMP_EN_SHIFT 2 |
| 6707 | #define MT6325_RG_BC11_IPD_EN_MASK 0x3 |
| 6708 | #define MT6325_RG_BC11_IPD_EN_SHIFT 4 |
| 6709 | #define MT6325_RG_BC11_IPU_EN_MASK 0x3 |
| 6710 | #define MT6325_RG_BC11_IPU_EN_SHIFT 6 |
| 6711 | #define MT6325_RG_BC11_BIAS_EN_MASK 0x1 |
| 6712 | #define MT6325_RG_BC11_BIAS_EN_SHIFT 8 |
| 6713 | #define MT6325_RG_CSDAC_STP_INC_MASK 0x7 |
| 6714 | #define MT6325_RG_CSDAC_STP_INC_SHIFT 0 |
| 6715 | #define MT6325_RG_CSDAC_STP_DEC_MASK 0x7 |
| 6716 | #define MT6325_RG_CSDAC_STP_DEC_SHIFT 4 |
| 6717 | #define MT6325_RG_CSDAC_DLY_MASK 0x7 |
| 6718 | #define MT6325_RG_CSDAC_DLY_SHIFT 0 |
| 6719 | #define MT6325_RG_CSDAC_STP_MASK 0x7 |
| 6720 | #define MT6325_RG_CSDAC_STP_SHIFT 4 |
| 6721 | #define MT6325_RG_LOW_ICH_DB_MASK 0x3F |
| 6722 | #define MT6325_RG_LOW_ICH_DB_SHIFT 0 |
| 6723 | #define MT6325_RG_CHRIND_ON_MASK 0x1 |
| 6724 | #define MT6325_RG_CHRIND_ON_SHIFT 6 |
| 6725 | #define MT6325_RG_CHRIND_DIMMING_MASK 0x1 |
| 6726 | #define MT6325_RG_CHRIND_DIMMING_SHIFT 7 |
| 6727 | #define MT6325_RG_CV_MODE_MASK 0x1 |
| 6728 | #define MT6325_RG_CV_MODE_SHIFT 0 |
| 6729 | #define MT6325_RG_VCDT_MODE_MASK 0x1 |
| 6730 | #define MT6325_RG_VCDT_MODE_SHIFT 1 |
| 6731 | #define MT6325_RG_CSDAC_MODE_MASK 0x1 |
| 6732 | #define MT6325_RG_CSDAC_MODE_SHIFT 2 |
| 6733 | #define MT6325_RG_TRACKING_EN_MASK 0x1 |
| 6734 | #define MT6325_RG_TRACKING_EN_SHIFT 4 |
| 6735 | #define MT6325_RG_HWCV_EN_MASK 0x1 |
| 6736 | #define MT6325_RG_HWCV_EN_SHIFT 6 |
| 6737 | #define MT6325_RG_ULC_DET_EN_MASK 0x1 |
| 6738 | #define MT6325_RG_ULC_DET_EN_SHIFT 7 |
| 6739 | #define MT6325_RG_BGR_TRIM_EN_MASK 0x1 |
| 6740 | #define MT6325_RG_BGR_TRIM_EN_SHIFT 0 |
| 6741 | #define MT6325_RG_ICHRG_TRIM_MASK 0xF |
| 6742 | #define MT6325_RG_ICHRG_TRIM_SHIFT 4 |
| 6743 | #define MT6325_RG_BGR_TRIM_MASK 0x1F |
| 6744 | #define MT6325_RG_BGR_TRIM_SHIFT 0 |
| 6745 | #define MT6325_RG_OVP_TRIM_MASK 0xF |
| 6746 | #define MT6325_RG_OVP_TRIM_SHIFT 0 |
| 6747 | #define MT6325_RG_CHR_OSC_TRIM_MASK 0x1F |
| 6748 | #define MT6325_RG_CHR_OSC_TRIM_SHIFT 0 |
| 6749 | #define MT6325_QI_BGR_EXT_BUF_EN_MASK 0x1 |
| 6750 | #define MT6325_QI_BGR_EXT_BUF_EN_SHIFT 5 |
| 6751 | #define MT6325_RG_BGR_TEST_EN_MASK 0x1 |
| 6752 | #define MT6325_RG_BGR_TEST_EN_SHIFT 6 |
| 6753 | #define MT6325_RG_BGR_TEST_RSTB_MASK 0x1 |
| 6754 | #define MT6325_RG_BGR_TEST_RSTB_SHIFT 7 |
| 6755 | #define MT6325_RG_DAC_USBDL_MAX_MASK 0x3FF |
| 6756 | #define MT6325_RG_DAC_USBDL_MAX_SHIFT 0 |
| 6757 | #define MT6325_RG_CM_VDEC_TRIG_MASK 0x1 |
| 6758 | #define MT6325_RG_CM_VDEC_TRIG_SHIFT 0 |
| 6759 | #define MT6325_PCHR_CM_VDEC_STATUS_MASK 0x3 |
| 6760 | #define MT6325_PCHR_CM_VDEC_STATUS_SHIFT 4 |
| 6761 | #define MT6325_RG_CM_VINC_TRIG_MASK 0x1 |
| 6762 | #define MT6325_RG_CM_VINC_TRIG_SHIFT 0 |
| 6763 | #define MT6325_PCHR_CM_VINC_STATUS_MASK 0x3 |
| 6764 | #define MT6325_PCHR_CM_VINC_STATUS_SHIFT 4 |
| 6765 | #define MT6325_RG_CM_VDEC_HPRD1_MASK 0x3F |
| 6766 | #define MT6325_RG_CM_VDEC_HPRD1_SHIFT 0 |
| 6767 | #define MT6325_RG_CM_VDEC_HPRD2_MASK 0x3F |
| 6768 | #define MT6325_RG_CM_VDEC_HPRD2_SHIFT 8 |
| 6769 | #define MT6325_RG_CM_VDEC_HPRD3_MASK 0x3F |
| 6770 | #define MT6325_RG_CM_VDEC_HPRD3_SHIFT 0 |
| 6771 | #define MT6325_RG_CM_VDEC_HPRD4_MASK 0x3F |
| 6772 | #define MT6325_RG_CM_VDEC_HPRD4_SHIFT 8 |
| 6773 | #define MT6325_RG_CM_VDEC_HPRD5_MASK 0x3F |
| 6774 | #define MT6325_RG_CM_VDEC_HPRD5_SHIFT 0 |
| 6775 | #define MT6325_RG_CM_VDEC_HPRD6_MASK 0x3F |
| 6776 | #define MT6325_RG_CM_VDEC_HPRD6_SHIFT 8 |
| 6777 | #define MT6325_RG_CM_VINC_HPRD1_MASK 0x3F |
| 6778 | #define MT6325_RG_CM_VINC_HPRD1_SHIFT 0 |
| 6779 | #define MT6325_RG_CM_VINC_HPRD2_MASK 0x3F |
| 6780 | #define MT6325_RG_CM_VINC_HPRD2_SHIFT 8 |
| 6781 | #define MT6325_RG_CM_VINC_HPRD3_MASK 0x3F |
| 6782 | #define MT6325_RG_CM_VINC_HPRD3_SHIFT 0 |
| 6783 | #define MT6325_RG_CM_VINC_HPRD4_MASK 0x3F |
| 6784 | #define MT6325_RG_CM_VINC_HPRD4_SHIFT 8 |
| 6785 | #define MT6325_RG_CM_VINC_HPRD5_MASK 0x3F |
| 6786 | #define MT6325_RG_CM_VINC_HPRD5_SHIFT 0 |
| 6787 | #define MT6325_RG_CM_VINC_HPRD6_MASK 0x3F |
| 6788 | #define MT6325_RG_CM_VINC_HPRD6_SHIFT 8 |
| 6789 | #define MT6325_RG_CM_LPRD_MASK 0x3F |
| 6790 | #define MT6325_RG_CM_LPRD_SHIFT 0 |
| 6791 | #define MT6325_RG_CM_CS_VTHL_MASK 0xF |
| 6792 | #define MT6325_RG_CM_CS_VTHL_SHIFT 0 |
| 6793 | #define MT6325_RG_CM_CS_VTHH_MASK 0xF |
| 6794 | #define MT6325_RG_CM_CS_VTHH_SHIFT 4 |
| 6795 | #define MT6325_RG_PCHR_RSV_MASK 0xFF |
| 6796 | #define MT6325_RG_PCHR_RSV_SHIFT 0 |
| 6797 | #define MT6325_EOSC_CALI_START_MASK 0x1 |
| 6798 | #define MT6325_EOSC_CALI_START_SHIFT 0 |
| 6799 | #define MT6325_EOSC_CALI_START_SET_MASK 0x1 |
| 6800 | #define MT6325_EOSC_CALI_START_SET_SHIFT 1 |
| 6801 | #define MT6325_EOSC_CALI_TD_MASK 0x7 |
| 6802 | #define MT6325_EOSC_CALI_TD_SHIFT 5 |
| 6803 | #define MT6325_EOSC_CALI_TD_SET_MASK 0x1 |
| 6804 | #define MT6325_EOSC_CALI_TD_SET_SHIFT 8 |
| 6805 | #define MT6325_EOSC_CALI_TEST_MASK 0xF |
| 6806 | #define MT6325_EOSC_CALI_TEST_SHIFT 9 |
| 6807 | #define MT6325_EOSC_CALI_FLAG_SEL_MASK 0xF |
| 6808 | #define MT6325_EOSC_CALI_FLAG_SEL_SHIFT 0 |
| 6809 | #define MT6325_EOSC_CALI_FLAG_EN_MASK 0x1 |
| 6810 | #define MT6325_EOSC_CALI_FLAG_EN_SHIFT 4 |
| 6811 | #define MT6325_FRC_VTCXO0_ON_MASK 0x1 |
| 6812 | #define MT6325_FRC_VTCXO0_ON_SHIFT 8 |
| 6813 | #define MT6325_FRC_VTCXO0_ON_SET_MASK 0x1 |
| 6814 | #define MT6325_FRC_VTCXO0_ON_SET_SHIFT 9 |
| 6815 | #define MT6325_EOSC_CALI_RSV_SET_MASK 0x1 |
| 6816 | #define MT6325_EOSC_CALI_RSV_SET_SHIFT 10 |
| 6817 | #define MT6325_EOSC_CALI_RSV_MASK 0xF |
| 6818 | #define MT6325_EOSC_CALI_RSV_SHIFT 11 |
| 6819 | |
| 6820 | #endif // #ifdef PMIC_6325_REG_API |
| 6821 | #endif // #ifndef __DCL_PMIC6325_HW_H_STRUCT__ |
| 6822 | |