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rjw6c1fd8f2022-11-30 14:33:01 +08001/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
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13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
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15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
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19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
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21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * drv_asm.h
41 *
42 * Project:
43 * --------
44 * UMOLY_Software
45 *
46 * Description:
47 * ------------
48 * This file defines ASM drivers interface
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *==============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58
59 *------------------------------------------------------------------------------
60 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
61 *============================================================================
62 ****************************************************************************/
63
64#ifndef __DRV_ASM_H__
65#define __DRV_ASM_H__
66
67#include "kal_general_types.h"
68
69typedef enum {
70 ASM_SW_SWLA_MODE = 0,
71 ASM_SW_SWTR_MODE,
72 ASM_HW_SWLA_STRAM_MODE,
73 ASM_HW_SWLA_WRAP_MODE,
74 ASM_HW_SWTR_STRAM_MODE,
75 ASM_HW_SWTR_WRAP_MODE,
76 ASM_MODE_END
77}ASM_MODE;
78
79#if defined (__MD93__)
80
81typedef enum
82{
83 ASM_CORE0_INT = 0,
84 ASM_CORE1_INT,
85}ASM_INT_CORE_NUM;
86
87
88typedef enum
89{
90 ASM_CORE0 = 0,
91 ASM_CORE1,
92 ASM_NUM
93}ASM_MCU_CORE;
94
95typedef enum
96{
97 ASM_TC_ID_CORE_ID_EN = 0,
98 ASM_PC_EN,
99 ASM_MCU_PMC0_EN,
100 ASM_MCU_PMC1_EN,
101 ASM_MCU_ELM_CNT0_EN,
102 ASM_MCU_ELM_CNT1_EN,
103 ASM_MCU_ELM_CNT2_EN,
104 ASM_MCU_ELM_CNT3_EN,
105 ASM_ADDON_INFO0_EN,
106 ASM_ADDON_INFO1_EN,
107 ASM_ADDON_INFO2_EN,
108 ASM_ADDON_INFO3_EN,
109 ASM_PROFILE_END,
110}ASM_PROFILE_OPTION;
111
112
113
114#elif defined (__MD95__)
115
116typedef enum
117{
118 ASM_CORE0_INT = 0,
119 ASM_CORE1_INT,
120#ifndef __MD95_IS_2CORES__
121 ASM_CORE2_INT,
122#endif // ifndef(__MD95_IS_2CORES__)
123}ASM_INT_CORE_NUM;
124
125
126typedef enum
127{
128 ASM_CORE0 = 0,
129 ASM_CORE1,
130#ifndef __MD95_IS_2CORES__
131 ASM_CORE2,
132#endif // ifndef(__MD95_IS_2CORES__)
133 ASM_NUM
134}ASM_MCU_CORE;
135
136typedef enum
137{
138 ASM_TC_ID_CORE_ID_EN = 0,
139 ASM_PC_EN,
140 ASM_MCU_PMC0_EN,
141 ASM_MCU_PMC1_EN,
142 ASM_MCU_ELM_CNT0_EN,
143 ASM_MCU_ELM_CNT1_EN,
144 ASM_MCU_ELM_CNT2_EN,
145 ASM_MCU_ELM_CNT3_EN,
146 ASM_MCU_ELM_CNT4_EN,
147 ASM_MCU_ELM_CNT5_EN,
148 ASM_ADDON_INFO0_EN,
149 ASM_ADDON_INFO1_EN,
150 ASM_ADDON_INFO2_EN,
151 ASM_ADDON_INFO3_EN,
152 ASM_PROFILE_END,
153}ASM_PROFILE_OPTION;
154
155
156#else
157
158typedef enum
159{
160 ASM_CORE0_INT = 0,
161 ASM_CORE1_INT,
162 ASM_CORE2_INT,
163 ASM_CORE3_INT,
164}ASM_INT_CORE_NUM;
165
166
167typedef enum
168{
169 ASM_CORE0 = 0,
170 ASM_CORE1,
171 ASM_CORE2,
172 ASM_CORE3,
173 ASM_NUM
174}ASM_MCU_CORE;
175
176
177typedef enum
178{
179 ASM_TC_ID_CORE_ID_EN = 0,
180 ASM_PC_EN,
181 ASM_MCU_PMC0_EN,
182 ASM_MCU_PMC1_EN,
183 ASM_MCU_ELM_CNT0_EN,
184 ASM_MCU_ELM_CNT1_EN,
185 ASM_MCU_ELM_CNT2_EN,
186 ASM_MCU_ELM_CNT3_EN,
187 ASM_MCU_ELM_CNT4_EN,
188 ASM_MCU_ELM_CNT5_EN,
189 ASM_ADDON_INFO0_EN,
190 ASM_ADDON_INFO1_EN,
191 ASM_ADDON_INFO2_EN,
192 ASM_ADDON_INFO3_EN,
193 ASM_PROFILE_END,
194}ASM_PROFILE_OPTION;
195
196
197#endif // if defined (__MD93__)
198
199
200
201typedef enum
202{
203 ASM_THRESHOLD_INT = 0,
204 ASM_AGGRESSIVE_TRIG_INT,
205 ASM_APB_WR_GCR_ILLEGAL_INT,
206 ASM_ILLEGAL_DISABLE_INT,
207 ASM_PDI_INT,
208}ASM_INT_TYPE;
209
210
211
212typedef enum
213{
214 ASM_ERROR_CODE_NO_ERROR = 0, // NO error
215 ASM_ERROR_CODE_BUFFER_TOO_SMALL, // Buffer size is less than 1KB
216 ASM_ERROR_CODE_BUFFER_TOO_LARGE, // Buffer size is over limitation
217 ASM_ERROR_CODE_WRONG_MODE, // ASM mode is not defined
218 ASM_ERROR_CODE_WAIT_IDLE_FAIL, // wait idle timeout
219 ASM_ERROR_CODE_OVER_ADDON_INDEX, // start index is not druing addon range
220 ASM_ERROR_CODE_OVER_ADDON_SIZE, // addon size over 8
221 ASM_ERROR_CODE_INVALID_SAMPLE_RATE, // sampeling = 0
222 ASM_ERROR_CODE_INVALID_RW_POINTER, // invalid r/w pointer
223
224}ASM_ERROR_CODE;
225
226//////////////////ASM API/////////////////////////////
227
228//#define ASM_SendTriggerCmd(core,tc) {kal_uint32 val;ASM_SET_SWLA_TRIG(core,tc);ASM_GET_SWLA_TRIG(core,val);}
229
230void ASM_GetBufferInfor(kal_uint32 core,kal_uint32* addr,kal_uint32* size, kal_uint32* read_addr, kal_uint32* write_addr);
231ASM_ERROR_CODE ASM_GetBufReadWriteAddress(kal_uint32 core,kal_uint32* rd_addr, kal_uint32* wr_addr,kal_uint32 *remain_size);
232void ASM_UpdateBufReadAddress(kal_uint32 core,kal_uint32 addr);
233
234void ASM_GetBufReadWritePtr(kal_uint32 core,kal_uint32* rd_ptr, kal_uint32* wr_ptr);
235kal_uint32 ASM_GetBufferSettingSize(kal_uint32 core);
236kal_bool ASM_BufferIsWrap(kal_uint32 core);
237void ASM_UpdateBufReadPtr(kal_uint32 core,kal_uint32 addr);
238
239
240ASM_ERROR_CODE ASM_InitSetting(kal_uint32 core,kal_uint32 mode, kal_uint32 *buffer,kal_uint32 buffer_size,kal_uint32 option_en,kal_uint32 sampling_rate);
241ASM_ERROR_CODE ASM_Start(kal_uint32 core);
242ASM_ERROR_CODE ASM_Stop(kal_uint32 core);
243void ASM_StopWithoutWaitIdle(kal_uint32 core);
244void ASM_SetSwtrTc(kal_uint32 core,kal_uint32 value);
245ASM_ERROR_CODE ASM_SetMcuSwtrAuto(kal_uint32 core);
246
247void ASM_McuIntRegsterLISR(void* reg_lisr);
248void ASM_McuIntIRQUnMask(void);
249void ASM_McuIntIRQMask(void);
250void ASM_McuCoreIntIRQMask(kal_uint32 core);
251void ASM_McuCoreIntIRQUnMask(kal_uint32 core);
252void ASM_McuCoreIntIRQAck(kal_uint32 core);
253void ASM_GetMcuIntStatusAndMask(kal_uint32* status,kal_uint32* mask);
254
255void Asm_InitInforAllCore(void);
256ASM_ERROR_CODE ASM_SetAddon(kal_uint32 core,kal_uint32 tc,kal_uint32* addon_infor,kal_uint32 size,kal_uint32 start_index );
257kal_uint32 ASM_GetBufferWrapCnt(kal_uint32 core);
258void ASM_EnableApbWrite(kal_uint32 core);
259void ASM_DisableApbWrite(kal_uint32 core);
260void ASM_SendTrigger(kal_uint32 core,kal_uint32 tc);
261
262//extern ASM_STRUCT Asm_Infor[];
263//void ASM_SendTrigger(kal_uint32 core, kal_uint32 tc);
264//#define ASM_SendTrigger(core,tc) {Asm_Infor[core].trigger_cnt++; ASM_SET_GCR_SWLA_TRIG(core,tc);}
265//#define ASM_SendTrigger(core,tc) {Asm_Infor[core].trigger_cnt++; ASM_SET_SWLA_TRIG(core,tc);}
266#define ASM_SendAPBTrigger(core,tc) ASM_SET_SWLA_TRIG(core,tc)
267#define ASM_SendGCRTrigger(core,tc) ASM_SET_GCR_SWLA_TRIG(core,tc)
268
269kal_uint32 ASM_GetPDICnt(kal_uint32 core);
270
271void ASM_SaveConfigForSPM_AllCore(void);
272void ASM_SaveCoreConfigForSPM(void);
273void ASM_SaveConfigForSPM(kal_uint32 core);
274void ASM_RestoreConfigforSPM_AllCore(void);
275void ASM_RestoreCoreConfigforSPM(void);
276void ASM_RestoreConfigforSPM(kal_uint32 core);
277
278void ASM_SetTCContextID(kal_uint32 core, kal_uint32 tc,kal_uint32 id);
279kal_uint32 ASM_GetTcContextId(kal_uint32 core,kal_uint32 tc);
280
281kal_uint32 ASM_GetSRAMWaterLevel(kal_uint32 core);
282void ASM_SetDumpRegion(void);
283
284
285
286#endif //__DRV_ASM_H__