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192.168.1.100 / T800_MD / 6c1fd8fba87d5723e0e5614ae30b4258b603cb70 / . / mcu / interface / driver / devdrv / busmpu / gen97_busmpu.h
blob: 3c3b11f0b926973f35c56fcace62dfc26ff43625 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame^]1#ifndef __GEN97_BUSMPU_H__
2#define __GEN97_BUSMPU_H__
3
4#if defined(MT6297) || defined(CHIP10992)
5#define EMIMPU_MD2AP_INFODUMP_ENABLE
6#endif
7
8/*****************************************************************************
9 * Symbol/Type Definition *
10 *****************************************************************************/
11typedef kal_uint32 FIELD;
12
13/**
14 * 0x00 : MPU_IOCU_CTRL
15 */
16typedef union {
17 struct {
18 FIELD reg_mpu_iocu_disable : 1; //default:1 (RW)
19 FIELD reg_mpu_iocu_bank2_default_pms : 2; //default:3 (RW)
20 FIELD reg_mpu_iocu_bank3_default_pms : 2; //default:3 (RW)
21 FIELD reg_mpu_iocu_bank9f_default_pms : 2; //default:3 (RW)
22 FIELD reg_mpu_iocu_err_trig_mode : 1; //default:0 (RW)
23 FIELD reg_mpu_iocu_vio_clr : 1; //default:0 (W1C)
24 FIELD reg_mpu_iocu_vio_info_clr : 1; //default:0 (W1C)
25 FIELD reg_mpu_iocu_int_en : 1; //default:1 (RW)
26 FIELD reg_mpu_iocu_align_int_en : 1; //default:0 (RW)
27 FIELD reg_mpu_ctrl_update : 1; //default:0 (WP)
28 FIELD reg_mpu_algin_rule_sel : 1; //default:0 (RW)
29 FIELD reg_mpu_iocu_int_msk : 1; //default:1 (RW)
30 FIELD reg_mpu_unused : 16;
31 FIELD reg_speed_sim : 1; //default:0 (RW)
32 } Bits;
33 FIELD Raw;
34} busmpu_iocu_ctrl, *pbusmpu_iocu_ctrl;
35
36/**
37 * 0x04 : MPU_IOCU_IRQ_STS
38 */
39typedef union {
40 struct {
41 FIELD o_vio_mpu_iocu_wt : 1; //default:0 (RU)
42 FIELD o_vio_mpu_iocu_rd : 1; //default:0 (RU)
43 FIELD o_vio_mpu_iocu_wt_align : 1; //default:0 (RU)
44 FIELD o_vio_mpu_iocu_rd_align : 1; //default:0 (RU)
45 FIELD o_vio_mpu_iocu_int_status : 1; //default:0 (RU)
46 FIELD o_vio_mpu_iocu_id : 12;//default:0 (RU)
47 FIELD o_vio_mpu_iocu_ro : 1; //default:0 (RU)
48 FIELD o_vio_mpu_iocu_region : 5; //default:0 (RU)
49 FIELD o_vio_mpu_iocu_burst : 2; //default:0 (RU)
50 FIELD o_vio_mpu_iocu_size : 3; //default:0 (RU)
51 FIELD o_vio_mpu_iocu_len : 4; //default:0 (RU)
52 } Bits;
53 FIELD Raw;
54} busmpu_irq_status, *pbusmpu_irq_status;
55
56/**
57 * 0x8 : MPU_IOCU_VIO_ADDR
58 */
59typedef union {
60 struct {
61 FIELD iocu_vio_addr : 32; //default:0 (RU)
62 } Bits;
63 FIELD Raw;
64} busmpu_iocu_vio_addr, *pbusmpu_iocu_vio_addr;
65
66typedef struct {
67 busmpu_iocu_vio_addr addr;
68} busmpu_iocu_vio_data, busmpu_mdinfra_error_info_st;
69
70typedef volatile struct {
71 busmpu_iocu_ctrl iocu_ctrl; // 0000
72} busmpu_reg, *pbusmpu_reg;
73
74typedef struct{
75 kal_uint32 axi_id;
76 kal_uint32 port_id;
77 kal_uint32 vio_addr;
78 kal_uint32 wt_vio;
79 kal_uint32 rd_vio;
80} emimpu_vio_info_debug;
81
82
83typedef struct{
84 kal_uint32 mpus;
85 kal_uint32 mput;
86 kal_uint32 mput_2;
87 emimpu_vio_info_debug emimpu_info_debug;
88} emimpu_vio_info;
89
90//init RMPU & busmpu @HWDInitialization
91extern void rmpu_md_init(void);
92
93//dump busmpu info called by exception handler
94extern kal_bool busmpu_mdinfra_dump_err(void);
95extern kal_bool busmpu_dump_irq_sts(void);
96extern volatile busmpu_iocu_vio_data busmpu_iocu_err;
97extern volatile busmpu_irq_status busmpu_irq_sts;
98#if defined(EMIMPU_MD2AP_INFODUMP_ENABLE)
99extern volatile emimpu_vio_info emimpu_vio_dump;
100#endif
101
102//for bank2 wb
103extern void busmpu_wb_permission(kal_uint32 start_addr, kal_uint32 end_addr, kal_uint32 mask_filter, kal_uint32 busid);
104
105//bank2
106extern kal_uint32 IOCU2_00_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
107extern kal_uint32 IOCU2_00_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
108extern kal_uint32 IOCU2_01_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
109extern kal_uint32 IOCU2_01_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
110extern kal_uint32 IOCU2_02_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
111extern kal_uint32 IOCU2_02_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
112extern kal_uint32 IOCU2_03_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
113extern kal_uint32 IOCU2_03_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
114extern kal_uint32 IOCU2_04_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
115extern kal_uint32 IOCU2_04_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
116extern kal_uint32 IOCU2_05_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
117extern kal_uint32 IOCU2_05_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
118extern kal_uint32 IOCU2_06_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
119extern kal_uint32 IOCU2_06_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
120extern kal_uint32 IOCU2_07_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
121extern kal_uint32 IOCU2_07_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
122extern kal_uint32 IOCU2_08_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
123extern kal_uint32 IOCU2_08_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
124extern kal_uint32 IOCU2_09_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
125extern kal_uint32 IOCU2_09_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
126extern kal_uint32 IOCU2_10_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
127extern kal_uint32 IOCU2_10_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
128extern kal_uint32 IOCU2_11_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
129extern kal_uint32 IOCU2_11_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
130extern kal_uint32 IOCU2_12_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
131extern kal_uint32 IOCU2_12_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
132extern kal_uint32 IOCU2_13_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
133extern kal_uint32 IOCU2_13_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
134extern kal_uint32 IOCU2_14_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
135extern kal_uint32 IOCU2_14_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
136extern kal_uint32 IOCU2_15_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
137extern kal_uint32 IOCU2_15_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
138
139//bank3
140extern kal_uint32 IOCU3_00_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
141extern kal_uint32 IOCU3_00_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
142extern kal_uint32 IOCU3_01_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
143extern kal_uint32 IOCU3_01_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
144extern kal_uint32 IOCU3_02_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
145extern kal_uint32 IOCU3_02_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
146extern kal_uint32 IOCU3_03_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
147extern kal_uint32 IOCU3_03_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
148extern kal_uint32 IOCU3_04_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
149extern kal_uint32 IOCU3_04_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
150extern kal_uint32 IOCU3_05_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
151extern kal_uint32 IOCU3_05_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
152extern kal_uint32 IOCU3_06_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
153extern kal_uint32 IOCU3_06_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
154extern kal_uint32 IOCU3_07_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
155extern kal_uint32 IOCU3_07_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
156extern kal_uint32 IOCU3_08_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
157extern kal_uint32 IOCU3_08_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
158extern kal_uint32 IOCU3_09_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
159extern kal_uint32 IOCU3_09_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
160extern kal_uint32 IOCU3_10_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
161extern kal_uint32 IOCU3_10_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
162extern kal_uint32 IOCU3_11_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
163extern kal_uint32 IOCU3_11_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
164extern kal_uint32 IOCU3_12_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
165extern kal_uint32 IOCU3_12_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
166extern kal_uint32 IOCU3_13_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
167extern kal_uint32 IOCU3_13_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
168extern kal_uint32 IOCU3_14_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
169extern kal_uint32 IOCU3_14_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
170extern kal_uint32 IOCU3_15_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
171extern kal_uint32 IOCU3_15_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
172#endif /*__GEN97_BUSMPU_H__*/
173