| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame^] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2012 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /******************************************************************************* |
| 37 | * Filename: |
| 38 | * --------- |
| 39 | * pcie.h |
| 40 | * |
| 41 | * Project: |
| 42 | * -------- |
| 43 | * VMOLY |
| 44 | * |
| 45 | * Description: |
| 46 | * ------------ |
| 47 | * PCIE device driver |
| 48 | * |
| 49 | * Author: |
| 50 | * ------- |
| 51 | * ------- |
| 52 | * |
| 53 | * ========================================================================== |
| 54 | * $Log$ |
| 55 | * |
| 56 | * 10 09 2020 cindy.tu |
| 57 | * [MOLY00579078] [MT6880][Colgin][M.2][Low Power] Colgin Data Card(連 RVP) Flight mode suspend current: 4.3 mA > target 4.1 mA |
| 58 | * |
| 59 | * . |
| 60 | * |
| 61 | * 08 14 2020 cody.lee |
| 62 | * [MOLY00558825] [Colgin] PCIE Loopback Test - add test option for one lane |
| 63 | * . |
| 64 | * |
| 65 | * 07 16 2020 cindy.tu |
| 66 | * [MOLY00520457] [PCIE][Colgin] PCIE driver |
| 67 | * Fix modis link error. |
| 68 | * |
| 69 | * 07 13 2020 cody.lee |
| 70 | * [MOLY00545672] [Colgin] PCIE MTCMOS CTRL API |
| 71 | * |
| 72 | * 06 01 2020 cindy.tu |
| 73 | * [MOLY00520457] [PCIE][Colgin] PCIE driver |
| 74 | * |
| 75 | * Sync pcie driver and fix build error |
| 76 | * |
| 77 | * 05 25 2020 cindy.tu |
| 78 | * [MOLY00503259] [PCIE][M70] PCIE link API |
| 79 | * |
| 80 | * Set SPM to use high speed clock instead of 32K when PCIE in low power state |
| 81 | * |
| 82 | * |
| 83 | ****************************************************************************/ |
| 84 | |
| 85 | #ifndef __PCIE_IF_H__ |
| 86 | #define __PCIE_IF_H__ |
| 87 | |
| 88 | typedef enum{ |
| 89 | PCIE_LINK_READY = 0, |
| 90 | PCIE_NOT_INIT_ERR = 1, |
| 91 | PCIE_LINK_NOT_READY = 2, |
| 92 | PCIE_LINK_NOT_STABLE = 3, |
| 93 | PCIE_LINK_UNKNOWN = 0xF, |
| 94 | }PCIE_detect_result_e; |
| 95 | typedef struct _pcie_link_status{ |
| 96 | kal_uint32 lane_num; |
| 97 | kal_uint32 rate_level; |
| 98 | }pcie_link_status_t; |
| 99 | |
| 100 | PCIE_detect_result_e pcie_detect(void); |
| 101 | |
| 102 | #ifdef __MTK_TARGET__ |
| 103 | PCIE_detect_result_e pcie_get_link_state(void); |
| 104 | #else |
| 105 | #define pcie_get_link_state() (PCIE_LINK_UNKNOWN) |
| 106 | #endif |
| 107 | |
| 108 | void pcie_report_link_status(pcie_link_status_t* pcie_link_status); |
| 109 | |
| 110 | extern kal_bool pcie_phy_loopback_test(kal_uint32); |
| 111 | |
| 112 | extern void pcie_mac_mtcmos_ctrl(kal_bool); |
| 113 | extern void pcie_phy_mtcmos_ctrl(kal_bool); |
| 114 | extern void pcie_cg_enable(void); |
| 115 | extern void pcie_cg_disable(void); |
| 116 | |
| 117 | #endif |