Blame - mcu/interface/driver/devdrv/pll/pll_gen97p.h - T800_MD

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/*******************************************************************************

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* Copyright Statement:

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* --------------------

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* This software is protected by Copyright and the information contained

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* herein is confidential. The software may not be copied and the information

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* contained herein may not be used or disclosed except with the written

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*

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* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES

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* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")

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* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON

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* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,

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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF

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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.

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* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE

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* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR

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* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH

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* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO

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* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S

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* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.

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*

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* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE

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* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,

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* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,

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* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO

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* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.

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*

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* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE

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* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF

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* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND

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* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER

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* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).

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*

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******************************************************************************/

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/*******************************************************************************

* Filename:

* ---------

* pll_gen97p.h

*

* Project:

* --------

* UMOLYE

*

* Description:

* ------------

* PLL Related Functions

*

* Author:

* -------

* -------

*

* ============================================================================

* $Log$

*

*

*

****************************************************************************/

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#ifndef __PLL_MT6297P_H__

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#define __PLL_MT6297P_H__

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//wolf: the code below is not ready, just for build pass~

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/*******************************************************************************

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* Locally Used Options

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******************************************************************************/

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#define PLL_REG32(addr) *(volatile kal_uint32 *)(addr)

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#define PLL_TYPE (volatile kal_uint32 *)

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/*******************************************************************************

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* Define macro for boot code

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******************************************************************************/

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#define __SECTION__(S) __attribute__((__section__(#S)))

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#define __PLL_CODE_IN_BOOT__ __SECTION__(BR_EXT)/* "BR_EXT" section for bootROM */

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/*******************************************************************************

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* Register Define

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******************************************************************************/

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///////////////////////////////////////////////////////////////////////////////

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/// PLLMIXED (0xA0140000)

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///////////////////////////////////////////////////////////////////////////////

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/* ==========PLL setting========== */

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#define REG_MDTOP_PLLMIXED_CODA_VERSION (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x0))

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#define REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4))

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#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8))

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#define REG_MDTOP_PLLMIXED_DCXO_MODE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC))

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#define REG_MDTOP_PLLMIXED_PLL_ON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10))

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#define REG_MDTOP_PLLMIXED_PLL_SW_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x14))

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#define REG_MDTOP_PLLMIXED_PLL_SW_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x18))

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#define REG_MDTOP_PLLMIXED_PLL_SW_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x1C))

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#define REG_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x20))

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#define REG_MDTOP_PLLMIXED_RF_SETTLE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x24))

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#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30))

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#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x34))

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#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x38))

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/* ==========PLL frequency control==> PCW & POSDIV========== */

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#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x40))

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#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x44))

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#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x48))

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#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4C))

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#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50))

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#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54))

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#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x58))

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#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C))

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#define REG_MDTOP_PLLMIXED_MDNRPLL0_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x68))

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#define REG_MDTOP_PLLMIXED_MDNRPLL0_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x6C))

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#define REG_MDTOP_PLLMIXED_MDNRPLL1_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x70))

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#define REG_MDTOP_PLLMIXED_MDNRPLL1_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x74))

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#define REG_MDTOP_PLLMIXED_MDNRPLL2_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x78))

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#define REG_MDTOP_PLLMIXED_MDNRPLL2_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x7C))

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#define REG_MDTOP_PLLMIXED_MDNRPLL3_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x80))

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#define REG_MDTOP_PLLMIXED_MDNRPLL3_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x84))

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#define REG_MDTOP_PLLMIXED_MDNRPLL4_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x88))

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#define REG_MDTOP_PLLMIXED_MDNRPLL4_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8C))

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#define REG_MDTOP_PLLMIXED_MDNRPLL5_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x90))

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#define REG_MDTOP_PLLMIXED_MDNRPLL5_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x94))

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#define REG_MDTOP_PLLMIXED_MDPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x98))

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#define REG_MDTOP_PLLMIXED_MDPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x9C))

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#define REG_MDTOP_PLLMIXED_MDPLLGP_RESERVE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xA0))

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#define REG_MDTOP_PLLMIXED_MDPLLGP1_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x100))

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#define REG_MDTOP_PLLMIXED_MDPLLGP2_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x104))

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#define REG_MDTOP_PLLMIXED_PLL_RESERVE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10C))

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#define REG_MDTOP_PLLMIXED_PLL_RESERVE2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x110))

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#define REG_MDTOP_PLLMIXED_PLL_RESERVE3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x114))

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#define REG_MDTOP_PLLMIXED_PLL_RESERVE4 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x118))

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#define REG_MDTOP_PLLMIXED_PLL_DIV_RSTB (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x120))

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#define REG_MDTOP_PLLMIXED_PLL_DIV_EN0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x124))

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#define REG_MDTOP_PLLMIXED_PLL_DIV_EN2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x12C))

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#define REG_MDTOP_PLLMIXED_PLL_DIV_EN3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x130))

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#define REG_MDTOP_PLLMIXED_PLL_SRC_SEL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x140))

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#define REG_MDTOP_PLLMIXED_PLL_FHCTL_RST (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x200))

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/* ==========PLL IRQ related========== */

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#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x300))

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#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x304))

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#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x308))

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#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30C))

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#define REG_MDTOP_PLLMIXED_PLL_REQ_ABNORM_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x310))

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#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x314))

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#define PLLMIXED_MDMCUPLL_HP_RDY_IRQ_OFFSET (1)

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#define PLLMIXED_MDVDSPPLL_HP_RDY_IRQ_OFFSET (2)

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#define PLLMIXED_MDBRPPLL_HP_RDY_IRQ_OFFSET (3)

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#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x318))

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#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x31C))

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/* PLL IRQ related macro */

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#define PLLMIXED_PLL_HP_RDY_IRQ_MASK (0x1)/* mask bit numbers for each IRQ */

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/* ==========PLL FHCTL========== */

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#define REG_MDTOP_PLLMIXED_MDMCUPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x400))

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#define REG_MDTOP_PLLMIXED_MDMCUPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x404))

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#define REG_MDTOP_PLLMIXED_MDMCUPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x408))

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#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x410))

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#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x414))

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#define REG_MDTOP_PLLMIXED_MDVDSPPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x418))

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#define REG_MDTOP_PLLMIXED_MDBRPPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x420))

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#define REG_MDTOP_PLLMIXED_MDBRPPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x424))

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#define REG_MDTOP_PLLMIXED_MDBRPPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x428))

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#define REG_MDTOP_PLLMIXED_MDBPIPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x430))

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#define REG_MDTOP_PLLMIXED_MDBPIPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x434))

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#define REG_MDTOP_PLLMIXED_MDBPIPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x438))

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#define REG_MDTOP_PLLMIXED_MDNRPLL0_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x450))

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#define REG_MDTOP_PLLMIXED_MDNRPLL0_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x454))

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#define REG_MDTOP_PLLMIXED_MDNRPLL0_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x458))

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#define REG_MDTOP_PLLMIXED_MDNRPLL1_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x460))

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#define REG_MDTOP_PLLMIXED_MDNRPLL1_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x464))

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#define REG_MDTOP_PLLMIXED_MDNRPLL1_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x468))

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#define REG_MDTOP_PLLMIXED_MDNRPLL2_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x470))

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#define REG_MDTOP_PLLMIXED_MDNRPLL2_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x474))

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#define REG_MDTOP_PLLMIXED_MDNRPLL2_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x478))

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#define REG_MDTOP_PLLMIXED_MDNRPLL3_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x480))

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#define REG_MDTOP_PLLMIXED_MDNRPLL3_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x484))

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#define REG_MDTOP_PLLMIXED_MDNRPLL3_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x488))

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#define REG_MDTOP_PLLMIXED_MDNRPLL4_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x490))

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#define REG_MDTOP_PLLMIXED_MDNRPLL4_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x494))

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#define REG_MDTOP_PLLMIXED_MDNRPLL4_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x498))

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#define REG_MDTOP_PLLMIXED_MDNRPLL5_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A0))

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#define REG_MDTOP_PLLMIXED_MDNRPLL5_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A4))

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#define REG_MDTOP_PLLMIXED_MDNRPLL5_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A8))

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#define REG_MDTOP_PLLMIXED_MDPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B0))

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#define REG_MDTOP_PLLMIXED_MDPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B4))

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#define REG_MDTOP_PLLMIXED_MDPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B8))

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/* ==========PLL Gear Set========== */

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#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x500))

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#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x504))

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#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x508))

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#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50C))

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#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x510))

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#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x514))

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#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x518))

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#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x51C))

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#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x520))

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#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x524))

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#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x528))

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#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x52C))

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/* ==========PLL Status========== */

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#define REG_MDTOP_PLLMIXED_MDMCUPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x800))

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#define REG_MDTOP_PLLMIXED_MDVDSPPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x804))

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#define REG_MDTOP_PLLMIXED_MDBRPPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x808))

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#define REG_MDTOP_PLLMIXED_MDBPIBPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x810))

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#define REG_MDTOP_PLLMIXED_MDNRPLL0_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x818))

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#define REG_MDTOP_PLLMIXED_MDNRPLL1_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x81C))

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#define REG_MDTOP_PLLMIXED_MDNRPLL2_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x820))

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#define REG_MDTOP_PLLMIXED_MDNRPLL3_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x824))

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#define REG_MDTOP_PLLMIXED_MDNRPLL4_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x828))

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#define REG_MDTOP_PLLMIXED_MDNRPLL5_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x82C))

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#define REG_MDTOP_PLLMIXED_MDPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x830))

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#define REG_MDTOP_PLLMIXED_MDMCUPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC14))

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#define REG_MDTOP_PLLMIXED_MDVDSPPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC18))

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#define REG_MDTOP_PLLMIXED_MDBRPPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC1C))

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#define REG_MDTOP_PLLMIXED_MDBPIPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC20))

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#define REG_MDTOP_PLLMIXED_MDNRPLL0_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC28))

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#define REG_MDTOP_PLLMIXED_MDNRPLL1_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC2C))

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#define REG_MDTOP_PLLMIXED_MDNRPLL2_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC30))

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#define REG_MDTOP_PLLMIXED_MDNRPLL3_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC34))

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#define REG_MDTOP_PLLMIXED_MDNRPLL4_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC38))

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#define REG_MDTOP_PLLMIXED_MDNRPLL5_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC3C))

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#define REG_MDTOP_PLLMIXED_MDPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC40))

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#define REG_MDTOP_PLLMIXED_FRDDS_OFF_IRQ_MODE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD00))

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#define REG_MDTOP_PLLMIXED_HP_RDY_OFF_IRQ_MODE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD04))

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#define REG_MDTOP_PLLMIXED_PLL_DUMMY (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF00))

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#define REG_MDTOP_PLLMIXED_PLL_DUMMY1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF04))

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#define REG_MDTOP_PLLMIXED_PLL_DUMMY2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF08))

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#define REG_MDTOP_PLLMIXED_PLL_DUMMY3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF0C))

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#define REG_MDTOP_PLLMIXED_PLL_STATUS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF10))

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///////////////////////////////////////////////////////////////////////////////

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/// CLKSW (0xA0150000)

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///////////////////////////////////////////////////////////////////////////////

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#define REG_MDTOP_CLKSW_CODA_VERSION (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x0))

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#define REG_MDTOP_CLKSW_MD_SLEEP_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4))

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#define REG_MDTOP_CLKSW_RFSLPC_SW_CTRL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x8))

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#define REG_MDTOP_CLKSW_MDTOPSM_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10))

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#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x14))

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#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x18))

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#define REG_MDTOP_CLKSW_CKOFF_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x1C))

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#define REG_MDTOP_CLKSW_CLKON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x20))

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#define REG_MDTOP_CLKSW_CLKSEL_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x24))

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#define REG_MDTOP_CLKSW_CLKSEL_CTL_2 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x28))

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/* ==========SDF clock control related========== */

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#define REG_MDTOP_CLKSW_SDF_ATB_CK_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x2C))

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#define REG_MDTOP_CLKSW_ATB_LOG_SDF_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30))

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#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x34))

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#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x38))

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#define REG_MDTOP_CLKSW_EXTCK_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40))

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/* ==========FLEXCKGEN_SEL========== */

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#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x44))

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#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x48))

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#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4C))

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#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x50))

269

#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x54))

270

#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x58))

271

#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x5C))

272

#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x70))

273

#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x74))

274

#define REG_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x78))

275

#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x7C))

276

#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x80))

277

278

#define REG_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x84))

279

#define REG_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x88))

280

#define REG_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x8C))

281

#define REG_MDTOP_CLKSW_VCORE_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x90))

282

#define REG_MDTOP_CLKSW_MCORE_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x94))

283

#define REG_MDTOP_CLKSW_RXDDM_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x98))

284

#define REG_MDTOP_CLKSW_RXDBRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x9C))

285

286

#define REG_MDTOP_CLKSW_FETXBSRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA4))

287

#define REG_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA8))

288

#define REG_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xAC))

289

#define REG_MDTOP_CLKSW_CPC_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB0))

290

#define REG_MDTOP_CLKSW_TOP_BUS4X_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB4))

291

#define REG_MDTOP_CLKSW_RXDFE_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB8))

292

#define REG_MDTOP_CLKSW_BUS2X_NODCM_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xBC))

293

#define REG_MDTOP_CLKSW_TOP_BUS4X_FIXED_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC0))

294

295

/* ==========FLEXCKGEN_STS========== */

296

#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xCC))

297

#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD0))

298

#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD4))

299

#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD8))

300

#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xDC))

301

#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE0))

302

#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE4))

303

#define REG_MDTOP_CLKSW_MDPLL_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE8))

304

305

#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF0))

306

#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF4))

307

#define REG_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF8))

308

#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xFC))

309

#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x100))

310

#define REG_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x104))

311

#define REG_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x108))

312

#define REG_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10C))

313

#define REG_MDTOP_CLKSW_VCORE_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x110))

314

#define REG_MDTOP_CLKSW_MCORE_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x114))

315

#define REG_MDTOP_CLKSW_RXDDM_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x118))

316

#define REG_MDTOP_CLKSW_RXDBRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x11C))

317

318

#define REG_MDTOP_CLKSW_FETXBSRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x124))

319

#define REG_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x12C))

320

#define REG_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x130))

321

#define REG_MDTOP_CLKSW_CPC_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x134))

322

#define REG_MDTOP_CLKSW_TOP_BUS4X_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x138))

323

#define REG_MDTOP_CLKSW_RXDFE_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x13C))

324

#define REG_MDTOP_CLKSW_BUS2X_NODCM_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x140))

325

#define REG_MDTOP_CLKSW_TOP_BUS4X_FIXED_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x144))

326

327

#define REG_MDTOP_CLKSW_CKMUX_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x200))

328

#define REG_MDTOP_CLKSW_PLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x210))

329

#define REG_MDTOP_CLKSW_DFS_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x220))

330

#define REG_MDTOP_CLKSW_DFS_STS_2 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x224))

331

332

/* ==========direct pll request========== */

333

#define REG_MDTOP_CLKSW_MDMCU_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x300))

334

#define REG_MDTOP_CLKSW_MDBUS_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x304))

335

#define REG_MDTOP_CLKSW_VDSP_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x308))

336

#define REG_MDTOP_CLKSW_BRP_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30C))

337

338

/* ==========Frequency Meter========== */

339

#define REG_MDTOP_CLKSW_CKMON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x400))

340

#define REG_MDTOP_CLKSW_FREQ_METER_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x404))

341

#define REG_MDTOP_CLKSW_FREQ_METER_XTAL_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x408))

342

#define REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40C))

343

#define REG_MDTOP_CLKSW_FREQ_METER_H (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x410))

344

#define REG_MDTOP_CLKSW_FREQ_METER_L (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x414))

345

346

#define REG_MDTOP_CLKSW_CLK_REQ_MON (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x500))

347

#define REG_MDTOP_CLKSW_CLK_RDY_MON (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x504))

348

349

/* ==========DUMMY & STATUS========== */

350

#define REG_MDTOP_CLKSW_CLK_DUMMY (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF00))

351

#define REG_MDTOP_CLKSW_CLK_STATUS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF04))

352

353

354

/*******************************************************************************

355

* Define Macro

356

******************************************************************************/

357

#define MD_PLL_MAGIC_NUM 0x62970000

358

#define MD_PLL_MAGIC_26M 0x62970026

359

#define MD_PLL_MAGIC_MD 0x62971111

360

361

362

/*------------------------------------------------------------------------

363

* Purpose: Transfer PCW in xxxPLL_STS to Mhz. This macro is porting from md_dvfs_pll_freq_get(const PLL_SOURCE pll).

364

* Parameters:

365

* Input: pcw: The PCW value in xxxPLL_STS.

366

* divier: The divier for this PLL(EX: ICCPLL_DIVIDER, IMCPLL_DIVIDER...).

367

* Output: None.

368

* returns : Mhz.

369

* Note : This macr is only used to transfer pcw in xxxPLL_STS to Mhz.

370

* You should not used this macro to transfer pcw in xxxPLL_CTL0 to Mhz due to the meaning is different.

371

* (PCW in xxxPLL_STS is bit [21:7] of xxxPLL_CTL0.)

372

*------------------------------------------------------------------------

373

*/

374

#define PLLMIXED_PLL_STS_SDM_PCW_TO_MHZ(pcw, divier) ((((pcw) * 26) / (1 << 7)) / divier)

375

376

/*******************************************************************************

377

* ENUM

378

******************************************************************************/

379

// frequency meter index list (debug only)

380

typedef enum {

381

PLL_FM_SOURCE_START = 0x0,

382

PLL_FM_AD_MDNRPLL5 = 0x0,

383

PLL_FM_AD_MDNRPLL4_1 = 0x1,

384

PLL_FM_AD_MDNRPLL4_0 = 0x2,

385

PLL_FM_AD_MDNRPLL3 = 0x3,

386

PLL_FM_AD_MDNRPLL2 = 0x4,

387

PLL_FM_AD_MDNRPLL1 = 0x5,

388

PLL_FM_AD_MDNRPLL0 = 0x6,

389

PLL_FM_MDSYS_NRL2_CLOCK = 0x7, // NRL2 = MML2

390

PLL_FM_MDRXSYS_DFESYNC_CLOCK = 0x8,

391

PLL_FM_MDTOP_F216P7M_CLOCK = 0x9,

392

PLL_FM_TRACE_MON_CLOCK = 0xA,

393

PLL_FM_MDSYS_216P7M_CLOCK = 0xB,

394

PLL_FM_MDRXSYS_RAKE_CLOCK = 0xC,

395

PLL_FM_MDRXSYS_BRP_CLOCK = 0xD,

396

PLL_FM_MDRXSYS_VDSP_CLOCK = 0xE,

397

PLL_FM_MDTOP_LOG_ATB_CLOCK = 0xF,

398

PLL_FM_FESYS_CSYS_CLOCK = 0x10,

399

PLL_FM_MDSYS_SHAOLIN_CLOCK = 0x11,

400

PLL_FM_FESYS_BSI_CLOCK = 0x12,

401

PLL_FM_MDSYS_MDCORE_CLOCK = 0x13,

402

PLL_FM_MDSYS_BUS2X_NODCM_CLOCK = 0x14,

403

PLL_FM_MDSYS_BUS4X_CLOCK = 0x15,

404

PLL_FM_MDTOP_DBG_CLOCK = 0x16,

405

PLL_FM_MDTOP_F32K_CLOCK = 0x17,

406

PLL_FM_AD_MDBPI_PLL_D7 = 0x18, /* AD means "analog to digital" */

407

PLL_FM_AD_MDBPI_PLL_D5 = 0x19,

408

PLL_FM_AD_MDBPI_PLL_D4 = 0x1A,

409

PLL_FM_AD_MDBPI_PLL_D3 = 0x1B,

410

PLL_FM_AD_MDBPI_PLL_D2 = 0x1C,

411

PLL_FM_AD_MDBRP_PLL = 0x1D,

412

PLL_FM_AD_MDVDSP_PLL = 0x1E,

413

PLL_FM_AD_MDMCU_PLL = 0x1F,

414

/* CKMON_SRC_SEL2 = 1 */

415

416

PLL_FM_DFESYS_RXDFE_BB_CORE_CLOCK = 0x2E,

417

PLL_FM_AD_MDNRPLL4_2 = 0x2F,

418

PLL_FM_MDTOP_BUS4X_FIXED_CLOCK = 0x30,

419

PLL_FM_DA_DRF_26M_CLOCK = 0x31,

420

PLL_FM_MDTOP_BUS4X_CLOCK = 0x32,

421

PLL_FM_RXCPC_CPC_CLOCK = 0x33,

422

423

PLL_FM_RXDDMBRP_RXDBRP_CLOCK = 0x35,

424

PLL_FM_RXDDMBRP_RXDDM_CLOCK = 0x36,

425

PLL_FM_MCORE_MCORE_CLOCK = 0x37,

426

PLL_FM_VCOREHRAM_VCORE_CLOCK = 0x38,

427

PLL_FM_VCOREHRAM_HRAM_CLOCK = 0x39,

428

PLL_FM_FESYS_TXBSRP_CLOCK = 0x3A,

429

PLL_FM_FESYS_MDPLL_CLOCK = 0x3B,

430

PLL_FM_TX_CS_NR_RXT2F_NR_CLOCK = 0x3C,

431

PLL_FM_TX_CS_NR_TXBSRP_NR_CLOCK= 0x3D,

432

PLL_FM_TX_CS_NR_CM_NR_CLOCK = 0x3E,

433

PLL_FM_TX_CS_NR_CS_NR_CLOCK = 0x3F,

434

PLL_FM_SOURCE_END = 0x3F

} PLL_FM_SOURCE;

typedef enum {

CLKSW_SDF_SRC_MDPLL_F650M = 0,

439

CLKSW_SDF_SRC_TOP_BUS4X = 1,

440

CLKSW_SDF_SRC_MDPLL_F325M = 2,

441

CLKSW_SDF_SRC_MDPLL_F216P7M = 3,

CLKSW_SDF_SRC_26M,

CLKSW_SDF_SRC_END

} PLL_CLKSW_SDF_SRC;

typedef enum {

CLKSW_SDF_SRC_DIV_1 = 0,

448

CLKSW_SDF_SRC_DIV_2 = 1,

449

CLKSW_SDF_SRC_DIV_3 = 2,

450

CLKSW_SDF_SRC_DIV_4 = 3

451

} PLL_CLKSW_SDF_SRC_DIV;

452

453

/* Below for debugging */

454

455

#define PLL_FM_NUM 48 /* Note: This number should also sync to EE owner. */

456

typedef struct {

457

kal_uint32 AD_MDNRPLL5; /* 0 */

458

kal_uint32 AD_MDNRPLL4_1;

459

kal_uint32 AD_MDNRPLL4_0;

460

kal_uint32 AD_MDNRPLL3;

461

kal_uint32 AD_MDNRPLL2;

462

kal_uint32 AD_MDNRPLL1; /* 5 */

463

kal_uint32 AD_MDNRPLL0;

464

kal_uint32 MDSYS_NRL2_CLOCK;

465

kal_uint32 MDRXSYS_DFESYNC_CLOCK;

466

kal_uint32 MDTOP_F216P7M_CLOCK;

467

kal_uint32 TRACE_MON_CLOCK; /* 10 */

468

kal_uint32 MDSYS_216P7M_CLOCK;

469

kal_uint32 MDRXSYS_RAKE_CLOCK;

470

kal_uint32 MDRXSYS_BRP_CLOCK;

471

kal_uint32 MDRXSYS_VDSP_CLOCK;

472

kal_uint32 MDTOP_LOG_ATB_CLOCK; /* 15 */

473

kal_uint32 FESYS_CSYS_CLOCK;

474

kal_uint32 MDSYS_SHAOLIN_CLOCK;

475

kal_uint32 FESYS_BSI_CLOCK;

476

kal_uint32 MDSYS_MDCORE_CLOCK;

477

kal_uint32 MDSYS_BUS2X_NODCM_CLOCK; /* 20 */

478

kal_uint32 MDSYS_BUS4X_CLOCK;

479

kal_uint32 MDTOP_DBG_CLOCK;

480

kal_uint32 AD_MDBPI_PLL_D7;

481

kal_uint32 AD_MDBPI_PLL_D5;

482

kal_uint32 AD_MDBPI_PLL_D4; /* 25 */

483

kal_uint32 AD_MDBPI_PLL_D3;

484

kal_uint32 AD_MDBPI_PLL_D2;

485

kal_uint32 AD_MDBRP_PLL;

486

kal_uint32 AD_MDVDSP_PLL;

487

kal_uint32 AD_MDMCU_PLL; /* 30 */

488

kal_uint32 DFESYS_RXDFE_BB_CORE_CLOCK;

489

kal_uint32 AD_MDNRPLL4_2;

490

kal_uint32 MDTOP_BUS4X_FIXED_CLOCK;

491

kal_uint32 DA_DRF_26M_CLOCK;

492

kal_uint32 MDTOP_BUS4X_CLOCK; /* 35 */

493

kal_uint32 RXCPC_CPC_CLOCK;

494

kal_uint32 RXDDMBRP_RXDBRP_CLOCK;

495

kal_uint32 RXDDMBRP_RXDDM_CLOCK;

496

kal_uint32 MCORE_MCORE_CLOCK;

497

kal_uint32 VCOREHRAM_VCORE_CLOCK; /* 40 */

498

kal_uint32 VCOREHRAM_HRAM_CLOCK;

499

kal_uint32 FESYS_TXBSRP_CLOCK;

500

kal_uint32 FESYS_MDPLL_CLOCK;

501

kal_uint32 TX_CS_NR_RXT2F_NR_CLOCK;

502

kal_uint32 TX_CS_NR_TXBSRP_NR_CLOCK;/* 45 */

503

kal_uint32 TX_CS_NR_CM_NR_CLOCK;

504

kal_uint32 TX_CS_NR_CS_NR_CLOCK;

505

/* we couldn't add more PLL here... */

} PLL_CLK_INFO;

extern PLL_CLK_INFO g_pll_info;

510

extern const char PLL_FM_clock[PLL_FM_NUM][32];

511

512

/* Above for debugging */

513

514

/*******************************************************************************

515

* Include header files

516

******************************************************************************/

517

extern void PLL_MD_Pll_Init(void);

518

extern void PLL_Set_CLK_To_26M(void);

519

520

extern void PLL_Check_26M_ACK_Status(kal_uint32 identifier);

521

extern void PLL_exception_dump(void);

522

extern kal_uint32 PLL_FrequencyMeter_GetFreq(PLL_FM_SOURCE index);

523

524

/* For SDF user in driver/sib_drv/sdf/src/md97/drv_sdf_97.c */

525

extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Get();

526

extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Div_Get();

527

extern kal_bool PLL_CLKSW_SDF_SRC_CKSEL_Set(PLL_CLKSW_SDF_SRC src_clk, PLL_CLKSW_SDF_SRC_DIV src_div);

528

529

#endif /* !__PLL_MT6297P_H__ */

530