Gitiles
Code Review Sign In
192.168.1.100 / T800_MD / 6c1fd8fba87d5723e0e5614ae30b4258b603cb70 / . / mcu / interface / driver / sleep_drv / ostd_public.h
blob: 27e1bcd34398832d64e352a18f7c551c1fea38dc [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame^]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*******************************************************************************
37 *
38 * Filename:
39 * ---------
40 * ostd_public.h
41 *
42 * Project:
43 * --------
44 * MTK6276
45 *
46 * Description:
47 * ------------
48 * This is the driver layer and corresponding Sleep Mode of ARM OS Timer HW
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * removed!
59 * removed!
60 * removed!
61 *
62 * removed!
63 * removed!
64 * removed!
65 *
66 * removed!
67 * removed!
68 * removed!
69 * removed!
70 *
71 * removed!
72 * removed!
73 * removed!
74 *
75 * removed!
76 * removed!
77 * removed!
78 *
79 * removed!
80 * removed!
81 * removed!
82 * removed!
83 * removed!
84 *
85 * removed!
86 * removed!
87 * removed!
88 *
89 * removed!
90 * removed!
91 * removed!
92 *
93 * removed!
94 * removed!
95 * removed!
96 * removed!
97 *
98 * removed!
99 * removed!
100 *
101 * removed!
102 * removed!
103 *
104 * removed!
105 * removed!
106 * removed!
107 *
108 * removed!
109 * removed!
110 * removed!
111 * removed!
112 * removed!
113 *
114 * removed!
115 * removed!
116 * removed!
117 * removed!
118 *
119 * removed!
120 * removed!
121 * removed!
122 * removed!
123 *
124 * removed!
125 * removed!
126 * removed!
127 * removed!
128 *
129 * removed!
130 * removed!
131 * removed!
132 *
133 * removed!
134 * removed!
135 * removed!
136 *
137 * removed!
138 * removed!
139 * removed!
140 * removed!
141 *
142 * removed!
143 * removed!
144 * removed!
145 *
146 * removed!
147 * removed!
148 * removed!
149 *
150 * removed!
151 * removed!
152 *
153 * removed!
154 * removed!
155 * removed!
156 *
157 * removed!
158 * removed!
159 * removed!
160 *
161 * removed!
162 * removed!
163 * removed!
164 * removed!
165 * removed!
166 *
167 * removed!
168 * removed!
169 * removed!
170 *
171 * removed!
172 * removed!
173 * removed!
174 * removed!
175 * removed!
176 * removed!
177 * removed!
178 * removed!
179 * removed!
180 * removed!
181 * removed!
182 * removed!
183 * removed!
184 * removed!
185 *
186 * removed!
187 * removed!
188 * removed!
189 *
190 * removed!
191 * removed!
192 * removed!
193 *
194 * removed!
195 * removed!
196 * removed!
197 *
198 * removed!
199 * removed!
200 * removed!
201 *
202 * removed!
203 * removed!
204 * removed!
205 *
206 * removed!
207 * removed!
208 * removed!
209 *
210 * removed!
211 *------------------------------------------------------------------------------
212 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
213 *============================================================================
214 ****************************************************************************/
215#if 1
216
217#ifndef OSTD_PUBLIC_H
218#define OSTD_PUBLIC_H
219
220#include "kal_general_types.h"
221#ifndef L1_SIM
222#include "ps_public_enum.h"
223#endif
224
225typedef void (*AP_STATUS_CHAGE_CALLBACK) (kal_uint32 ap_status);
226
227typedef enum
228{
229 OSTD_SUCCESS_FALSE = 0, /*OSTD read back AFN/UFN and found that current value is <=2*/
230 OSTD_SUCCESS_TRUE, /*OSTD has successfully set the AFN value into ARM OS Timer HW*/
231 OSTD_TIME_OUT, /*OSTD failed to poll ready bit*/
232 OSTD_FAIL, /* Other unknown fail reason */
233 OSTD_RESULT_NUM
234} OSTD_RESULT_E;
235
236typedef struct _OSTD_FRM_INFO_T
237{
238 kal_uint32 curr_afn; /* for OSTD to fill back current AFN value */
239 kal_uint32 curr_ufn; /* for OSTD to fill back current UFN value */
240 kal_uint32 curr_afn_dly; /* for OSTD to fill back current AFN_DLY value */
241} OSTD_FRM_INFO_T;
242
243typedef struct
244{
245 char* module_name;
246 module_type mod_id;
247 AP_STATUS_CHAGE_CALLBACK funp;
248 kal_bool pending_urc;
249} ostd_urc_src_module_info_struct;
250
251typedef enum _OSTD_TIMER_TYPE_E
252{
253 OSTD_OST,
254 OSTD_2G,
255 OSTD_3G_FDD,
256 OSTD_3G_TDD,
257 OSTD_3G_C2K_1X,
258 OSTD_3G_C2K_DO,
259 OSTD_4G,
260 OSTD_5G,
261 OSTD_TIMER_MAX
262} OSTD_TIMER_TYPE_E;
263
264typedef enum {
265 OSTD_BUSY,
266 OSTD_WAIT,
267 OSTD_DORMANT
268} kal_checksleep_e;
269
270typedef enum {
271 OSTD_ChkSlp_No_InfiniteSleep,
272 OSTD_ChkSlp_EFUN_CFUN,
273 OSTD_ChkSlp_EPOF
274} kal_chkslp_inf_e;
275
276typedef enum {
277 OSTD_IDLE_VPE0_ENTER,
278 OSTD_IDLE_VPE0_LEAVE,
279 OSTD_IDLE_VPE1_ENTER,
280 OSTD_IDLE_VPE1_LEAVE,
281 OSTD_IDLE_CALCULATE,
282 OSTD_IDLE_PRINT
283} kal_idlerate_e;
284
285#if defined(__MD97__)
286#if defined(CHIP10992)
287typedef enum
288{
289 EVENT_l1sm_timer_trig_F32K = 0,
290 EVENT_mdsm_timer_trig_F32K = 1,
291 EVENT_dem_trig_md_int_le_F32K = 2,
292 EVENT_fe_md_share_d12mint1_b_F32K = 3,
293 EVENT_fe_md_cssys_ltel1_cs_irq_b_F32K = 4,
294 EVENT_mcu_bus_decerr_irq_F32K = 5,
295 EVENT_usip_ia_ostimer_wakeup_b_F32K = 6,
296 EVENT_cs_nr_irq_F32K = 7,
297 EVENT_cs_err_irq_F32K = 8,
298 EVENT_ulsp_log_md_rt_int_F32K = 9,
299 EVENT_ulsp_log_md_od_int_F32K = 10,
300 EVENT_ulsp_log_dsp4g_rt_int_F32K = 11,
301 EVENT_ulsp_log_dsp4g_od_int_F32K = 12,
302 EVENT_ulsp_log_dsp5g_rt_int_F32K = 13,
303 EVENT_ulsp_log_dsp5g_od_int_F32K = 14,
304 EVENT_mcore0_mml1_dsppmu_top_emi_irq_F32K = 15,
305 EVENT_mcore1_mml1_dsppmu_top_emi_irq_F32K = 16,
306 EVENT_mml1_dspcsif_top_s2c0_cirq_F32K = 17,
307 EVENT_mml1_dspcsif_top_s2c1_cirq_F32K = 18,
308 EVENT_mml1_dspcsif_top_err_cirq_F32K = 19,
309 EVENT_ap2md_usb_rx_not_empty_F32K = 20,
310 EVENT_ap2md_usb_rx_gpd_done_F32K = 21,
311 EVENT_ap2md_usb_dma_active_F32K = 22,
312 EVENT_ap2md_usb_ip_wakeup_F32K = 23,
313 EVENT_ap2md_usb_mcu_irq_b_F32K = 24,
314 EVENT_ap2md_ssusb_rx_not_empty_F32K = 25,
315 EVENT_ap2md_ssusb_rx_gpd_done_F32K = 26,
316 EVENT_ap2md_ssusb_dma_active_F32K = 27,
317 EVENT_ap2md_ssusb_ip_wakeup_F32K = 28,
318 EVENT_ap2md_ssusb_dev_int_b_F32K = 29,
319 EVENT_ap2md_ccif0_md_event_b_F32K = 30,
320 EVENT_ap2md_ccif1_md_event_b_F32K = 31,
321 EVENT_ap2md_cldma_ip_busy_F32K = 32,
322 EVENT_ap2md_dpmaif_mdtopsm_int_F32K = 33,
323 EVENT_conn2md_pdma_irq_b_F32K = 34,
324 EVENT_ap2md_conn_bgf_ccif_md_event_b_F32K = 35,
325 EVENT_ap2md_conn_wf_ccif_md_event_b_F32K = 36,
326 EVENT_ipsec_so_int_lv_F32K = 37,
327 EVENT_conn_bt_cvsd_int_b_F32K = 38,
328 EVENT_conn_bt_isoch_irq_b_F32K = 39,
329 EVENT_rgu2md_irq_b_F32K = 40,
330 EVENT_ap2md_ccif2_md_event_b_F32K = 41,
331 EVENT_mhccif_sap2md_event_b_F32K = 42,
332 EVENT_ap2md_apmcu_suspend_irq_F32K = 43,
333 EVENT_ap2md_apmcu_active_irq_F32K = 44,
334 EVENT_eint_event0_F32K = 45,
335 EVENT_eint_event1_F32K = 46,
336 EVENT_eint_event2_F32K = 47,
337 EVENT_eint_event3_F32K = 48,
338 EVENT_eint_event4_F32K = 49,
339 EVENT_eint_event5_F32K = 50,
340 EVENT_eint_event6_F32K = 51,
341 EVENT_eint_event7_F32K = 52,
342 EVENT_eint_event8_F32K = 53,
343 EVENT_eint_event9_F32K = 54,
344 EVENT_eint_event10_F32K = 55,
345 EVENT_eint_event11_F32K = 56,
346 EVENT_ap2md_cldma0_md_ip_busy_lv_md_F32K = 57,
347 EVENT_ap2md_cldma1_md_ip_busy_lv_md_F32K = 58,
348 EVENT_ap2md_cldma2_md_ip_busy_lv_md_F32K = 59,
349 EVENT_ap2md_cldma3_md_ip_busy_lv_md_F32K = 60,
350 EVENT_pcie_interrupt_out_F32K = 61,
351
352 EVENT_l1sm_timer_trig_NON_F32K = 64,
353 EVENT_mdsm_timer_trig_NON_F32K = 65,
354 EVENT_dem_trig_md_int_le_NON_F32K = 66,
355 EVENT_fe_md_share_d12mint1_b_NON_F32K = 67,
356 EVENT_fe_md_cssys_ltel1_cs_irq_b_NON_F32K = 68,
357 EVENT_mcu_bus_decerr_irq_NON_F32K = 69,
358 EVENT_usip_ia_ostimer_wakeup_b_NON_F32K = 70,
359 EVENT_cs_nr_irq_NON_F32K,
360 EVENT_cs_err_irq_NON_F32K,
361 EVENT_ulsp_log_md_rt_int_NON_F32K = 73,
362 EVENT_ulsp_log_md_od_int_NON_F32K = 74,
363 EVENT_ulsp_log_dsp4g_rt_int_NON_F32K = 75,
364 EVENT_ulsp_log_dsp4g_od_int_NON_F32K = 76,
365 EVENT_ulsp_log_dsp5g_rt_int_NON_F32K = 77,
366 EVENT_ulsp_log_dsp5g_od_int_NON_F32K = 78,
367 EVENT_mcore0_mml1_dsppmu_top_emi_irq_NON_F32K = 79,
368 EVENT_mcore1_mml1_dsppmu_top_emi_irq_NON_F32K = 80,
369 EVENT_mml1_dspcsif_top_s2c0_cirq_NON_F32K = 81,
370 EVENT_mml1_dspcsif_top_s2c1_cirq_NON_F32K = 82,
371 EVENT_mml1_dspcsif_top_err_cirq_NON_F32K = 83,
372 EVENT_ap2md_usb_rx_not_empty_NON_F32K = 84,
373 EVENT_ap2md_usb_rx_gpd_done_NON_F32K = 85,
374 EVENT_ap2md_usb_dma_active_NON_F32K = 86,
375 EVENT_ap2md_usb_ip_wakeup_NON_F32K = 87,
376 EVENT_ap2md_usb_mcu_irq_b_NON_F32K = 88,
377 EVENT_ap2md_ssusb_rx_not_empty_NON_F32K = 89,
378 EVENT_ap2md_ssusb_rx_gpd_done_NON_F32K = 90,
379 EVENT_ap2md_ssusb_dma_active_NON_F32K = 91,
380 EVENT_ap2md_ssusb_ip_wakeup_NON_F32K = 92,
381 EVENT_ap2md_ssusb_dev_int_b_NON_F32K = 93,
382 EVENT_ap2md_ccif0_md_event_b_NON_F32K = 94,
383 EVENT_ap2md_ccif1_md_event_b_NON_F32K = 95,
384 EVENT_ap2md_cldma_ip_busy_NON_F32K = 96,
385 EVENT_ap2md_dpmaif_mdtopsm_int_NON_F32K = 97,
386 EVENT_conn2md_pdma_irq_b_NON_F32K = 98,
387 EVENT_ap2md_conn_bgf_ccif_md_event_b_NON_F32K = 99,
388 EVENT_ap2md_conn_wf_ccif_md_event_b_NON_F32K = 100,
389 EVENT_ipsec_so_int_lv_NON_F32K = 101,
390 EVENT_conn_bt_cvsd_int_b_NON_F32K = 102,
391 EVENT_conn_bt_isoch_irq_b_NON_F32K = 103,
392 EVENT_rgu2md_irq_b_NON_F32K = 104,
393 EVENT_ap2md_ccif2_md_event_b_NON_F32K = 105,
394 EVENT_mhccif_sap2md_event_b_NON_F32K = 106,
395 EVENT_ap2md_apmcu_suspend_irq_NON_F32K = 107,
396 EVENT_ap2md_apmcu_active_irq_NON_F32K = 108,
397 EVENT_eint_event0_NON_F32K = 109,
398 EVENT_eint_event1_NON_F32K = 110,
399 EVENT_eint_event2_NON_F32K = 111,
400 EVENT_eint_event3_NON_F32K = 112,
401 EVENT_eint_event4_NON_F32K = 113,
402 EVENT_eint_event5_NON_F32K = 114,
403 EVENT_eint_event6_NON_F32K = 115,
404 EVENT_eint_event7_NON_F32K = 116,
405 EVENT_eint_event8_NON_F32K = 117,
406 EVENT_eint_event9_NON_F32K = 118,
407 EVENT_eint_event10_NON_F32K = 119,
408 EVENT_eint_event11_NON_F32K = 120,
409 EVENT_ap2md_cldma0_md_ip_busy_lv_md_NON_F32K = 121,
410 EVENT_ap2md_cldma1_md_ip_busy_lv_md_NON_F32K = 122,
411 EVENT_ap2md_cldma2_md_ip_busy_lv_md_NON_F32K = 123,
412 EVENT_ap2md_cldma3_md_ip_busy_lv_md_NON_F32K = 124,
413 EVENT_pcie_interrupt_out_NON_F32K = 125,
414} sm_event_e;
415#elif defined(MT6885)
416typedef enum
417{
418 EVENT_l1sm_timer_trig_F32K = 0,
419 EVENT_mdsm_timer_trig_F32K = 1,
420 EVENT_dem_trig_md_int_le_F32K = 2,
421 EVENT_fe_md_share_d12mint1_b_F32K = 3,
422 EVENT_fe_md_cssys_ltel1_cs_irq_b_F32K = 4,
423 EVENT_mcu_bus_decerr_irq_F32K = 5,
424 EVENT_usip_ia_ostimer_wakeup_b_F32K = 6,
425 EVENT_cs_nr_irq_F32K,
426 EVENT_cs_err_irq_F32K,
427 EVENT_ulsp_log_md_rt_int_F32K = 9,
428 EVENT_ulsp_log_md_od_int_F32K = 10,
429 EVENT_ulsp_log_dsp4g_rt_int_F32K = 11,
430 EVENT_ulsp_log_dsp4g_od_int_F32K = 12,
431 EVENT_ulsp_log_dsp5g_rt_int_F32K = 13,
432 EVENT_ulsp_log_dsp5g_od_int_F32K = 14,
433 EVENT_mcore0_mml1_dsppmu_top_emi_irq_F32K = 15,
434 EVENT_mcore1_mml1_dsppmu_top_emi_irq_F32K = 16,
435 EVENT_vcore_mml1_dsppmu_top_emi_irq_F32K = 17,
436 EVENT_mml1_dspcsif_top_s2c0_cirq_F32K = 18,
437 EVENT_mml1_dspcsif_top_s2c1_cirq_F32K = 19,
438 EVENT_mml1_dspcsif_top_err_cirq_F32K = 20,
439 EVENT_ap2md_usb_rx_not_empty_F32K,
440 EVENT_ap2md_usb_rx_gpd_done_F32K = 22,
441 EVENT_ap2md_usb_dma_active_F32K,
442 EVENT_ap2md_usb_ip_wakeup_F32K = 24,
443 EVENT_ap2md_usb_mcu_irq_b_F32K =25,
444 EVENT_ap2md_ssusb_rx_not_empty_F32K,
445 EVENT_ap2md_ssusb_rx_gpd_done_F32K = 27,
446 EVENT_ap2md_ssusb_dma_active_F32K,
447 EVENT_ap2md_ssusb_ip_wakeup_F32K = 29,
448 EVENT_ap2md_ssusb_dev_int_b_F32K = 30,
449 EVENT_ap2md_ccif0_md_event_b_F32K = 31,
450 EVENT_ap2md_ccif1_md_event_b_F32K = 32,
451 EVENT_ap2md_cldma_ip_busy_F32K = 33,
452 EVENT_ap2md_dpmaif_mdtopsm_int_F32K = 34,
453 EVENT_conn2md_pdma_irq_b_F32K = 35,
454 EVENT_ap2md_conn_bgf_ccif_md_event_b_F32K = 36,
455 EVENT_ap2md_conn_wf_ccif_md_event_b_F32K = 37,
456 EVENT_ipsec_so_int_lv_F32K = 38,
457 EVENT_conn_bt_cvsd_int_b_F32K = 39,
458 EVENT_conn_bt_isoch_irq_b_F32K = 40,
459 EVENT_eint_int_lv_F32K = 41,
460 EVENT_eint_event0_F32K = 42,
461 EVENT_eint_event1_F32K = 43,
462 EVENT_eint_event2_F32K = 44,
463 EVENT_eint_event3_F32K = 45,
464 EVENT_rgu2md_irq_b_F32K = 46,
465 EVENT_ap2md_ccif2_md_event_b_F32K = 47,
466
467 EVENT_l1sm_timer_trig_NON_F32K = 64,
468 EVENT_mdsm_timer_trig_NON_F32K = 65,
469 EVENT_dem_trig_md_int_le_NON_F32K,
470 EVENT_fe_md_share_d12mint1_b_NON_F32K = 67,
471 EVENT_fe_md_cssys_ltel1_cs_irq_b_NON_F32K = 68,
472 EVENT_mcu_bus_decerr_irq_NON_F32K = 69,
473 EVENT_usip_ia_ostimer_wakeup_b_NON_F32K = 70,
474 EVENT_cs_nr_irq_NON_F32K,
475 EVENT_cs_err_irq_NON_F32K,
476 EVENT_ulsp_log_md_rt_int_NON_F32K = 73,
477 EVENT_ulsp_log_md_od_int_NON_F32K = 74,
478 EVENT_ulsp_log_dsp4g_rt_int_NON_F32K = 75,
479 EVENT_ulsp_log_dsp4g_od_int_NON_F32K = 76,
480 EVENT_ulsp_log_dsp5g_rt_int_NON_F32K = 77,
481 EVENT_ulsp_log_dsp5g_od_int_NON_F32K = 78,
482 EVENT_mcore0_mml1_dsppmu_top_emi_irq_NON_F32K = 79,
483 EVENT_mcore1_mml1_dsppmu_top_emi_irq_NON_F32K = 80,
484 EVENT_vcore_mml1_dsppmu_top_emi_irq_NON_F32K = 81,
485 EVENT_mml1_dspcsif_top_s2c0_cirq_NON_F32K,
486 EVENT_mml1_dspcsif_top_s2c1_cirq_NON_F32K,
487 EVENT_mml1_dspcsif_top_err_cirq_NON_F32K = 84,
488 EVENT_ap2md_usb_rx_not_empty_NON_F32K = 85,
489 EVENT_ap2md_usb_rx_gpd_done_NON_F32K,
490 EVENT_ap2md_usb_dma_active_NON_F32K = 87,
491 EVENT_ap2md_usb_ip_wakeup_NON_F32K,
492 EVENT_ap2md_usb_mcu_irq_b_NON_F32K,
493 EVENT_ap2md_ssusb_rx_not_empty_NON_F32K = 90,
494 EVENT_ap2md_ssusb_rx_gpd_done_NON_F32K,
495 EVENT_ap2md_ssusb_dma_active_NON_F32K = 92,
496 EVENT_ap2md_ssusb_ip_wakeup_NON_F32K,
497 EVENT_ap2md_ssusb_dev_int_b_NON_F32K,
498 EVENT_ap2md_ccif0_md_event_b_NON_F32K = 95,
499 EVENT_ap2md_ccif1_md_event_b_NON_F32K = 96,
500 EVENT_ap2md_cldma_ip_busy_NON_F32K = 97,
501 EVENT_ap2md_dpmaif_mdtopsm_int_NON_F32K = 98,
502 EVENT_conn2md_pdma_irq_b_NON_F32K = 99,
503 EVENT_ap2md_conn_bgf_ccif_md_event_b_NON_F32K = 100,
504 EVENT_ap2md_conn_wf_ccif_md_event_b_NON_F32K = 101,
505 EVENT_ipsec_so_int_lv_NON_F32K = 102,
506 EVENT_conn_bt_cvsd_int_b_NON_F32K = 103,
507 EVENT_conn_bt_isoch_irq_b_NON_F32K = 104,
508 EVENT_eint_int_lv_NON_F32K = 105,
509 EVENT_eint_event0_NON_F32K = 106,
510 EVENT_eint_event1_NON_F32K = 107,
511 EVENT_eint_event2_NON_F32K = 108,
512 EVENT_eint_event3_NON_F32K = 109,
513 EVENT_rgu2md_irq_b_NON_F32K = 110,
514 EVENT_ap2md_ccif2_md_event_b_NON_F32K = 111,
515} sm_event_e;
516#else
517typedef enum
518{
519 EVENT_l1sm_timer_trig_F32K = 0,
520 EVENT_mdsm_timer_trig_F32K = 1,
521 EVENT_dem_trig_md_int_le_F32K = 2,
522 EVENT_fe_md_share_d12mint1_b_F32K = 3,
523 EVENT_fe_md_cssys_ltel1_cs_irq_b_F32K = 4,
524 EVENT_mcu_bus_decerr_irq_F32K = 5,
525 EVENT_usip_ia_ostimer_wakeup_b_F32K = 6,
526 EVENT_cs_nr_irq_F32K,
527 EVENT_cs_err_irq_F32K,
528 EVENT_ulsp_log_md_rt_int_F32K = 9,
529 EVENT_ulsp_log_md_od_int_F32K = 10,
530 EVENT_ulsp_log_dsp4g_rt_int_F32K = 11,
531 EVENT_ulsp_log_dsp4g_od_int_F32K = 12,
532 EVENT_ulsp_log_dsp5g_rt_int_F32K = 13,
533 EVENT_ulsp_log_dsp5g_od_int_F32K = 14,
534 EVENT_mcore0_mml1_dsppmu_top_emi_irq_F32K = 15,
535 EVENT_mcore1_mml1_dsppmu_top_emi_irq_F32K = 16,
536 EVENT_vcore_mml1_dsppmu_top_emi_irq_F32K = 17,
537 EVENT_mml1_dspcsif_top_s2c0_cirq_F32K = 18,
538 EVENT_mml1_dspcsif_top_s2c1_cirq_F32K = 19,
539 EVENT_mml1_dspcsif_top_err_cirq_F32K = 20,
540 EVENT_ap2md_usb_rx_not_empty_F32K,
541 EVENT_ap2md_usb_rx_gpd_done_F32K = 22,
542 EVENT_ap2md_usb_dma_active_F32K,
543 EVENT_ap2md_usb_ip_wakeup_F32K = 24,
544 EVENT_ap2md_usb_mcu_irq_b_F32K =25,
545 EVENT_ap2md_ssusb_rx_not_empty_F32K,
546 EVENT_ap2md_ssusb_rx_gpd_done_F32K = 27,
547 EVENT_ap2md_ssusb_dma_active_F32K,
548 EVENT_ap2md_ssusb_ip_wakeup_F32K = 29,
549 EVENT_ap2md_ssusb_dev_int_b_F32K = 30,
550 EVENT_ap2md_ccif0_md_event_b_F32K = 31,
551 EVENT_ap2md_ccif1_md_event_b_F32K = 32,
552 EVENT_ap2md_cldma_ip_busy_F32K = 33,
553 EVENT_ap2md_dpmaif_mdtopsm_int_F32K = 34,
554 EVENT_conn2md_pdma_irq_b_F32K = 35,
555 EVENT_ap2md_conn_bgf_ccif_md_event_b_F32K = 36,
556 EVENT_ap2md_conn_wf_ccif_md_event_b_F32K = 37,
557 EVENT_ipsec_so_int_lv_F32K = 38,
558 EVENT_conn_bt_cvsd_int_b_F32K = 39,
559 EVENT_conn_bt_isoch_irq_b_F32K = 40,
560 EVENT_eint_int_lv_F32K = 41,
561 EVENT_eint_event0_F32K = 42,
562 EVENT_eint_event1_F32K = 43,
563 EVENT_eint_event2_F32K = 44,
564 EVENT_eint_event3_F32K = 45,
565 EVENT_rgu2md_irq_b_F32K = 46,
566 EVENT_ap2md_ccif2_md_event_b_F32K = 47,
567 EVENT_ap2md_apmcu_suspend_irq_F32K = 48,
568 EVENT_ap2md_apmcu_active_irq_F32K = 49,
569
570 EVENT_l1sm_timer_trig_NON_F32K = 64,
571 EVENT_mdsm_timer_trig_NON_F32K = 65,
572 EVENT_dem_trig_md_int_le_NON_F32K,
573 EVENT_fe_md_share_d12mint1_b_NON_F32K = 67,
574 EVENT_fe_md_cssys_ltel1_cs_irq_b_NON_F32K = 68,
575 EVENT_mcu_bus_decerr_irq_NON_F32K = 69,
576 EVENT_usip_ia_ostimer_wakeup_b_NON_F32K = 70,
577 EVENT_cs_nr_irq_NON_F32K,
578 EVENT_cs_err_irq_NON_F32K,
579 EVENT_ulsp_log_md_rt_int_NON_F32K = 73,
580 EVENT_ulsp_log_md_od_int_NON_F32K = 74,
581 EVENT_ulsp_log_dsp4g_rt_int_NON_F32K = 75,
582 EVENT_ulsp_log_dsp4g_od_int_NON_F32K = 76,
583 EVENT_ulsp_log_dsp5g_rt_int_NON_F32K = 77,
584 EVENT_ulsp_log_dsp5g_od_int_NON_F32K = 78,
585 EVENT_mcore0_mml1_dsppmu_top_emi_irq_NON_F32K = 79,
586 EVENT_mcore1_mml1_dsppmu_top_emi_irq_NON_F32K = 80,
587 EVENT_vcore_mml1_dsppmu_top_emi_irq_NON_F32K = 81,
588 EVENT_mml1_dspcsif_top_s2c0_cirq_NON_F32K,
589 EVENT_mml1_dspcsif_top_s2c1_cirq_NON_F32K,
590 EVENT_mml1_dspcsif_top_err_cirq_NON_F32K = 84,
591 EVENT_ap2md_usb_rx_not_empty_NON_F32K = 85,
592 EVENT_ap2md_usb_rx_gpd_done_NON_F32K,
593 EVENT_ap2md_usb_dma_active_NON_F32K = 87,
594 EVENT_ap2md_usb_ip_wakeup_NON_F32K,
595 EVENT_ap2md_usb_mcu_irq_b_NON_F32K,
596 EVENT_ap2md_ssusb_rx_not_empty_NON_F32K = 90,
597 EVENT_ap2md_ssusb_rx_gpd_done_NON_F32K,
598 EVENT_ap2md_ssusb_dma_active_NON_F32K = 92,
599 EVENT_ap2md_ssusb_ip_wakeup_NON_F32K,
600 EVENT_ap2md_ssusb_dev_int_b_NON_F32K,
601 EVENT_ap2md_ccif0_md_event_b_NON_F32K = 95,
602 EVENT_ap2md_ccif1_md_event_b_NON_F32K = 96,
603 EVENT_ap2md_cldma_ip_busy_NON_F32K = 97,
604 EVENT_ap2md_dpmaif_mdtopsm_int_NON_F32K = 98,
605 EVENT_conn2md_pdma_irq_b_NON_F32K = 99,
606 EVENT_ap2md_conn_bgf_ccif_md_event_b_NON_F32K = 100,
607 EVENT_ap2md_conn_wf_ccif_md_event_b_NON_F32K = 101,
608 EVENT_ipsec_so_int_lv_NON_F32K = 102,
609 EVENT_conn_bt_cvsd_int_b_NON_F32K = 103,
610 EVENT_conn_bt_isoch_irq_b_NON_F32K = 104,
611 EVENT_eint_int_lv_NON_F32K = 105,
612 EVENT_eint_event0_NON_F32K = 106,
613 EVENT_eint_event1_NON_F32K = 107,
614 EVENT_eint_event2_NON_F32K = 108,
615 EVENT_eint_event3_NON_F32K = 109,
616 EVENT_ap2md_apmcu_suspend_irq_NON_F32K = 110,
617 EVENT_ap2md_apmcu_active_irq_NON_F32K = 111,
618} sm_event_e;
619#endif
620#endif
621
622/*****************************************************************************
623* Functions provided by OSTD
624*****************************************************************************/
625
626/* For ARM Side OS Timer Upper Layer */
627extern void OSTD_Init( void );
628extern void OSTD_EnOST( kal_bool enable );
629extern void OSTD_SetFrmDur( kal_uint16 frm_dur );
630extern void OSTD_GetCurrFrm( OSTD_FRM_INFO_T *pFrm_Info );
631extern OSTD_RESULT_E OSTD_SetAfn( kal_uint32 afn );
632extern OSTD_RESULT_E OSTD_SetUfn( kal_uint32 ufn );
633extern OSTD_RESULT_E OSTD_SetAfnUfn( kal_uint32 afn,kal_uint32 ufn );
634
635
636/* For ARM Side OS Timer Sleep Mode Manager */
637extern kal_checksleep_e OSTD_CheckSleep( void );
638extern void OSTD_CSC_handler( void );
639extern kal_uint32 OSTD_CheckIsSleepLock(void);
640
641/* For AT CMD of AT+SLEEPCOUNT */
642extern kal_bool OSTD_SleepCountGet( kal_uint32 * cnt, kal_uint32 * time, kal_uint32 * acc_time );
643extern kal_bool OSTD_SleepCountSet( kal_uint32 op );
644extern kal_bool OSTD_GetModemSleepTime( kal_uint32 *acc_time );
645
646/* For Modem Infinite Sleep */
647extern kal_bool OSTD_Radio_On_Query(void);
648extern kal_bool OSTD_Infinite_Sleep_Query(void);
649extern kal_chkslp_inf_e OSTD_chkslp_is_all_timers_infinite_sleep(void);
650extern OSTD_RESULT_E OSTD_MD_Infinite_Sleep(void);
651extern OSTD_RESULT_E OSTD_Infinite_Sleep_TimerInform(OSTD_TIMER_TYPE_E timer, kal_bool sta);
652extern void OSTD_Radio_ON(void);
653extern void OSTD_Radio_OFF(void);
654extern void OSTD_Radio_OFF_SleepCheck(void);
655extern void OSTD_UnmaskIRQ( void );
656
657/* For Power Modelling */
658extern void OSTD_Idle_Rate_Logging(kal_uint32);
659
660/* For Mumtas*/
661#ifndef L1_SIM
662extern ostd_ap_core_status_enum OSTD_return_AP_status(void);
663extern void is_pending_data(char* module_name, kal_bool flag);
664#endif
665#endif
666
667#endif /*__CENTRALIZED_SLEEP_MANAGER__*/
668