Gitiles
Code Review Sign In
192.168.1.100 / T800_MD / 6c1fd8fba87d5723e0e5614ae30b4258b603cb70 / . / mcu / interface / driver / sys_drv / mdm_trc.h
blob: 069ebd0152ac8c5c66b8f0ef839b9f92e903410b [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame^]1
2/*****************************************************************************
3* Copyright Statement:
4* --------------------
5* This software is protected by Copyright and the information contained
6* herein is confidential. The software may not be copied and the information
7* contained herein may not be used or disclosed except with the written
8* permission of MediaTek Inc. (C) 2005
9*
10* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
11* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
12* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
13* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
14* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
15* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
16* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
17* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
18* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
19* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
20* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
21* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
22*
23* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
24* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
25* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
26* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
27* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
28*
29* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
30* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
31* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
32* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
33* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
34*
35*****************************************************************************/
36
37/*****************************************************************************
38 *
39 * Filename:
40 * ---------
41 * mdm_trc.h
42 *
43 * Project:
44 * --------
45 * UMOLYA
46 *
47 * Description:
48 * ------------
49 * This file defines the index trace of MDM module.
50 *
51 * Author:
52 * -------
53 * -------
54 *
55 *==============================================================================
56 * HISTORY
57 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
58 *------------------------------------------------------------------------------
59 * removed!
60 * removed!
61 * removed!
62 *
63 * removed!
64 * removed!
65 * removed!
66 *
67 * removed!
68 * removed!
69 * removed!
70 *
71 * removed!
72 * removed!
73 * removed!
74 *
75 * removed!
76 * removed!
77 * removed!
78 *
79 * removed!
80 * removed!
81 * removed!
82 *
83
84 *------------------------------------------------------------------------------
85 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
86 *============================================================================
87 ****************************************************************************/
88#ifndef _MDM_TRACE_H
89#define _MDM_TRACE_H
90
91void MDM_ASSERT(kal_uint32 e1, kal_uint32 e2, kal_uint32 e3);
92void MDM_kal_fatal_error_handler(kal_uint32 code1, kal_uint32 code2);
93void MDM_EXCEPTION(void);
94
95#define MDM_BASE 0xb0490000
96#define MDM32P volatile unsigned int *
97#define MDM_TM_TINFOMSG ((MDM32P)(MDM_BASE+0x0000)) //apb32 Information Message Register (T)
98#define MDM_TM_TPAR ((MDM32P)(MDM_BASE+0x0004)) //apb32 message parameter
99#define MDM_TM_INFOMSG ((MDM32P)(MDM_BASE+0x0008)) //apb32 Information Message Register
100#define MDM_TM_ERRMSG ((MDM32P)(MDM_BASE+0x000C)) //apb32 Error Message Register
101#define MDM_TM_TTAG ((MDM32P)(MDM_BASE+0x0010)) //apb32 TTAG
102#define MDM_TM_ENDSIM ((MDM32P)(MDM_BASE+0x0014)) //apb32 End Simulation Register
103#define MDM_TM_ERRCNT ((MDM32P)(MDM_BASE+0x0018)) //apb32 Error Count Register
104#define MDM_TM_DBGINFO ((MDM32P)(MDM_BASE+0x001c)) //apb32 Debug Infomation
105#define MDM_TM_TERRMSG ((MDM32P)(MDM_BASE+0x0020)) //apb32 Error Message Register (T)
106#define MDM_TM_TBLANK ((MDM32P)(MDM_BASE+0x0024)) //apb32 Blank line (T)
107#define MDM_TM_ENDFAIL ((MDM32P)(MDM_BASE+0x0028)) //apb32 End Simulation With Fail Msg
108#define MDM_TM_ENDSUCC ((MDM32P)(MDM_BASE+0x002C)) //apb32 End Simulation With Success Msg
109#define MDM_TM_ENDASSERT ((MDM32P)(MDM_BASE+0x0030)) //apb32 End Simulation Register
110#define MDM_TM_ALLFMT32B ((MDM32P)(MDM_BASE+0x0034)) //apb32 Display All Format 32b Value
111#define MDM_TM_HEXFMT32B ((MDM32P)(MDM_BASE+0x0038)) //apb32 Display Hexa Format 32b Value
112#define MDM_TM_DECFMT32B ((MDM32P)(MDM_BASE+0x003C)) //apb32 Display Dec Format 32b Value
113#define MDM_TM_BINFMT32B ((MDM32P)(MDM_BASE+0x0040)) //apb32 Display Bin Format 32b Value
114#define MDM_TM_HEXFMT16B ((MDM32P)(MDM_BASE+0x0044)) //apb32 Display Hexa Format 16b Value
115#define MDM_TM_DECFMT16B ((MDM32P)(MDM_BASE+0x0048)) //apb32 Display Dec Format 16b Value
116#define MDM_TM_BINFMT16B ((MDM32P)(MDM_BASE+0x004C)) //apb32 Display Bin Format 16b Value
117
118#define MDM_TM_MEMDUMPSTR ((MDM32P)(MDM_BASE+0x0050)) //apb32 Start Address of Memory Dumping
119#define MDM_TM_MEMDUMPSTOP ((MDM32P)(MDM_BASE+0x0054)) //apb32 Stop Address of Memory Dumping
120
121#define MDM_TM_MEMGOLDENSTR ((MDM32P)(MDM_BASE+0x0058)) //apb32 Start Address of Memory Compare(Golden)
122#define MDM_TM_MEMGOLDENSTOP ((MDM32P)(MDM_BASE+0x005C)) //apb32 Stop Address of Memory Compare(Golden)
123
124#define MDM_TM_MEMREVISESTR ((MDM32P)(MDM_BASE+0x0060)) //apb32 Start Address of Memory Compare(Revised)
125#define MDM_TM_MEMREVISESTOP ((MDM32P)(MDM_BASE+0x0064)) //apb32 Stop Address of Memory Compare(Revised)
126#define MDM_TM_EXT_MEM_INFO ((MDM32P)(MDM_BASE+0x0068)) // apb32
127 // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
128 // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
129 // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
130 // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
131 // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
132 // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
133#define MDM_TM_RUNTIME_USEC ((MDM32P)(MDM_BASE+0x006C)) // apb32
134#define MDM_TM_PHASE ((MDM32P)(MDM_BASE+0x0070)) // apb32 rtl/post
135 // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
136 // [5:4]: {0:none, 1:max, 2:typ, 3:min}
137#define MDM_TM_SIM_OPTION ((MDM32P)(MDM_BASE+0x0074)) // apb32
138 // [0]: PLL enable -> {0:OFF, 1:ON}
139//`define TM_CFSDB_CTRL ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
140//`define TM_DMESS_CTRL ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
141
142#define MDM_TM_FSDBDUMPFILE ((MDM32P)(MDM_BASE+0x0080)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
143#define MDM_TM_FSDBDUMPVARS ((MDM32P)(MDM_BASE+0x0084)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
144#define MDM_TM_FSDBDUMP ((MDM32P)(MDM_BASE+0x0088)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
145#define MDM_TM_FSDBDUMPSCOPE ((MDM32P)(MDM_BASE+0x008C)) // apb32
146
147#define MDM_TM_STR_CLEAR ((MDM32P)(MDM_BASE+0x0090)) // apb32 clear string ptr
148#define MDM_TM_STR_DISPLAY ((MDM32P)(MDM_BASE+0x0094)) // apb32 display string buf
149#define MDM_TM_STR0 ((MDM32P)(MDM_BASE+0x0098)) // apb32 string buffer to be displayed
150#define MDM_TM_STR1 ((MDM32P)(MDM_BASE+0x009c)) // apb32 string buffer to be displayed
151#define MDM_TM_STR2 ((MDM32P)(MDM_BASE+0x00a0)) // apb32 string buffer to be displayed
152#define MDM_TM_STR3 ((MDM32P)(MDM_BASE+0x00a4)) // apb32 string buffer to be displayed
153#define MDM_TM_STR4 ((MDM32P)(MDM_BASE+0x00a8)) // apb32 string buffer to be displayed
154#define MDM_TM_STR5 ((MDM32P)(MDM_BASE+0x00ac)) // apb32 string buffer to be displayed
155#define MDM_TM_STR6 ((MDM32P)(MDM_BASE+0x00b0)) // apb32 string buffer to be displayed
156#define MDM_TM_STR7 ((MDM32P)(MDM_BASE+0x00b4)) // apb32 string buffer to be displayed
157
158#define MDM_TRIG_IRQ ((MDM32P)(MDM_BASE+0x00b8)) // apb32 trigger EIRQ
159#define MDM_TRIG_IRQ2 ((MDM32P)(MDM_BASE+0x00bC)) // apb32 trigger EIRQ
160#define MDM_WAIT_TRIG ((MDM32P)(MDM_BASE+0x0078)) // apb32 trigger EIRQ
161#define MDM_WAIT_TRIG2 ((MDM32P)(MDM_BASE+0x007C)) // apb32 trigger EIRQ
162
163 // for MDM_cosim purpose, to replace bsi_reg usage
164#define MDM_CORE0VPE0_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00C0)) //core 0 to core0
165#define MDM_CORE0VPE1_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00C4)) //core 1 to core0
166#define MDM_CORE1VPE0_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00C8)) //core 2 to core0
167#define MDM_CORE1VPE1_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00CC)) //core 3 to core0
168#define MDM_CORE2VPE0_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00D0)) //core 4 to core0
169#define MDM_CORE2VPE1_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00D4)) //core 5 to core0
170#define MDM_CORE3VPE0_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00D8)) //core 6 to core0
171#define MDM_CORE3VPE1_TO_CORE0VPE0 ((MDM32P)(MDM_BASE+0x00DC)) //core 7 to core0
172
173#define MDM_MDM_SIMIF0_CTRL ((MDM32P)(MDM_BASE+0x00E0)) //apb32
174#define MDM_MDM_SIMIF1_CTRL ((MDM32P)(MDM_BASE+0x00E4)) //apb32
175
176#define MDM_TM_FH_CTRL ((MDM32P)(MDM_BASE+0x00E8)) //apb32
177#define MDM_DELAY ((MDM32P)(MDM_BASE+0x00EC)) //apb32
178#define MDM_RANDOM_DELAY_MIN ((MDM32P)(MDM_BASE+0x00F0)) //apb32
179#define MDM_RANDOM_DELAY_MAX ((MDM32P)(MDM_BASE+0x00F4)) //apb32
180#define MDM_URANDOM_RANGE_MIN ((MDM32P)(MDM_BASE+0x00F8)) //apb32
181#define MDM_URANDOM_RANGE_MAX ((MDM32P)(MDM_BASE+0x00FC)) //apb32
182
183
184#define MDM_TM_TINFOMSG_01 ((MDM32P)(MDM_BASE+0x0100)) //apb32 Information Message Register (T)
185#define MDM_TM_TPAR_01 ((MDM32P)(MDM_BASE+0x0104)) //apb32 message parameter
186#define MDM_TM_INFOMSG_01 ((MDM32P)(MDM_BASE+0x0108)) //apb32 Information Message Register
187#define MDM_TM_ERRMSG_01 ((MDM32P)(MDM_BASE+0x010C)) //apb32 Error Message Register
188#define MDM_TM_TTAG_01 ((MDM32P)(MDM_BASE+0x0110)) //apb32 TTAG
189#define MDM_TM_ENDSIM_01 ((MDM32P)(MDM_BASE+0x0114)) //apb32 End Simulation Register
190#define MDM_TM_ERRCNT_01 ((MDM32P)(MDM_BASE+0x0118)) //apb32 Error Count Register
191#define MDM_TM_DBGINFO_01 ((MDM32P)(MDM_BASE+0x011c)) //apb32 Debug Infomation
192#define MDM_TM_TERRMSG_01 ((MDM32P)(MDM_BASE+0x0120)) //apb32 Error Message Register (T)
193#define MDM_TM_TBLANK_01 ((MDM32P)(MDM_BASE+0x0124)) //apb32 Blank line (T)
194#define MDM_TM_ENDFAIL_01 ((MDM32P)(MDM_BASE+0x0128)) //apb32 End Simulation With Fail Msg
195#define MDM_TM_ENDSUCC_01 ((MDM32P)(MDM_BASE+0x012C)) //apb32 End Simulation With Success Msg
196#define MDM_TM_ENDASSERT_01 ((MDM32P)(MDM_BASE+0x0130)) //apb32 End Simulation Register
197#define MDM_TM_ALLFMT32B_01 ((MDM32P)(MDM_BASE+0x0134)) //apb32 Display All Format 32b Value
198#define MDM_TM_HEXFMT32B_01 ((MDM32P)(MDM_BASE+0x0138)) //apb32 Display Hexa Format 32b Value
199#define MDM_TM_DECFMT32B_01 ((MDM32P)(MDM_BASE+0x013C)) //apb32 Display Dec Format 32b Value
200#define MDM_TM_BINFMT32B_01 ((MDM32P)(MDM_BASE+0x0140)) //apb32 Display Bin Format 32b Value
201#define MDM_TM_HEXFMT16B_01 ((MDM32P)(MDM_BASE+0x0144)) //apb32 Display Hexa Format 16b Value
202#define MDM_TM_DECFMT16B_01 ((MDM32P)(MDM_BASE+0x0148)) //apb32 Display Dec Format 16b Value
203#define MDM_TM_BINFMT16B_01 ((MDM32P)(MDM_BASE+0x014C)) //apb32 Display Bin Format 16b Value
204
205#define MDM_TM_MEMDUMPSTR_01 ((MDM32P)(MDM_BASE+0x0150)) //apb32 Start Address of Memory Dumping
206#define MDM_TM_MEMDUMPSTOP_01 ((MDM32P)(MDM_BASE+0x0154)) //apb32 Stop Address of Memory Dumping
207
208#define MDM_TM_MEMGOLDENSTR_01 ((MDM32P)(MDM_BASE+0x0158)) //apb32 Start Address of Memory Compare(Golden)
209#define MDM_TM_MEMGOLDENSTOP_01 ((MDM32P)(MDM_BASE+0x015C)) //apb32 Stop Address of Memory Compare(Golden)
210
211#define MDM_TM_MEMREVISESTR_01 ((MDM32P)(MDM_BASE+0x0160)) //apb32 Start Address of Memory Compare(Revised)
212#define MDM_TM_MEMREVISESTOP_01 ((MDM32P)(MDM_BASE+0x0164)) //apb32 Stop Address of Memory Compare(Revised)
213#define MDM_TM_EXT_MEM_INFO_01 ((MDM32P)(MDM_BASE+0x0168)) // apb32
214 // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
215 // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
216 // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
217 // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
218 // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
219 // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
220#define MDM_TM_RUNTIME_USEC_01 ((MDM32P)(MDM_BASE+0x016C)) // apb32
221#define MDM_TM_PHASE_01 ((MDM32P)(MDM_BASE+0x0170)) // apb32 rtl/post
222 // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
223 // [5:4]: {0:none, 1:max, 2:typ, 3:min}
224#define MDM_TM_SIM_OPTION_01 ((MDM32P)(MDM_BASE+0x0174)) // apb32
225 // [0]: PLL enable -> {0:OFF, 1:ON}
226//`define TM_CFSDB_CTRL_01 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
227//`define TM_DMESS_CTRL_01 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
228
229#define MDM_TM_FSDBDUMPFILE_01 ((MDM32P)(MDM_BASE+0x0180)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
230#define MDM_TM_FSDBDUMPVARS_01 ((MDM32P)(MDM_BASE+0x0184)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
231#define MDM_TM_FSDBDUMP_01 ((MDM32P)(MDM_BASE+0x0188)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
232#define MDM_TM_FSDBDUMPSCOPE_01 ((MDM32P)(MDM_BASE+0x018C)) // apb32
233
234#define MDM_TM_STR_CLEAR_01 ((MDM32P)(MDM_BASE+0x0190)) // apb32 clear string ptr
235#define MDM_TM_STR_DISPLAY_01 ((MDM32P)(MDM_BASE+0x0194)) // apb32 display string buf
236#define MDM_TM_STR0_01 ((MDM32P)(MDM_BASE+0x0198)) // apb32 string buffer to be displayed
237#define MDM_TM_STR1_01 ((MDM32P)(MDM_BASE+0x019C)) // apb32 string buffer to be displayed
238#define MDM_TM_STR2_01 ((MDM32P)(MDM_BASE+0x01A0)) // apb32 string buffer to be displayed
239#define MDM_TM_STR3_01 ((MDM32P)(MDM_BASE+0x01A4)) // apb32 string buffer to be displayed
240#define MDM_TM_STR4_01 ((MDM32P)(MDM_BASE+0x01A8)) // apb32 string buffer to be displayed
241#define MDM_TM_STR5_01 ((MDM32P)(MDM_BASE+0x01AC)) // apb32 string buffer to be displayed
242#define MDM_TM_STR6_01 ((MDM32P)(MDM_BASE+0x01B0)) // apb32 string buffer to be displayed
243#define MDM_TM_STR7_01 ((MDM32P)(MDM_BASE+0x01B4)) // apb32 string buffer to be displayed
244
245#define MDM_TRIG_IRQ_01 ((MDM32P)(MDM_BASE+0x01B8)) // apb32 trigger EIRQ
246#define MDM_TRIG_IRQ2_01 ((MDM32P)(MDM_BASE+0x01BC)) // apb32 trigger EIRQ
247#define MDM_WAIT_TRIG_01 ((MDM32P)(MDM_BASE+0x0178)) // apb32 trigger EIRQ
248#define MDM_WAIT_TRIG2_01 ((MDM32P)(MDM_BASE+0x017C)) // apb32 trigger EIRQ
249
250 // for MDM_cosim purpose, to replace bsi_reg usage
251#define MDM_CORE0VPE0_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01C0)) //core 0 to core0
252#define MDM_CORE0VPE1_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01C4)) //core 1 to core0
253#define MDM_CORE1VPE0_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01C8)) //core 2 to core0
254#define MDM_CORE1VPE1_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01CC)) //core 3 to core0
255#define MDM_CORE2VPE0_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01D0)) //core 4 to core0
256#define MDM_CORE2VPE1_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01D4)) //core 5 to core0
257#define MDM_CORE3VPE0_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01D8)) //core 6 to core0
258#define MDM_CORE3VPE1_TO_CORE0VPE1 ((MDM32P)(MDM_BASE+0x01DC)) //core 7 to core0
259
260#define MDM_MDM_SIMIF0_CTRL_01 ((MDM32P)(MDM_BASE+0x01E0)) //apb32
261#define MDM_MDM_SIMIF1_CTRL_01 ((MDM32P)(MDM_BASE+0x01E4)) //apb32
262
263#define MDM_TM_FH_CTRL_01 ((MDM32P)(MDM_BASE+0x01E8)) //apb32
264#define MDM_DELAY_01 ((MDM32P)(MDM_BASE+0x01EC)) //apb32
265#define MDM_RANDOM_DELAY_MIN_01 ((MDM32P)(MDM_BASE+0x01F0)) //apb32
266#define MDM_RANDOM_DELAY_MAX_01 ((MDM32P)(MDM_BASE+0x01F4)) //apb32
267#define MDM_URANDOM_RANGE_MIN_01 ((MDM32P)(MDM_BASE+0x01F8)) //apb32
268#define MDM_URANDOM_RANGE_MAX_01 ((MDM32P)(MDM_BASE+0x01FC)) //apb32
269
270#define MDM_TM_TINFOMSG_10 ((MDM32P)(MDM_BASE+0x1000)) //apb32 Information Message Register (T)
271#define MDM_TM_TPAR_10 ((MDM32P)(MDM_BASE+0x1004)) //apb32 message parameter
272#define MDM_TM_INFOMSG_10 ((MDM32P)(MDM_BASE+0x1008)) //apb32 Information Message Register
273#define MDM_TM_ERRMSG_10 ((MDM32P)(MDM_BASE+0x100C)) //apb32 Error Message Register
274#define MDM_TM_TTAG_10 ((MDM32P)(MDM_BASE+0x1010)) //apb32 TTAG
275#define MDM_TM_ENDSIM_10 ((MDM32P)(MDM_BASE+0x1014)) //apb32 End Simulation Register
276#define MDM_TM_ERRCNT_10 ((MDM32P)(MDM_BASE+0x1018)) //apb32 Error Count Register
277#define MDM_TM_DBGINFO_10 ((MDM32P)(MDM_BASE+0x101C)) //apb32 Debug Infomation
278#define MDM_TM_TERRMSG_10 ((MDM32P)(MDM_BASE+0x1020)) //apb32 Error Message Register (T)
279#define MDM_TM_TBLANK_10 ((MDM32P)(MDM_BASE+0x1024)) //apb32 Blank line (T)
280#define MDM_TM_ENDFAIL_10 ((MDM32P)(MDM_BASE+0x1028)) //apb32 End Simulation With Fail Msg
281#define MDM_TM_ENDSUCC_10 ((MDM32P)(MDM_BASE+0x102C)) //apb32 End Simulation With Success Msg
282#define MDM_TM_ENDASSERT_10 ((MDM32P)(MDM_BASE+0x1030)) //apb32 End Simulation Register
283#define MDM_TM_ALLFMT32B_10 ((MDM32P)(MDM_BASE+0x1034)) //apb32 Display All Format 32b Value
284#define MDM_TM_HEXFMT32B_10 ((MDM32P)(MDM_BASE+0x1038)) //apb32 Display Hexa Format 32b Value
285#define MDM_TM_DECFMT32B_10 ((MDM32P)(MDM_BASE+0x103C)) //apb32 Display Dec Format 32b Value
286#define MDM_TM_BINFMT32B_10 ((MDM32P)(MDM_BASE+0x1040)) //apb32 Display Bin Format 32b Value
287#define MDM_TM_HEXFMT16B_10 ((MDM32P)(MDM_BASE+0x1044)) //apb32 Display Hexa Format 16b Value
288#define MDM_TM_DECFMT16B_10 ((MDM32P)(MDM_BASE+0x1048)) //apb32 Display Dec Format 16b Value
289#define MDM_TM_BINFMT16B_10 ((MDM32P)(MDM_BASE+0x104C)) //apb32 Display Bin Format 16b Value
290
291#define MDM_TM_MEMDUMPSTR_10 ((MDM32P)(MDM_BASE+0x1050)) //apb32 Start Address of Memory Dumping
292#define MDM_TM_MEMDUMPSTOP_10 ((MDM32P)(MDM_BASE+0x1054)) //apb32 Stop Address of Memory Dumping
293
294#define MDM_TM_MEMGOLDENSTR_10 ((MDM32P)(MDM_BASE+0x1058)) //apb32 Start Address of Memory Compare(Golden)
295#define MDM_TM_MEMGOLDENSTOP_10 ((MDM32P)(MDM_BASE+0x105C)) //apb32 Stop Address of Memory Compare(Golden)
296
297#define MDM_TM_MEMREVISESTR_10 ((MDM32P)(MDM_BASE+0x1060)) //apb32 Start Address of Memory Compare(Revised)
298#define MDM_TM_MEMREVISESTOP_10 ((MDM32P)(MDM_BASE+0x1064)) //apb32 Stop Address of Memory Compare(Revised)
299#define MDM_TM_EXT_MEM_INFO_10 ((MDM32P)(MDM_BASE+0x1068)) // apb32
300 // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
301 // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
302 // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
303 // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
304 // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
305 // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
306#define MDM_TM_RUNTIME_USEC_10 ((MDM32P)(MDM_BASE+0x106C)) // apb32
307#define MDM_TM_PHASE_10 ((MDM32P)(MDM_BASE+0x1070)) // apb32 rtl/post
308 // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
309 // [5:4]: {0:none, 1:max, 2:typ, 3:min}
310#define MDM_TM_SIM_OPTION_10 ((MDM32P)(MDM_BASE+0x1074)) // apb32
311 // [0]: PLL enable -> {0:OFF, 1:ON}
312//`define TM_CFSDB_CTRL_10 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
313//`define TM_DMESS_CTRL_10 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
314
315#define MDM_TM_FSDBDUMPFILE_10 ((MDM32P)(MDM_BASE+0x1080)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
316#define MDM_TM_FSDBDUMPVARS_10 ((MDM32P)(MDM_BASE+0x1084)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
317#define MDM_TM_FSDBDUMP_10 ((MDM32P)(MDM_BASE+0x1088)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
318#define MDM_TM_FSDBDUMPSCOPE_10 ((MDM32P)(MDM_BASE+0x108C)) // apb32
319
320#define MDM_TM_STR_CLEAR_10 ((MDM32P)(MDM_BASE+0x1090)) // apb32 clear string ptr
321#define MDM_TM_STR_DISPLAY_10 ((MDM32P)(MDM_BASE+0x1094)) // apb32 display string buf
322#define MDM_TM_STR0_10 ((MDM32P)(MDM_BASE+0x1098)) // apb32 string buffer to be displayed
323#define MDM_TM_STR1_10 ((MDM32P)(MDM_BASE+0x109C)) // apb32 string buffer to be displayed
324#define MDM_TM_STR2_10 ((MDM32P)(MDM_BASE+0x10A0)) // apb32 string buffer to be displayed
325#define MDM_TM_STR3_10 ((MDM32P)(MDM_BASE+0x10A4)) // apb32 string buffer to be displayed
326#define MDM_TM_STR4_10 ((MDM32P)(MDM_BASE+0x10A8)) // apb32 string buffer to be displayed
327#define MDM_TM_STR5_10 ((MDM32P)(MDM_BASE+0x10AC)) // apb32 string buffer to be displayed
328#define MDM_TM_STR6_10 ((MDM32P)(MDM_BASE+0x10B0)) // apb32 string buffer to be displayed
329#define MDM_TM_STR7_10 ((MDM32P)(MDM_BASE+0x10B4)) // apb32 string buffer to be displayed
330
331#define MDM_TRIG_IRQ_10 ((MDM32P)(MDM_BASE+0x10B8)) // apb32 trigger EIRQ
332#define MDM_TRIG_IRQ2_10 ((MDM32P)(MDM_BASE+0x10BC)) // apb32 trigger EIRQ
333#define MDM_WAIT_TRIG_10 ((MDM32P)(MDM_BASE+0x1078)) // apb32 trigger EIRQ
334#define MDM_WAIT_TRIG2_10 ((MDM32P)(MDM_BASE+0x107C)) // apb32 trigger EIRQ
335
336 // for MDM_cosim purpose, to replace bsi_reg usage
337#define MDM_CORE0VPE0_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10C0)) //core 0 to core0
338#define MDM_CORE0VPE1_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10C4)) //core 1 to core0
339#define MDM_CORE1VPE0_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10C8)) //core 2 to core0
340#define MDM_CORE1VPE1_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10CC)) //core 3 to core0
341#define MDM_CORE2VPE0_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10D0)) //core 4 to core0
342#define MDM_CORE2VPE1_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10D4)) //core 5 to core0
343#define MDM_CORE3VPE0_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10D8)) //core 6 to core0
344#define MDM_CORE3VPE1_TO_CORE1VPE0 ((MDM32P)(MDM_BASE+0x10DC)) //core 7 to core0
345
346#define MDM_MDM_SIMIF0_CTRL_10 ((MDM32P)(MDM_BASE+0x10E0)) //apb32
347#define MDM_MDM_SIMIF1_CTRL_10 ((MDM32P)(MDM_BASE+0x10E4)) //apb32
348
349#define MDM_TM_FH_CTRL_10 ((MDM32P)(MDM_BASE+0x10E8)) //apb32
350#define MDM_DELAY_10 ((MDM32P)(MDM_BASE+0x10EC)) //apb32
351#define MDM_RANDOM_DELAY_MIN_10 ((MDM32P)(MDM_BASE+0x10F0)) //apb32
352#define MDM_RANDOM_DELAY_MAX_10 ((MDM32P)(MDM_BASE+0x10F4)) //apb32
353#define MDM_URANDOM_RANGE_MIN_10 ((MDM32P)(MDM_BASE+0x10F8)) //apb32
354#define MDM_URANDOM_RANGE_MAX_10 ((MDM32P)(MDM_BASE+0x10FC)) //apb32
355
356#define MDM_TM_TINFOMSG_11 ((MDM32P)(MDM_BASE+0x1100)) //apb32 Information Message Register (T)
357#define MDM_TM_TPAR_11 ((MDM32P)(MDM_BASE+0x1104)) //apb32 message parameter
358#define MDM_TM_INFOMSG_11 ((MDM32P)(MDM_BASE+0x1108)) //apb32 Information Message Register
359#define MDM_TM_ERRMSG_11 ((MDM32P)(MDM_BASE+0x110C)) //apb32 Error Message Register
360#define MDM_TM_TTAG_11 ((MDM32P)(MDM_BASE+0x1110)) //apb32 TTAG
361#define MDM_TM_ENDSIM_11 ((MDM32P)(MDM_BASE+0x1114)) //apb32 End Simulation Register
362#define MDM_TM_ERRCNT_11 ((MDM32P)(MDM_BASE+0x1118)) //apb32 Error Count Register
363#define MDM_TM_DBGINFO_11 ((MDM32P)(MDM_BASE+0x111C)) //apb32 Debug Infomation
364#define MDM_TM_TERRMSG_11 ((MDM32P)(MDM_BASE+0x1120)) //apb32 Error Message Register (T)
365#define MDM_TM_TBLANK_11 ((MDM32P)(MDM_BASE+0x1124)) //apb32 Blank line (T)
366#define MDM_TM_ENDFAIL_11 ((MDM32P)(MDM_BASE+0x1128)) //apb32 End Simulation With Fail Msg
367#define MDM_TM_ENDSUCC_11 ((MDM32P)(MDM_BASE+0x112C)) //apb32 End Simulation With Success Msg
368#define MDM_TM_ENDASSERT_11 ((MDM32P)(MDM_BASE+0x1130)) //apb32 End Simulation Register
369#define MDM_TM_ALLFMT32B_11 ((MDM32P)(MDM_BASE+0x1134)) //apb32 Display All Format 32b Value
370#define MDM_TM_HEXFMT32B_11 ((MDM32P)(MDM_BASE+0x1138)) //apb32 Display Hexa Format 32b Value
371#define MDM_TM_DECFMT32B_11 ((MDM32P)(MDM_BASE+0x113C)) //apb32 Display Dec Format 32b Value
372#define MDM_TM_BINFMT32B_11 ((MDM32P)(MDM_BASE+0x1140)) //apb32 Display Bin Format 32b Value
373#define MDM_TM_HEXFMT16B_11 ((MDM32P)(MDM_BASE+0x1144)) //apb32 Display Hexa Format 16b Value
374#define MDM_TM_DECFMT16B_11 ((MDM32P)(MDM_BASE+0x1148)) //apb32 Display Dec Format 16b Value
375#define MDM_TM_BINFMT16B_11 ((MDM32P)(MDM_BASE+0x114C)) //apb32 Display Bin Format 16b Value
376
377#define MDM_TM_MEMDUMPSTR_11 ((MDM32P)(MDM_BASE+0x1150)) //apb32 Start Address of Memory Dumping
378#define MDM_TM_MEMDUMPSTOP_11 ((MDM32P)(MDM_BASE+0x1154)) //apb32 Stop Address of Memory Dumping
379
380#define MDM_TM_MEMGOLDENSTR_11 ((MDM32P)(MDM_BASE+0x1158)) //apb32 Start Address of Memory Compare(Golden)
381#define MDM_TM_MEMGOLDENSTOP_11 ((MDM32P)(MDM_BASE+0x115C)) //apb32 Stop Address of Memory Compare(Golden)
382
383#define MDM_TM_MEMREVISESTR_11 ((MDM32P)(MDM_BASE+0x1160)) //apb32 Start Address of Memory Compare(Revised)
384#define MDM_TM_MEMREVISESTOP_11 ((MDM32P)(MDM_BASE+0x1164)) //apb32 Stop Address of Memory Compare(Revised)
385#define MDM_TM_EXT_MEM_INFO_11 ((MDM32P)(MDM_BASE+0x1168)) // apb32
386 // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
387 // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
388 // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
389 // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
390 // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
391 // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
392#define MDM_TM_RUNTIME_USEC_11 ((MDM32P)(MDM_BASE+0x116C)) // apb32
393#define MDM_TM_PHASE_11 ((MDM32P)(MDM_BASE+0x1170)) // apb32 rtl/post
394 // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
395 // [5:4]: {0:none, 1:max, 2:typ, 3:min}
396#define MDM_TM_SIM_OPTION_11 ((MDM32P)(MDM_BASE+0x1174)) // apb32
397 // [0]: PLL enable -> {0:OFF, 1:ON}
398//`define TM_CFSDB_CTRL_11 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
399//`define TM_DMESS_CTRL_11 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
400
401#define MDM_TM_FSDBDUMPFILE_11 ((MDM32P)(MDM_BASE+0x1180)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
402#define MDM_TM_FSDBDUMPVARS_11 ((MDM32P)(MDM_BASE+0x1184)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
403#define MDM_TM_FSDBDUMP_11 ((MDM32P)(MDM_BASE+0x1188)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
404#define MDM_TM_FSDBDUMPSCOPE_11 ((MDM32P)(MDM_BASE+0x118C)) // apb32
405
406#define MDM_TM_STR_CLEAR_11 ((MDM32P)(MDM_BASE+0x1190)) // apb32 clear string ptr
407#define MDM_TM_STR_DISPLAY_11 ((MDM32P)(MDM_BASE+0x1194)) // apb32 display string buf
408#define MDM_TM_STR0_11 ((MDM32P)(MDM_BASE+0x1198)) // apb32 string buffer to be displayed
409#define MDM_TM_STR1_11 ((MDM32P)(MDM_BASE+0x119C)) // apb32 string buffer to be displayed
410#define MDM_TM_STR2_11 ((MDM32P)(MDM_BASE+0x11A0)) // apb32 string buffer to be displayed
411#define MDM_TM_STR3_11 ((MDM32P)(MDM_BASE+0x11A4)) // apb32 string buffer to be displayed
412#define MDM_TM_STR4_11 ((MDM32P)(MDM_BASE+0x11A8)) // apb32 string buffer to be displayed
413#define MDM_TM_STR5_11 ((MDM32P)(MDM_BASE+0x11AC)) // apb32 string buffer to be displayed
414#define MDM_TM_STR6_11 ((MDM32P)(MDM_BASE+0x11B0)) // apb32 string buffer to be displayed
415#define MDM_TM_STR7_11 ((MDM32P)(MDM_BASE+0x11B4)) // apb32 string buffer to be displayed
416
417#define MDM_TRIG_IRQ_11 ((MDM32P)(MDM_BASE+0x11B8)) // apb32 trigger EIRQ
418#define MDM_TRIG_IRQ2_11 ((MDM32P)(MDM_BASE+0x11BC)) // apb32 trigger EIRQ
419#define MDM_WAIT_TRIG_11 ((MDM32P)(MDM_BASE+0x1178)) // apb32 trigger EIRQ
420#define MDM_WAIT_TRIG2_11 ((MDM32P)(MDM_BASE+0x117C)) // apb32 trigger EIRQ
421
422 // for MDM_cosim purpose, to replace bsi_reg usage
423#define MDM_CORE0VPE0_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11C0)) //core 0 to core0
424#define MDM_CORE0VPE1_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11C4)) //core 1 to core0
425#define MDM_CORE1VPE0_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11C8)) //core 2 to core0
426#define MDM_CORE1VPE1_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11CC)) //core 3 to core0
427#define MDM_CORE2VPE0_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11D0)) //core 4 to core0
428#define MDM_CORE2VPE1_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11D4)) //core 5 to core0
429#define MDM_CORE3VPE0_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11D8)) //core 6 to core0
430#define MDM_CORE3VPE1_TO_CORE1VPE1 ((MDM32P)(MDM_BASE+0x11DC)) //core 7 to core0
431
432#define MDM_MDM_SIMIF0_CTRL_11 ((MDM32P)(MDM_BASE+0x11E0)) //apb32
433#define MDM_MDM_SIMIF1_CTRL_11 ((MDM32P)(MDM_BASE+0x11E4)) //apb32
434
435#define MDM_TM_FH_CTRL_11 ((MDM32P)(MDM_BASE+0x11E8)) //apb32
436#define MDM_DELAY_11 ((MDM32P)(MDM_BASE+0x11EC)) //apb32
437#define MDM_RANDOM_DELAY_MIN_11 ((MDM32P)(MDM_BASE+0x11F0)) //apb32
438#define MDM_RANDOM_DELAY_MAX_11 ((MDM32P)(MDM_BASE+0x11F4)) //apb32
439#define MDM_URANDOM_RANGE_MIN_11 ((MDM32P)(MDM_BASE+0x11F8)) //apb32
440#define MDM_URANDOM_RANGE_MAX_11 ((MDM32P)(MDM_BASE+0x11Fc)) //apb32
441
442#ifdef INCLUDE_MT6293_NOT_INCLUDED_CORES
443#define MDM_TM_TINFOMSG_20 ((MDM32P)(MDM_BASE+0x2000)) //apb32 Information Message Register (T)
444#define MDM_TM_TPAR_20 ((MDM32P)(MDM_BASE+0x2004)) //apb32 message parameter
445#define MDM_TM_INFOMSG_20 ((MDM32P)(MDM_BASE+0x2008)) //apb32 Information Message Register
446#define MDM_TM_ERRMSG_20 ((MDM32P)(MDM_BASE+0x200C)) //apb32 Error Message Register
447#define MDM_TM_TTAG_20 ((MDM32P)(MDM_BASE+0x2010)) //apb32 TTAG
448#define MDM_TM_ENDSIM_20 ((MDM32P)(MDM_BASE+0x2014)) //apb32 End Simulation Register
449#define MDM_TM_ERRCNT_20 ((MDM32P)(MDM_BASE+0x2018)) //apb32 Error Count Register
450#define MDM_TM_DBGINFO_20 ((MDM32P)(MDM_BASE+0x201C)) //apb32 Debug Infomation
451#define MDM_TM_TERRMSG_20 ((MDM32P)(MDM_BASE+0x2020)) //apb32 Error Message Register (T)
452#define MDM_TM_TBLANK_20 ((MDM32P)(MDM_BASE+0x2024)) //apb32 Blank line (T)
453#define MDM_TM_ENDFAIL_20 ((MDM32P)(MDM_BASE+0x2028)) //apb32 End Simulation With Fail Msg
454#define MDM_TM_ENDSUCC_20 ((MDM32P)(MDM_BASE+0x202C)) //apb32 End Simulation With Success Msg
455#define MDM_TM_ENDASSERT_20 ((MDM32P)(MDM_BASE+0x2030)) //apb32 End Simulation Register
456#define MDM_TM_ALLFMT32B_20 ((MDM32P)(MDM_BASE+0x2034)) //apb32 Display All Format 32b Value
457#define MDM_TM_HEXFMT32B_20 ((MDM32P)(MDM_BASE+0x2038)) //apb32 Display Hexa Format 32b Value
458#define MDM_TM_DECFMT32B_20 ((MDM32P)(MDM_BASE+0x203C)) //apb32 Display Dec Format 32b Value
459#define MDM_TM_BINFMT32B_20 ((MDM32P)(MDM_BASE+0x2040)) //apb32 Display Bin Format 32b Value
460#define MDM_TM_HEXFMT16B_20 ((MDM32P)(MDM_BASE+0x2044)) //apb32 Display Hexa Format 16b Value
461#define MDM_TM_DECFMT16B_20 ((MDM32P)(MDM_BASE+0x2048)) //apb32 Display Dec Format 16b Value
462#define MDM_TM_BINFMT16B_20 ((MDM32P)(MDM_BASE+0x204C)) //apb32 Display Bin Format 16b Value
463
464#define MDM_TM_MEMDUMPSTR_20 ((MDM32P)(MDM_BASE+0x2050)) //apb32 Start Address of Memory Dumping
465#define MDM_TM_MEMDUMPSTOP_20 ((MDM32P)(MDM_BASE+0x2054)) //apb32 Stop Address of Memory Dumping
466
467#define MDM_TM_MEMGOLDENSTR_20 ((MDM32P)(MDM_BASE+0x2058)) //apb32 Start Address of Memory Compare(Golden)
468#define MDM_TM_MEMGOLDENSTOP_20 ((MDM32P)(MDM_BASE+0x205C)) //apb32 Stop Address of Memory Compare(Golden)
469
470#define MDM_TM_MEMREVISESTR_20 ((MDM32P)(MDM_BASE+0x2060)) //apb32 Start Address of Memory Compare(Revised)
471#define MDM_TM_MEMREVISESTOP_20 ((MDM32P)(MDM_BASE+0x2064)) //apb32 Stop Address of Memory Compare(Revised)
472#define MDM_TM_EXT_MEM_INFO_20 ((MDM32P)(MDM_BASE+0x2068)) // apb32
473 // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
474 // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
475 // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
476 // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
477 // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
478 // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
479#define MDM_TM_RUNTIME_USEC_20 ((MDM32P)(MDM_BASE+0x206C)) // apb32
480#define MDM_TM_PHASE_20 ((MDM32P)(MDM_BASE+0x2070)) // apb32 rtl/post
481 // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
482 // [5:4]: {0:none, 1:max, 2:typ, 3:min}
483#define MDM_TM_SIM_OPTION_20 ((MDM32P)(MDM_BASE+0x2074)) // apb32
484 // [0]: PLL enable -> {0:OFF, 1:ON}
485//`define TM_CFSDB_CTRL_20 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
486//`define TM_DMESS_CTRL_20 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
487
488#define MDM_TM_FSDBDUMPFILE_20 ((MDM32P)(MDM_BASE+0x2080)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
489#define MDM_TM_FSDBDUMPVARS_20 ((MDM32P)(MDM_BASE+0x2084)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
490#define MDM_TM_FSDBDUMP_20 ((MDM32P)(MDM_BASE+0x2088)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
491#define MDM_TM_FSDBDUMPSCOPE_20 ((MDM32P)(MDM_BASE+0x208C)) // apb32
492
493#define MDM_TM_STR_CLEAR_20 ((MDM32P)(MDM_BASE+0x2090)) // apb32 clear string ptr
494#define MDM_TM_STR_DISPLAY_20 ((MDM32P)(MDM_BASE+0x2094)) // apb32 display string buf
495#define MDM_TM_STR0_20 ((MDM32P)(MDM_BASE+0x2098)) // apb32 string buffer to be displayed
496#define MDM_TM_STR1_20 ((MDM32P)(MDM_BASE+0x209C)) // apb32 string buffer to be displayed
497#define MDM_TM_STR2_20 ((MDM32P)(MDM_BASE+0x20A0)) // apb32 string buffer to be displayed
498#define MDM_TM_STR3_20 ((MDM32P)(MDM_BASE+0x20A4)) // apb32 string buffer to be displayed
499#define MDM_TM_STR4_20 ((MDM32P)(MDM_BASE+0x20A8)) // apb32 string buffer to be displayed
500#define MDM_TM_STR5_20 ((MDM32P)(MDM_BASE+0x20AC)) // apb32 string buffer to be displayed
501#define MDM_TM_STR6_20 ((MDM32P)(MDM_BASE+0x20B0)) // apb32 string buffer to be displayed
502#define MDM_TM_STR7_20 ((MDM32P)(MDM_BASE+0x20B4)) // apb32 string buffer to be displayed
503
504#define MDM_TRIG_IRQ_20 ((MDM32P)(MDM_BASE+0x20B8)) // apb32 trigger EIRQ
505#define MDM_TRIG_IRQ2_20 ((MDM32P)(MDM_BASE+0x20BC)) // apb32 trigger EIRQ
506#define MDM_WAIT_TRIG_20 ((MDM32P)(MDM_BASE+0x2078)) // apb32 trigger EIRQ
507#define MDM_WAIT_TRIG2_20 ((MDM32P)(MDM_BASE+0x207C)) // apb32 trigger EIRQ
508
509 // for MDM_cosim purpose, to replace bsi_reg usage
510#define MDM_CORE0VPE0_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20C0)) //core 0 to core0
511#define MDM_CORE0VPE1_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20C4)) //core 1 to core0
512#define MDM_CORE1VPE0_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20C8)) //core 2 to core0
513#define MDM_CORE1VPE1_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20CC)) //core 3 to core0
514#define MDM_CORE2VPE0_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20D0)) //core 4 to core0
515#define MDM_CORE2VPE1_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20D4)) //core 5 to core0
516#define MDM_CORE3VPE0_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20D8)) //core 6 to core0
517#define MDM_CORE3VPE1_TO_CORE2VPE0 ((MDM32P)(MDM_BASE+0x20DC)) //core 7 to core0
518
519#define MDM_MDM_SIMIF0_CTRL_20 ((MDM32P)(MDM_BASE+0x20E0)) //apb32
520#define MDM_MDM_SIMIF1_CTRL_20 ((MDM32P)(MDM_BASE+0x20E4)) //apb32
521
522#define MDM_TM_FH_CTRL_20 ((MDM32P)(MDM_BASE+0x20E8)) //apb32
523#define MDM_DELAY_20 ((MDM32P)(MDM_BASE+0x20EC)) //apb32
524#define MDM_RANDOM_DELAY_MIN_20 ((MDM32P)(MDM_BASE+0x20F0)) //apb32
525#define MDM_RANDOM_DELAY_MAX_20 ((MDM32P)(MDM_BASE+0x20F4)) //apb32
526#define MDM_URANDOM_RANGE_MIN_20 ((MDM32P)(MDM_BASE+0x20F8)) //apb32
527#define MDM_URANDOM_RANGE_MAX_20 ((MDM32P)(MDM_BASE+0x20Fc)) //apb32
528
529#define MDM_TM_TINFOMSG_21 ((MDM32P)(MDM_BASE+0x2100)) //apb32 Information Message Register (T)
530#define MDM_TM_TPAR_21 ((MDM32P)(MDM_BASE+0x2104)) //apb32 message parameter
531#define MDM_TM_INFOMSG_21 ((MDM32P)(MDM_BASE+0x2108)) //apb32 Information Message Register
532#define MDM_TM_ERRMSG_21 ((MDM32P)(MDM_BASE+0x210C)) //apb32 Error Message Register
533#define MDM_TM_TTAG_21 ((MDM32P)(MDM_BASE+0x2110)) //apb32 TTAG
534#define MDM_TM_ENDSIM_21 ((MDM32P)(MDM_BASE+0x2114)) //apb32 End Simulation Register
535#define MDM_TM_ERRCNT_21 ((MDM32P)(MDM_BASE+0x2118)) //apb32 Error Count Register
536#define MDM_TM_DBGINFO_21 ((MDM32P)(MDM_BASE+0x211c)) //apb32 Debug Infomation
537#define MDM_TM_TERRMSG_21 ((MDM32P)(MDM_BASE+0x2120)) //apb32 Error Message Register (T)
538#define MDM_TM_TBLANK_21 ((MDM32P)(MDM_BASE+0x2124)) //apb32 Blank line (T)
539#define MDM_TM_ENDFAIL_21 ((MDM32P)(MDM_BASE+0x2128)) //apb32 End Simulation With Fail Msg
540#define MDM_TM_ENDSUCC_21 ((MDM32P)(MDM_BASE+0x212C)) //apb32 End Simulation With Success Msg
541#define MDM_TM_ENDASSERT_21 ((MDM32P)(MDM_BASE+0x2130)) //apb32 End Simulation Register
542#define MDM_TM_ALLFMT32B_21 ((MDM32P)(MDM_BASE+0x2134)) //apb32 Display All Format 32b Value
543#define MDM_TM_HEXFMT32B_21 ((MDM32P)(MDM_BASE+0x2138)) //apb32 Display Hexa Format 32b Value
544#define MDM_TM_DECFMT32B_21 ((MDM32P)(MDM_BASE+0x213C)) //apb32 Display Dec Format 32b Value
545#define MDM_TM_BINFMT32B_21 ((MDM32P)(MDM_BASE+0x2140)) //apb32 Display Bin Format 32b Value
546#define MDM_TM_HEXFMT16B_21 ((MDM32P)(MDM_BASE+0x2144)) //apb32 Display Hexa Format 16b Value
547#define MDM_TM_DECFMT16B_21 ((MDM32P)(MDM_BASE+0x2148)) //apb32 Display Dec Format 16b Value
548#define MDM_TM_BINFMT16B_21 ((MDM32P)(MDM_BASE+0x214C)) //apb32 Display Bin Format 16b Value
549
550#define MDM_TM_MEMDUMPSTR_21 ((MDM32P)(MDM_BASE+0x2150)) //apb32 Start Address of Memory Dumping
551#define MDM_TM_MEMDUMPSTOP_21 ((MDM32P)(MDM_BASE+0x2154)) //apb32 Stop Address of Memory Dumping
552
553#define MDM_TM_MEMGOLDENSTR_21 ((MDM32P)(MDM_BASE+0x2158)) //apb32 Start Address of Memory Compare(Golden)
554#define MDM_TM_MEMGOLDENSTOP_21 ((MDM32P)(MDM_BASE+0x215C)) //apb32 Stop Address of Memory Compare(Golden)
555
556#define MDM_TM_MEMREVISESTR_21 ((MDM32P)(MDM_BASE+0x2160)) //apb32 Start Address of Memory Compare(Revised)
557#define MDM_TM_MEMREVISESTOP_21 ((MDM32P)(MDM_BASE+0x2164)) //apb32 Stop Address of Memory Compare(Revised)
558#define MDM_TM_EXT_MEM_INFO_21 ((MDM32P)(MDM_BASE+0x2168)) // apb32
559 // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
560 // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
561 // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
562 // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
563 // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
564 // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
565#define MDM_TM_RUNTIME_USEC_21 ((MDM32P)(MDM_BASE+0x216C)) // apb32
566#define MDM_TM_PHASE_21 ((MDM32P)(MDM_BASE+0x2170)) // apb32 rtl/post
567 // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
568 // [5:4]: {0:none, 1:max, 2:typ, 3:min}
569#define MDM_TM_SIM_OPTION_21 ((MDM32P)(MDM_BASE+0x2174)) // apb32
570 // [0]: PLL enable -> {0:OFF, 1:ON}
571//`define TM_CFSDB_CTRL_21 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
572//`define TM_DMESS_CTRL_21 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
573
574#define MDM_TM_FSDBDUMPFILE_21 ((MDM32P)(MDM_BASE+0x2180)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
575#define MDM_TM_FSDBDUMPVARS_21 ((MDM32P)(MDM_BASE+0x2184)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
576#define MDM_TM_FSDBDUMP_21 ((MDM32P)(MDM_BASE+0x2188)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
577#define MDM_TM_FSDBDUMPSCOPE_21 ((MDM32P)(MDM_BASE+0x218C)) // apb32
578
579#define MDM_TM_STR_CLEAR_21 ((MDM32P)(MDM_BASE+0x2190)) // apb32 clear string ptr
580#define MDM_TM_STR_DISPLAY_21 ((MDM32P)(MDM_BASE+0x2194)) // apb32 display string buf
581#define MDM_TM_STR0_21 ((MDM32P)(MDM_BASE+0x2198)) // apb32 string buffer to be displayed
582#define MDM_TM_STR1_21 ((MDM32P)(MDM_BASE+0x219C)) // apb32 string buffer to be displayed
583#define MDM_TM_STR2_21 ((MDM32P)(MDM_BASE+0x21A0)) // apb32 string buffer to be displayed
584#define MDM_TM_STR3_21 ((MDM32P)(MDM_BASE+0x21A4)) // apb32 string buffer to be displayed
585#define MDM_TM_STR4_21 ((MDM32P)(MDM_BASE+0x21A8)) // apb32 string buffer to be displayed
586#define MDM_TM_STR5_21 ((MDM32P)(MDM_BASE+0x21AC)) // apb32 string buffer to be displayed
587#define MDM_TM_STR6_21 ((MDM32P)(MDM_BASE+0x21B0)) // apb32 string buffer to be displayed
588#define MDM_TM_STR7_21 ((MDM32P)(MDM_BASE+0x21B4)) // apb32 string buffer to be displayed
589
590#define MDM_TRIG_IRQ_21 ((MDM32P)(MDM_BASE+0x21B8)) // apb32 trigger EIRQ
591#define MDM_TRIG_IRQ2_21 ((MDM32P)(MDM_BASE+0x21BC)) // apb32 trigger EIRQ
592#define MDM_WAIT_TRIG_21 ((MDM32P)(MDM_BASE+0x2178)) // apb32 trigger EIRQ
593#define MDM_WAIT_TRIG2_21 ((MDM32P)(MDM_BASE+0x217C)) // apb32 trigger EIRQ
594
595 // for MDM_cosim purpose, to replace bsi_reg usage
596#define MDM_CORE0VPE0_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21C0)) //core 0 to core0
597#define MDM_CORE0VPE1_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21C4)) //core 1 to core0
598#define MDM_CORE1VPE0_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21C8)) //core 2 to core0
599#define MDM_CORE1VPE1_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21CC)) //core 3 to core0
600#define MDM_CORE2VPE0_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21D0)) //core 4 to core0
601#define MDM_CORE2VPE1_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21D4)) //core 5 to core0
602#define MDM_CORE3VPE0_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21D8)) //core 6 to core0
603#define MDM_CORE3VPE1_TO_CORE2VPE1 ((MDM32P)(MDM_BASE+0x21DC)) //core 7 to core0
604
605#define MDM_MDM_SIMIF0_CTRL_21 ((MDM32P)(MDM_BASE+0x21E0)) //apb32
606#define MDM_MDM_SIMIF1_CTRL_21 ((MDM32P)(MDM_BASE+0x21E4)) //apb32
607
608#define MDM_TM_FH_CTRL_21 ((MDM32P)(MDM_BASE+0x21E8)) //apb32
609#define MDM_DELAY_21 ((MDM32P)(MDM_BASE+0x21Ec)) //apb32
610#define MDM_RANDOM_DELAY_MIN_21 ((MDM32P)(MDM_BASE+0x21F0)) //apb32
611#define MDM_RANDOM_DELAY_MAX_21 ((MDM32P)(MDM_BASE+0x21F4)) //apb32
612#define MDM_URANDOM_RANGE_MIN_21 ((MDM32P)(MDM_BASE+0x21F8)) //apb32
613#define MDM_URANDOM_RANGE_MAX_21 ((MDM32P)(MDM_BASE+0x21Fc)) //apb32
614
615#define MDM_TM_TINFOMSG_30 ((MDM32P)(MDM_BASE+0x3000)) //apb32 Information Message Register (T)
616#define MDM_TM_TPAR_30 ((MDM32P)(MDM_BASE+0x3004)) //apb32 message parameter
617#define MDM_TM_INFOMSG_30 ((MDM32P)(MDM_BASE+0x3008)) //apb32 Information Message Register
618#define MDM_TM_ERRMSG_30 ((MDM32P)(MDM_BASE+0x300C)) //apb32 Error Message Register
619#define MDM_TM_TTAG_30 ((MDM32P)(MDM_BASE+0x3010)) //apb32 TTAG
620#define MDM_TM_ENDSIM_30 ((MDM32P)(MDM_BASE+0x3014)) //apb32 End Simulation Register
621#define MDM_TM_ERRCNT_30 ((MDM32P)(MDM_BASE+0x3018)) //apb32 Error Count Register
622#define MDM_TM_DBGINFO_30 ((MDM32P)(MDM_BASE+0x301c)) //apb32 Debug Infomation
623#define MDM_TM_TERRMSG_30 ((MDM32P)(MDM_BASE+0x3020)) //apb32 Error Message Register (T)
624#define MDM_TM_TBLANK_30 ((MDM32P)(MDM_BASE+0x3024)) //apb32 Blank line (T)
625#define MDM_TM_ENDFAIL_30 ((MDM32P)(MDM_BASE+0x3028)) //apb32 End Simulation With Fail Msg
626#define MDM_TM_ENDSUCC_30 ((MDM32P)(MDM_BASE+0x302C)) //apb32 End Simulation With Success Msg
627#define MDM_TM_ENDASSERT_30 ((MDM32P)(MDM_BASE+0x3030)) //apb32 End Simulation Register
628#define MDM_TM_ALLFMT32B_30 ((MDM32P)(MDM_BASE+0x3034)) //apb32 Display All Format 32b Value
629#define MDM_TM_HEXFMT32B_30 ((MDM32P)(MDM_BASE+0x3038)) //apb32 Display Hexa Format 32b Value
630#define MDM_TM_DECFMT32B_30 ((MDM32P)(MDM_BASE+0x303C)) //apb32 Display Dec Format 32b Value
631#define MDM_TM_BINFMT32B_30 ((MDM32P)(MDM_BASE+0x3040)) //apb32 Display Bin Format 32b Value
632#define MDM_TM_HEXFMT16B_30 ((MDM32P)(MDM_BASE+0x3044)) //apb32 Display Hexa Format 16b Value
633#define MDM_TM_DECFMT16B_30 ((MDM32P)(MDM_BASE+0x3048)) //apb32 Display Dec Format 16b Value
634#define MDM_TM_BINFMT16B_30 ((MDM32P)(MDM_BASE+0x304C)) //apb32 Display Bin Format 16b Value
635
636#define MDM_TM_MEMDUMPSTR_30 ((MDM32P)(MDM_BASE+0x3050)) //apb32 Start Address of Memory Dumping
637#define MDM_TM_MEMDUMPSTOP_30 ((MDM32P)(MDM_BASE+0x3054)) //apb32 Stop Address of Memory Dumping
638
639#define MDM_TM_MEMGOLDENSTR_30 ((MDM32P)(MDM_BASE+0x3058)) //apb32 Start Address of Memory Compare(Golden)
640#define MDM_TM_MEMGOLDENSTOP_30 ((MDM32P)(MDM_BASE+0x305C)) //apb32 Stop Address of Memory Compare(Golden)
641
642#define MDM_TM_MEMREVISESTR_30 ((MDM32P)(MDM_BASE+0x3060)) //apb32 Start Address of Memory Compare(Revised)
643#define MDM_TM_MEMREVISESTOP_30 ((MDM32P)(MDM_BASE+0x3064)) //apb32 Stop Address of Memory Compare(Revised)
644#define MDM_TM_EXT_MEM_INFO_30 ((MDM32P)(MDM_BASE+0x3068)) // apb32
645 // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
646 // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
647 // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
648 // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
649 // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
650 // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
651#define MDM_TM_RUNTIME_USEC_30 ((MDM32P)(MDM_BASE+0x306C)) // apb32
652#define MDM_TM_PHASE_30 ((MDM32P)(MDM_BASE+0x3070)) // apb32 rtl/post
653 // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
654 // [5:4]: {0:none, 1:max, 2:typ, 3:min}
655#define MDM_TM_SIM_OPTION_30 ((MDM32P)(MDM_BASE+0x3074)) // apb32
656 // [0]: PLL enable -> {0:OFF, 1:ON}
657//`define TM_CFSDB_CTRL_30 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
658//`define TM_DMESS_CTRL_30 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
659
660#define MDM_TM_FSDBDUMPFILE_30 ((MDM32P)(MDM_BASE+0x3080)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
661#define MDM_TM_FSDBDUMPVARS_30 ((MDM32P)(MDM_BASE+0x3084)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
662#define MDM_TM_FSDBDUMP_30 ((MDM32P)(MDM_BASE+0x3088)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
663#define MDM_TM_FSDBDUMPSCOPE_30 ((MDM32P)(MDM_BASE+0x308C)) // apb32
664
665#define MDM_TM_STR_CLEAR_30 ((MDM32P)(MDM_BASE+0x3090)) // apb32 clear string ptr
666#define MDM_TM_STR_DISPLAY_30 ((MDM32P)(MDM_BASE+0x3094)) // apb32 display string buf
667#define MDM_TM_STR0_30 ((MDM32P)(MDM_BASE+0x3098)) // apb32 string buffer to be displayed
668#define MDM_TM_STR1_30 ((MDM32P)(MDM_BASE+0x309c)) // apb32 string buffer to be displayed
669#define MDM_TM_STR2_30 ((MDM32P)(MDM_BASE+0x30a0)) // apb32 string buffer to be displayed
670#define MDM_TM_STR3_30 ((MDM32P)(MDM_BASE+0x30a4)) // apb32 string buffer to be displayed
671#define MDM_TM_STR4_30 ((MDM32P)(MDM_BASE+0x30a8)) // apb32 string buffer to be displayed
672#define MDM_TM_STR5_30 ((MDM32P)(MDM_BASE+0x30ac)) // apb32 string buffer to be displayed
673#define MDM_TM_STR6_30 ((MDM32P)(MDM_BASE+0x30b0)) // apb32 string buffer to be displayed
674#define MDM_TM_STR7_30 ((MDM32P)(MDM_BASE+0x30b4)) // apb32 string buffer to be displayed
675
676#define MDM_TRIG_IRQ_30 ((MDM32P)(MDM_BASE+0x30b8)) // apb32 trigger EIRQ
677#define MDM_TRIG_IRQ2_30 ((MDM32P)(MDM_BASE+0x30bC)) // apb32 trigger EIRQ
678#define MDM_WAIT_TRIG_30 ((MDM32P)(MDM_BASE+0x3078)) // apb32 trigger EIRQ
679#define MDM_WAIT_TRIG2_30 ((MDM32P)(MDM_BASE+0x307C)) // apb32 trigger EIRQ
680
681 // for MDM_cosim purpose, to replace bsi_reg usage
682#define MDM_CORE0VPE0_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30C0)) //core 0 to core0
683#define MDM_CORE0VPE1_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30C4)) //core 1 to core0
684#define MDM_CORE1VPE0_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30C8)) //core 2 to core0
685#define MDM_CORE1VPE1_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30CC)) //core 3 to core0
686#define MDM_CORE2VPE0_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30D0)) //core 4 to core0
687#define MDM_CORE2VPE1_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30D4)) //core 5 to core0
688#define MDM_CORE3VPE0_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30D8)) //core 6 to core0
689#define MDM_CORE3VPE1_TO_CORE3VPE0 ((MDM32P)(MDM_BASE+0x30DC)) //core 7 to core0
690
691#define MDM_MDM_SIMIF0_CTRL_30 ((MDM32P)(MDM_BASE+0x30E0)) //apb32
692#define MDM_MDM_SIMIF1_CTRL_30 ((MDM32P)(MDM_BASE+0x30E4)) //apb32
693
694#define MDM_TM_FH_CTRL_30 ((MDM32P)(MDM_BASE+0x30E8)) //apb32
695#define MDM_DELAY_30 ((MDM32P)(MDM_BASE+0x30Ec)) //apb32
696#define MDM_RANDOM_DELAY_MIN_30 ((MDM32P)(MDM_BASE+0x30F0)) //apb32
697#define MDM_RANDOM_DELAY_MAX_30 ((MDM32P)(MDM_BASE+0x30F4)) //apb32
698#define MDM_URANDOM_RANGE_MIN_30 ((MDM32P)(MDM_BASE+0x30F8)) //apb32
699#define MDM_URANDOM_RANGE_MAX_30 ((MDM32P)(MDM_BASE+0x30Fc)) //apb32
700
701#define MDM_TM_TINFOMSG_31 ((MDM32P)(MDM_BASE+0x3100)) //apb32 Information Message Register (T)
702#define MDM_TM_TPAR_31 ((MDM32P)(MDM_BASE+0x3104)) //apb32 message parameter
703#define MDM_TM_INFOMSG_31 ((MDM32P)(MDM_BASE+0x3108)) //apb32 Information Message Register
704#define MDM_TM_ERRMSG_31 ((MDM32P)(MDM_BASE+0x310C)) //apb32 Error Message Register
705#define MDM_TM_TTAG_31 ((MDM32P)(MDM_BASE+0x3110)) //apb32 TTAG
706#define MDM_TM_ENDSIM_31 ((MDM32P)(MDM_BASE+0x3114)) //apb32 End Simulation Register
707#define MDM_TM_ERRCNT_31 ((MDM32P)(MDM_BASE+0x3118)) //apb32 Error Count Register
708#define MDM_TM_DBGINFO_31 ((MDM32P)(MDM_BASE+0x311c)) //apb32 Debug Infomation
709#define MDM_TM_TERRMSG_31 ((MDM32P)(MDM_BASE+0x3120)) //apb32 Error Message Register (T)
710#define MDM_TM_TBLANK_31 ((MDM32P)(MDM_BASE+0x3124)) //apb32 Blank line (T)
711#define MDM_TM_ENDFAIL_31 ((MDM32P)(MDM_BASE+0x3128)) //apb32 End Simulation With Fail Msg
712#define MDM_TM_ENDSUCC_31 ((MDM32P)(MDM_BASE+0x312C)) //apb32 End Simulation With Success Msg
713#define MDM_TM_ENDASSERT_31 ((MDM32P)(MDM_BASE+0x3130)) //apb32 End Simulation Register
714#define MDM_TM_ALLFMT32B_31 ((MDM32P)(MDM_BASE+0x3134)) //apb32 Display All Format 32b Value
715#define MDM_TM_HEXFMT32B_31 ((MDM32P)(MDM_BASE+0x3138)) //apb32 Display Hexa Format 32b Value
716#define MDM_TM_DECFMT32B_31 ((MDM32P)(MDM_BASE+0x313C)) //apb32 Display Dec Format 32b Value
717#define MDM_TM_BINFMT32B_31 ((MDM32P)(MDM_BASE+0x3140)) //apb32 Display Bin Format 32b Value
718#define MDM_TM_HEXFMT16B_31 ((MDM32P)(MDM_BASE+0x3144)) //apb32 Display Hexa Format 16b Value
719#define MDM_TM_DECFMT16B_31 ((MDM32P)(MDM_BASE+0x3148)) //apb32 Display Dec Format 16b Value
720#define MDM_TM_BINFMT16B_31 ((MDM32P)(MDM_BASE+0x314C)) //apb32 Display Bin Format 16b Value
721
722#define MDM_TM_MEMDUMPSTR_31 ((MDM32P)(MDM_BASE+0x3150)) //apb32 Start Address of Memory Dumping
723#define MDM_TM_MEMDUMPSTOP_31 ((MDM32P)(MDM_BASE+0x3154)) //apb32 Stop Address of Memory Dumping
724
725#define MDM_TM_MEMGOLDENSTR_31 ((MDM32P)(MDM_BASE+0x3158)) //apb32 Start Address of Memory Compare(Golden)
726#define MDM_TM_MEMGOLDENSTOP_31 ((MDM32P)(MDM_BASE+0x315C)) //apb32 Stop Address of Memory Compare(Golden)
727
728#define MDM_TM_MEMREVISESTR_31 ((MDM32P)(MDM_BASE+0x3160)) //apb32 Start Address of Memory Compare(Revised)
729#define MDM_TM_MEMREVISESTOP_31 ((MDM32P)(MDM_BASE+0x3164)) //apb32 Stop Address of Memory Compare(Revised)
730#define MDM_TM_EXT_MEM_INFO_31 ((MDM32P)(MDM_BASE+0x3168)) // apb32
731 // [7:0]: DRAM type -> {0:SDR16, 1:SDR32, 2:DDR16, 3:DDR32, 4:DDR2}
732 // [15:8]: SRAM type -> {0:ASRAM, 1:PSRAM}
733 // [19:16]: Bank0 type -> {0:NONE, 1:SRAM, 2:DRAM}
734 // [23:20]: Bank1 type -> {0:NONE, 1:SRAM, 2:DRAM}
735 // [27:24]: Bank2 type -> {0:NONE, 1:SRAM, 2:DRAM}
736 // [31:28]: Bank3 type -> {0:NONE, 1:SRAM, 2:DRAM}
737#define MDM_TM_RUNTIME_USEC_31 ((MDM32P)(MDM_BASE+0x316C)) // apb32
738#define MDM_TM_PHASE_31 ((MDM32P)(MDM_BASE+0x3170)) // apb32 rtl/post
739 // [1:0]: {0:none, 1:rtl, 2:pre, 3:post}
740 // [5:4]: {0:none, 1:max, 2:typ, 3:min}
741#define MDM_TM_SIM_OPTION_31 ((MDM32P)(MDM_BASE+0x3174)) // apb32
742 // [0]: PLL enable -> {0:OFF, 1:ON}
743//`define TM_CFSDB_CTRL_31 ((MDM32P)(MDM_BASE+0x0b0c)) // apb32 CFSDB ctrl switch (+cfsdb_ctrl_off)
744//`define TM_DMESS_CTRL_31 ((MDM32P)(MDM_BASE+0x0b10)) // apb32 dynamic message ctrl switch (+cmess_ctrl_off)
745
746#define MDM_TM_FSDBDUMPFILE_31 ((MDM32P)(MDM_BASE+0x3180)) // apb32 $fsdbAutoSwitchDumpfile {0:divide per 200MB, others:divide per custom size}
747#define MDM_TM_FSDBDUMPVARS_31 ((MDM32P)(MDM_BASE+0x3184)) // apb32 $fsdbDumpvars(custom, `PROJ_TMDL)
748#define MDM_TM_FSDBDUMP_31 ((MDM32P)(MDM_BASE+0x3188)) // apb32 {0:$fsdbDumpoff, 1:$fsdbDumpon}
749#define MDM_TM_FSDBDUMPSCOPE_31 ((MDM32P)(MDM_BASE+0x318C)) // apb32
750
751#define MDM_TM_STR_CLEAR_31 ((MDM32P)(MDM_BASE+0x3190)) // apb32 clear string ptr
752#define MDM_TM_STR_DISPLAY_31 ((MDM32P)(MDM_BASE+0x3194)) // apb32 display string buf
753#define MDM_TM_STR0_31 ((MDM32P)(MDM_BASE+0x3198)) // apb32 string buffer to be displayed
754#define MDM_TM_STR1_31 ((MDM32P)(MDM_BASE+0x319c)) // apb32 string buffer to be displayed
755#define MDM_TM_STR2_31 ((MDM32P)(MDM_BASE+0x31a0)) // apb32 string buffer to be displayed
756#define MDM_TM_STR3_31 ((MDM32P)(MDM_BASE+0x31a4)) // apb32 string buffer to be displayed
757#define MDM_TM_STR4_31 ((MDM32P)(MDM_BASE+0x31a8)) // apb32 string buffer to be displayed
758#define MDM_TM_STR5_31 ((MDM32P)(MDM_BASE+0x31ac)) // apb32 string buffer to be displayed
759#define MDM_TM_STR6_31 ((MDM32P)(MDM_BASE+0x31b0)) // apb32 string buffer to be displayed
760#define MDM_TM_STR7_31 ((MDM32P)(MDM_BASE+0x31b4)) // apb32 string buffer to be displayed
761
762#define MDM_TRIG_IRQ_31 ((MDM32P)(MDM_BASE+0x31b8)) // apb32 trigger EIRQ
763#define MDM_TRIG_IRQ2_31 ((MDM32P)(MDM_BASE+0x31bC)) // apb32 trigger EIRQ
764#define MDM_WAIT_TRIG_31 ((MDM32P)(MDM_BASE+0x3178)) // apb32 trigger EIRQ
765#define MDM_WAIT_TRIG2_31 ((MDM32P)(MDM_BASE+0x317C)) // apb32 trigger EIRQ
766
767 // for MDM_cosim purpose, to replace bsi_reg usage
768#define MDM_CORE0VPE0_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31C0)) //core 0 to core0
769#define MDM_CORE0VPE1_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31C4)) //core 1 to core0
770#define MDM_CORE1VPE0_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31C8)) //core 2 to core0
771#define MDM_CORE1VPE1_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31CC)) //core 3 to core0
772#define MDM_CORE2VPE0_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31D0)) //core 4 to core0
773#define MDM_CORE2VPE1_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31D4)) //core 5 to core0
774#define MDM_CORE3VPE0_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31D8)) //core 6 to core0
775#define MDM_CORE3VPE1_TO_CORE3VPE1 ((MDM32P)(MDM_BASE+0x31DC)) //core 7 to core0
776
777#define MDM_MDM_SIMIF0_CTRL_31 ((MDM32P)(MDM_BASE+0x31E0)) //apb32
778#define MDM_MDM_SIMIF1_CTRL_31 ((MDM32P)(MDM_BASE+0x31E4)) //apb32
779
780#define MDM_TM_FH_CTRL_31 ((MDM32P)(MDM_BASE+0x31E8)) //apb32
781#define MDM_DELAY_31 ((MDM32P)(MDM_BASE+0x31Ec)) //apb32
782#define MDM_RANDOM_DELAY_MIN_31 ((MDM32P)(MDM_BASE+0x31F0)) //apb32
783#define MDM_RANDOM_DELAY_MAX_31 ((MDM32P)(MDM_BASE+0x31F4)) //apb32
784#define MDM_URANDOM_RANGE_MIN_31 ((MDM32P)(MDM_BASE+0x31F8)) //apb32
785#define MDM_URANDOM_RANGE_MAX_31 ((MDM32P)(MDM_BASE+0x31Fc)) //apb32
786
787#endif
788
789#define MIPS_CORE0_TERR_BASE 0x00020001
790#define MIPS_CORE0_TINFO_BASE 0x00020017
791#define MIPS_CORE0_FSDBSCOPE_BASE 0x0002003b
792
793#ifndef __MTK_TARGET__
794static char *terr_msg[] = {
795"data check error read_back_data=%x,golden_data=%x", //0
796"REG_MDCFGCTL_DUMMY miscompare", //1
797"REG_MDGDMA_FDSAR1_DV_DUMMY miscompare", //2
798"REG_MDGPTM_DUMMY miscompare", //3
799"REG_MDPERIMISC_MD_AP_DUMMY miscompare", //4
800"REG_MDPERIMISC_MDINFRA_DUMMY miscompare", //5
801"REG_MDPERIMISC_MDMCU_DUMMY miscompare", //6
802"REG_MDPERIMISC_L1_AP_DUMMY miscompare", //7
803"REG_MDPERIMISC_DUMMY miscompare", //8
804"REG_MDCIRQ_DUMMY miscompare", //9
805"REG_MDOSTIMER_DUMMY0_REG miscompare", //10
806"REG_MDRGU_DUMMY miscompare", //11
807"REG_MDEINT_MD_DUMMY miscompare", //12
808"REG_MDTOP_GLBCON_MD_TOP_DUMMY miscompare", //13
809"REG_MDTOP_PLLMIXED_PLL_DUMMY miscompare", //14
810"REG_MDTOP_CLKSW_CLK_DUMMY miscompare", //15
811"REG_SOE_DUMMY_0 miscompare", //16
812"REG_MDINFRAMISC_DUMMY_REGISTER miscompare", //17
813"REG_L1_IDC_CTRL_IDC_CTRL_DUMMY_ADDR miscompare", //18
814"REG_MDMCU_BUS_CONFIG_MCU_BUS_CONFIG4 miscompare", //19
815"usip slave reg test miscompare", //20
816"rxbrp slave reg test miscompare" //21
817};
818
819static char *tinfo_msg[] = {
820"Hello world, this is IRQ_Proc... ", //0
821"Irq service begin... ", //1
822"Read IRQ_Proc id is %x...", //2
823"Irq service end... ", //3
824"Enter core0_vpe0... with cpu_num %x", //4
825"execute the md_common ...", //5
826"user testcase start ...", //6
827"user testcase end...", //7
828"Enter core0_vpe1... with cpu_num %x", //8
829"Enter core1_vpe0... with cpu_num %x", //9
830"Enter core1_vpe1... with cpu_num %x", //10
831"read&write emi test begin", //11
832"read&write emi test end", //12
833"REG_MDCFGCTL_DUMMY:", //13
834"write data: %x", //14
835"read data: %x", //15
836"REG_MDGDMA_FDSAR1_DV_DUMMY:", //16
837"REG_MDGPTM_DUMMY:", //17
838"REG_MDPERIMISC_MD_AP_DUMMY:", //18
839"REG_MDPERIMISC_MDINFRA_DUMMY:", //19
840"REG_MDPERIMISC_MDMCU_DUMMY:", //20
841"REG_MDPERIMISC_L1_AP_DUMMY:", //21
842"REG_MDPERIMISC_DUMMY:", //22
843"REG_MDCIRQ_DUMMY:", //23
844"REG_MDOSTIMER_DUMMY0_REG:", //24
845"REG_MDRGU_DUMMY:", //25
846"REG_MDEINT_MD_DUMMY:", //26
847"REG_MDTOP_GLBCON_MD_TOP_DUMMY:", //27
848"REG_MDTOP_PLLMIXED_PLL_DUMMY:", //28
849"REG_MDTOP_CLKSW_CLK_DUMMY:", //29
850"REG_SOE_DUMMY_0:", //30
851"REG_MDINFRAMISC_DUMMY_REGISTER:", //31
852"REG_L1_IDC_CTRL_IDC_CTRL_DUMMY_ADDR:", //32
853"REG_MDMCU_BUS_CONFIG_MCU_BUS_CONFIG4:", //33
854"usip slave test:", //34
855"rxbrp slave test:" //35
856};
857#endif
858
859
860#define FATAL_ERROR_MAGIC 0x4C544146 //ASCII code FATL
861#define ASSERT_ERROR_MAGIC 0x54525341 //ASCII code ASRT
862#define VPE_HEADER_MAGIC 0xFF000000 //VPE number
863#define EXCEPTION_ERROR_MAGIC 0x50435845 //ASCII code EXCP
864#define MDM_APP_INIT_MAGIC 0x30504100
865
866#if !defined(__COSIM_BYPASS_DRV__)
867
868#define MDM_INT32_WRITE(int32_log)
869#define MDM_TMMEMDUMP_STR_WRITE(int32_log)
870#define MDM_TMMEMDUMP_STOP_WRITE(int32_log)
871#define MDM_TM_END_FAIL_WRITE
872#define MDM_TM_END_SUCC_WRITE
873#define MDM_STR0_WRITE(char_write)
874#define MDM_TM_STR_CLEAR_WRITE(clear_buffer_num)
875#define MDM_TM_STR_DISPLAY_WRITE(display_buffer_num)
876
877#else
878
879// Check these macro defines are the same for MT6763 Cosim?
880#define MDM_TM_HEXFMT_32B MDM_TM_HEXFMT32B
881
882extern void MDM_ASSERT(kal_uint32 e1, kal_uint32 e2, kal_uint32 e3);
883extern void MDM_kal_fatal_error_handler(kal_uint32 code1, kal_uint32 code2);
884
885#define MDM_INT32_WRITE(int32_log) \
886do { \
887 (*MDM_TM_HEXFMT32B)=(kal_uint32)VPE_HEADER_MAGIC|kal_get_current_vpe_id(); \
888 (*MDM_TM_HEXFMT32B)=(kal_uint32)(int32_log); \
889} while(0)
890
891#define MDM_TMMEMDUMP_STR_WRITE(int32_log)
892#define MDM_TMMEMDUMP_STOP_WRITE(int32_log)
893#define MDM_TM_END_FAIL_WRITE (*MDM_TM_ENDFAIL=0);
894#define MDM_TM_END_SUCC_WRITE (*MDM_TM_ENDSUCC=0);
895#define MDM_STR0_WRITE(char_write) (*MDM_TM_STR0 = (unsigned int)(char_write))
896#define MDM_TM_STR_CLEAR_WRITE(clear_buffer_num) (*MDM_TM_STR_CLEAR = (unsigned int)(clear_buffer_num))
897#define MDM_TM_STR_DISPLAY_WRITE(display_buffer_num) (*MDM_TM_STR_DISPLAY = (unsigned int)(display_buffer_num))
898
899#endif
900
901#endif //_MDM_TRACE_H
902