| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame^] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2016 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | #ifndef _CPH_RX_MM_EVENT_GEN_H_ |
| 36 | #define _CPH_RX_MM_EVENT_GEN_H_ |
| 37 | |
| 38 | |
| 39 | typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| 40 | typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| 41 | typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| 42 | typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| 43 | typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| 44 | typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| 45 | typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| 46 | typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| 47 | typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| 48 | |
| 49 | |
| 50 | #define MM_RX_RF_EVENTGEN_REG_BASE (0x00000000) |
| 51 | |
| 52 | #define MM_RX_RF_EVENTGEN_end (MM_RX_RF_EVENTGEN_REG_BASE + 0x2014 + 32*4) |
| 53 | |
| 54 | |
| 55 | |
| 56 | #define MM_EVENTGEN_LTE_BSI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0000)) |
| 57 | #define MM_EVENTGEN_FDD_BSI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0004)) |
| 58 | #define MM_EVENTGEN_GSM_BSI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0008)) |
| 59 | #define MM_EVENTGEN_BSI_EVENT_STATUS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x000C)) |
| 60 | #define MM_EVENTGEN_BSI_EVENT_STOP ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0010)) |
| 61 | #define MM_EVENTGEN_BSI_EVENT(n) ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0014 + (n)*4)) //n is from 0 to 31 |
| 62 | #define MM_EVENTGEN_LTE_MIPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1000)) |
| 63 | #define MM_EVENTGEN_FDD_MIPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1004)) |
| 64 | #define MM_EVENTGEN_GSM_MIPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1008)) |
| 65 | #define MM_EVENTGEN_MIPI_EVENT_STATUS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x100C)) |
| 66 | #define MM_EVENTGEN_MIPI_EVENT_STOP ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1010)) |
| 67 | #define MM_EVENTGEN_MIPI_EVENT(n) ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1014 + (n)*4)) //n is from 0 to 31 |
| 68 | #define MM_EVENTGEN_LTE_BPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2000)) |
| 69 | #define MM_EVENTGEN_FDD_BPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2004)) |
| 70 | #define MM_EVENTGEN_GSM_BPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2008)) |
| 71 | #define MM_EVENTGEN_BPI_EVENT_STATUS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x200C)) |
| 72 | #define MM_EVENTGEN_BPI_EVENT_STOP ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2010)) |
| 73 | #define MM_EVENTGEN_BPI_EVENT(n) ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2014 + (n)*4)) //n is from 0 to 31 |
| 74 | |
| 75 | |
| 76 | #define MM_EVENTGEN_LTE_BSI_BIAS_LTE_BSI_BIAS_LSB (0) |
| 77 | #define MM_EVENTGEN_LTE_BSI_BIAS_LTE_BSI_BIAS_WIDTH (20) |
| 78 | #define MM_EVENTGEN_LTE_BSI_BIAS_LTE_BSI_BIAS_MASK (0x000FFFFF) |
| 79 | |
| 80 | #define MM_EVENTGEN_FDD_BSI_BIAS_FDD_BSI_BIAS_LSB (0) |
| 81 | #define MM_EVENTGEN_FDD_BSI_BIAS_FDD_BSI_BIAS_WIDTH (16) |
| 82 | #define MM_EVENTGEN_FDD_BSI_BIAS_FDD_BSI_BIAS_MASK (0x0000FFFF) |
| 83 | |
| 84 | #define MM_EVENTGEN_GSM_BSI_BIAS_GSM_BSI_BIAS_LSB (0) |
| 85 | #define MM_EVENTGEN_GSM_BSI_BIAS_GSM_BSI_BIAS_WIDTH (14) |
| 86 | #define MM_EVENTGEN_GSM_BSI_BIAS_GSM_BSI_BIAS_MASK (0x00003FFF) |
| 87 | |
| 88 | #define MM_EVENTGEN_BSI_EVENT_STATUS_BSI_EVENT_STATUS_LSB (0) |
| 89 | #define MM_EVENTGEN_BSI_EVENT_STATUS_BSI_EVENT_STATUS_WIDTH (32) |
| 90 | #define MM_EVENTGEN_BSI_EVENT_STATUS_BSI_EVENT_STATUS_MASK (0xFFFFFFFF) |
| 91 | |
| 92 | #define MM_EVENTGEN_BSI_EVENT_STOP_BSI_EVENT_STOP_LSB (0) |
| 93 | #define MM_EVENTGEN_BSI_EVENT_STOP_BSI_EVENT_STOP_WIDTH (32) |
| 94 | #define MM_EVENTGEN_BSI_EVENT_STOP_BSI_EVENT_STOP_MASK (0xFFFFFFFF) |
| 95 | |
| 96 | #define MM_EVENTGEN_BSI_EVENT_MODE_LSB (29) |
| 97 | #define MM_EVENTGEN_BSI_EVENT_MODE_WIDTH (3) |
| 98 | #define MM_EVENTGEN_BSI_EVENT_MODE_MASK (0xE0000000) |
| 99 | |
| 100 | #define MM_EVENTGEN_BSI_EVENT_BSI_EVENT_TIME_LSB (0) |
| 101 | #define MM_EVENTGEN_BSI_EVENT_BSI_EVENT_TIME_WIDTH (20) |
| 102 | #define MM_EVENTGEN_BSI_EVENT_BSI_EVENT_TIME_MASK (0x000FFFFF) |
| 103 | |
| 104 | #define MM_EVENTGEN_LTE_MIPI_BIAS_LTE_MIPI_BIAS_LSB (0) |
| 105 | #define MM_EVENTGEN_LTE_MIPI_BIAS_LTE_MIPI_BIAS_WIDTH (20) |
| 106 | #define MM_EVENTGEN_LTE_MIPI_BIAS_LTE_MIPI_BIAS_MASK (0x000FFFFF) |
| 107 | |
| 108 | #define MM_EVENTGEN_FDD_MIPI_BIAS_FDD_MIPI_BIAS_LSB (0) |
| 109 | #define MM_EVENTGEN_FDD_MIPI_BIAS_FDD_MIPI_BIAS_WIDTH (16) |
| 110 | #define MM_EVENTGEN_FDD_MIPI_BIAS_FDD_MIPI_BIAS_MASK (0x0000FFFF) |
| 111 | |
| 112 | #define MM_EVENTGEN_GSM_MIPI_BIAS_GSM_MIPI_BIAS_LSB (0) |
| 113 | #define MM_EVENTGEN_GSM_MIPI_BIAS_GSM_MIPI_BIAS_WIDTH (14) |
| 114 | #define MM_EVENTGEN_GSM_MIPI_BIAS_GSM_MIPI_BIAS_MASK (0x00003FFF) |
| 115 | |
| 116 | #define MM_EVENTGEN_MIPI_EVENT_STATUS_MIPI_EVENT_STATUS_LSB (0) |
| 117 | #define MM_EVENTGEN_MIPI_EVENT_STATUS_MIPI_EVENT_STATUS_WIDTH (32) |
| 118 | #define MM_EVENTGEN_MIPI_EVENT_STATUS_MIPI_EVENT_STATUS_MASK (0xFFFFFFFF) |
| 119 | |
| 120 | #define MM_EVENTGEN_MIPI_EVENT_STOP_MIPI_EVENT_STOP_LSB (0) |
| 121 | #define MM_EVENTGEN_MIPI_EVENT_STOP_MIPI_EVENT_STOP_WIDTH (32) |
| 122 | #define MM_EVENTGEN_MIPI_EVENT_STOP_MIPI_EVENT_STOP_MASK (0xFFFFFFFF) |
| 123 | |
| 124 | #define MM_EVENTGEN_MIPI_EVENT_MODE_LSB (29) |
| 125 | #define MM_EVENTGEN_MIPI_EVENT_MODE_WIDTH (3) |
| 126 | #define MM_EVENTGEN_MIPI_EVENT_MODE_MASK (0xE0000000) |
| 127 | |
| 128 | #define MM_EVENTGEN_MIPI_EVENT_MIPI_EVENT_TIME_LSB (0) |
| 129 | #define MM_EVENTGEN_MIPI_EVENT_MIPI_EVENT_TIME_WIDTH (20) |
| 130 | #define MM_EVENTGEN_MIPI_EVENT_MIPI_EVENT_TIME_MASK (0x000FFFFF) |
| 131 | |
| 132 | #define MM_EVENTGEN_LTE_BPI_BIAS_LTE_BPI_BIAS_LSB (0) |
| 133 | #define MM_EVENTGEN_LTE_BPI_BIAS_LTE_BPI_BIAS_WIDTH (20) |
| 134 | #define MM_EVENTGEN_LTE_BPI_BIAS_LTE_BPI_BIAS_MASK (0x000FFFFF) |
| 135 | |
| 136 | #define MM_EVENTGEN_FDD_BPI_BIAS_FDD_BPI_BIAS_LSB (0) |
| 137 | #define MM_EVENTGEN_FDD_BPI_BIAS_FDD_BPI_BIAS_WIDTH (16) |
| 138 | #define MM_EVENTGEN_FDD_BPI_BIAS_FDD_BPI_BIAS_MASK (0x0000FFFF) |
| 139 | |
| 140 | #define MM_EVENTGEN_GSM_BPI_BIAS_GSM_BPI_BIAS_LSB (0) |
| 141 | #define MM_EVENTGEN_GSM_BPI_BIAS_GSM_BPI_BIAS_WIDTH (14) |
| 142 | #define MM_EVENTGEN_GSM_BPI_BIAS_GSM_BPI_BIAS_MASK (0x00003FFF) |
| 143 | |
| 144 | #define MM_EVENTGEN_BPI_EVENT_STATUS_BPI_EVENT_STATUS_LSB (0) |
| 145 | #define MM_EVENTGEN_BPI_EVENT_STATUS_BPI_EVENT_STATUS_WIDTH (32) |
| 146 | #define MM_EVENTGEN_BPI_EVENT_STATUS_BPI_EVENT_STATUS_MASK (0xFFFFFFFF) |
| 147 | |
| 148 | #define MM_EVENTGEN_BPI_EVENT_STOP_BPI_EVENT_STOP_LSB (0) |
| 149 | #define MM_EVENTGEN_BPI_EVENT_STOP_BPI_EVENT_STOP_WIDTH (32) |
| 150 | #define MM_EVENTGEN_BPI_EVENT_STOP_BPI_EVENT_STOP_MASK (0xFFFFFFFF) |
| 151 | |
| 152 | #define MM_EVENTGEN_BPI_EVENT_MODE_LSB (29) |
| 153 | #define MM_EVENTGEN_BPI_EVENT_MODE_WIDTH (3) |
| 154 | #define MM_EVENTGEN_BPI_EVENT_MODE_MASK (0xE0000000) |
| 155 | |
| 156 | #define MM_EVENTGEN_BPI_EVENT_BPI_EVENT_TIME_LSB (0) |
| 157 | #define MM_EVENTGEN_BPI_EVENT_BPI_EVENT_TIME_WIDTH (20) |
| 158 | #define MM_EVENTGEN_BPI_EVENT_BPI_EVENT_TIME_MASK (0x000FFFFF) |
| 159 | |
| 160 | |
| 161 | #endif //#ifndef _CPH_RX_MM_EVENT_GEN_H_ |