| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame^] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2016 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | #ifndef _CPHSLPCTRL_H_ |
| 36 | #define _CPHSLPCTRL_H_ |
| 37 | |
| 38 | |
| 39 | typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| 40 | typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| 41 | typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| 42 | typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| 43 | typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| 44 | typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| 45 | typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| 46 | typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| 47 | typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| 48 | |
| 49 | #if (defined(__MD93__)||defined(__MD95__)) |
| 50 | #define ST_SM_REG_BASE (0xA60D0000)/*SM REG BASE 93&95*/ |
| 51 | #elif defined(__MD97__) || defined(__MD97P__) |
| 52 | #define ST_SM_REG_BASE (0xA80D0000)/*SM REG BASE 97*/ |
| 53 | #endif |
| 54 | |
| 55 | #define ST_SM_CON(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000000)) |
| 56 | #define ST_SM_PAUSE_TIME(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000004)) |
| 57 | #define ST_SM_STA(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000008)) |
| 58 | #define ST_SM_CFG(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000000C)) |
| 59 | #define ST_SM_START_TIME(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000010)) |
| 60 | #define ST_SM_SW_WAKE_CON(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000014)) |
| 61 | #define ST_SM_STEP_FRAC(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000018)) |
| 62 | #define ST_SM_SYSCNT_F32K_INT(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000001C)) |
| 63 | #define ST_SM_SYSCNT_F32K_FRAC(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000020)) |
| 64 | #define ST_SM_SUPFRM_F32K_L(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000024)) |
| 65 | #define ST_SM_SUPFRM_F32K_H(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000028)) |
| 66 | #define ST_SM_SLEEP_OFFSET(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000002C)) |
| 67 | #define ST_SM_TIME_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000030)) |
| 68 | #define ST_SM_SUPFRM_TIME_L_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000034)) |
| 69 | #define ST_SM_SUPFRM_TIME_H_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000038)) |
| 70 | #define ST_SM_TIME_SLTBD(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000003C)) |
| 71 | #define ST_SM_SUPFRM_TIME_L_SLTBD(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000040)) |
| 72 | #define ST_SM_SUPFRM_TIME_H_SLTBD(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000044)) |
| 73 | #define ST_SM_TIME_WAKEUP_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000048)) |
| 74 | #define ST_SM_SUPFRM_TIME_L_WAKEUP_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000004C)) |
| 75 | #define ST_SM_SUPFRM_TIME_H_WAKEUP_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000050)) |
| 76 | #define ST_SM_FINAL_PAUSE_DURATION(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000054)) |
| 77 | #define ST_SM_PRESLP_CNT(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000058)) |
| 78 | #define ST_SM_SLT_START_F32K(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000005C)) |
| 79 | #define ST_SM_WAKEUP_START_F32K(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000060)) |
| 80 | |
| 81 | |
| 82 | #define ST_SM_CON_CLR_CNT_LSB (15) |
| 83 | #define ST_SM_CON_CLR_CNT_WIDTH (1) |
| 84 | #define ST_SM_CON_CLR_CNT_MASK (0x00008000) |
| 85 | #define ST_SM_CON_CLR_CNT_BIT (0x00008000) |
| 86 | |
| 87 | #define ST_SM_CON_PAUSE_START_LSB (1) |
| 88 | #define ST_SM_CON_PAUSE_START_WIDTH (1) |
| 89 | #define ST_SM_CON_PAUSE_START_MASK (0x00000002) |
| 90 | #define ST_SM_CON_PAUSE_START_BIT (0x00000002) |
| 91 | |
| 92 | #define ST_SM_CON_PAUSE_MODE_LSB (0) |
| 93 | #define ST_SM_CON_PAUSE_MODE_WIDTH (1) |
| 94 | #define ST_SM_CON_PAUSE_MODE_MASK (0x00000001) |
| 95 | #define ST_SM_CON_PAUSE_MODE_BIT (0x00000001) |
| 96 | |
| 97 | #define ST_SM_PAUSE_TIME_PAUSE_TIME_LSB (0) |
| 98 | #define ST_SM_PAUSE_TIME_PAUSE_TIME_WIDTH (32) |
| 99 | #define ST_SM_PAUSE_TIME_PAUSE_TIME_MASK (0xFFFFFFFF) |
| 100 | |
| 101 | #define ST_SM_STA_SLP_EXIT_CPL_LSB (7) |
| 102 | #define ST_SM_STA_SLP_EXIT_CPL_WIDTH (1) |
| 103 | #define ST_SM_STA_SLP_EXIT_CPL_MASK (0x00000080) |
| 104 | #define ST_SM_STA_SLP_EXIT_CPL_BIT (0x00000080) |
| 105 | |
| 106 | #define ST_SM_STA_PAUSE_CPL_LSB (6) |
| 107 | #define ST_SM_STA_PAUSE_CPL_WIDTH (1) |
| 108 | #define ST_SM_STA_PAUSE_CPL_MASK (0x00000040) |
| 109 | #define ST_SM_STA_PAUSE_CPL_BIT (0x00000040) |
| 110 | |
| 111 | #define ST_SM_CFG_SW_WAKE_EN_LSB (8) |
| 112 | #define ST_SM_CFG_SW_WAKE_EN_WIDTH (1) |
| 113 | #define ST_SM_CFG_SW_WAKE_EN_MASK (0x00000100) |
| 114 | #define ST_SM_CFG_SW_WAKE_EN_BIT (0x00000100) |
| 115 | |
| 116 | #define ST_SM_CFG_IRQ_EN_LSB (1) |
| 117 | #define ST_SM_CFG_IRQ_EN_WIDTH (1) |
| 118 | #define ST_SM_CFG_IRQ_EN_MASK (0x00000002) |
| 119 | #define ST_SM_CFG_IRQ_EN_BIT (0x00000002) |
| 120 | |
| 121 | #define ST_SM_START_TIME_SYSTEM_TIME_CNT_LSB (2) |
| 122 | #define ST_SM_START_TIME_SYSTEM_TIME_CNT_WIDTH (18) |
| 123 | #define ST_SM_START_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC) |
| 124 | |
| 125 | #define ST_SM_SW_WAKE_CON_SW_EVENT_LSB (0) |
| 126 | #define ST_SM_SW_WAKE_CON_SW_EVENT_WIDTH (1) |
| 127 | #define ST_SM_SW_WAKE_CON_SW_EVENT_MASK (0x00000001) |
| 128 | #define ST_SM_SW_WAKE_CON_SW_EVENT_BIT (0x00000001) |
| 129 | |
| 130 | #define ST_SM_STEP_FRAC_STEP_INT_LSB (18) |
| 131 | #define ST_SM_STEP_FRAC_STEP_INT_WIDTH (9) |
| 132 | #define ST_SM_STEP_FRAC_STEP_INT_MASK (0x07FC0000) |
| 133 | |
| 134 | #define ST_SM_STEP_FRAC_STEP_FRAC_LSB (0) |
| 135 | #define ST_SM_STEP_FRAC_STEP_FRAC_WIDTH (18) |
| 136 | #define ST_SM_STEP_FRAC_STEP_FRAC_MASK (0x0003FFFF) |
| 137 | |
| 138 | #define ST_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_LSB (0) |
| 139 | #define ST_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_WIDTH (20) |
| 140 | #define ST_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_MASK (0x000FFFFF) |
| 141 | |
| 142 | #define ST_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_LSB (0) |
| 143 | #define ST_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_WIDTH (18) |
| 144 | #define ST_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_MASK (0x0003FFFF) |
| 145 | |
| 146 | #define ST_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_LSB (0) |
| 147 | #define ST_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_WIDTH (32) |
| 148 | #define ST_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_MASK (0xFFFFFFFF) |
| 149 | |
| 150 | #define ST_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_LSB (0) |
| 151 | #define ST_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_WIDTH (4) |
| 152 | #define ST_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_MASK (0x0000000F) |
| 153 | |
| 154 | #define ST_SM_SLEEP_OFFSET_CHIP_OFFSET_LSB (2) |
| 155 | #define ST_SM_SLEEP_OFFSET_CHIP_OFFSET_WIDTH (14) |
| 156 | #define ST_SM_SLEEP_OFFSET_CHIP_OFFSET_MASK (0x0000FFFC) |
| 157 | |
| 158 | #define ST_SM_TIME_START_SM_TIME_START_LSB (0) |
| 159 | #define ST_SM_TIME_START_SM_TIME_START_WIDTH (20) |
| 160 | #define ST_SM_TIME_START_SM_TIME_START_MASK (0x000FFFFF) |
| 161 | |
| 162 | #define ST_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_LSB (0) |
| 163 | #define ST_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_WIDTH (32) |
| 164 | #define ST_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_MASK (0xFFFFFFFF) |
| 165 | |
| 166 | #define ST_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_LSB (0) |
| 167 | #define ST_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_WIDTH (4) |
| 168 | #define ST_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_MASK (0x0000000F) |
| 169 | |
| 170 | #define ST_SM_TIME_SLTBD_SM_TIME_SLTBD_LSB (0) |
| 171 | #define ST_SM_TIME_SLTBD_SM_TIME_SLTBD_WIDTH (20) |
| 172 | #define ST_SM_TIME_SLTBD_SM_TIME_SLTBD_MASK (0x000FFFFF) |
| 173 | |
| 174 | #define ST_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0) |
| 175 | #define ST_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (32) |
| 176 | #define ST_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0xFFFFFFFF) |
| 177 | |
| 178 | #define ST_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0) |
| 179 | #define ST_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (4) |
| 180 | #define ST_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0x0000000F) |
| 181 | |
| 182 | #define ST_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_LSB (0) |
| 183 | #define ST_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_WIDTH (20) |
| 184 | #define ST_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_MASK (0x000FFFFF) |
| 185 | |
| 186 | #define ST_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0) |
| 187 | #define ST_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (32) |
| 188 | #define ST_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0xFFFFFFFF) |
| 189 | |
| 190 | #define ST_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0) |
| 191 | #define ST_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (4) |
| 192 | #define ST_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0x0000000F) |
| 193 | |
| 194 | #define ST_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_LSB (0) |
| 195 | #define ST_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_WIDTH (32) |
| 196 | #define ST_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_MASK (0xFFFFFFFF) |
| 197 | |
| 198 | #define ST_SM_PRESLP_CNT_SM_PRESLP_CNT_LSB (0) |
| 199 | #define ST_SM_PRESLP_CNT_SM_PRESLP_CNT_WIDTH (6) |
| 200 | #define ST_SM_PRESLP_CNT_SM_PRESLP_CNT_MASK (0x0000003F) |
| 201 | |
| 202 | #define ST_SM_SLT_START_F32K_SM_SLT_START_F32K_LSB (0) |
| 203 | #define ST_SM_SLT_START_F32K_SM_SLT_START_F32K_WIDTH (6) |
| 204 | #define ST_SM_SLT_START_F32K_SM_SLT_START_F32K_MASK (0x0000003F) |
| 205 | |
| 206 | #define ST_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_LSB (0) |
| 207 | #define ST_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_WIDTH (32) |
| 208 | #define ST_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_MASK (0xFFFFFFFF) |
| 209 | |
| 210 | |
| 211 | #endif /* _CPHSLPCTRL_H_ */ |