| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame^] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2016 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | #ifndef _CPHSYSTEMTIMER_H_ |
| 36 | #define _CPHSYSTEMTIMER_H_ |
| 37 | |
| 38 | typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| 39 | typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| 40 | typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| 41 | typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| 42 | typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| 43 | typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| 44 | typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| 45 | typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| 46 | typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| 47 | |
| 48 | #if (defined(__MD93__)||defined(__MD95__)) |
| 49 | #define ST_RX_TIMER_REG_BASE (0xA60C0000)/*RX TIMER REG BASE 93&95*/ |
| 50 | #elif defined(__MD97__) || defined(__MD97P__) |
| 51 | #define ST_RX_TIMER_REG_BASE (0xA80C0000)/*RX TIMER REG BASE 97*/ |
| 52 | #endif |
| 53 | |
| 54 | #define ST_ADV_RET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000000)) |
| 55 | #define ST_SYNC_TIME(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000004)) |
| 56 | #define ST_SYNC_SYSCNT_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000008)) |
| 57 | #define ST_SYNC_SUPFRM_CNT_L_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000000C)) |
| 58 | #define ST_SYNC_SUPFRM_CNT_H_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000010)) |
| 59 | #define ST_SYNC_TIME_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000014)) |
| 60 | #define ST_SUPFRM_CNT_L_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000018)) |
| 61 | #define ST_SUPFRM_CNT_H_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000001C)) |
| 62 | #define ST_SUPFRM_CNT_INI_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000020)) |
| 63 | #define ST_FRM_TYPE(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000024)) |
| 64 | #define ST_CPINT_OFFSET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000028)) |
| 65 | #define ST_CPINT_MASK(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000002C)) |
| 66 | #define ST_CPINT_CLR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000030)) |
| 67 | #define ST_CPINT_SRC(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000034)) |
| 68 | #define ST_CPINT_ISR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000038)) |
| 69 | #define ST_HALF_CPINT_OFFSET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000003C)) |
| 70 | #define ST_HALF_CPINT_MASK(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000040)) |
| 71 | #define ST_HALF_CPINT_CLR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000044)) |
| 72 | #define ST_HALF_CPINT_SRC(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000048)) |
| 73 | #define ST_HALF_CPINT_ISR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000004C)) |
| 74 | #define ST_CFG_CPINT_TIME(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000050)) |
| 75 | #define ST_CFG_CPINT_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000054)) |
| 76 | #define ST_CFG_CPINT_ISR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000058)) |
| 77 | #define ST_CFG_CPINT_CLR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000005C)) |
| 78 | #ifdef __MD93__ |
| 79 | #define ST_SUBFR_STATUS(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000060)) |
| 80 | #endif |
| 81 | #define ST_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000064)) |
| 82 | #define ST_SUPFRM_CNT_L(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000068)) |
| 83 | #define ST_SUPFRM_CNT_H(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000006C)) |
| 84 | #define ST_FRC_TIMING_SYNC_MODE(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000070)) |
| 85 | #define ST_FRC_TIMING_SYNC_CMP(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000074)) |
| 86 | #define ST_FRC_TIMING_SYNC_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000078)) |
| 87 | #define ST_FRC_TIMING_SYNC_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000007C)) |
| 88 | #define ST_FRC_TIMING_SYNC_SUPFRM_CNT_L(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000080)) |
| 89 | #define ST_FRC_TIMING_SYNC_SUPFRM_CNT_H(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000084)) |
| 90 | #define ST_MU_SFO(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000088)) |
| 91 | #define ST_MU_ACC_INI_L(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000008C)) |
| 92 | #define ST_MU_ACC_INI_H(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000090)) |
| 93 | #define ST_MU_ACC_SET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000094)) |
| 94 | #define ST_RAKE_CTL_TIME3(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000098)) |
| 95 | #define ST_GSR_CTL_TIME2(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000009C)) |
| 96 | #define ST_GSR_SYNC_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000A0)) |
| 97 | #define ST_GSR_SYNC_TAG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000A4)) |
| 98 | #ifdef __MD93__ |
| 99 | #define ST_1XDO_TIMING_SYNC_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000A8)) |
| 100 | #define ST_1XDO_TIMING_SYNC_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000AC)) |
| 101 | #else |
| 102 | #define ST_1XDO_TIMING_SYNC_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000C0)) |
| 103 | #define ST_1XDO_TIMING_SYNC_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000C4)) |
| 104 | #define ST_1XDO_TIMING_SYNC_SUPFRM_CNT_L(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000C8)) |
| 105 | #define ST_1XDO_TIMING_SYNC_SUPFRM_CNT_H(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000CC)) |
| 106 | #endif |
| 107 | #define ST_1XDOMRG_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000B0)) |
| 108 | #define ST_1XDOMRG_INI_TIME(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000B4)) |
| 109 | #define ST_1XDOMRG_OFFSET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000B8)) |
| 110 | #define ST_GPS_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000BC)) |
| 111 | #if defined(__MD97__) || defined(__MD97P__) |
| 112 | #define ST_1XDO_US_SYNC_IMM_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000200)) |
| 113 | #define ST_1XDO_US_SYNC_IMM_UCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000204)) |
| 114 | #define ST_1XDO_US_SYNC_IMM_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000208)) |
| 115 | #define ST_1XDO_US_SYNC_SCH_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000210)) |
| 116 | #define ST_1XDO_US_SYNC_SCH_TIME(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000020c)) |
| 117 | #define ST_1XDO_US_SYNC_SCH_UCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000214)) |
| 118 | #endif |
| 119 | |
| 120 | |
| 121 | #define ST_ADV_RET_MODE_LSB (0) |
| 122 | #define ST_ADV_RET_MODE_WIDTH (2) |
| 123 | #define ST_ADV_RET_MODE_MASK (0x00000003) |
| 124 | #define ST_ADV_RET_MODE_ADV (0x00000001) |
| 125 | #define ST_ADV_RET_MODE_RET (0x00000002) |
| 126 | |
| 127 | #define ST_ADV_RET_ADJ_TC8_LSB (2) |
| 128 | #define ST_ADV_RET_ADJ_TC8_WIDTH (9) |
| 129 | #define ST_ADV_RET_ADJ_TC8_MASK (0x000007FC) |
| 130 | |
| 131 | |
| 132 | #define ST_SYNC_TIME_SYSTEM_TIME_CNT_LSB (2) |
| 133 | #define ST_SYNC_TIME_SYSTEM_TIME_CNT_WIDTH (18) |
| 134 | #define ST_SYNC_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC) |
| 135 | |
| 136 | #define ST_SYSCNT_INI_SYSTEM_TIME_CNT_LSB (0) |
| 137 | #define ST_SYSCNT_INI_SYSTEM_TIME_CNT_WIDTH (20) |
| 138 | #define ST_SYSCNT_INI_SYSTEM_TIME_CNT_MASK (0x000FFFFF) |
| 139 | |
| 140 | #define ST_SYNC_SUPFRM_CNT_L_INI_SUPFRM_CNT_LSB (0) |
| 141 | #define ST_SYNC_SUPFRM_CNT_L_INI_SUPFRM_CNT_WIDTH (32) |
| 142 | #define ST_SYNC_SUPFRM_CNT_L_INI_SUPFRM_CNT_MASK (0xFFFFFFFF) |
| 143 | |
| 144 | #define ST_SYNC_SUPFRM_CNT_H_INI_SUPFRM_CNT_LSB (0) |
| 145 | #define ST_SYNC_SUPFRM_CNT_H_INI_SUPFRM_CNT_WIDTH (4) |
| 146 | #define ST_SYNC_SUPFRM_CNT_H_INI_SUPFRM_CNT_MASK (0x0000000F) |
| 147 | |
| 148 | #define ST_SYNC_TIME_EN_EN_LSB (0) |
| 149 | #define ST_SYNC_TIME_EN_EN_WIDTH (1) |
| 150 | #define ST_SYNC_TIME_EN_EN_MASK (0x00000001) |
| 151 | #define ST_SYNC_TIME_EN_EN_BIT (0x00000001) |
| 152 | |
| 153 | #define ST_SUPFRM_CNT_L_INI_SUPFRM_CNT_LSB (0) |
| 154 | #define ST_SUPFRM_CNT_L_INI_SUPFRM_CNT_WIDTH (32) |
| 155 | #define ST_SUPFRM_CNT_L_INI_SUPFRM_CNT_MASK (0xFFFFFFFF) |
| 156 | |
| 157 | #define ST_SUPFRM_CNT_H_INI_SUPFRM_CNT_LSB (0) |
| 158 | #define ST_SUPFRM_CNT_H_INI_SUPFRM_CNT_WIDTH (4) |
| 159 | #define ST_SUPFRM_CNT_H_INI_SUPFRM_CNT_MASK (0x0000000F) |
| 160 | |
| 161 | #define ST_SUPFRM_CNT_INI_TRIG_TRIG_LSB (0) |
| 162 | #define ST_SUPFRM_CNT_INI_TRIG_TRIG_WIDTH (1) |
| 163 | #define ST_SUPFRM_CNT_INI_TRIG_TRIG_MASK (0x00000001) |
| 164 | #define ST_SUPFRM_CNT_INI_TRIG_TRIG_BIT (0x00000001) |
| 165 | |
| 166 | #define ST_FRM_TYPE_FRM_TYPE_LSB (0) |
| 167 | #define ST_FRM_TYPE_FRM_TYPE_WIDTH (1) |
| 168 | #define ST_FRM_TYPE_FRM_TYPE_MASK (0x00000001) |
| 169 | #define ST_FRM_TYPE_FRM_TYPE_26MS (0x00000000) |
| 170 | #define ST_FRM_TYPE_FRM_TYPE_20MS (0x00000001) |
| 171 | |
| 172 | #define ST_CPINT_OFFSET_CHIP_OFFSET_LSB (2) |
| 173 | #define ST_CPINT_OFFSET_CHIP_OFFSET_WIDTH (18) |
| 174 | #define ST_CPINT_OFFSET_CHIP_OFFSET_MASK (0x000FFFFC) |
| 175 | |
| 176 | #define ST_CPINT_MASK_MSK15_LSB (15) |
| 177 | #define ST_CPINT_MASK_MSK15_WIDTH (1) |
| 178 | #define ST_CPINT_MASK_MSK15_MASK (0x00008000) |
| 179 | #define ST_CPINT_MASK_MSK15_BIT (0x00008000) |
| 180 | |
| 181 | #define ST_CPINT_MASK_MSK14_LSB (14) |
| 182 | #define ST_CPINT_MASK_MSK14_WIDTH (1) |
| 183 | #define ST_CPINT_MASK_MSK14_MASK (0x00004000) |
| 184 | #define ST_CPINT_MASK_MSK14_BIT (0x00004000) |
| 185 | |
| 186 | #define ST_CPINT_MASK_MSK13_LSB (13) |
| 187 | #define ST_CPINT_MASK_MSK13_WIDTH (1) |
| 188 | #define ST_CPINT_MASK_MSK13_MASK (0x00002000) |
| 189 | #define ST_CPINT_MASK_MSK13_BIT (0x00002000) |
| 190 | |
| 191 | #define ST_CPINT_MASK_MSK12_LSB (12) |
| 192 | #define ST_CPINT_MASK_MSK12_WIDTH (1) |
| 193 | #define ST_CPINT_MASK_MSK12_MASK (0x00001000) |
| 194 | #define ST_CPINT_MASK_MSK12_BIT (0x00001000) |
| 195 | |
| 196 | #define ST_CPINT_MASK_MSK11_LSB (11) |
| 197 | #define ST_CPINT_MASK_MSK11_WIDTH (1) |
| 198 | #define ST_CPINT_MASK_MSK11_MASK (0x00000800) |
| 199 | #define ST_CPINT_MASK_MSK11_BIT (0x00000800) |
| 200 | |
| 201 | #define ST_CPINT_MASK_MSK10_LSB (10) |
| 202 | #define ST_CPINT_MASK_MSK10_WIDTH (1) |
| 203 | #define ST_CPINT_MASK_MSK10_MASK (0x00000400) |
| 204 | #define ST_CPINT_MASK_MSK10_BIT (0x00000400) |
| 205 | |
| 206 | #define ST_CPINT_MASK_MSK9_LSB (9) |
| 207 | #define ST_CPINT_MASK_MSK9_WIDTH (1) |
| 208 | #define ST_CPINT_MASK_MSK9_MASK (0x00000200) |
| 209 | #define ST_CPINT_MASK_MSK9_BIT (0x00000200) |
| 210 | |
| 211 | #define ST_CPINT_MASK_MSK8_LSB (8) |
| 212 | #define ST_CPINT_MASK_MSK8_WIDTH (1) |
| 213 | #define ST_CPINT_MASK_MSK8_MASK (0x00000100) |
| 214 | #define ST_CPINT_MASK_MSK8_BIT (0x00000100) |
| 215 | |
| 216 | #define ST_CPINT_MASK_MSK7_LSB (7) |
| 217 | #define ST_CPINT_MASK_MSK7_WIDTH (1) |
| 218 | #define ST_CPINT_MASK_MSK7_MASK (0x00000080) |
| 219 | #define ST_CPINT_MASK_MSK7_BIT (0x00000080) |
| 220 | |
| 221 | #define ST_CPINT_MASK_MSK6_LSB (6) |
| 222 | #define ST_CPINT_MASK_MSK6_WIDTH (1) |
| 223 | #define ST_CPINT_MASK_MSK6_MASK (0x00000040) |
| 224 | #define ST_CPINT_MASK_MSK6_BIT (0x00000040) |
| 225 | |
| 226 | #define ST_CPINT_MASK_MSK5_LSB (5) |
| 227 | #define ST_CPINT_MASK_MSK5_WIDTH (1) |
| 228 | #define ST_CPINT_MASK_MSK5_MASK (0x00000020) |
| 229 | #define ST_CPINT_MASK_MSK5_BIT (0x00000020) |
| 230 | |
| 231 | #define ST_CPINT_MASK_MSK4_LSB (4) |
| 232 | #define ST_CPINT_MASK_MSK4_WIDTH (1) |
| 233 | #define ST_CPINT_MASK_MSK4_MASK (0x00000010) |
| 234 | #define ST_CPINT_MASK_MSK4_BIT (0x00000010) |
| 235 | |
| 236 | #define ST_CPINT_MASK_MSK3_LSB (3) |
| 237 | #define ST_CPINT_MASK_MSK3_WIDTH (1) |
| 238 | #define ST_CPINT_MASK_MSK3_MASK (0x00000008) |
| 239 | #define ST_CPINT_MASK_MSK3_BIT (0x00000008) |
| 240 | |
| 241 | #define ST_CPINT_MASK_MSK2_LSB (2) |
| 242 | #define ST_CPINT_MASK_MSK2_WIDTH (1) |
| 243 | #define ST_CPINT_MASK_MSK2_MASK (0x00000004) |
| 244 | #define ST_CPINT_MASK_MSK2_BIT (0x00000004) |
| 245 | |
| 246 | #define ST_CPINT_MASK_MSK1_LSB (1) |
| 247 | #define ST_CPINT_MASK_MSK1_WIDTH (1) |
| 248 | #define ST_CPINT_MASK_MSK1_MASK (0x00000002) |
| 249 | #define ST_CPINT_MASK_MSK1_BIT (0x00000002) |
| 250 | |
| 251 | #define ST_CPINT_MASK_MSK0_LSB (0) |
| 252 | #define ST_CPINT_MASK_MSK0_WIDTH (1) |
| 253 | #define ST_CPINT_MASK_MSK0_MASK (0x00000001) |
| 254 | #define ST_CPINT_MASK_MSK0_BIT (0x00000001) |
| 255 | |
| 256 | #define ST_CPINT_CLR_CLR15_LSB (15) |
| 257 | #define ST_CPINT_CLR_CLR15_WIDTH (1) |
| 258 | #define ST_CPINT_CLR_CLR15_MASK (0x00008000) |
| 259 | #define ST_CPINT_CLR_CLR15_BIT (0x00008000) |
| 260 | |
| 261 | #define ST_CPINT_CLR_CLR14_LSB (14) |
| 262 | #define ST_CPINT_CLR_CLR14_WIDTH (1) |
| 263 | #define ST_CPINT_CLR_CLR14_MASK (0x00004000) |
| 264 | #define ST_CPINT_CLR_CLR14_BIT (0x00004000) |
| 265 | |
| 266 | #define ST_CPINT_CLR_CLR13_LSB (13) |
| 267 | #define ST_CPINT_CLR_CLR13_WIDTH (1) |
| 268 | #define ST_CPINT_CLR_CLR13_MASK (0x00002000) |
| 269 | #define ST_CPINT_CLR_CLR13_BIT (0x00002000) |
| 270 | |
| 271 | #define ST_CPINT_CLR_CLR12_LSB (12) |
| 272 | #define ST_CPINT_CLR_CLR12_WIDTH (1) |
| 273 | #define ST_CPINT_CLR_CLR12_MASK (0x00001000) |
| 274 | #define ST_CPINT_CLR_CLR12_BIT (0x00001000) |
| 275 | |
| 276 | #define ST_CPINT_CLR_CLR11_LSB (11) |
| 277 | #define ST_CPINT_CLR_CLR11_WIDTH (1) |
| 278 | #define ST_CPINT_CLR_CLR11_MASK (0x00000800) |
| 279 | #define ST_CPINT_CLR_CLR11_BIT (0x00000800) |
| 280 | |
| 281 | #define ST_CPINT_CLR_CLR10_LSB (10) |
| 282 | #define ST_CPINT_CLR_CLR10_WIDTH (1) |
| 283 | #define ST_CPINT_CLR_CLR10_MASK (0x00000400) |
| 284 | #define ST_CPINT_CLR_CLR10_BIT (0x00000400) |
| 285 | |
| 286 | #define ST_CPINT_CLR_CLR9_LSB (9) |
| 287 | #define ST_CPINT_CLR_CLR9_WIDTH (1) |
| 288 | #define ST_CPINT_CLR_CLR9_MASK (0x00000200) |
| 289 | #define ST_CPINT_CLR_CLR9_BIT (0x00000200) |
| 290 | |
| 291 | #define ST_CPINT_CLR_CLR8_LSB (8) |
| 292 | #define ST_CPINT_CLR_CLR8_WIDTH (1) |
| 293 | #define ST_CPINT_CLR_CLR8_MASK (0x00000100) |
| 294 | #define ST_CPINT_CLR_CLR8_BIT (0x00000100) |
| 295 | |
| 296 | #define ST_CPINT_CLR_CLR7_LSB (7) |
| 297 | #define ST_CPINT_CLR_CLR7_WIDTH (1) |
| 298 | #define ST_CPINT_CLR_CLR7_MASK (0x00000080) |
| 299 | #define ST_CPINT_CLR_CLR7_BIT (0x00000080) |
| 300 | |
| 301 | #define ST_CPINT_CLR_CLR6_LSB (6) |
| 302 | #define ST_CPINT_CLR_CLR6_WIDTH (1) |
| 303 | #define ST_CPINT_CLR_CLR6_MASK (0x00000040) |
| 304 | #define ST_CPINT_CLR_CLR6_BIT (0x00000040) |
| 305 | |
| 306 | #define ST_CPINT_CLR_CLR5_LSB (5) |
| 307 | #define ST_CPINT_CLR_CLR5_WIDTH (1) |
| 308 | #define ST_CPINT_CLR_CLR5_MASK (0x00000020) |
| 309 | #define ST_CPINT_CLR_CLR5_BIT (0x00000020) |
| 310 | |
| 311 | #define ST_CPINT_CLR_CLR4_LSB (4) |
| 312 | #define ST_CPINT_CLR_CLR4_WIDTH (1) |
| 313 | #define ST_CPINT_CLR_CLR4_MASK (0x00000010) |
| 314 | #define ST_CPINT_CLR_CLR4_BIT (0x00000010) |
| 315 | |
| 316 | #define ST_CPINT_CLR_CLR3_LSB (3) |
| 317 | #define ST_CPINT_CLR_CLR3_WIDTH (1) |
| 318 | #define ST_CPINT_CLR_CLR3_MASK (0x00000008) |
| 319 | #define ST_CPINT_CLR_CLR3_BIT (0x00000008) |
| 320 | |
| 321 | #define ST_CPINT_CLR_CLR2_LSB (2) |
| 322 | #define ST_CPINT_CLR_CLR2_WIDTH (1) |
| 323 | #define ST_CPINT_CLR_CLR2_MASK (0x00000004) |
| 324 | #define ST_CPINT_CLR_CLR2_BIT (0x00000004) |
| 325 | |
| 326 | #define ST_CPINT_CLR_CLR1_LSB (1) |
| 327 | #define ST_CPINT_CLR_CLR1_WIDTH (1) |
| 328 | #define ST_CPINT_CLR_CLR1_MASK (0x00000002) |
| 329 | #define ST_CPINT_CLR_CLR1_BIT (0x00000002) |
| 330 | |
| 331 | #define ST_CPINT_CLR_CLR0_LSB (0) |
| 332 | #define ST_CPINT_CLR_CLR0_WIDTH (1) |
| 333 | #define ST_CPINT_CLR_CLR0_MASK (0x00000001) |
| 334 | #define ST_CPINT_CLR_CLR0_BIT (0x00000001) |
| 335 | |
| 336 | #define ST_CPINT_SRC_SRC15_LSB (15) |
| 337 | #define ST_CPINT_SRC_SRC15_WIDTH (1) |
| 338 | #define ST_CPINT_SRC_SRC15_MASK (0x00008000) |
| 339 | #define ST_CPINT_SRC_SRC15_BIT (0x00008000) |
| 340 | |
| 341 | #define ST_CPINT_SRC_SRC14_LSB (14) |
| 342 | #define ST_CPINT_SRC_SRC14_WIDTH (1) |
| 343 | #define ST_CPINT_SRC_SRC14_MASK (0x00004000) |
| 344 | #define ST_CPINT_SRC_SRC14_BIT (0x00004000) |
| 345 | |
| 346 | #define ST_CPINT_SRC_SRC13_LSB (13) |
| 347 | #define ST_CPINT_SRC_SRC13_WIDTH (1) |
| 348 | #define ST_CPINT_SRC_SRC13_MASK (0x00002000) |
| 349 | #define ST_CPINT_SRC_SRC13_BIT (0x00002000) |
| 350 | |
| 351 | #define ST_CPINT_SRC_SRC12_LSB (12) |
| 352 | #define ST_CPINT_SRC_SRC12_WIDTH (1) |
| 353 | #define ST_CPINT_SRC_SRC12_MASK (0x00001000) |
| 354 | #define ST_CPINT_SRC_SRC12_BIT (0x00001000) |
| 355 | |
| 356 | #define ST_CPINT_SRC_SRC11_LSB (11) |
| 357 | #define ST_CPINT_SRC_SRC11_WIDTH (1) |
| 358 | #define ST_CPINT_SRC_SRC11_MASK (0x00000800) |
| 359 | #define ST_CPINT_SRC_SRC11_BIT (0x00000800) |
| 360 | |
| 361 | #define ST_CPINT_SRC_SRC10_LSB (10) |
| 362 | #define ST_CPINT_SRC_SRC10_WIDTH (1) |
| 363 | #define ST_CPINT_SRC_SRC10_MASK (0x00000400) |
| 364 | #define ST_CPINT_SRC_SRC10_BIT (0x00000400) |
| 365 | |
| 366 | #define ST_CPINT_SRC_SRC9_LSB (9) |
| 367 | #define ST_CPINT_SRC_SRC9_WIDTH (1) |
| 368 | #define ST_CPINT_SRC_SRC9_MASK (0x00000200) |
| 369 | #define ST_CPINT_SRC_SRC9_BIT (0x00000200) |
| 370 | |
| 371 | #define ST_CPINT_SRC_SRC8_LSB (8) |
| 372 | #define ST_CPINT_SRC_SRC8_WIDTH (1) |
| 373 | #define ST_CPINT_SRC_SRC8_MASK (0x00000100) |
| 374 | #define ST_CPINT_SRC_SRC8_BIT (0x00000100) |
| 375 | |
| 376 | #define ST_CPINT_SRC_SRC7_LSB (7) |
| 377 | #define ST_CPINT_SRC_SRC7_WIDTH (1) |
| 378 | #define ST_CPINT_SRC_SRC7_MASK (0x00000080) |
| 379 | #define ST_CPINT_SRC_SRC7_BIT (0x00000080) |
| 380 | |
| 381 | #define ST_CPINT_SRC_SRC6_LSB (6) |
| 382 | #define ST_CPINT_SRC_SRC6_WIDTH (1) |
| 383 | #define ST_CPINT_SRC_SRC6_MASK (0x00000040) |
| 384 | #define ST_CPINT_SRC_SRC6_BIT (0x00000040) |
| 385 | |
| 386 | #define ST_CPINT_SRC_SRC5_LSB (5) |
| 387 | #define ST_CPINT_SRC_SRC5_WIDTH (1) |
| 388 | #define ST_CPINT_SRC_SRC5_MASK (0x00000020) |
| 389 | #define ST_CPINT_SRC_SRC5_BIT (0x00000020) |
| 390 | |
| 391 | #define ST_CPINT_SRC_SRC4_LSB (4) |
| 392 | #define ST_CPINT_SRC_SRC4_WIDTH (1) |
| 393 | #define ST_CPINT_SRC_SRC4_MASK (0x00000010) |
| 394 | #define ST_CPINT_SRC_SRC4_BIT (0x00000010) |
| 395 | |
| 396 | #define ST_CPINT_SRC_SRC3_LSB (3) |
| 397 | #define ST_CPINT_SRC_SRC3_WIDTH (1) |
| 398 | #define ST_CPINT_SRC_SRC3_MASK (0x00000008) |
| 399 | #define ST_CPINT_SRC_SRC3_BIT (0x00000008) |
| 400 | |
| 401 | #define ST_CPINT_SRC_SRC2_LSB (2) |
| 402 | #define ST_CPINT_SRC_SRC2_WIDTH (1) |
| 403 | #define ST_CPINT_SRC_SRC2_MASK (0x00000004) |
| 404 | #define ST_CPINT_SRC_SRC2_BIT (0x00000004) |
| 405 | |
| 406 | #define ST_CPINT_SRC_SRC1_LSB (1) |
| 407 | #define ST_CPINT_SRC_SRC1_WIDTH (1) |
| 408 | #define ST_CPINT_SRC_SRC1_MASK (0x00000002) |
| 409 | #define ST_CPINT_SRC_SRC1_BIT (0x00000002) |
| 410 | |
| 411 | #define ST_CPINT_SRC_SRC0_LSB (0) |
| 412 | #define ST_CPINT_SRC_SRC0_WIDTH (1) |
| 413 | #define ST_CPINT_SRC_SRC0_MASK (0x00000001) |
| 414 | #define ST_CPINT_SRC_SRC0_BIT (0x00000001) |
| 415 | |
| 416 | #define ST_CPINT_ISR_ISR15_LSB (15) |
| 417 | #define ST_CPINT_ISR_ISR15_WIDTH (1) |
| 418 | #define ST_CPINT_ISR_ISR15_MASK (0x00008000) |
| 419 | #define ST_CPINT_ISR_ISR15_BIT (0x00008000) |
| 420 | |
| 421 | #define ST_CPINT_ISR_ISR14_LSB (14) |
| 422 | #define ST_CPINT_ISR_ISR14_WIDTH (1) |
| 423 | #define ST_CPINT_ISR_ISR14_MASK (0x00004000) |
| 424 | #define ST_CPINT_ISR_ISR14_BIT (0x00004000) |
| 425 | |
| 426 | #define ST_CPINT_ISR_ISR13_LSB (13) |
| 427 | #define ST_CPINT_ISR_ISR13_WIDTH (1) |
| 428 | #define ST_CPINT_ISR_ISR13_MASK (0x00002000) |
| 429 | #define ST_CPINT_ISR_ISR13_BIT (0x00002000) |
| 430 | |
| 431 | #define ST_CPINT_ISR_ISR12_LSB (12) |
| 432 | #define ST_CPINT_ISR_ISR12_WIDTH (1) |
| 433 | #define ST_CPINT_ISR_ISR12_MASK (0x00001000) |
| 434 | #define ST_CPINT_ISR_ISR12_BIT (0x00001000) |
| 435 | |
| 436 | #define ST_CPINT_ISR_ISR11_LSB (11) |
| 437 | #define ST_CPINT_ISR_ISR11_WIDTH (1) |
| 438 | #define ST_CPINT_ISR_ISR11_MASK (0x00000800) |
| 439 | #define ST_CPINT_ISR_ISR11_BIT (0x00000800) |
| 440 | |
| 441 | #define ST_CPINT_ISR_ISR10_LSB (10) |
| 442 | #define ST_CPINT_ISR_ISR10_WIDTH (1) |
| 443 | #define ST_CPINT_ISR_ISR10_MASK (0x00000400) |
| 444 | #define ST_CPINT_ISR_ISR10_BIT (0x00000400) |
| 445 | |
| 446 | #define ST_CPINT_ISR_ISR9_LSB (9) |
| 447 | #define ST_CPINT_ISR_ISR9_WIDTH (1) |
| 448 | #define ST_CPINT_ISR_ISR9_MASK (0x00000200) |
| 449 | #define ST_CPINT_ISR_ISR9_BIT (0x00000200) |
| 450 | |
| 451 | #define ST_CPINT_ISR_ISR8_LSB (8) |
| 452 | #define ST_CPINT_ISR_ISR8_WIDTH (1) |
| 453 | #define ST_CPINT_ISR_ISR8_MASK (0x00000100) |
| 454 | #define ST_CPINT_ISR_ISR8_BIT (0x00000100) |
| 455 | |
| 456 | #define ST_CPINT_ISR_ISR7_LSB (7) |
| 457 | #define ST_CPINT_ISR_ISR7_WIDTH (1) |
| 458 | #define ST_CPINT_ISR_ISR7_MASK (0x00000080) |
| 459 | #define ST_CPINT_ISR_ISR7_BIT (0x00000080) |
| 460 | |
| 461 | #define ST_CPINT_ISR_ISR6_LSB (6) |
| 462 | #define ST_CPINT_ISR_ISR6_WIDTH (1) |
| 463 | #define ST_CPINT_ISR_ISR6_MASK (0x00000040) |
| 464 | #define ST_CPINT_ISR_ISR6_BIT (0x00000040) |
| 465 | |
| 466 | #define ST_CPINT_ISR_ISR5_LSB (5) |
| 467 | #define ST_CPINT_ISR_ISR5_WIDTH (1) |
| 468 | #define ST_CPINT_ISR_ISR5_MASK (0x00000020) |
| 469 | #define ST_CPINT_ISR_ISR5_BIT (0x00000020) |
| 470 | |
| 471 | #define ST_CPINT_ISR_ISR4_LSB (4) |
| 472 | #define ST_CPINT_ISR_ISR4_WIDTH (1) |
| 473 | #define ST_CPINT_ISR_ISR4_MASK (0x00000010) |
| 474 | #define ST_CPINT_ISR_ISR4_BIT (0x00000010) |
| 475 | |
| 476 | #define ST_CPINT_ISR_ISR3_LSB (3) |
| 477 | #define ST_CPINT_ISR_ISR3_WIDTH (1) |
| 478 | #define ST_CPINT_ISR_ISR3_MASK (0x00000008) |
| 479 | #define ST_CPINT_ISR_ISR3_BIT (0x00000008) |
| 480 | |
| 481 | #define ST_CPINT_ISR_ISR2_LSB (2) |
| 482 | #define ST_CPINT_ISR_ISR2_WIDTH (1) |
| 483 | #define ST_CPINT_ISR_ISR2_MASK (0x00000004) |
| 484 | #define ST_CPINT_ISR_ISR2_BIT (0x00000004) |
| 485 | |
| 486 | #define ST_CPINT_ISR_ISR1_LSB (1) |
| 487 | #define ST_CPINT_ISR_ISR1_WIDTH (1) |
| 488 | #define ST_CPINT_ISR_ISR1_MASK (0x00000002) |
| 489 | #define ST_CPINT_ISR_ISR1_BIT (0x00000002) |
| 490 | |
| 491 | #define ST_CPINT_ISR_ISR0_LSB (0) |
| 492 | #define ST_CPINT_ISR_ISR0_WIDTH (1) |
| 493 | #define ST_CPINT_ISR_ISR0_MASK (0x00000001) |
| 494 | #define ST_CPINT_ISR_ISR0_BIT (0x00000001) |
| 495 | |
| 496 | #define ST_HALF_CPINT_OFFSET_CHIP_OFFSET_LSB (2) |
| 497 | #define ST_HALF_CPINT_OFFSET_CHIP_OFFSET_WIDTH (11) |
| 498 | #define ST_HALF_CPINT_OFFSET_CHIP_OFFSET_MASK (0x00001FFC) |
| 499 | |
| 500 | #define ST_HALF_CPINT_MASK_MSK31_LSB (31) |
| 501 | #define ST_HALF_CPINT_MASK_MSK31_WIDTH (1) |
| 502 | #define ST_HALF_CPINT_MASK_MSK31_MASK (0x80000000) |
| 503 | #define ST_HALF_CPINT_MASK_MSK31_BIT (0x80000000) |
| 504 | |
| 505 | #define ST_HALF_CPINT_MASK_MSK30_LSB (30) |
| 506 | #define ST_HALF_CPINT_MASK_MSK30_WIDTH (1) |
| 507 | #define ST_HALF_CPINT_MASK_MSK30_MASK (0x40000000) |
| 508 | #define ST_HALF_CPINT_MASK_MSK30_BIT (0x40000000) |
| 509 | |
| 510 | #define ST_HALF_CPINT_MASK_MSK29_LSB (29) |
| 511 | #define ST_HALF_CPINT_MASK_MSK29_WIDTH (1) |
| 512 | #define ST_HALF_CPINT_MASK_MSK29_MASK (0x20000000) |
| 513 | #define ST_HALF_CPINT_MASK_MSK29_BIT (0x20000000) |
| 514 | |
| 515 | #define ST_HALF_CPINT_MASK_MSK28_LSB (28) |
| 516 | #define ST_HALF_CPINT_MASK_MSK28_WIDTH (1) |
| 517 | #define ST_HALF_CPINT_MASK_MSK28_MASK (0x10000000) |
| 518 | #define ST_HALF_CPINT_MASK_MSK28_BIT (0x10000000) |
| 519 | |
| 520 | #define ST_HALF_CPINT_MASK_MSK27_LSB (27) |
| 521 | #define ST_HALF_CPINT_MASK_MSK27_WIDTH (1) |
| 522 | #define ST_HALF_CPINT_MASK_MSK27_MASK (0x08000000) |
| 523 | #define ST_HALF_CPINT_MASK_MSK27_BIT (0x08000000) |
| 524 | |
| 525 | #define ST_HALF_CPINT_MASK_MSK26_LSB (26) |
| 526 | #define ST_HALF_CPINT_MASK_MSK26_WIDTH (1) |
| 527 | #define ST_HALF_CPINT_MASK_MSK26_MASK (0x04000000) |
| 528 | #define ST_HALF_CPINT_MASK_MSK26_BIT (0x04000000) |
| 529 | |
| 530 | #define ST_HALF_CPINT_MASK_MSK25_LSB (25) |
| 531 | #define ST_HALF_CPINT_MASK_MSK25_WIDTH (1) |
| 532 | #define ST_HALF_CPINT_MASK_MSK25_MASK (0x02000000) |
| 533 | #define ST_HALF_CPINT_MASK_MSK25_BIT (0x02000000) |
| 534 | |
| 535 | #define ST_HALF_CPINT_MASK_MSK24_LSB (24) |
| 536 | #define ST_HALF_CPINT_MASK_MSK24_WIDTH (1) |
| 537 | #define ST_HALF_CPINT_MASK_MSK24_MASK (0x01000000) |
| 538 | #define ST_HALF_CPINT_MASK_MSK24_BIT (0x01000000) |
| 539 | |
| 540 | #define ST_HALF_CPINT_MASK_MSK23_LSB (23) |
| 541 | #define ST_HALF_CPINT_MASK_MSK23_WIDTH (1) |
| 542 | #define ST_HALF_CPINT_MASK_MSK23_MASK (0x00800000) |
| 543 | #define ST_HALF_CPINT_MASK_MSK23_BIT (0x00800000) |
| 544 | |
| 545 | #define ST_HALF_CPINT_MASK_MSK22_LSB (22) |
| 546 | #define ST_HALF_CPINT_MASK_MSK22_WIDTH (1) |
| 547 | #define ST_HALF_CPINT_MASK_MSK22_MASK (0x00400000) |
| 548 | #define ST_HALF_CPINT_MASK_MSK22_BIT (0x00400000) |
| 549 | |
| 550 | #define ST_HALF_CPINT_MASK_MSK21_LSB (21) |
| 551 | #define ST_HALF_CPINT_MASK_MSK21_WIDTH (1) |
| 552 | #define ST_HALF_CPINT_MASK_MSK21_MASK (0x00200000) |
| 553 | #define ST_HALF_CPINT_MASK_MSK21_BIT (0x00200000) |
| 554 | |
| 555 | #define ST_HALF_CPINT_MASK_MSK20_LSB (20) |
| 556 | #define ST_HALF_CPINT_MASK_MSK20_WIDTH (1) |
| 557 | #define ST_HALF_CPINT_MASK_MSK20_MASK (0x00100000) |
| 558 | #define ST_HALF_CPINT_MASK_MSK20_BIT (0x00100000) |
| 559 | |
| 560 | #define ST_HALF_CPINT_MASK_MSK19_LSB (19) |
| 561 | #define ST_HALF_CPINT_MASK_MSK19_WIDTH (1) |
| 562 | #define ST_HALF_CPINT_MASK_MSK19_MASK (0x00080000) |
| 563 | #define ST_HALF_CPINT_MASK_MSK19_BIT (0x00080000) |
| 564 | |
| 565 | #define ST_HALF_CPINT_MASK_MSK18_LSB (18) |
| 566 | #define ST_HALF_CPINT_MASK_MSK18_WIDTH (1) |
| 567 | #define ST_HALF_CPINT_MASK_MSK18_MASK (0x00040000) |
| 568 | #define ST_HALF_CPINT_MASK_MSK18_BIT (0x00040000) |
| 569 | |
| 570 | #define ST_HALF_CPINT_MASK_MSK17_LSB (17) |
| 571 | #define ST_HALF_CPINT_MASK_MSK17_WIDTH (1) |
| 572 | #define ST_HALF_CPINT_MASK_MSK17_MASK (0x00020000) |
| 573 | #define ST_HALF_CPINT_MASK_MSK17_BIT (0x00020000) |
| 574 | |
| 575 | #define ST_HALF_CPINT_MASK_MSK16_LSB (16) |
| 576 | #define ST_HALF_CPINT_MASK_MSK16_WIDTH (1) |
| 577 | #define ST_HALF_CPINT_MASK_MSK16_MASK (0x00010000) |
| 578 | #define ST_HALF_CPINT_MASK_MSK16_BIT (0x00010000) |
| 579 | |
| 580 | #define ST_HALF_CPINT_MASK_MSK15_LSB (15) |
| 581 | #define ST_HALF_CPINT_MASK_MSK15_WIDTH (1) |
| 582 | #define ST_HALF_CPINT_MASK_MSK15_MASK (0x00008000) |
| 583 | #define ST_HALF_CPINT_MASK_MSK15_BIT (0x00008000) |
| 584 | |
| 585 | #define ST_HALF_CPINT_MASK_MSK14_LSB (14) |
| 586 | #define ST_HALF_CPINT_MASK_MSK14_WIDTH (1) |
| 587 | #define ST_HALF_CPINT_MASK_MSK14_MASK (0x00004000) |
| 588 | #define ST_HALF_CPINT_MASK_MSK14_BIT (0x00004000) |
| 589 | |
| 590 | #define ST_HALF_CPINT_MASK_MSK13_LSB (13) |
| 591 | #define ST_HALF_CPINT_MASK_MSK13_WIDTH (1) |
| 592 | #define ST_HALF_CPINT_MASK_MSK13_MASK (0x00002000) |
| 593 | #define ST_HALF_CPINT_MASK_MSK13_BIT (0x00002000) |
| 594 | |
| 595 | #define ST_HALF_CPINT_MASK_MSK12_LSB (12) |
| 596 | #define ST_HALF_CPINT_MASK_MSK12_WIDTH (1) |
| 597 | #define ST_HALF_CPINT_MASK_MSK12_MASK (0x00001000) |
| 598 | #define ST_HALF_CPINT_MASK_MSK12_BIT (0x00001000) |
| 599 | |
| 600 | #define ST_HALF_CPINT_MASK_MSK11_LSB (11) |
| 601 | #define ST_HALF_CPINT_MASK_MSK11_WIDTH (1) |
| 602 | #define ST_HALF_CPINT_MASK_MSK11_MASK (0x00000800) |
| 603 | #define ST_HALF_CPINT_MASK_MSK11_BIT (0x00000800) |
| 604 | |
| 605 | #define ST_HALF_CPINT_MASK_MSK10_LSB (10) |
| 606 | #define ST_HALF_CPINT_MASK_MSK10_WIDTH (1) |
| 607 | #define ST_HALF_CPINT_MASK_MSK10_MASK (0x00000400) |
| 608 | #define ST_HALF_CPINT_MASK_MSK10_BIT (0x00000400) |
| 609 | |
| 610 | #define ST_HALF_CPINT_MASK_MSK9_LSB (9) |
| 611 | #define ST_HALF_CPINT_MASK_MSK9_WIDTH (1) |
| 612 | #define ST_HALF_CPINT_MASK_MSK9_MASK (0x00000200) |
| 613 | #define ST_HALF_CPINT_MASK_MSK9_BIT (0x00000200) |
| 614 | |
| 615 | #define ST_HALF_CPINT_MASK_MSK8_LSB (8) |
| 616 | #define ST_HALF_CPINT_MASK_MSK8_WIDTH (1) |
| 617 | #define ST_HALF_CPINT_MASK_MSK8_MASK (0x00000100) |
| 618 | #define ST_HALF_CPINT_MASK_MSK8_BIT (0x00000100) |
| 619 | |
| 620 | #define ST_HALF_CPINT_MASK_MSK7_LSB (7) |
| 621 | #define ST_HALF_CPINT_MASK_MSK7_WIDTH (1) |
| 622 | #define ST_HALF_CPINT_MASK_MSK7_MASK (0x00000080) |
| 623 | #define ST_HALF_CPINT_MASK_MSK7_BIT (0x00000080) |
| 624 | |
| 625 | #define ST_HALF_CPINT_MASK_MSK6_LSB (6) |
| 626 | #define ST_HALF_CPINT_MASK_MSK6_WIDTH (1) |
| 627 | #define ST_HALF_CPINT_MASK_MSK6_MASK (0x00000040) |
| 628 | #define ST_HALF_CPINT_MASK_MSK6_BIT (0x00000040) |
| 629 | |
| 630 | #define ST_HALF_CPINT_MASK_MSK5_LSB (5) |
| 631 | #define ST_HALF_CPINT_MASK_MSK5_WIDTH (1) |
| 632 | #define ST_HALF_CPINT_MASK_MSK5_MASK (0x00000020) |
| 633 | #define ST_HALF_CPINT_MASK_MSK5_BIT (0x00000020) |
| 634 | |
| 635 | #define ST_HALF_CPINT_MASK_MSK4_LSB (4) |
| 636 | #define ST_HALF_CPINT_MASK_MSK4_WIDTH (1) |
| 637 | #define ST_HALF_CPINT_MASK_MSK4_MASK (0x00000010) |
| 638 | #define ST_HALF_CPINT_MASK_MSK4_BIT (0x00000010) |
| 639 | |
| 640 | #define ST_HALF_CPINT_MASK_MSK3_LSB (3) |
| 641 | #define ST_HALF_CPINT_MASK_MSK3_WIDTH (1) |
| 642 | #define ST_HALF_CPINT_MASK_MSK3_MASK (0x00000008) |
| 643 | #define ST_HALF_CPINT_MASK_MSK3_BIT (0x00000008) |
| 644 | |
| 645 | #define ST_HALF_CPINT_MASK_MSK2_LSB (2) |
| 646 | #define ST_HALF_CPINT_MASK_MSK2_WIDTH (1) |
| 647 | #define ST_HALF_CPINT_MASK_MSK2_MASK (0x00000004) |
| 648 | #define ST_HALF_CPINT_MASK_MSK2_BIT (0x00000004) |
| 649 | |
| 650 | #define ST_HALF_CPINT_MASK_MSK1_LSB (1) |
| 651 | #define ST_HALF_CPINT_MASK_MSK1_WIDTH (1) |
| 652 | #define ST_HALF_CPINT_MASK_MSK1_MASK (0x00000002) |
| 653 | #define ST_HALF_CPINT_MASK_MSK1_BIT (0x00000002) |
| 654 | |
| 655 | #define ST_HALF_CPINT_MASK_MSK0_LSB (0) |
| 656 | #define ST_HALF_CPINT_MASK_MSK0_WIDTH (1) |
| 657 | #define ST_HALF_CPINT_MASK_MSK0_MASK (0x00000001) |
| 658 | #define ST_HALF_CPINT_MASK_MSK0_BIT (0x00000001) |
| 659 | |
| 660 | #define ST_HALF_CPINT_CLR_CLR31_LSB (31) |
| 661 | #define ST_HALF_CPINT_CLR_CLR31_WIDTH (1) |
| 662 | #define ST_HALF_CPINT_CLR_CLR31_MASK (0x80000000) |
| 663 | #define ST_HALF_CPINT_CLR_CLR31_BIT (0x80000000) |
| 664 | |
| 665 | #define ST_HALF_CPINT_CLR_CLR30_LSB (30) |
| 666 | #define ST_HALF_CPINT_CLR_CLR30_WIDTH (1) |
| 667 | #define ST_HALF_CPINT_CLR_CLR30_MASK (0x40000000) |
| 668 | #define ST_HALF_CPINT_CLR_CLR30_BIT (0x40000000) |
| 669 | |
| 670 | #define ST_HALF_CPINT_CLR_CLR29_LSB (29) |
| 671 | #define ST_HALF_CPINT_CLR_CLR29_WIDTH (1) |
| 672 | #define ST_HALF_CPINT_CLR_CLR29_MASK (0x20000000) |
| 673 | #define ST_HALF_CPINT_CLR_CLR29_BIT (0x20000000) |
| 674 | |
| 675 | #define ST_HALF_CPINT_CLR_CLR28_LSB (28) |
| 676 | #define ST_HALF_CPINT_CLR_CLR28_WIDTH (1) |
| 677 | #define ST_HALF_CPINT_CLR_CLR28_MASK (0x10000000) |
| 678 | #define ST_HALF_CPINT_CLR_CLR28_BIT (0x10000000) |
| 679 | |
| 680 | #define ST_HALF_CPINT_CLR_CLR27_LSB (27) |
| 681 | #define ST_HALF_CPINT_CLR_CLR27_WIDTH (1) |
| 682 | #define ST_HALF_CPINT_CLR_CLR27_MASK (0x08000000) |
| 683 | #define ST_HALF_CPINT_CLR_CLR27_BIT (0x08000000) |
| 684 | |
| 685 | #define ST_HALF_CPINT_CLR_CLR26_LSB (26) |
| 686 | #define ST_HALF_CPINT_CLR_CLR26_WIDTH (1) |
| 687 | #define ST_HALF_CPINT_CLR_CLR26_MASK (0x04000000) |
| 688 | #define ST_HALF_CPINT_CLR_CLR26_BIT (0x04000000) |
| 689 | |
| 690 | #define ST_HALF_CPINT_CLR_CLR25_LSB (25) |
| 691 | #define ST_HALF_CPINT_CLR_CLR25_WIDTH (1) |
| 692 | #define ST_HALF_CPINT_CLR_CLR25_MASK (0x02000000) |
| 693 | #define ST_HALF_CPINT_CLR_CLR25_BIT (0x02000000) |
| 694 | |
| 695 | #define ST_HALF_CPINT_CLR_CLR24_LSB (24) |
| 696 | #define ST_HALF_CPINT_CLR_CLR24_WIDTH (1) |
| 697 | #define ST_HALF_CPINT_CLR_CLR24_MASK (0x01000000) |
| 698 | #define ST_HALF_CPINT_CLR_CLR24_BIT (0x01000000) |
| 699 | |
| 700 | #define ST_HALF_CPINT_CLR_CLR23_LSB (23) |
| 701 | #define ST_HALF_CPINT_CLR_CLR23_WIDTH (1) |
| 702 | #define ST_HALF_CPINT_CLR_CLR23_MASK (0x00800000) |
| 703 | #define ST_HALF_CPINT_CLR_CLR23_BIT (0x00800000) |
| 704 | |
| 705 | #define ST_HALF_CPINT_CLR_CLR22_LSB (22) |
| 706 | #define ST_HALF_CPINT_CLR_CLR22_WIDTH (1) |
| 707 | #define ST_HALF_CPINT_CLR_CLR22_MASK (0x00400000) |
| 708 | #define ST_HALF_CPINT_CLR_CLR22_BIT (0x00400000) |
| 709 | |
| 710 | #define ST_HALF_CPINT_CLR_CLR21_LSB (21) |
| 711 | #define ST_HALF_CPINT_CLR_CLR21_WIDTH (1) |
| 712 | #define ST_HALF_CPINT_CLR_CLR21_MASK (0x00200000) |
| 713 | #define ST_HALF_CPINT_CLR_CLR21_BIT (0x00200000) |
| 714 | |
| 715 | #define ST_HALF_CPINT_CLR_CLR20_LSB (20) |
| 716 | #define ST_HALF_CPINT_CLR_CLR20_WIDTH (1) |
| 717 | #define ST_HALF_CPINT_CLR_CLR20_MASK (0x00100000) |
| 718 | #define ST_HALF_CPINT_CLR_CLR20_BIT (0x00100000) |
| 719 | |
| 720 | #define ST_HALF_CPINT_CLR_CLR19_LSB (19) |
| 721 | #define ST_HALF_CPINT_CLR_CLR19_WIDTH (1) |
| 722 | #define ST_HALF_CPINT_CLR_CLR19_MASK (0x00080000) |
| 723 | #define ST_HALF_CPINT_CLR_CLR19_BIT (0x00080000) |
| 724 | |
| 725 | #define ST_HALF_CPINT_CLR_CLR18_LSB (18) |
| 726 | #define ST_HALF_CPINT_CLR_CLR18_WIDTH (1) |
| 727 | #define ST_HALF_CPINT_CLR_CLR18_MASK (0x00040000) |
| 728 | #define ST_HALF_CPINT_CLR_CLR18_BIT (0x00040000) |
| 729 | |
| 730 | #define ST_HALF_CPINT_CLR_CLR17_LSB (17) |
| 731 | #define ST_HALF_CPINT_CLR_CLR17_WIDTH (1) |
| 732 | #define ST_HALF_CPINT_CLR_CLR17_MASK (0x00020000) |
| 733 | #define ST_HALF_CPINT_CLR_CLR17_BIT (0x00020000) |
| 734 | |
| 735 | #define ST_HALF_CPINT_CLR_CLR16_LSB (16) |
| 736 | #define ST_HALF_CPINT_CLR_CLR16_WIDTH (1) |
| 737 | #define ST_HALF_CPINT_CLR_CLR16_MASK (0x00010000) |
| 738 | #define ST_HALF_CPINT_CLR_CLR16_BIT (0x00010000) |
| 739 | |
| 740 | #define ST_HALF_CPINT_CLR_CLR15_LSB (15) |
| 741 | #define ST_HALF_CPINT_CLR_CLR15_WIDTH (1) |
| 742 | #define ST_HALF_CPINT_CLR_CLR15_MASK (0x00008000) |
| 743 | #define ST_HALF_CPINT_CLR_CLR15_BIT (0x00008000) |
| 744 | |
| 745 | #define ST_HALF_CPINT_CLR_CLR14_LSB (14) |
| 746 | #define ST_HALF_CPINT_CLR_CLR14_WIDTH (1) |
| 747 | #define ST_HALF_CPINT_CLR_CLR14_MASK (0x00004000) |
| 748 | #define ST_HALF_CPINT_CLR_CLR14_BIT (0x00004000) |
| 749 | |
| 750 | #define ST_HALF_CPINT_CLR_CLR13_LSB (13) |
| 751 | #define ST_HALF_CPINT_CLR_CLR13_WIDTH (1) |
| 752 | #define ST_HALF_CPINT_CLR_CLR13_MASK (0x00002000) |
| 753 | #define ST_HALF_CPINT_CLR_CLR13_BIT (0x00002000) |
| 754 | |
| 755 | #define ST_HALF_CPINT_CLR_CLR12_LSB (12) |
| 756 | #define ST_HALF_CPINT_CLR_CLR12_WIDTH (1) |
| 757 | #define ST_HALF_CPINT_CLR_CLR12_MASK (0x00001000) |
| 758 | #define ST_HALF_CPINT_CLR_CLR12_BIT (0x00001000) |
| 759 | |
| 760 | #define ST_HALF_CPINT_CLR_CLR11_LSB (11) |
| 761 | #define ST_HALF_CPINT_CLR_CLR11_WIDTH (1) |
| 762 | #define ST_HALF_CPINT_CLR_CLR11_MASK (0x00000800) |
| 763 | #define ST_HALF_CPINT_CLR_CLR11_BIT (0x00000800) |
| 764 | |
| 765 | #define ST_HALF_CPINT_CLR_CLR10_LSB (10) |
| 766 | #define ST_HALF_CPINT_CLR_CLR10_WIDTH (1) |
| 767 | #define ST_HALF_CPINT_CLR_CLR10_MASK (0x00000400) |
| 768 | #define ST_HALF_CPINT_CLR_CLR10_BIT (0x00000400) |
| 769 | |
| 770 | #define ST_HALF_CPINT_CLR_CLR9_LSB (9) |
| 771 | #define ST_HALF_CPINT_CLR_CLR9_WIDTH (1) |
| 772 | #define ST_HALF_CPINT_CLR_CLR9_MASK (0x00000200) |
| 773 | #define ST_HALF_CPINT_CLR_CLR9_BIT (0x00000200) |
| 774 | |
| 775 | #define ST_HALF_CPINT_CLR_CLR8_LSB (8) |
| 776 | #define ST_HALF_CPINT_CLR_CLR8_WIDTH (1) |
| 777 | #define ST_HALF_CPINT_CLR_CLR8_MASK (0x00000100) |
| 778 | #define ST_HALF_CPINT_CLR_CLR8_BIT (0x00000100) |
| 779 | |
| 780 | #define ST_HALF_CPINT_CLR_CLR7_LSB (7) |
| 781 | #define ST_HALF_CPINT_CLR_CLR7_WIDTH (1) |
| 782 | #define ST_HALF_CPINT_CLR_CLR7_MASK (0x00000080) |
| 783 | #define ST_HALF_CPINT_CLR_CLR7_BIT (0x00000080) |
| 784 | |
| 785 | #define ST_HALF_CPINT_CLR_CLR6_LSB (6) |
| 786 | #define ST_HALF_CPINT_CLR_CLR6_WIDTH (1) |
| 787 | #define ST_HALF_CPINT_CLR_CLR6_MASK (0x00000040) |
| 788 | #define ST_HALF_CPINT_CLR_CLR6_BIT (0x00000040) |
| 789 | |
| 790 | #define ST_HALF_CPINT_CLR_CLR5_LSB (5) |
| 791 | #define ST_HALF_CPINT_CLR_CLR5_WIDTH (1) |
| 792 | #define ST_HALF_CPINT_CLR_CLR5_MASK (0x00000020) |
| 793 | #define ST_HALF_CPINT_CLR_CLR5_BIT (0x00000020) |
| 794 | |
| 795 | #define ST_HALF_CPINT_CLR_CLR4_LSB (4) |
| 796 | #define ST_HALF_CPINT_CLR_CLR4_WIDTH (1) |
| 797 | #define ST_HALF_CPINT_CLR_CLR4_MASK (0x00000010) |
| 798 | #define ST_HALF_CPINT_CLR_CLR4_BIT (0x00000010) |
| 799 | |
| 800 | #define ST_HALF_CPINT_CLR_CLR3_LSB (3) |
| 801 | #define ST_HALF_CPINT_CLR_CLR3_WIDTH (1) |
| 802 | #define ST_HALF_CPINT_CLR_CLR3_MASK (0x00000008) |
| 803 | #define ST_HALF_CPINT_CLR_CLR3_BIT (0x00000008) |
| 804 | |
| 805 | #define ST_HALF_CPINT_CLR_CLR2_LSB (2) |
| 806 | #define ST_HALF_CPINT_CLR_CLR2_WIDTH (1) |
| 807 | #define ST_HALF_CPINT_CLR_CLR2_MASK (0x00000004) |
| 808 | #define ST_HALF_CPINT_CLR_CLR2_BIT (0x00000004) |
| 809 | |
| 810 | #define ST_HALF_CPINT_CLR_CLR1_LSB (1) |
| 811 | #define ST_HALF_CPINT_CLR_CLR1_WIDTH (1) |
| 812 | #define ST_HALF_CPINT_CLR_CLR1_MASK (0x00000002) |
| 813 | #define ST_HALF_CPINT_CLR_CLR1_BIT (0x00000002) |
| 814 | |
| 815 | #define ST_HALF_CPINT_CLR_CLR0_LSB (0) |
| 816 | #define ST_HALF_CPINT_CLR_CLR0_WIDTH (1) |
| 817 | #define ST_HALF_CPINT_CLR_CLR0_MASK (0x00000001) |
| 818 | #define ST_HALF_CPINT_CLR_CLR0_BIT (0x00000001) |
| 819 | |
| 820 | #define ST_HALF_CPINT_SRC_SRC31_LSB (31) |
| 821 | #define ST_HALF_CPINT_SRC_SRC31_WIDTH (1) |
| 822 | #define ST_HALF_CPINT_SRC_SRC31_MASK (0x80000000) |
| 823 | #define ST_HALF_CPINT_SRC_SRC31_BIT (0x80000000) |
| 824 | |
| 825 | #define ST_HALF_CPINT_SRC_SRC30_LSB (30) |
| 826 | #define ST_HALF_CPINT_SRC_SRC30_WIDTH (1) |
| 827 | #define ST_HALF_CPINT_SRC_SRC30_MASK (0x40000000) |
| 828 | #define ST_HALF_CPINT_SRC_SRC30_BIT (0x40000000) |
| 829 | |
| 830 | #define ST_HALF_CPINT_SRC_SRC29_LSB (29) |
| 831 | #define ST_HALF_CPINT_SRC_SRC29_WIDTH (1) |
| 832 | #define ST_HALF_CPINT_SRC_SRC29_MASK (0x20000000) |
| 833 | #define ST_HALF_CPINT_SRC_SRC29_BIT (0x20000000) |
| 834 | |
| 835 | #define ST_HALF_CPINT_SRC_SRC28_LSB (28) |
| 836 | #define ST_HALF_CPINT_SRC_SRC28_WIDTH (1) |
| 837 | #define ST_HALF_CPINT_SRC_SRC28_MASK (0x10000000) |
| 838 | #define ST_HALF_CPINT_SRC_SRC28_BIT (0x10000000) |
| 839 | |
| 840 | #define ST_HALF_CPINT_SRC_SRC27_LSB (27) |
| 841 | #define ST_HALF_CPINT_SRC_SRC27_WIDTH (1) |
| 842 | #define ST_HALF_CPINT_SRC_SRC27_MASK (0x08000000) |
| 843 | #define ST_HALF_CPINT_SRC_SRC27_BIT (0x08000000) |
| 844 | |
| 845 | #define ST_HALF_CPINT_SRC_SRC26_LSB (26) |
| 846 | #define ST_HALF_CPINT_SRC_SRC26_WIDTH (1) |
| 847 | #define ST_HALF_CPINT_SRC_SRC26_MASK (0x04000000) |
| 848 | #define ST_HALF_CPINT_SRC_SRC26_BIT (0x04000000) |
| 849 | |
| 850 | #define ST_HALF_CPINT_SRC_SRC25_LSB (25) |
| 851 | #define ST_HALF_CPINT_SRC_SRC25_WIDTH (1) |
| 852 | #define ST_HALF_CPINT_SRC_SRC25_MASK (0x02000000) |
| 853 | #define ST_HALF_CPINT_SRC_SRC25_BIT (0x02000000) |
| 854 | |
| 855 | #define ST_HALF_CPINT_SRC_SRC24_LSB (24) |
| 856 | #define ST_HALF_CPINT_SRC_SRC24_WIDTH (1) |
| 857 | #define ST_HALF_CPINT_SRC_SRC24_MASK (0x01000000) |
| 858 | #define ST_HALF_CPINT_SRC_SRC24_BIT (0x01000000) |
| 859 | |
| 860 | #define ST_HALF_CPINT_SRC_SRC23_LSB (23) |
| 861 | #define ST_HALF_CPINT_SRC_SRC23_WIDTH (1) |
| 862 | #define ST_HALF_CPINT_SRC_SRC23_MASK (0x00800000) |
| 863 | #define ST_HALF_CPINT_SRC_SRC23_BIT (0x00800000) |
| 864 | |
| 865 | #define ST_HALF_CPINT_SRC_SRC22_LSB (22) |
| 866 | #define ST_HALF_CPINT_SRC_SRC22_WIDTH (1) |
| 867 | #define ST_HALF_CPINT_SRC_SRC22_MASK (0x00400000) |
| 868 | #define ST_HALF_CPINT_SRC_SRC22_BIT (0x00400000) |
| 869 | |
| 870 | #define ST_HALF_CPINT_SRC_SRC21_LSB (21) |
| 871 | #define ST_HALF_CPINT_SRC_SRC21_WIDTH (1) |
| 872 | #define ST_HALF_CPINT_SRC_SRC21_MASK (0x00200000) |
| 873 | #define ST_HALF_CPINT_SRC_SRC21_BIT (0x00200000) |
| 874 | |
| 875 | #define ST_HALF_CPINT_SRC_SRC20_LSB (20) |
| 876 | #define ST_HALF_CPINT_SRC_SRC20_WIDTH (1) |
| 877 | #define ST_HALF_CPINT_SRC_SRC20_MASK (0x00100000) |
| 878 | #define ST_HALF_CPINT_SRC_SRC20_BIT (0x00100000) |
| 879 | |
| 880 | #define ST_HALF_CPINT_SRC_SRC19_LSB (19) |
| 881 | #define ST_HALF_CPINT_SRC_SRC19_WIDTH (1) |
| 882 | #define ST_HALF_CPINT_SRC_SRC19_MASK (0x00080000) |
| 883 | #define ST_HALF_CPINT_SRC_SRC19_BIT (0x00080000) |
| 884 | |
| 885 | #define ST_HALF_CPINT_SRC_SRC18_LSB (18) |
| 886 | #define ST_HALF_CPINT_SRC_SRC18_WIDTH (1) |
| 887 | #define ST_HALF_CPINT_SRC_SRC18_MASK (0x00040000) |
| 888 | #define ST_HALF_CPINT_SRC_SRC18_BIT (0x00040000) |
| 889 | |
| 890 | #define ST_HALF_CPINT_SRC_SRC17_LSB (17) |
| 891 | #define ST_HALF_CPINT_SRC_SRC17_WIDTH (1) |
| 892 | #define ST_HALF_CPINT_SRC_SRC17_MASK (0x00020000) |
| 893 | #define ST_HALF_CPINT_SRC_SRC17_BIT (0x00020000) |
| 894 | |
| 895 | #define ST_HALF_CPINT_SRC_SRC16_LSB (16) |
| 896 | #define ST_HALF_CPINT_SRC_SRC16_WIDTH (1) |
| 897 | #define ST_HALF_CPINT_SRC_SRC16_MASK (0x00010000) |
| 898 | #define ST_HALF_CPINT_SRC_SRC16_BIT (0x00010000) |
| 899 | |
| 900 | #define ST_HALF_CPINT_SRC_SRC15_LSB (15) |
| 901 | #define ST_HALF_CPINT_SRC_SRC15_WIDTH (1) |
| 902 | #define ST_HALF_CPINT_SRC_SRC15_MASK (0x00008000) |
| 903 | #define ST_HALF_CPINT_SRC_SRC15_BIT (0x00008000) |
| 904 | |
| 905 | #define ST_HALF_CPINT_SRC_SRC14_LSB (14) |
| 906 | #define ST_HALF_CPINT_SRC_SRC14_WIDTH (1) |
| 907 | #define ST_HALF_CPINT_SRC_SRC14_MASK (0x00004000) |
| 908 | #define ST_HALF_CPINT_SRC_SRC14_BIT (0x00004000) |
| 909 | |
| 910 | #define ST_HALF_CPINT_SRC_SRC13_LSB (13) |
| 911 | #define ST_HALF_CPINT_SRC_SRC13_WIDTH (1) |
| 912 | #define ST_HALF_CPINT_SRC_SRC13_MASK (0x00002000) |
| 913 | #define ST_HALF_CPINT_SRC_SRC13_BIT (0x00002000) |
| 914 | |
| 915 | #define ST_HALF_CPINT_SRC_SRC12_LSB (12) |
| 916 | #define ST_HALF_CPINT_SRC_SRC12_WIDTH (1) |
| 917 | #define ST_HALF_CPINT_SRC_SRC12_MASK (0x00001000) |
| 918 | #define ST_HALF_CPINT_SRC_SRC12_BIT (0x00001000) |
| 919 | |
| 920 | #define ST_HALF_CPINT_SRC_SRC11_LSB (11) |
| 921 | #define ST_HALF_CPINT_SRC_SRC11_WIDTH (1) |
| 922 | #define ST_HALF_CPINT_SRC_SRC11_MASK (0x00000800) |
| 923 | #define ST_HALF_CPINT_SRC_SRC11_BIT (0x00000800) |
| 924 | |
| 925 | #define ST_HALF_CPINT_SRC_SRC10_LSB (10) |
| 926 | #define ST_HALF_CPINT_SRC_SRC10_WIDTH (1) |
| 927 | #define ST_HALF_CPINT_SRC_SRC10_MASK (0x00000400) |
| 928 | #define ST_HALF_CPINT_SRC_SRC10_BIT (0x00000400) |
| 929 | |
| 930 | #define ST_HALF_CPINT_SRC_SRC9_LSB (9) |
| 931 | #define ST_HALF_CPINT_SRC_SRC9_WIDTH (1) |
| 932 | #define ST_HALF_CPINT_SRC_SRC9_MASK (0x00000200) |
| 933 | #define ST_HALF_CPINT_SRC_SRC9_BIT (0x00000200) |
| 934 | |
| 935 | #define ST_HALF_CPINT_SRC_SRC8_LSB (8) |
| 936 | #define ST_HALF_CPINT_SRC_SRC8_WIDTH (1) |
| 937 | #define ST_HALF_CPINT_SRC_SRC8_MASK (0x00000100) |
| 938 | #define ST_HALF_CPINT_SRC_SRC8_BIT (0x00000100) |
| 939 | |
| 940 | #define ST_HALF_CPINT_SRC_SRC7_LSB (7) |
| 941 | #define ST_HALF_CPINT_SRC_SRC7_WIDTH (1) |
| 942 | #define ST_HALF_CPINT_SRC_SRC7_MASK (0x00000080) |
| 943 | #define ST_HALF_CPINT_SRC_SRC7_BIT (0x00000080) |
| 944 | |
| 945 | #define ST_HALF_CPINT_SRC_SRC6_LSB (6) |
| 946 | #define ST_HALF_CPINT_SRC_SRC6_WIDTH (1) |
| 947 | #define ST_HALF_CPINT_SRC_SRC6_MASK (0x00000040) |
| 948 | #define ST_HALF_CPINT_SRC_SRC6_BIT (0x00000040) |
| 949 | |
| 950 | #define ST_HALF_CPINT_SRC_SRC5_LSB (5) |
| 951 | #define ST_HALF_CPINT_SRC_SRC5_WIDTH (1) |
| 952 | #define ST_HALF_CPINT_SRC_SRC5_MASK (0x00000020) |
| 953 | #define ST_HALF_CPINT_SRC_SRC5_BIT (0x00000020) |
| 954 | |
| 955 | #define ST_HALF_CPINT_SRC_SRC4_LSB (4) |
| 956 | #define ST_HALF_CPINT_SRC_SRC4_WIDTH (1) |
| 957 | #define ST_HALF_CPINT_SRC_SRC4_MASK (0x00000010) |
| 958 | #define ST_HALF_CPINT_SRC_SRC4_BIT (0x00000010) |
| 959 | |
| 960 | #define ST_HALF_CPINT_SRC_SRC3_LSB (3) |
| 961 | #define ST_HALF_CPINT_SRC_SRC3_WIDTH (1) |
| 962 | #define ST_HALF_CPINT_SRC_SRC3_MASK (0x00000008) |
| 963 | #define ST_HALF_CPINT_SRC_SRC3_BIT (0x00000008) |
| 964 | |
| 965 | #define ST_HALF_CPINT_SRC_SRC2_LSB (2) |
| 966 | #define ST_HALF_CPINT_SRC_SRC2_WIDTH (1) |
| 967 | #define ST_HALF_CPINT_SRC_SRC2_MASK (0x00000004) |
| 968 | #define ST_HALF_CPINT_SRC_SRC2_BIT (0x00000004) |
| 969 | |
| 970 | #define ST_HALF_CPINT_SRC_SRC1_LSB (1) |
| 971 | #define ST_HALF_CPINT_SRC_SRC1_WIDTH (1) |
| 972 | #define ST_HALF_CPINT_SRC_SRC1_MASK (0x00000002) |
| 973 | #define ST_HALF_CPINT_SRC_SRC1_BIT (0x00000002) |
| 974 | |
| 975 | #define ST_HALF_CPINT_SRC_SRC0_LSB (0) |
| 976 | #define ST_HALF_CPINT_SRC_SRC0_WIDTH (1) |
| 977 | #define ST_HALF_CPINT_SRC_SRC0_MASK (0x00000001) |
| 978 | #define ST_HALF_CPINT_SRC_SRC0_BIT (0x00000001) |
| 979 | |
| 980 | #define ST_HALF_CPINT_ISR_ISR31_LSB (31) |
| 981 | #define ST_HALF_CPINT_ISR_ISR31_WIDTH (1) |
| 982 | #define ST_HALF_CPINT_ISR_ISR31_MASK (0x80000000) |
| 983 | #define ST_HALF_CPINT_ISR_ISR31_BIT (0x80000000) |
| 984 | |
| 985 | #define ST_HALF_CPINT_ISR_ISR30_LSB (30) |
| 986 | #define ST_HALF_CPINT_ISR_ISR30_WIDTH (1) |
| 987 | #define ST_HALF_CPINT_ISR_ISR30_MASK (0x40000000) |
| 988 | #define ST_HALF_CPINT_ISR_ISR30_BIT (0x40000000) |
| 989 | |
| 990 | #define ST_HALF_CPINT_ISR_ISR29_LSB (29) |
| 991 | #define ST_HALF_CPINT_ISR_ISR29_WIDTH (1) |
| 992 | #define ST_HALF_CPINT_ISR_ISR29_MASK (0x20000000) |
| 993 | #define ST_HALF_CPINT_ISR_ISR29_BIT (0x20000000) |
| 994 | |
| 995 | #define ST_HALF_CPINT_ISR_ISR28_LSB (28) |
| 996 | #define ST_HALF_CPINT_ISR_ISR28_WIDTH (1) |
| 997 | #define ST_HALF_CPINT_ISR_ISR28_MASK (0x10000000) |
| 998 | #define ST_HALF_CPINT_ISR_ISR28_BIT (0x10000000) |
| 999 | |
| 1000 | #define ST_HALF_CPINT_ISR_ISR27_LSB (27) |
| 1001 | #define ST_HALF_CPINT_ISR_ISR27_WIDTH (1) |
| 1002 | #define ST_HALF_CPINT_ISR_ISR27_MASK (0x08000000) |
| 1003 | #define ST_HALF_CPINT_ISR_ISR27_BIT (0x08000000) |
| 1004 | |
| 1005 | #define ST_HALF_CPINT_ISR_ISR26_LSB (26) |
| 1006 | #define ST_HALF_CPINT_ISR_ISR26_WIDTH (1) |
| 1007 | #define ST_HALF_CPINT_ISR_ISR26_MASK (0x04000000) |
| 1008 | #define ST_HALF_CPINT_ISR_ISR26_BIT (0x04000000) |
| 1009 | |
| 1010 | #define ST_HALF_CPINT_ISR_ISR25_LSB (25) |
| 1011 | #define ST_HALF_CPINT_ISR_ISR25_WIDTH (1) |
| 1012 | #define ST_HALF_CPINT_ISR_ISR25_MASK (0x02000000) |
| 1013 | #define ST_HALF_CPINT_ISR_ISR25_BIT (0x02000000) |
| 1014 | |
| 1015 | #define ST_HALF_CPINT_ISR_ISR24_LSB (24) |
| 1016 | #define ST_HALF_CPINT_ISR_ISR24_WIDTH (1) |
| 1017 | #define ST_HALF_CPINT_ISR_ISR24_MASK (0x01000000) |
| 1018 | #define ST_HALF_CPINT_ISR_ISR24_BIT (0x01000000) |
| 1019 | |
| 1020 | #define ST_HALF_CPINT_ISR_ISR23_LSB (23) |
| 1021 | #define ST_HALF_CPINT_ISR_ISR23_WIDTH (1) |
| 1022 | #define ST_HALF_CPINT_ISR_ISR23_MASK (0x00800000) |
| 1023 | #define ST_HALF_CPINT_ISR_ISR23_BIT (0x00800000) |
| 1024 | |
| 1025 | #define ST_HALF_CPINT_ISR_ISR22_LSB (22) |
| 1026 | #define ST_HALF_CPINT_ISR_ISR22_WIDTH (1) |
| 1027 | #define ST_HALF_CPINT_ISR_ISR22_MASK (0x00400000) |
| 1028 | #define ST_HALF_CPINT_ISR_ISR22_BIT (0x00400000) |
| 1029 | |
| 1030 | #define ST_HALF_CPINT_ISR_ISR21_LSB (21) |
| 1031 | #define ST_HALF_CPINT_ISR_ISR21_WIDTH (1) |
| 1032 | #define ST_HALF_CPINT_ISR_ISR21_MASK (0x00200000) |
| 1033 | #define ST_HALF_CPINT_ISR_ISR21_BIT (0x00200000) |
| 1034 | |
| 1035 | #define ST_HALF_CPINT_ISR_ISR20_LSB (20) |
| 1036 | #define ST_HALF_CPINT_ISR_ISR20_WIDTH (1) |
| 1037 | #define ST_HALF_CPINT_ISR_ISR20_MASK (0x00100000) |
| 1038 | #define ST_HALF_CPINT_ISR_ISR20_BIT (0x00100000) |
| 1039 | |
| 1040 | #define ST_HALF_CPINT_ISR_ISR19_LSB (19) |
| 1041 | #define ST_HALF_CPINT_ISR_ISR19_WIDTH (1) |
| 1042 | #define ST_HALF_CPINT_ISR_ISR19_MASK (0x00080000) |
| 1043 | #define ST_HALF_CPINT_ISR_ISR19_BIT (0x00080000) |
| 1044 | |
| 1045 | #define ST_HALF_CPINT_ISR_ISR18_LSB (18) |
| 1046 | #define ST_HALF_CPINT_ISR_ISR18_WIDTH (1) |
| 1047 | #define ST_HALF_CPINT_ISR_ISR18_MASK (0x00040000) |
| 1048 | #define ST_HALF_CPINT_ISR_ISR18_BIT (0x00040000) |
| 1049 | |
| 1050 | #define ST_HALF_CPINT_ISR_ISR17_LSB (17) |
| 1051 | #define ST_HALF_CPINT_ISR_ISR17_WIDTH (1) |
| 1052 | #define ST_HALF_CPINT_ISR_ISR17_MASK (0x00020000) |
| 1053 | #define ST_HALF_CPINT_ISR_ISR17_BIT (0x00020000) |
| 1054 | |
| 1055 | #define ST_HALF_CPINT_ISR_ISR16_LSB (16) |
| 1056 | #define ST_HALF_CPINT_ISR_ISR16_WIDTH (1) |
| 1057 | #define ST_HALF_CPINT_ISR_ISR16_MASK (0x00010000) |
| 1058 | #define ST_HALF_CPINT_ISR_ISR16_BIT (0x00010000) |
| 1059 | |
| 1060 | #define ST_HALF_CPINT_ISR_ISR15_LSB (15) |
| 1061 | #define ST_HALF_CPINT_ISR_ISR15_WIDTH (1) |
| 1062 | #define ST_HALF_CPINT_ISR_ISR15_MASK (0x00008000) |
| 1063 | #define ST_HALF_CPINT_ISR_ISR15_BIT (0x00008000) |
| 1064 | |
| 1065 | #define ST_HALF_CPINT_ISR_ISR14_LSB (14) |
| 1066 | #define ST_HALF_CPINT_ISR_ISR14_WIDTH (1) |
| 1067 | #define ST_HALF_CPINT_ISR_ISR14_MASK (0x00004000) |
| 1068 | #define ST_HALF_CPINT_ISR_ISR14_BIT (0x00004000) |
| 1069 | |
| 1070 | #define ST_HALF_CPINT_ISR_ISR13_LSB (13) |
| 1071 | #define ST_HALF_CPINT_ISR_ISR13_WIDTH (1) |
| 1072 | #define ST_HALF_CPINT_ISR_ISR13_MASK (0x00002000) |
| 1073 | #define ST_HALF_CPINT_ISR_ISR13_BIT (0x00002000) |
| 1074 | |
| 1075 | #define ST_HALF_CPINT_ISR_ISR12_LSB (12) |
| 1076 | #define ST_HALF_CPINT_ISR_ISR12_WIDTH (1) |
| 1077 | #define ST_HALF_CPINT_ISR_ISR12_MASK (0x00001000) |
| 1078 | #define ST_HALF_CPINT_ISR_ISR12_BIT (0x00001000) |
| 1079 | |
| 1080 | #define ST_HALF_CPINT_ISR_ISR11_LSB (11) |
| 1081 | #define ST_HALF_CPINT_ISR_ISR11_WIDTH (1) |
| 1082 | #define ST_HALF_CPINT_ISR_ISR11_MASK (0x00000800) |
| 1083 | #define ST_HALF_CPINT_ISR_ISR11_BIT (0x00000800) |
| 1084 | |
| 1085 | #define ST_HALF_CPINT_ISR_ISR10_LSB (10) |
| 1086 | #define ST_HALF_CPINT_ISR_ISR10_WIDTH (1) |
| 1087 | #define ST_HALF_CPINT_ISR_ISR10_MASK (0x00000400) |
| 1088 | #define ST_HALF_CPINT_ISR_ISR10_BIT (0x00000400) |
| 1089 | |
| 1090 | #define ST_HALF_CPINT_ISR_ISR9_LSB (9) |
| 1091 | #define ST_HALF_CPINT_ISR_ISR9_WIDTH (1) |
| 1092 | #define ST_HALF_CPINT_ISR_ISR9_MASK (0x00000200) |
| 1093 | #define ST_HALF_CPINT_ISR_ISR9_BIT (0x00000200) |
| 1094 | |
| 1095 | #define ST_HALF_CPINT_ISR_ISR8_LSB (8) |
| 1096 | #define ST_HALF_CPINT_ISR_ISR8_WIDTH (1) |
| 1097 | #define ST_HALF_CPINT_ISR_ISR8_MASK (0x00000100) |
| 1098 | #define ST_HALF_CPINT_ISR_ISR8_BIT (0x00000100) |
| 1099 | |
| 1100 | #define ST_HALF_CPINT_ISR_ISR7_LSB (7) |
| 1101 | #define ST_HALF_CPINT_ISR_ISR7_WIDTH (1) |
| 1102 | #define ST_HALF_CPINT_ISR_ISR7_MASK (0x00000080) |
| 1103 | #define ST_HALF_CPINT_ISR_ISR7_BIT (0x00000080) |
| 1104 | |
| 1105 | #define ST_HALF_CPINT_ISR_ISR6_LSB (6) |
| 1106 | #define ST_HALF_CPINT_ISR_ISR6_WIDTH (1) |
| 1107 | #define ST_HALF_CPINT_ISR_ISR6_MASK (0x00000040) |
| 1108 | #define ST_HALF_CPINT_ISR_ISR6_BIT (0x00000040) |
| 1109 | |
| 1110 | #define ST_HALF_CPINT_ISR_ISR5_LSB (5) |
| 1111 | #define ST_HALF_CPINT_ISR_ISR5_WIDTH (1) |
| 1112 | #define ST_HALF_CPINT_ISR_ISR5_MASK (0x00000020) |
| 1113 | #define ST_HALF_CPINT_ISR_ISR5_BIT (0x00000020) |
| 1114 | |
| 1115 | #define ST_HALF_CPINT_ISR_ISR4_LSB (4) |
| 1116 | #define ST_HALF_CPINT_ISR_ISR4_WIDTH (1) |
| 1117 | #define ST_HALF_CPINT_ISR_ISR4_MASK (0x00000010) |
| 1118 | #define ST_HALF_CPINT_ISR_ISR4_BIT (0x00000010) |
| 1119 | |
| 1120 | #define ST_HALF_CPINT_ISR_ISR3_LSB (3) |
| 1121 | #define ST_HALF_CPINT_ISR_ISR3_WIDTH (1) |
| 1122 | #define ST_HALF_CPINT_ISR_ISR3_MASK (0x00000008) |
| 1123 | #define ST_HALF_CPINT_ISR_ISR3_BIT (0x00000008) |
| 1124 | |
| 1125 | #define ST_HALF_CPINT_ISR_ISR2_LSB (2) |
| 1126 | #define ST_HALF_CPINT_ISR_ISR2_WIDTH (1) |
| 1127 | #define ST_HALF_CPINT_ISR_ISR2_MASK (0x00000004) |
| 1128 | #define ST_HALF_CPINT_ISR_ISR2_BIT (0x00000004) |
| 1129 | |
| 1130 | #define ST_HALF_CPINT_ISR_ISR1_LSB (1) |
| 1131 | #define ST_HALF_CPINT_ISR_ISR1_WIDTH (1) |
| 1132 | #define ST_HALF_CPINT_ISR_ISR1_MASK (0x00000002) |
| 1133 | #define ST_HALF_CPINT_ISR_ISR1_BIT (0x00000002) |
| 1134 | |
| 1135 | #define ST_HALF_CPINT_ISR_ISR0_LSB (0) |
| 1136 | #define ST_HALF_CPINT_ISR_ISR0_WIDTH (1) |
| 1137 | #define ST_HALF_CPINT_ISR_ISR0_MASK (0x00000001) |
| 1138 | #define ST_HALF_CPINT_ISR_ISR0_BIT (0x00000001) |
| 1139 | |
| 1140 | #define ST_CFG_CPINT_TIME_SYSTEM_TIME_CNT_LSB (2) |
| 1141 | #define ST_CFG_CPINT_TIME_SYSTEM_TIME_CNT_WIDTH (18) |
| 1142 | #define ST_CFG_CPINT_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC) |
| 1143 | |
| 1144 | #define ST_CFG_CPINT_EN_EN_LSB (0) |
| 1145 | #define ST_CFG_CPINT_EN_EN_WIDTH (1) |
| 1146 | #define ST_CFG_CPINT_EN_EN_MASK (0x00000001) |
| 1147 | #define ST_CFG_CPINT_EN_EN_BIT (0x00000001) |
| 1148 | |
| 1149 | #define ST_CFG_CPINT_ISR_ISR_LSB (0) |
| 1150 | #define ST_CFG_CPINT_ISR_ISR_WIDTH (1) |
| 1151 | #define ST_CFG_CPINT_ISR_ISR_MASK (0x00000001) |
| 1152 | #define ST_CFG_CPINT_ISR_ISR_BIT (0x00000001) |
| 1153 | |
| 1154 | #define ST_CFG_CPINT_CLR_CLR_LSB (0) |
| 1155 | #define ST_CFG_CPINT_CLR_CLR_WIDTH (1) |
| 1156 | #define ST_CFG_CPINT_CLR_CLR_MASK (0x00000001) |
| 1157 | #define ST_CFG_CPINT_CLR_CLR_BIT (0x00000001) |
| 1158 | |
| 1159 | #define ST_SUBFR_STATUS_SUBFR_STATUS_LSB (0) |
| 1160 | #define ST_SUBFR_STATUS_SUBFR_STATUS_WIDTH (6) |
| 1161 | #define ST_SUBFR_STATUS_SUBFR_STATUS_MASK (0x0000003F) |
| 1162 | |
| 1163 | #define ST_SYSCNT_SYSTEM_TIME_CNT_LSB (0) |
| 1164 | #define ST_SYSCNT_SYSTEM_TIME_CNT_WIDTH (20) |
| 1165 | #define ST_SYSCNT_SYSTEM_TIME_CNT_MASK (0x000FFFFF) |
| 1166 | #define ST_SYSCNT_SYSTEM_TIME_CNT_MAX (0x000BFFFF) |
| 1167 | #define ST_SYSCNT_SYSTEM_TIME_CNT_ROUND (0x000C0000) |
| 1168 | |
| 1169 | #define ST_SUPFRM_CNT_L_SUPFRM_CNT_LSB (0) |
| 1170 | #define ST_SUPFRM_CNT_L_SUPFRM_CNT_WIDTH (32) |
| 1171 | #define ST_SUPFRM_CNT_L_SUPFRM_CNT_MASK (0xFFFFFFFF) |
| 1172 | |
| 1173 | #define ST_SUPFRM_CNT_H_SUPFRM_CNT_LSB (0) |
| 1174 | #define ST_SUPFRM_CNT_H_SUPFRM_CNT_WIDTH (4) |
| 1175 | #define ST_SUPFRM_CNT_H_SUPFRM_CNT_MASK (0x0000000F) |
| 1176 | |
| 1177 | #define ST_FRC_TIMING_SYNC_MODE_MODE_LSB (0) |
| 1178 | #define ST_FRC_TIMING_SYNC_MODE_MODE_WIDTH (1) |
| 1179 | #define ST_FRC_TIMING_SYNC_MODE_MODE_MASK (0x00000001) |
| 1180 | #define ST_FRC_TIMING_SYNC_MODE_MODE_BIT (0x00000001) |
| 1181 | |
| 1182 | #define ST_FRC_TIMING_SYNC_CMP_SYSTEM_TIME_CNT_LSB (2) |
| 1183 | #define ST_FRC_TIMING_SYNC_CMP_SYSTEM_TIME_CNT_WIDTH (18) |
| 1184 | #define ST_FRC_TIMING_SYNC_CMP_SYSTEM_TIME_CNT_MASK (0x000FFFFC) |
| 1185 | |
| 1186 | #define ST_FRC_TIMING_SYNC_TRIG_TRIG_LSB (0) |
| 1187 | #define ST_FRC_TIMING_SYNC_TRIG_TRIG_WIDTH (1) |
| 1188 | #define ST_FRC_TIMING_SYNC_TRIG_TRIG_MASK (0x00000001) |
| 1189 | #define ST_FRC_TIMING_SYNC_TRIG_TRIG_BIT (0x00000001) |
| 1190 | |
| 1191 | #define ST_FRC_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_LSB (0) |
| 1192 | #define ST_FRC_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_WIDTH (20) |
| 1193 | #define ST_FRC_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_MASK (0x000FFFFF) |
| 1194 | |
| 1195 | #define ST_FRC_TIMING_SYNC_SUPFRM_CNT_L_SUPFRM_CNT_LSB (0) |
| 1196 | #define ST_FRC_TIMING_SYNC_SUPFRM_CNT_L_SUPFRM_CNT_WIDTH (32) |
| 1197 | #define ST_FRC_TIMING_SYNC_SUPFRM_CNT_L_SUPFRM_CNT_MASK (0xFFFFFFFF) |
| 1198 | |
| 1199 | #define ST_FRC_TIMING_SYNC_SUPFRM_CNT_H_SUPFRM_CNT_LSB (0) |
| 1200 | #define ST_FRC_TIMING_SYNC_SUPFRM_CNT_H_SUPFRM_CNT_WIDTH (4) |
| 1201 | #define ST_FRC_TIMING_SYNC_SUPFRM_CNT_H_SUPFRM_CNT_MASK (0x0000000F) |
| 1202 | |
| 1203 | #define ST_MU_SFO_EN_LSB (31) |
| 1204 | #define ST_MU_SFO_EN_WIDTH (1) |
| 1205 | #define ST_MU_SFO_EN_MASK (0x80000000) |
| 1206 | #define ST_MU_SFO_EN_BIT (0x80000000) |
| 1207 | |
| 1208 | #define ST_MU_SFO_AFC_PPB_LSB (0) |
| 1209 | #define ST_MU_SFO_AFC_PPB_WIDTH (16) |
| 1210 | #define ST_MU_SFO_AFC_PPB_MASK (0x0000FFFF) |
| 1211 | |
| 1212 | #define ST_MU_ACC_INI_L_MU_ACC_INI_LSB_LSB (0) |
| 1213 | #define ST_MU_ACC_INI_L_MU_ACC_INI_LSB_WIDTH (32) |
| 1214 | #define ST_MU_ACC_INI_L_MU_ACC_INI_LSB_MASK (0xFFFFFFFF) |
| 1215 | |
| 1216 | #define ST_MU_ACC_INI_H_MU_ACC_INI_MSB_LSB (0) |
| 1217 | #define ST_MU_ACC_INI_H_MU_ACC_INI_MSB_WIDTH (8) |
| 1218 | #define ST_MU_ACC_INI_H_MU_ACC_INI_MSB_MASK (0x000000FF) |
| 1219 | |
| 1220 | #define ST_MU_ACC_SET_EN_LSB (31) |
| 1221 | #define ST_MU_ACC_SET_EN_WIDTH (1) |
| 1222 | #define ST_MU_ACC_SET_EN_MASK (0x80000000) |
| 1223 | #define ST_MU_ACC_SET_EN_BIT (0x80000000) |
| 1224 | |
| 1225 | #define ST_MU_ACC_SET_SYSTEM_TIME_CNT_LSB (2) |
| 1226 | #define ST_MU_ACC_SET_SYSTEM_TIME_CNT_WIDTH (18) |
| 1227 | #define ST_MU_ACC_SET_SYSTEM_TIME_CNT_MASK (0x000FFFFC) |
| 1228 | |
| 1229 | #define ST_RAKE_CTL_TIME3_EN_LSB (31) |
| 1230 | #define ST_RAKE_CTL_TIME3_EN_WIDTH (1) |
| 1231 | #define ST_RAKE_CTL_TIME3_EN_MASK (0x80000000) |
| 1232 | #define ST_RAKE_CTL_TIME3_EN_BIT (0x80000000) |
| 1233 | |
| 1234 | #define ST_RAKE_CTL_TIME3_SYSTEM_TIME_CNT_LSB (7) |
| 1235 | #define ST_RAKE_CTL_TIME3_SYSTEM_TIME_CNT_WIDTH (13) |
| 1236 | #define ST_RAKE_CTL_TIME3_SYSTEM_TIME_CNT_MASK (0x000FFF80) |
| 1237 | |
| 1238 | #define ST_GSR_CTL_TIME2_SYSTEM_TIME_CNT_LSB (2) |
| 1239 | #define ST_GSR_CTL_TIME2_SYSTEM_TIME_CNT_WIDTH (18) |
| 1240 | #define ST_GSR_CTL_TIME2_SYSTEM_TIME_CNT_MASK (0x000FFFFC) |
| 1241 | |
| 1242 | #define ST_GSR_SYNC_TRIG_TRIG_LSB (31) |
| 1243 | #define ST_GSR_SYNC_TRIG_TRIG_WIDTH (1) |
| 1244 | #define ST_GSR_SYNC_TRIG_TRIG_MASK (0x80000000) |
| 1245 | #define ST_GSR_SYNC_TRIG_TRIG_BIT (0x80000000) |
| 1246 | |
| 1247 | #define ST_GSR_SYNC_TAG_GSR_SAMPLE_CNT_LSB (2) |
| 1248 | #define ST_GSR_SYNC_TAG_GSR_SAMPLE_CNT_WIDTH (18) |
| 1249 | #define ST_GSR_SYNC_TAG_GSR_SAMPLE_CNT_MASK (0x000FFFFC) |
| 1250 | |
| 1251 | #define ST_1XDO_TIMING_SYNC_TRIG_TRIG_LSB (0) |
| 1252 | #define ST_1XDO_TIMING_SYNC_TRIG_TRIG_WIDTH (1) |
| 1253 | #define ST_1XDO_TIMING_SYNC_TRIG_TRIG_MASK (0x00000001) |
| 1254 | #define ST_1XDO_TIMING_SYNC_TRIG_TRIG_BIT (0x00000001) |
| 1255 | |
| 1256 | #define ST_1XDO_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_LSB (0) |
| 1257 | #define ST_1XDO_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_WIDTH (20) |
| 1258 | #define ST_1XDO_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_MASK (0x000FFFFF) |
| 1259 | |
| 1260 | #define ST_1XDOMRG_EN_EN_LSB (0) |
| 1261 | #define ST_1XDOMRG_EN_EN_WIDTH (1) |
| 1262 | #define ST_1XDOMRG_EN_EN_MASK (0x00000001) |
| 1263 | #define ST_1XDOMRG_EN_EN_BIT (0x00000001) |
| 1264 | |
| 1265 | #define ST_1XDOMRG_INI_TIME_SYSTEM_TIME_CNT_LSB (3) |
| 1266 | #define ST_1XDOMRG_INI_TIME_SYSTEM_TIME_CNT_WIDTH (17) |
| 1267 | #define ST_1XDOMRG_INI_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFF8) |
| 1268 | |
| 1269 | #define ST_1XDOMRG_OFFSET_SYSTEM_TIME_CNT_OFFSET_LSB (3) |
| 1270 | #define ST_1XDOMRG_OFFSET_SYSTEM_TIME_CNT_OFFSET_WIDTH (17) |
| 1271 | #define ST_1XDOMRG_OFFSET_SYSTEM_TIME_CNT_OFFSET_MASK (0x000FFFF8) |
| 1272 | |
| 1273 | #define ST_GPS_EN_GPS_EN_LSB (0) |
| 1274 | #define ST_GPS_EN_GPS_EN_WIDTH (1) |
| 1275 | #define ST_GPS_EN_GPS_EN_MASK (0x00000001) |
| 1276 | #define ST_GPS_EN_GPS_EN_BIT (0x00000001) |
| 1277 | |
| 1278 | #endif |