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192.168.1.100 / T800_MD / 6c1fd8fba87d5723e0e5614ae30b4258b603cb70 / . / mcu / interface / service / nvram / l1_nvram_def.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame^]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
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15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
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24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
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28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
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31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 *
41 *
42 * Project:
43 * --------
44 * MAUI
45 *
46 * Description:
47 * ------------
48 *
49 *
50 * Author:
51 * -------
52 *
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
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179 *------------------------------------------------------------------------------
180 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
181 *============================================================================
182 ****************************************************************************/
183#ifndef __L1_NVRAM_DEF_H__
184#define __L1_NVRAM_DEF_H__
185
186#ifdef __cplusplus
187extern "C"
188{
189#endif /* __cplusplus */
190
191#if 0
192/* under construction !*/
193/* under construction !*/
194/* under construction !*/
195/* under construction !*/
196/* under construction !*/
197#endif
198
199
200#include "kal_general_types.h"
201#include "kal_public_defs.h" /* END_OF_MOD_ID */
202#include "stack_buff_pool.h"
203#include "ctrl_buff_pool.h"
204#include "sysconf_statistics.h"
205#include "kal_public_defs.h" /* LAST_SAP_CODE */
206#include "sysservice_msgid.h"
207#include "tst.h"
208#include "global_def.h"
209
210#include "nvram_defs.h"
211
212#include "l1d_cid.h"
213
214#if(defined(ISP_SUPPORT))
215#include "drv_sw_features_isp.h"
216#include "isp_nvram.h"
217#endif
218
219#if defined(__MA_L1__)
220#include "stack_common_ma.h"
221#endif /* __MA_L1__ */
222
223#ifdef __GAIN_TABLE_SUPPORT__
224#include "gain_table.h"
225#endif /* __GAIN_TABLE_SUPPORT__ */
226
227//#include "drv_features.h"
228//#include "drv_features_adc.h"
229//#include "drv_features_rtc.h"
230//#include "drv_features_sim.h"
231
232#ifdef __HMU_ENABLE__
233#include "hmu_conf_data.h"
234#endif
235
236#ifdef __NMU_ENABLE__
237#include "nmu.h"
238#endif
239
240#include "dcl.h" /* port_setting_struct */
241
242#ifdef __MULTI_LEVEL_BACKLIGHT_SUPPORT__
243#include "custom_hw_default.h"
244#endif
245
246#if defined(__UMTS_RAT__) && defined(__MTK_UL1_FDD__)
247#include "ul1cal.h"
248#endif
249
250#ifdef __AST_TL1_TDD__
251#include "tl1cal_ast.h"
252#include "tl1d_custom_drdi.h"
253#include "tl1d_rf_cal_poc_data.h"
254#ifdef __TAS_SUPPORT__
255#include "tl1d_custom_rf_tas_struct.h"
256#endif
257#endif
258
259#ifdef __MULTI_LEVEL_BACKLIGHT_SUPPORT__
260#include "custom_hw_default.h"
261#endif
262
263#ifdef __LTE_RAT__
264#include "el1d_custom_data.h"
265#include "el1d_rf_custom_data.h"
266#include "el1d_rf_drdi.h" /* Dynamic Radio-setting Dedicated Image */
267#endif
268
269#include "mml1_rf_global.h"
270#include "mml1_mipi_public.h"
271#include "mml1_drdi_public.h"
272
273#include "custom_nvram_sec.h" /* nvram_sml_context_struct */
274
275#include "ps_public_enum.h"
276#include "sbp_public_utility.h"
277#include "cust_chl_interface.h"
278#include "device.h"
279
280
281
282
283/************************************************************
284 * Start of L1 Calibration data
285 ************************************************************/
286/**
287 * Total number of L1 Calibration data items
288 */
289#if defined(__EPSK_TX__)
290#define NVRAM_EF_L1_EPSK_SUBTRAHEND 0
291#else
292#define NVRAM_EF_L1_EPSK_SUBTRAHEND (NVRAM_EF_L1_EPSK_END - NVRAM_EF_L1_EPSK_START + 1)
293#endif
294
295#if defined(__PS_SERVICE__)
296 #define NVRAM_EF_L1_PS_SERVICE_SUBTRAHEND 0
297#else
298 #define NVRAM_EF_L1_GMSK_TX_POWER_ROLLBACK_SUBTRAHEND 1
299
300 #define NVRAM_EF_L1_PS_SERVICE_SUBTRAHEND (NVRAM_EF_L1_GMSK_TX_POWER_ROLLBACK_SUBTRAHEND)
301#endif /*defined(__PS_SERVICE__)*/
302
303#if defined(__EGPRS_MODE__)
304 #define NVRAM_EF_L1_EGPRS_MODE_SUBTRAHEND 0
305#else
306 #define NVRAM_EF_L1_EPSK_TX_POWER_ROLLBACK_SUBTRAHEND 1
307
308 #define NVRAM_EF_L1_EGPRS_MODE_SUBTRAHEND (NVRAM_EF_L1_EPSK_TX_POWER_ROLLBACK_SUBTRAHEND)
309#endif /*defined(__EGPRS_MODE__)*/
310
311#if defined(__2G_TX_POWER_CONTROL_SUPPORT__)
312 #if defined(__EPSK_TX__)
313#define NVRAM_EF_L1_EPSK_TXPC_SUBTRAHEND 0
314 #else
315#define NVRAM_EF_L1_EPSK_TXPC_SUBTRAHEND 1
316 #endif /*__EPSK_TX__*/
317#else
318#define NVRAM_EF_L1_EPSK_TXPC_SUBTRAHEND 2
319#endif /*__2G_TX_POWER_CONTROL_SUPPORT__*/
320
321#if defined(__MULTI_LNA_MODE_CALIBRATION_SUPPORT__)
322#define NVRAM_EF_L1_LNAPATHLOSS_SUBTRAHEND 0
323#else
324#define NVRAM_EF_L1_LNAPATHLOSS_SUBTRAHEND 1
325#endif
326
327#if defined(__2G_TX_POWER_CONTROL_SUPPORT__)
328 #if !defined(__UMTS_RAT__) || !defined(__MTK_UL1_FDD__)|| defined(__MULTI_RAT_AFC_TADC_SHARE_SUPPORT__)
329#define NVRAM_EF_L1_TEMPERATURE_ADC_SUBTRAHEND 0
330 #else
331#define NVRAM_EF_L1_TEMPERATURE_ADC_SUBTRAHEND 1
332 #endif
333#else
334#define NVRAM_EF_L1_TEMPERATURE_ADC_SUBTRAHEND 1
335#endif /*__2G_TX_POWER_CONTROL_SUPPORT__*/
336
337#if defined(__F32_XOSC_REMOVAL_SUPPORT__)
338#define NVRAM_EF_L1_CLOAD_FREQ_OFFSET_SUBTRAHEND 0
339#else
340#define NVRAM_EF_L1_CLOAD_FREQ_OFFSET_SUBTRAHEND 1
341#endif /*__F32_XOSC_REMOVAL_SUPPORT__*/
342
343#if defined(__2G_TX_GAIN_RF_CALIBRATION__)
344#define NVRAM_EF_L1_GAINRF_LID_SUBTRAHEND 0
345#else
346#define NVRAM_EF_L1_GAINRF_LID_SUBTRAHEND 1
347#endif /*__2G_TX_GAIN_RF_CALIBRATION__*/
348
349#if defined(__TX_POWER_OFFSET_SUPPORT__)
350#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_LID_SUBTRAHEND 0
351#else
352#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_LID_SUBTRAHEND 9
353#endif /*__TX_POWER_OFFSET_SUPPORT__*/
354
355#if defined(__RX_POWER_OFFSET_SUPPORT__)
356#define NVRAM_EF_L1_RX_POWER_OFFSET_LID_SUBTRAHEND 0
357#else
358#define NVRAM_EF_L1_RX_POWER_OFFSET_LID_SUBTRAHEND 2
359#endif /*__RX_POWER_OFFSET_SUPPORT__*/
360
361#if defined (__NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__)
362 #if defined(__EPSK_ADJUST_TPO_SUPPORT__)
363#define NVRAM_EF_L1_NSFT_ADJUST_TPO_LID_SUBTRAHEND 0
364 #else
365#define NVRAM_EF_L1_NSFT_ADJUST_TPO_LID_SUBTRAHEND 4
366 #endif//__EPSK_ADJUST_TPO_SUPPORT__
367#else
368#define NVRAM_EF_L1_NSFT_ADJUST_TPO_LID_SUBTRAHEND 8
369#endif /*__NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__*/
370
371#define NVRAM_L1CAL_ELEMENT_TOTAL (NVRAM_EF_L1_END - NVRAM_EF_L1_START + 1 - \
372 NVRAM_EF_L1_EPSK_SUBTRAHEND - \
373 NVRAM_EF_L1_PS_SERVICE_SUBTRAHEND - \
374 NVRAM_EF_L1_EGPRS_MODE_SUBTRAHEND - \
375 NVRAM_EF_L1_EPSK_TXPC_SUBTRAHEND - \
376 NVRAM_EF_L1_LNAPATHLOSS_SUBTRAHEND - \
377 NVRAM_EF_L1_TEMPERATURE_ADC_SUBTRAHEND - \
378 NVRAM_EF_L1_CLOAD_FREQ_OFFSET_SUBTRAHEND - \
379 NVRAM_EF_L1_GAINRF_LID_SUBTRAHEND - \
380 NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_LID_SUBTRAHEND - \
381 NVRAM_EF_L1_RX_POWER_OFFSET_LID_SUBTRAHEND - \
382 NVRAM_EF_L1_NSFT_ADJUST_TPO_LID_SUBTRAHEND)
383
384
385
386
387// LID Enums
388
389typedef enum
390{
391 NVRAM_EF_L1_START = NVRAM_LID_GRP_L1(0),
392 NVRAM_EF_L1_AGCPATHLOSS_LID = NVRAM_EF_L1_START, // 0
393 NVRAM_EF_L1_RAMPTABLE_GSM850_LID = NVRAM_LID_GRP_L1(1),
394 NVRAM_EF_L1_RAMPTABLE_GSM900_LID = NVRAM_LID_GRP_L1(2),
395 NVRAM_EF_L1_RAMPTABLE_DCS1800_LID = NVRAM_LID_GRP_L1(3),
396 NVRAM_EF_L1_RAMPTABLE_PCS1900_LID = NVRAM_LID_GRP_L1(4),
397 NVRAM_EF_L1_EPSK_START = NVRAM_LID_GRP_L1(5),
398 NVRAM_EF_L1_EPSK_RAMPTABLE_GSM850_LID = NVRAM_EF_L1_EPSK_START,
399 NVRAM_EF_L1_EPSK_RAMPTABLE_GSM900_LID = NVRAM_LID_GRP_L1(6),
400 NVRAM_EF_L1_EPSK_RAMPTABLE_DCS1800_LID = NVRAM_LID_GRP_L1(7),
401 NVRAM_EF_L1_EPSK_RAMPTABLE_PCS1900_LID = NVRAM_LID_GRP_L1(8),
402 NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_GSM850_LID = NVRAM_LID_GRP_L1(9),
403 NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_GSM900_LID = NVRAM_LID_GRP_L1(10),
404 NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_DCS1800_LID = NVRAM_LID_GRP_L1(11),
405 NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_PCS1900_LID = NVRAM_LID_GRP_L1(12),
406 NVRAM_EF_L1_EPSK_END = NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_PCS1900_LID, //12
407 NVRAM_EF_L1_AFCDATA_LID = NVRAM_LID_GRP_L1(13),
408 NVRAM_EF_L1_TXIQ_LID = NVRAM_LID_GRP_L1(14),
409 NVRAM_EF_L1_RFSPECIALCOEF_LID = NVRAM_LID_GRP_L1(15),
410 NVRAM_EF_L1_INTERSLOT_RAMP_GSM850_LID = NVRAM_LID_GRP_L1(16),
411 NVRAM_EF_L1_INTERSLOT_RAMP_GSM900_LID = NVRAM_LID_GRP_L1(17),
412 NVRAM_EF_L1_INTERSLOT_RAMP_DCS1800_LID = NVRAM_LID_GRP_L1(18),
413 NVRAM_EF_L1_INTERSLOT_RAMP_PCS1900_LID = NVRAM_LID_GRP_L1(19),
414 NVRAM_EF_L1_CRYSTAL_AFCDATA_LID = NVRAM_LID_GRP_L1(20),
415 NVRAM_EF_L1_CRYSTAL_CAPDATA_LID = NVRAM_LID_GRP_L1(21),
416 /*Chuwei: for TX power rollback*/
417 NVRAM_EF_L1_GMSK_TX_POWER_ROLLBACK_TABLE_LID = NVRAM_LID_GRP_L1(22),
418 NVRAM_EF_L1_EPSK_TX_POWER_ROLLBACK_TABLE_LID = NVRAM_LID_GRP_L1(23),
419 /*for TX power control*/
420 NVRAM_EF_L1_GMSK_TXPC_LID = NVRAM_LID_GRP_L1(24),
421 NVRAM_EF_L1_EPSK_TXPC_LID = NVRAM_LID_GRP_L1(25),
422 /*for LNA Middle/Low mode*/
423 NVRAM_EF_L1_LNAPATHLOSS_LID = NVRAM_LID_GRP_L1(26),
424 /*for Temperature ADC*/
425 NVRAM_EF_L1_TEMPERATURE_ADC_LID = NVRAM_LID_GRP_L1(27),
426 /*for DCXO LPM Cload freq. offset*/
427 NVRAM_EF_L1_CLOAD_FREQ_OFFSET_LID = NVRAM_LID_GRP_L1(28),
428 NVRAM_EF_L1_GAINRF_LID = NVRAM_LID_GRP_L1(29),
429 /* for 2g Tx power Offset */
430 NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM850_LID = NVRAM_LID_GRP_L1(30),
431 NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM900_LID = NVRAM_LID_GRP_L1(31),
432 NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_DCS_LID = NVRAM_LID_GRP_L1(32),
433 NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_PCS_LID = NVRAM_LID_GRP_L1(33),
434 NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM850_LID = NVRAM_LID_GRP_L1(34),
435 NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM900_LID = NVRAM_LID_GRP_L1(35),
436 NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_DCS_LID = NVRAM_LID_GRP_L1(36),
437 NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_PCS_LID = NVRAM_LID_GRP_L1(37),
438 /*for modem bin update tool*/
439 NVRAM_EF_L1_2G_RF_PARAMETER_LID = NVRAM_LID_GRP_L1(38),
440 /* for GGE MIPI CTRL TABLE AT NVRAM */
441 NVRAM_EF_L1_MIPI_CTRL_TABLE_GSM850_LID = NVRAM_LID_GRP_L1(39),
442 NVRAM_EF_L1_MIPI_CTRL_TABLE_GSM900_LID = NVRAM_LID_GRP_L1(40),
443 NVRAM_EF_L1_MIPI_CTRL_TABLE_DCS1800_LID = NVRAM_LID_GRP_L1(41),
444 NVRAM_EF_L1_MIPI_CTRL_TABLE_PCS1900_LID = NVRAM_LID_GRP_L1(42),
445 NVRAM_EF_L1_CUSTOM_BAND_SUPPORT_LID = NVRAM_LID_GRP_L1(43),
446 NVRAM_EF_L1_TAS_CUSTOM_PARAMES_LID = NVRAM_LID_GRP_L1(44),
447 NVRAM_EF_L1_TAS_CUSTOM_FE_PARAMS_LID = NVRAM_LID_GRP_L1(45),
448 NVRAM_EF_L1_TAS_CUSTOM_INHERIT_LTE_BAND_LID = NVRAM_LID_GRP_L1(46),
449 NVRAM_EF_L1_RFC_LID = NVRAM_LID_GRP_L1(47),
450 NVRAM_EF_L1_2G_RF_RX_PARAMETER_EXT_LID = NVRAM_LID_GRP_L1(48),
451 NVRAM_EF_L1_AGCPATHLOSS_OFFSET_LID = NVRAM_LID_GRP_L1(49),
452 NVRAM_EF_L1_DAT_CUSTOM_FE_ROUTE_PARAMES_LID = NVRAM_LID_GRP_L1(50),
453 NVRAM_EF_L1_DAT_CUSTOM_FE_CAT_A_PARAMES_LID = NVRAM_LID_GRP_L1(51),
454 NVRAM_EF_L1_DAT_CUSTOM_FE_CAT_B_PARAMES_LID = NVRAM_LID_GRP_L1(52),
455 NVRAM_EF_L1_ANT_RXPWR_OFFSET_LID = NVRAM_LID_GRP_L1(53),
456 /* for 2g NSFT Adjust tx power offset */
457 NVRAM_EF_L1_GMSK_ADJUST_TPO_GSM850_LID = NVRAM_LID_GRP_L1(54),
458 NVRAM_EF_L1_GMSK_ADJUST_TPO_GSM900_LID = NVRAM_LID_GRP_L1(55),
459 NVRAM_EF_L1_GMSK_ADJUST_TPO_DCS_LID = NVRAM_LID_GRP_L1(56),
460 NVRAM_EF_L1_GMSK_ADJUST_TPO_PCS_LID = NVRAM_LID_GRP_L1(57),
461 NVRAM_EF_L1_EPSK_ADJUST_TPO_GSM850_LID = NVRAM_LID_GRP_L1(58),
462 NVRAM_EF_L1_EPSK_ADJUST_TPO_GSM900_LID = NVRAM_LID_GRP_L1(59),
463 NVRAM_EF_L1_EPSK_ADJUST_TPO_DCS_LID = NVRAM_LID_GRP_L1(60),
464 NVRAM_EF_L1_EPSK_ADJUST_TPO_PCS_LID = NVRAM_LID_GRP_L1(61),
465 /* for 2G RXD*/
466 NVRAM_EF_L1_AGCPATHLOSS_RXD_LID = NVRAM_LID_GRP_L1(62),
467 NVRAM_EF_L1_LNAPATHLOSS_RXD_LID = NVRAM_LID_GRP_L1(63),
468 NVRAM_EF_L1_AGCPATHLOSS_OFFSET_RXD_LID = NVRAM_LID_GRP_L1(64),
469 NVRAM_EF_L1_WCOEF_RXD_LID = NVRAM_LID_GRP_L1(65),
470 NVRAM_EF_L1_RAS_CUSTOM_PARAMES_LID = NVRAM_LID_GRP_L1(66),
471 /* for 2G SAR TX POWER BACKOFF DB*/
472 NVRAM_EF_L1_SAR_TX_BACKOFF_DB_CUSTOM_PARAMES_LID = NVRAM_LID_GRP_L1(67),
473 NVRAM_EF_L1_END = NVRAM_EF_L1_SAR_TX_BACKOFF_DB_CUSTOM_PARAMES_LID,
474 NVRAM_EF_L1_LAST_LID = NVRAM_LID_GRP_L1(255)
475}nvram_lid_l1_enum;
476
477// VERNO
478#define NVRAM_EF_L1_AGCPATHLOSS_LID_VERNO "002"
479#if IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT
480#define NVRAM_EF_L1_RAMPTABLE_GSM850_LID_VERNO "003"
481#define NVRAM_EF_L1_RAMPTABLE_GSM900_LID_VERNO "003"
482#define NVRAM_EF_L1_RAMPTABLE_DCS1800_LID_VERNO "003"
483#define NVRAM_EF_L1_RAMPTABLE_PCS1900_LID_VERNO "003"
484#define NVRAM_EF_L1_EPSK_RAMPTABLE_GSM850_LID_VERNO "003"
485#define NVRAM_EF_L1_EPSK_RAMPTABLE_GSM900_LID_VERNO "003"
486#define NVRAM_EF_L1_EPSK_RAMPTABLE_DCS1800_LID_VERNO "003"
487#define NVRAM_EF_L1_EPSK_RAMPTABLE_PCS1900_LID_VERNO "003"
488#else
489#define NVRAM_EF_L1_RAMPTABLE_GSM850_LID_VERNO "002"
490#define NVRAM_EF_L1_RAMPTABLE_GSM900_LID_VERNO "002"
491#define NVRAM_EF_L1_RAMPTABLE_DCS1800_LID_VERNO "002"
492#define NVRAM_EF_L1_RAMPTABLE_PCS1900_LID_VERNO "002"
493#define NVRAM_EF_L1_EPSK_RAMPTABLE_GSM850_LID_VERNO "002"
494#define NVRAM_EF_L1_EPSK_RAMPTABLE_GSM900_LID_VERNO "002"
495#define NVRAM_EF_L1_EPSK_RAMPTABLE_DCS1800_LID_VERNO "002"
496#define NVRAM_EF_L1_EPSK_RAMPTABLE_PCS1900_LID_VERNO "002"
497#endif
498#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_GSM850_LID_VERNO "002"
499#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_GSM900_LID_VERNO "002"
500#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_DCS1800_LID_VERNO "002"
501#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_PCS1900_LID_VERNO "002"
502#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
503#define NVRAM_EF_L1_AFCDATA_LID_VERNO "003"
504#else
505#define NVRAM_EF_L1_AFCDATA_LID_VERNO "002"
506#endif
507#if IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT
508#define NVRAM_EF_L1_TXIQ_LID_VERNO "005"
509#else
510#define NVRAM_EF_L1_TXIQ_LID_VERNO "004"
511#endif
512#define NVRAM_EF_L1_RFSPECIALCOEF_LID_VERNO "006"
513#define NVRAM_EF_L1_INTERSLOT_RAMP_GSM850_LID_VERNO "002"
514#define NVRAM_EF_L1_INTERSLOT_RAMP_GSM900_LID_VERNO "002"
515#define NVRAM_EF_L1_INTERSLOT_RAMP_DCS1800_LID_VERNO "002"
516#define NVRAM_EF_L1_INTERSLOT_RAMP_PCS1900_LID_VERNO "002"
517#define NVRAM_EF_L1_CRYSTAL_AFCDATA_LID_VERNO "003"
518#define NVRAM_EF_L1_CRYSTAL_CAPDATA_LID_VERNO "002"
519 /*Chuwei: for TX power rollback*/
520#define NVRAM_EF_L1_GMSK_TX_POWER_ROLLBACK_TABLE_LID_VERNO "000"
521#define NVRAM_EF_L1_EPSK_TX_POWER_ROLLBACK_TABLE_LID_VERNO "000"
522/*for TX power control*/
523#define NVRAM_EF_L1_GMSK_TXPC_LID_VERNO "000"
524#define NVRAM_EF_L1_EPSK_TXPC_LID_VERNO "000"
525/*for LNA Middle/Low mode*/
526#define NVRAM_EF_L1_LNAPATHLOSS_LID_VERNO "002"
527
528 #if defined(__MD97__)
529#define NVRAM_EF_L1_2G_RF_PARAMETER_LID_VERNO "003"
530 #else
531#define NVRAM_EF_L1_2G_RF_PARAMETER_LID_VERNO "000"
532 #endif
533/*for Temperature ADC*/
534#define NVRAM_EF_L1_TEMPERATURE_ADC_LID_VERNO "000"
535/*for CLoad freq offset*/
536#define NVRAM_EF_L1_CLOAD_FREQ_OFFSET_LID_VERNO "000"
537/*for TX gain rf cal */
538#define NVRAM_EF_L1_GAINRF_LID_VERNO "000"
539/*for MIPI NVRAM CTRL TABLE */
540#define NVRAM_EF_L1_MIPI_CTRL_TABLE_GSM850_LID_VERNO "000"
541#define NVRAM_EF_L1_MIPI_CTRL_TABLE_GSM900_LID_VERNO "000"
542#define NVRAM_EF_L1_MIPI_CTRL_TABLE_DCS1800_LID_VERNO "000"
543#define NVRAM_EF_L1_MIPI_CTRL_TABLE_PCS1900_LID_VERNO "000"
544#define NVRAM_EF_L1_CUSTOM_BAND_SUPPORT_LID_VERNO "000"
545/* for 2g Tx power Offset */
546 #if defined(__MD97__)
547#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM850_LID_VERNO "002"
548#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM900_LID_VERNO "002"
549#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_DCS_LID_VERNO "002"
550#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_PCS_LID_VERNO "002"
551#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM850_LID_VERNO "002"
552#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM900_LID_VERNO "002"
553#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_DCS_LID_VERNO "002"
554#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_PCS_LID_VERNO "002"
555 #else
556#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM850_LID_VERNO "001"
557#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM900_LID_VERNO "001"
558#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_DCS_LID_VERNO "001"
559#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_PCS_LID_VERNO "001"
560#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM850_LID_VERNO "001"
561#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM900_LID_VERNO "001"
562#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_DCS_LID_VERNO "001"
563#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_PCS_LID_VERNO "001"
564 #endif
565
566/* for 2g Rx power Offset */
567#define NVRAM_EF_L1_2G_RF_RX_PARAMETER_EXT_LID_VERNO "000"
568#define NVRAM_EF_L1_AGCPATHLOSS_OFFSET_LID_VERNO "000"
569
570/* for 2g DAT */
571#if defined(__MD97__)
572#define NVRAM_EF_L1_DAT_CUSTOM_FE_ROUTE_PARAMES_LID_VERNO "001"
573#else
574#define NVRAM_EF_L1_DAT_CUSTOM_FE_ROUTE_PARAMES_LID_VERNO "000"
575#endif
576#if defined(__MD93__)
577#define NVRAM_EF_L1_DAT_CUSTOM_FE_CAT_A_PARAMES_LID_VERNO "000"
578#define NVRAM_EF_L1_DAT_CUSTOM_FE_CAT_B_PARAMES_LID_VERNO "000"
579#endif
580/* for 2g antenna rx power offset */
581#define NVRAM_EF_L1_ANT_RXPWR_OFFSET_LID_VERNO "000"
582
583/* for 2g adjust Tx power Offset */
584#define NVRAM_EF_L1_GMSK_ADJUST_TPO_GSM850_LID_VERNO "000"
585#define NVRAM_EF_L1_GMSK_ADJUST_TPO_GSM900_LID_VERNO "000"
586#define NVRAM_EF_L1_GMSK_ADJUST_TPO_DCS_LID_VERNO "000"
587#define NVRAM_EF_L1_GMSK_ADJUST_TPO_PCS_LID_VERNO "000"
588#define NVRAM_EF_L1_EPSK_ADJUST_TPO_GSM850_LID_VERNO "000"
589#define NVRAM_EF_L1_EPSK_ADJUST_TPO_GSM900_LID_VERNO "000"
590#define NVRAM_EF_L1_EPSK_ADJUST_TPO_DCS_LID_VERNO "000"
591#define NVRAM_EF_L1_EPSK_ADJUST_TPO_PCS_LID_VERNO "000"
592
593#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
594/* for 2G RXD */
595#define NVRAM_EF_L1_AGCPATHLOSS_RXD_LID_VERNO "000"
596#define NVRAM_EF_L1_LNAPATHLOSS_RXD_LID_VERNO "000"
597#define NVRAM_EF_L1_AGCPATHLOSS_OFFSET_RXD_LID_VERNO "000"
598#define NVRAM_EF_L1_WCOEF_RXD_LID_VERNO "000"
599#if IS_2G_C_VALUE_SUPPORT || IS_2G_RXD_BLACKLIST_SUPPORT
600 #if IS_2G_RXD_BLACKLIST_SUPPORT
601 #define NVRAM_EF_L1_RAS_CUSTOM_PARAMES_LID_VERNO "004"
602 #else
603 #define NVRAM_EF_L1_RAS_CUSTOM_PARAMES_LID_VERNO "003"
604 #endif
605#else
606#define NVRAM_EF_L1_RAS_CUSTOM_PARAMES_LID_VERNO "002"
607#endif
608#endif
609
610
611/*for 2G RF cal */
612#if defined(__MD97__)
613#else
614#define NVRAM_EF_L1_RFC_LID_VERNO "000"
615#endif
616
617/* for 2G TAS */
618 #if defined(__MD97__)/*Since the NVRAM structure is modified only for Gen97 not for Gen95*/
619#define NVRAM_EF_L1_TAS_CUSTOM_PARAMES_LID_VERNO "007"
620 #else
621#define NVRAM_EF_L1_TAS_CUSTOM_PARAMES_LID_VERNO "004"
622#define NVRAM_EF_L1_TAS_CUSTOM_FE_PARAMS_LID_VERNO "000"
623 #endif
624 #if defined(__MD93__) /*GL1D is not involved from Gen95 onwards since GL1C is taking care of it*/
625#define NVRAM_EF_L1_TAS_CUSTOM_INHERIT_LTE_BAND_LID_VERNO "000"
626 #endif
627
628#if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__)
629 #if defined(__MD97__)
630#define NVRAM_EF_L1_SAR_TX_BACKOFF_DB_CUSTOM_PARAMES_LID_VERNO "002"
631 #else
632#define NVRAM_EF_L1_SAR_TX_BACKOFF_DB_CUSTOM_PARAMES_LID_VERNO "001"
633 #endif
634#endif
635
636// HASH Key
637#define NVRAM_EF_L1_AGCPATHLOSS_LID_HASH 0xC134A6C7
638#if IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT
639#define NVRAM_EF_L1_RAMPTABLE_GSM850_LID_HASH 0x410017D6
640#define NVRAM_EF_L1_RAMPTABLE_GSM900_LID_HASH 0x55636111
641#define NVRAM_EF_L1_RAMPTABLE_DCS1800_LID_HASH 0x989562FD
642#define NVRAM_EF_L1_RAMPTABLE_PCS1900_LID_HASH 0x56E768B9
643#define NVRAM_EF_L1_EPSK_RAMPTABLE_GSM850_LID_HASH 0x2CA40824
644#define NVRAM_EF_L1_EPSK_RAMPTABLE_GSM900_LID_HASH 0xF12C9C73
645#define NVRAM_EF_L1_EPSK_RAMPTABLE_DCS1800_LID_HASH 0x443EFB5D
646#define NVRAM_EF_L1_EPSK_RAMPTABLE_PCS1900_LID_HASH 0x3AA23ACB
647#else
648#define NVRAM_EF_L1_RAMPTABLE_GSM850_LID_HASH 0xD8B140AA
649#define NVRAM_EF_L1_RAMPTABLE_GSM900_LID_HASH 0x9E6AA657
650#define NVRAM_EF_L1_RAMPTABLE_DCS1800_LID_HASH 0xF07DC3FD
651#define NVRAM_EF_L1_RAMPTABLE_PCS1900_LID_HASH 0x396DFD34
652#define NVRAM_EF_L1_EPSK_RAMPTABLE_GSM850_LID_HASH 0x91ED9472
653#define NVRAM_EF_L1_EPSK_RAMPTABLE_GSM900_LID_HASH 0x644B9807
654#define NVRAM_EF_L1_EPSK_RAMPTABLE_DCS1800_LID_HASH 0xC36520D1
655#define NVRAM_EF_L1_EPSK_RAMPTABLE_PCS1900_LID_HASH 0x49D62029
656#endif
657#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_GSM850_LID_HASH 0x1107D89D
658#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_GSM900_LID_HASH 0xCFDB2E1A
659#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_DCS1800_LID_HASH 0xC766FADF
660#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_PCS1900_LID_HASH 0x4EE24A2B
661#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
662#define NVRAM_EF_L1_AFCDATA_LID_HASH 0xA95E715C
663#else
664#define NVRAM_EF_L1_AFCDATA_LID_HASH 0x3DBF69B3
665#endif
666#if IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT
667#define NVRAM_EF_L1_TXIQ_LID_HASH 0x20ED5E0D
668#else
669#define NVRAM_EF_L1_TXIQ_LID_HASH 0x3B7FF0EC
670#endif
671#define NVRAM_EF_L1_RFSPECIALCOEF_LID_HASH 0xDCF9A6B9
672#define NVRAM_EF_L1_INTERSLOT_RAMP_GSM850_LID_HASH 0x2FB4032E
673#define NVRAM_EF_L1_INTERSLOT_RAMP_GSM900_LID_HASH 0x2A280DA7
674#define NVRAM_EF_L1_INTERSLOT_RAMP_DCS1800_LID_HASH 0xD40E7C0C
675#define NVRAM_EF_L1_INTERSLOT_RAMP_PCS1900_LID_HASH 0xD4906E05
676#define NVRAM_EF_L1_CRYSTAL_AFCDATA_LID_HASH 0xFA82CE1D
677#define NVRAM_EF_L1_CRYSTAL_CAPDATA_LID_HASH 0xC5533B2B
678#define NVRAM_EF_L1_GMSK_TX_POWER_ROLLBACK_TABLE_LID_HASH 0x37E08D6E
679#define NVRAM_EF_L1_EPSK_TX_POWER_ROLLBACK_TABLE_LID_HASH 0xB0CF9120
680#define NVRAM_EF_L1_GMSK_TXPC_LID_HASH 0xDFC9654C
681#define NVRAM_EF_L1_EPSK_TXPC_LID_HASH 0xCDB53FB4
682#define NVRAM_EF_L1_LNAPATHLOSS_LID_HASH 0xEAAA043E
683#define NVRAM_EF_L1_TEMPERATURE_ADC_LID_HASH 0xE07F9717
684#define NVRAM_EF_L1_CLOAD_FREQ_OFFSET_LID_HASH 0x5D08E624
685#define NVRAM_EF_L1_GAINRF_LID_HASH 0x998663C0
686
687 #if defined(__MD97__)
688#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM850_LID_HASH 0x7ED7743B
689#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM900_LID_HASH 0x9A0D92F4
690#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_DCS_LID_HASH 0x518F3EF8
691#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_PCS_LID_HASH 0x11E80559
692#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM850_LID_HASH 0xC33A1A5B
693#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM900_LID_HASH 0x489D5727
694#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_DCS_LID_HASH 0xDF0EB453
695#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_PCS_LID_HASH 0xE01C9FB2
696 #else
697#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM850_LID_HASH 0x35ADA79F
698#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM900_LID_HASH 0x7DECAEAF
699#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_DCS_LID_HASH 0xF73225CB
700#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_PCS_LID_HASH 0x772FA05F
701#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM850_LID_HASH 0x4328A933
702#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM900_LID_HASH 0xEEA3BE52
703#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_DCS_LID_HASH 0xE464199C
704#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_PCS_LID_HASH 0x8EF17D8E
705 #endif
706 #if defined(__MD97__)
707#define NVRAM_EF_L1_2G_RF_PARAMETER_LID_HASH 0xC22D1AE1
708 #else
709#define NVRAM_EF_L1_2G_RF_PARAMETER_LID_HASH 0xB1EB4B09
710 #endif
711
712#define NVRAM_EF_L1_MIPI_CTRL_TABLE_GSM850_LID_HASH 0x9BAA3563
713#define NVRAM_EF_L1_MIPI_CTRL_TABLE_GSM900_LID_HASH 0xAFB78A58
714#define NVRAM_EF_L1_MIPI_CTRL_TABLE_DCS1800_LID_HASH 0x57261FBD
715#define NVRAM_EF_L1_MIPI_CTRL_TABLE_PCS1900_LID_HASH 0x26028FAE
716#define NVRAM_EF_L1_CUSTOM_BAND_SUPPORT_LID_HASH 0x866BADD8
717 #if defined(__MD97__)/*Since the NVRAM structure is modified only for Gen97 not for Gen95*/
718#define NVRAM_EF_L1_TAS_CUSTOM_PARAMES_LID_HASH 0x83203116
719 #else
720#define NVRAM_EF_L1_TAS_CUSTOM_PARAMES_LID_HASH 0x99397C60
721#define NVRAM_EF_L1_TAS_CUSTOM_FE_PARAMS_LID_HASH 0x55D2FF23
722 #endif
723 #if defined(__MD93__) /*GL1D is not involved from Gen95 onwards since GL1C is taking care of it*/
724#define NVRAM_EF_L1_TAS_CUSTOM_INHERIT_LTE_BAND_LID_HASH 0xED2D97BC
725 #endif
726#if defined(__MD97__)
727#else
728#define NVRAM_EF_L1_RFC_LID_HASH 0xE38BED6F
729#endif
730#define NVRAM_EF_L1_2G_RF_RX_PARAMETER_EXT_LID_HASH 0x93978E87
731#define NVRAM_EF_L1_AGCPATHLOSS_OFFSET_LID_HASH 0x8DC7C68E
732#if defined(__MD97__)
733#define NVRAM_EF_L1_DAT_CUSTOM_FE_ROUTE_PARAMES_LID_HASH 0xD371E1AE
734#else
735#define NVRAM_EF_L1_DAT_CUSTOM_FE_ROUTE_PARAMES_LID_HASH 0xF612C36A
736#endif
737#define NVRAM_EF_L1_DAT_CUSTOM_FE_CAT_A_PARAMES_LID_HASH 0xEE77D89E
738#define NVRAM_EF_L1_DAT_CUSTOM_FE_CAT_B_PARAMES_LID_HASH 0x7DBDFD56
739#define NVRAM_EF_L1_ANT_RXPWR_OFFSET_LID_HASH 0x1A9191E0
740#define NVRAM_EF_L1_AGCPATHLOSS_RXD_LID_HASH 0xCE13B6D8
741#define NVRAM_EF_L1_LNAPATHLOSS_RXD_LID_HASH 0x227BBAF8
742#define NVRAM_EF_L1_AGCPATHLOSS_OFFSET_RXD_LID_HASH 0x566DBC60
743#define NVRAM_EF_L1_WCOEF_RXD_LID_HASH 0x5DE2439E
744#if IS_2G_C_VALUE_SUPPORT || IS_2G_RXD_BLACKLIST_SUPPORT
745 #if IS_2G_RXD_BLACKLIST_SUPPORT
746#define NVRAM_EF_L1_RAS_CUSTOM_PARAMES_LID_HASH 0x2FC382B2
747 #else
748#define NVRAM_EF_L1_RAS_CUSTOM_PARAMES_LID_HASH 0xEF4185B7
749 #endif
750#else
751#define NVRAM_EF_L1_RAS_CUSTOM_PARAMES_LID_HASH 0xFC42DE76
752#endif
753 #if defined(__MD97__)
754#define NVRAM_EF_L1_SAR_TX_BACKOFF_DB_CUSTOM_PARAMES_LID_HASH 0x8E3DD232
755 #else
756#define NVRAM_EF_L1_SAR_TX_BACKOFF_DB_CUSTOM_PARAMES_LID_HASH 0x8D25E7E1
757 #endif
758#define NVRAM_EF_L1_GMSK_ADJUST_TPO_GSM850_LID_HASH 0x1AAB5DDA
759#define NVRAM_EF_L1_GMSK_ADJUST_TPO_GSM900_LID_HASH 0xD85DFC40
760#define NVRAM_EF_L1_GMSK_ADJUST_TPO_DCS_LID_HASH 0x89406179
761#define NVRAM_EF_L1_GMSK_ADJUST_TPO_PCS_LID_HASH 0x557624CE
762#define NVRAM_EF_L1_EPSK_ADJUST_TPO_GSM850_LID_HASH 0xF3DF32D5
763#define NVRAM_EF_L1_EPSK_ADJUST_TPO_GSM900_LID_HASH 0x6A1AD662
764#define NVRAM_EF_L1_EPSK_ADJUST_TPO_DCS_LID_HASH 0x844D99E6
765#define NVRAM_EF_L1_EPSK_ADJUST_TPO_PCS_LID_HASH 0xC7F1D92B
766
767/**********************************************************************************/
768/**
769 * L1 Crystal AFC Data
770 */
771#if (defined(__MD93__) || defined(__MD95__))
772#define NVRAM_EF_L1_CRYSTAL_AFCDATA_SIZE sizeof(l1cal_crystalAfcData_T)
773#define NVRAM_EF_L1_CRYSTAL_AFCDATA_TOTAL 1
774#endif
775
776/**
777 * L1 Crystal CAP Data
778 */
779#define NVRAM_EF_L1_CRYSTAL_CAPDATA_SIZE sizeof(l1cal_crystalCapData_T)
780#define NVRAM_EF_L1_CRYSTAL_CAPDATA_TOTAL 1
781
782/**
783 * L1 Tx power rollback table
784 */
785#define NVRAM_EF_L1_GMSK_TX_POWER_ROLLBACK_TABLE_SIZE sizeof(l1cal_tx_power_rollback_T)
786#define NVRAM_EF_L1_GMSK_TX_POWER_ROLLBACK_TABLE_TOTAL 1
787
788#define NVRAM_EF_L1_EPSK_TX_POWER_ROLLBACK_TABLE_SIZE sizeof(l1cal_tx_power_rollback_T)
789#define NVRAM_EF_L1_EPSK_TX_POWER_ROLLBACK_TABLE_TOTAL 1
790
791/**
792 * L1 TX power control ADC Data
793 */
794#define NVRAM_EF_L1_GMSK_TXPC_SIZE sizeof(l1cal_txpc_T)
795#define NVRAM_EF_L1_GMSK_TXPC_TOTAL 1
796
797#define NVRAM_EF_L1_EPSK_TXPC_SIZE sizeof(l1cal_txpc_T)
798#define NVRAM_EF_L1_EPSK_TXPC_TOTAL 1
799
800/**
801 * L1 LNA Path Loss
802 */
803#define NVRAM_EF_L1_LNAPATHLOSS_SIZE sizeof(l1cal_lnaPathLoss_T)
804#define NVRAM_EF_L1_LNAPATHLOSS_TOTAL 1
805
806#define NVRAM_EF_L1_2G_RF_PARAMETER_SIZE sizeof(l1d_rf_custom_input_data_T)
807#define NVRAM_EF_L1_2G_RF_PARAMETER_TOTAL 1
808
809/**
810 * L1 Temperature ADC
811 */
812#define NVRAM_EF_L1_TEMPERATURE_ADC_SIZE sizeof(l1cal_temperatureADC_T)
813#define NVRAM_EF_L1_TEMPERATURE_ADC_TOTAL 1
814
815/************************************************************
816 * End of L1 Calibration data
817 ************************************************************/
818
819
820
821
822// Size and Total
823/**
824 * L1 AGC Path Loss
825 */
826#define NVRAM_EF_L1_AGCPATHLOSS_SIZE sizeof(l1cal_agcPathLoss_T)
827#define NVRAM_EF_L1_AGCPATHLOSS_TOTAL 1
828
829/**
830 * L1 Ramp Table for GSM850
831 */
832#define NVRAM_EF_L1_RAMPTABLE_GSM850_SIZE sizeof(l1cal_rampTable_T)
833#define NVRAM_EF_L1_RAMPTABLE_GSM850_TOTAL 1
834
835/**
836 * L1 Ramp Table for GSM900
837 */
838#define NVRAM_EF_L1_RAMPTABLE_GSM900_SIZE sizeof(l1cal_rampTable_T)
839#define NVRAM_EF_L1_RAMPTABLE_GSM900_TOTAL 1
840
841/**
842 * L1 Ramp Table for DCS1800
843 */
844#define NVRAM_EF_L1_RAMPTABLE_DCS1800_SIZE sizeof(l1cal_rampTable_T)
845#define NVRAM_EF_L1_RAMPTABLE_DCS1800_TOTAL 1
846
847/**
848 * L1 Ramp Table for PCS1900
849 */
850#define NVRAM_EF_L1_RAMPTABLE_PCS1900_SIZE sizeof(l1cal_rampTable_T)
851#define NVRAM_EF_L1_RAMPTABLE_PCS1900_TOTAL 1
852
853#if defined(__EPSK_TX__)
854/**
855 * L1 EPSK_Ramp Table for GSM850
856 */
857#define NVRAM_EF_L1_EPSK_RAMPTABLE_GSM850_SIZE sizeof(l1cal_rampTable_T)
858#define NVRAM_EF_L1_EPSK_RAMPTABLE_GSM850_TOTAL 1
859
860/**
861 * L1 EPSK_Ramp Table for GSM900
862 */
863#define NVRAM_EF_L1_EPSK_RAMPTABLE_GSM900_SIZE sizeof(l1cal_rampTable_T)
864#define NVRAM_EF_L1_EPSK_RAMPTABLE_GSM900_TOTAL 1
865
866/**
867 * L1 EPSK_Ramp Table for DCS1800
868 */
869#define NVRAM_EF_L1_EPSK_RAMPTABLE_DCS1800_SIZE sizeof(l1cal_rampTable_T)
870#define NVRAM_EF_L1_EPSK_RAMPTABLE_DCS1800_TOTAL 1
871
872/**
873 * L1 EPSK_Ramp Table for PCS1900
874 */
875#define NVRAM_EF_L1_EPSK_RAMPTABLE_PCS1900_SIZE sizeof(l1cal_rampTable_T)
876#define NVRAM_EF_L1_EPSK_RAMPTABLE_PCS1900_TOTAL 1
877#endif /* defined(__EPSK_TX__) */
878/**
879 * L1 AFC Data
880 */
881#define NVRAM_EF_L1_AFCDATA_SIZE sizeof(l1cal_afcData_T)
882#define NVRAM_EF_L1_AFCDATA_TOTAL 1
883
884/**
885 * L1 TXIQ Calibration data
886 */
887#define NVRAM_EF_L1_TXIQ_SIZE sizeof(l1cal_txiq_T)
888#define NVRAM_EF_L1_TXIQ_TOTAL 1
889
890/**
891 * L1 RF Special Coef Calibration data
892 */
893#define NVRAM_EF_L1_RFSPECIALCOEF_SIZE sizeof(l1cal_rfspecialcoef_T)
894#define NVRAM_EF_L1_RFSPECIALCOEF_TOTAL 1
895
896/**
897 * L1 CLoad freq offset Calibration data
898 */
899#define NVRAM_EF_L1_CLOAD_FREQ_OFFSET_SIZE sizeof(l1cal_cload_freq_offset_T)
900#define NVRAM_EF_L1_CLOAD_FREQ_OFFSET_TOTAL 1
901
902/**
903 * L1 TX GAIN RF Calibration data
904 */
905#define NVRAM_EF_L1_GAINRF_LID_SIZE sizeof(l1cal_gainrf_T)
906#define NVRAM_EF_L1_GAINRF_LID_TOTAL 1
907
908#if defined(__TX_POWER_OFFSET_SUPPORT__)
909/**
910 * L1 GMSK TX power offset parameter
911 */
912
913/**
914 * L1 GMSK TX power offset data for GSM850
915 */
916#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM850_SIZE sizeof(tx_power_offset_t)
917#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM850_TOTAL 1
918
919/**
920 * L1 GMSK TX power offset data for GSM900
921 */
922#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM900_SIZE sizeof(tx_power_offset_t)
923#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_GSM900_TOTAL 1
924
925/**
926 * L1 GMSK TX power offset data for DCS
927 */
928#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_DCS_SIZE sizeof(tx_power_offset_t)
929#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_DCS_TOTAL 1
930
931/**
932 * L1 GMSK TX power offset data for PCS
933 */
934#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_PCS_SIZE sizeof(tx_power_offset_t)
935#define NVRAM_EF_L1_GMSK_TX_POWER_OFFSET_PCS_TOTAL 1
936
937/**
938 * L1 EPSK TX power offset data for GSM850
939 */
940#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM850_SIZE sizeof(tx_power_offset_t)
941#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM850_TOTAL 1
942
943/**
944 * L1 EPSK TX power offset data for GSM900
945 */
946#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM900_SIZE sizeof(tx_power_offset_t)
947#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_GSM900_TOTAL 1
948
949/**
950 * L1 EPSK TX power offset data for DCS
951 */
952#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_DCS_SIZE sizeof(tx_power_offset_t)
953#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_DCS_TOTAL 1
954
955/**
956 * L1 EPSK TX power offset data for PCS
957 */
958#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_PCS_SIZE sizeof(tx_power_offset_t)
959#define NVRAM_EF_L1_EPSK_TX_POWER_OFFSET_PCS_TOTAL 1
960#endif /*__TX_POWER_OFFSET_SUPPORT__*/
961
962#if defined(__RX_POWER_OFFSET_SUPPORT__)
963/**
964 * L1 RX power offset parameter
965 */
966#define NVRAM_EF_L1_2G_RF_RX_PARAMETER_EXT_SIZE sizeof(l1_2g_rf_rx_parameter_ext_t)
967#define NVRAM_EF_L1_2G_RF_RX_PARAMETER_EXT_TOTAL 1
968
969/**
970 * L1 AGC Path Loss Offset
971 */
972#define NVRAM_EF_L1_AGCPATHLOSS_OFFSET_SIZE sizeof(l1cal_agclnaPathLoss_T)
973#define NVRAM_EF_L1_AGCPATHLOSS_OFFSET_TOTAL 1
974
975#endif/*__RX_POWER_OFFSET_SUPPORT__*/
976
977#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
978/**
979 * L1 LNA Path Loss RXD
980 */
981#define NVRAM_EF_L1_LNAPATHLOSS_RXD_SIZE sizeof(l1cal_lnaPathLoss_T)
982#define NVRAM_EF_L1_LNAPATHLOSS_RXD_TOTAL 1
983
984/**
985 * L1 AGC Path Loss RXD
986 */
987#define NVRAM_EF_L1_AGCPATHLOSS_RXD_SIZE sizeof(l1cal_agcPathLoss_T)
988#define NVRAM_EF_L1_AGCPATHLOSS_RXD_TOTAL 1
989
990/**
991 * L1 AGC Path Loss Offset RXD
992 */
993#define NVRAM_EF_L1_AGCPATHLOSS_OFFSET_RXD_SIZE sizeof(l1cal_agclnaPathLoss_T)
994#define NVRAM_EF_L1_AGCPATHLOSS_OFFSET_RXD_TOTAL 1
995
996/**
997 * L1 Wcoef RXD
998 */
999#define NVRAM_EF_L1_WCOEF_RXD_SIZE sizeof(l1cal_wcoef_T)
1000#define NVRAM_EF_L1_WCOEF_RXD_TOTAL 1
1001
1002/**
1003 * L1 RXD Custom Setting
1004 */
1005#define NVRAM_EF_L1_RAS_CUSTOM_PARAMES_SIZE sizeof(L1D_CUSTOM_RAS_NVRAM_T)
1006#define NVRAM_EF_L1_RAS_CUSTOM_PARAMES_TOTAL 1
1007#endif
1008
1009#if IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT //defined(__DYNAMIC_ANTENNA_TUNING__)
1010/**
1011 * L1 DAT CUSTOM PDATA
1012 */
1013#define NVRAM_EF_L1_DAT_CUSTOM_FE_ROUTE_PARAMES_SIZE sizeof(l1_dat_custom_fe_route_params_T)
1014#define NVRAM_EF_L1_DAT_CUSTOM_FE_ROUTE_PARAMES_TOTAL 1
1015 #if defined(__MD93__)
1016#define NVRAM_EF_L1_DAT_CUSTOM_FE_CAT_A_PARAMES_SIZE sizeof(l1_dat_custom_fe_cata_params_T)
1017#define NVRAM_EF_L1_DAT_CUSTOM_FE_CAT_A_PARAMES_TOTAL 1
1018
1019#define NVRAM_EF_L1_DAT_CUSTOM_FE_CAT_B_PARAMES_SIZE sizeof(l1_dat_custom_fe_catb_params_T)
1020#define NVRAM_EF_L1_DAT_CUSTOM_FE_CAT_B_PARAMES_TOTAL 1
1021 #endif
1022#endif /*__DYNAMIC_ANTENNA_TUNING__*/
1023
1024#if defined(__ANT_RXPWR_OFFSET_SUPPORT__)
1025/**
1026 * L1 Antenna Rx Power Offset
1027 */
1028#define NVRAM_EF_L1_ANT_RXPWR_OFFSET_SIZE sizeof(sL1D_ANT_RxPWR_Offset_T)
1029#define NVRAM_EF_L1_ANT_RXPWR_OFFSET_TOTAL 1
1030#endif
1031
1032#if defined (__NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__)
1033/**
1034 * L1 NSFT adjust tx power offset parameter
1035 */
1036
1037/**
1038 * L1 GMSK NSFT adjust tx power offset data for GSM850
1039 */
1040#define NVRAM_EF_L1_GMSK_ADJUST_TPO_GSM850_SIZE sizeof(nsft_adjust_tpo_t)
1041#define NVRAM_EF_L1_GMSK_ADJUST_TPO_GSM850_TOTAL 1
1042
1043/**
1044 * L1 GMSK NSFT adjust tx power offset data for GSM900
1045 */
1046#define NVRAM_EF_L1_GMSK_ADJUST_TPO_GSM900_SIZE sizeof(nsft_adjust_tpo_t)
1047#define NVRAM_EF_L1_GMSK_ADJUST_TPO_GSM900_TOTAL 1
1048
1049/**
1050 * L1 GMSK NSFT adjust tx power offset data for DCS
1051 */
1052#define NVRAM_EF_L1_GMSK_ADJUST_TPO_DCS_SIZE sizeof(nsft_adjust_tpo_t)
1053#define NVRAM_EF_L1_GMSK_ADJUST_TPO_DCS_TOTAL 1
1054
1055/**
1056 * L1 GMSK NSFT adjust tx power offset data for PCS
1057 */
1058#define NVRAM_EF_L1_GMSK_ADJUST_TPO_PCS_SIZE sizeof(nsft_adjust_tpo_t)
1059#define NVRAM_EF_L1_GMSK_ADJUST_TPO_PCS_TOTAL 1
1060
1061 #if defined(__EPSK_ADJUST_TPO_SUPPORT__)
1062/**
1063 * L1 EPSK NSFT adjust tx power offset data for GSM850
1064 */
1065#define NVRAM_EF_L1_EPSK_ADJUST_TPO_GSM850_SIZE sizeof(nsft_adjust_tpo_t)
1066#define NVRAM_EF_L1_EPSK_ADJUST_TPO_GSM850_TOTAL 1
1067
1068/**
1069 * L1 EPSK NSFT adjust tx power offset data for GSM900
1070 */
1071#define NVRAM_EF_L1_EPSK_ADJUST_TPO_GSM900_SIZE sizeof(nsft_adjust_tpo_t)
1072#define NVRAM_EF_L1_EPSK_ADJUST_TPO_GSM900_TOTAL 1
1073
1074/**
1075 * L1 EPSK NSFT adjust tx power offset data for DCS
1076 */
1077#define NVRAM_EF_L1_EPSK_ADJUST_TPO_DCS_SIZE sizeof(nsft_adjust_tpo_t)
1078#define NVRAM_EF_L1_EPSK_ADJUST_TPO_DCS_TOTAL 1
1079
1080/**
1081 * L1 EPSK NSFT adjust tx power offset data for PCS
1082 */
1083#define NVRAM_EF_L1_EPSK_ADJUST_TPO_PCS_SIZE sizeof(nsft_adjust_tpo_t)
1084#define NVRAM_EF_L1_EPSK_ADJUST_TPO_PCS_TOTAL 1
1085 #endif//__EPSK_ADJUST_TPO_SUPPORT__
1086#endif /* __NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__*/
1087
1088/**
1089 * L1 RF RF Calibration data
1090 */
1091#if defined(__MD97__)
1092#else
1093#define NVRAM_EF_L1_RFC_LID_SIZE sizeof(l1cal_mmrfc_result_T)
1094#define NVRAM_EF_L1_RFC_LID_TOTAL 1
1095#endif
1096
1097#if defined(__TAS_SUPPORT__)
1098/**
1099 * L1 TAS CUSTOM PARAMS
1100 */
1101#define NVRAM_EF_L1_TAS_CUSTOM_PARAMES_SIZE sizeof(L1D_CUSTOM_TAS_NVRAM_T)
1102#define NVRAM_EF_L1_TAS_CUSTOM_PARAMES_TOTAL 1
1103/**
1104 * L1 TAS CUSTOM FE PARAMS
1105 */
1106 #if (defined(__MD93__) || defined(__MD95__)) /*Not supported for Gen97*/
1107#define NVRAM_EF_L1_TAS_CUSTOM_FE_PARAMS_SIZE sizeof(L1D_CUSTOM_TAS_FE_NVRAM_T)
1108#define NVRAM_EF_L1_TAS_CUSTOM_FE_PARAMS_TOTAL 1
1109 #endif
1110/**
1111 * L1_TAS_CUSTOM_INHERIT_LTE_BAND
1112 */
1113 #if defined(__MD93__) /*GL1D is not involved from Gen95 onwards since GL1C is taking care of it*/
1114#define NVRAM_EF_L1_TAS_CUSTOM_INHERIT_LTE_BAND_SIZE sizeof(L1D_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_T)
1115#define NVRAM_EF_L1_TAS_CUSTOM_INHERIT_LTE_BAND_TOTAL 1
1116 #endif
1117#endif /*__TAS_SUPPORT__*/
1118
1119#if (defined(__MD93__) || defined(__MD95__)) && defined(__2G_MIPI_SUPPORT__)
1120/**
1121 * L1 MIPI CTRL tatble data gsm850
1122 */
1123#define NVRAM_EF_L1_MIPI_CTRL_TABLE_GSM850_SIZE sizeof(l1cal_mipi_ctrl_table_band_T)
1124#define NVRAM_EF_L1_MIPI_CTRL_TABLE_GSM850_TOTAL 1
1125/**
1126 * L1 MIPI CTRL tatble data gsm850
1127 */
1128#define NVRAM_EF_L1_MIPI_CTRL_TABLE_GSM900_SIZE sizeof(l1cal_mipi_ctrl_table_band_T)
1129#define NVRAM_EF_L1_MIPI_CTRL_TABLE_GSM900_TOTAL 1
1130/**
1131 * L1 MIPI CTRL tatble data gsm850
1132 */
1133#define NVRAM_EF_L1_MIPI_CTRL_TABLE_DCS1800_SIZE sizeof(l1cal_mipi_ctrl_table_band_T)
1134#define NVRAM_EF_L1_MIPI_CTRL_TABLE_DCS1800_TOTAL 1
1135/**
1136 * L1 MIPI CTRL tatble data gsm850
1137 */
1138#define NVRAM_EF_L1_MIPI_CTRL_TABLE_PCS1900_SIZE sizeof(l1cal_mipi_ctrl_table_band_T)
1139#define NVRAM_EF_L1_MIPI_CTRL_TABLE_PCS1900_TOTAL 1
1140#endif
1141
1142/* L1 Dynamic Radio-setting Dedicated Image (DRDI) */
1143#define NVRAM_EF_L1_CUSTOM_BAND_SUPPORT_SIZE (sizeof(l1cal_l1CustomBandSupport_T))
1144#define NVRAM_EF_L1_CUSTOM_BAND_SUPPORT_TOTAL 1
1145
1146/**
1147 * L1 Inter-slot ramp table Calibration data for GSM 850
1148 */
1149#define NVRAM_EF_L1_INTERSLOT_RAMP_GSM850_SIZE sizeof(l1cal_interRampData_T)
1150#define NVRAM_EF_L1_INTERSLOT_RAMP_GSM850_TOTAL 1
1151
1152/**
1153 * L1 Inter-slot ramp table Calibration data for GSM 900
1154 */
1155#define NVRAM_EF_L1_INTERSLOT_RAMP_GSM900_SIZE sizeof(l1cal_interRampData_T)
1156#define NVRAM_EF_L1_INTERSLOT_RAMP_GSM900_TOTAL 1
1157
1158/**
1159 * L1 Inter-slot ramp table Calibration data for DCS 1800
1160 */
1161#define NVRAM_EF_L1_INTERSLOT_RAMP_DCS1800_SIZE sizeof(l1cal_interRampData_T)
1162#define NVRAM_EF_L1_INTERSLOT_RAMP_DCS1800_TOTAL 1
1163
1164/**
1165 * L1 Inter-slot ramp table Calibration data for PCS 1900
1166 */
1167#define NVRAM_EF_L1_INTERSLOT_RAMP_PCS1900_SIZE sizeof(l1cal_interRampData_T)
1168#define NVRAM_EF_L1_INTERSLOT_RAMP_PCS1900_TOTAL 1
1169
1170#if defined(__EPSK_TX__)
1171/**********************************************************************************/
1172/**
1173 * L1 EPSK Inter-slot ramp table Calibration data for GSM 850
1174 */
1175#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_GSM850_SIZE sizeof(l1cal_EPSK_interRampData_T)
1176#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_GSM850_TOTAL 1
1177
1178/**
1179 * L1 EPSK Inter-slot ramp table Calibration data for GSM 900
1180 */
1181#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_GSM900_SIZE sizeof(l1cal_EPSK_interRampData_T)
1182#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_GSM900_TOTAL 1
1183
1184/**
1185 * L1 EPSK Inter-slot ramp table Calibration data for DCS 1800
1186 */
1187#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_DCS1800_SIZE sizeof(l1cal_EPSK_interRampData_T)
1188#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_DCS1800_TOTAL 1
1189
1190/**
1191 * L1 EPSK Inter-slot ramp table Calibration data for PCS 1900
1192 */
1193#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_PCS1900_SIZE sizeof(l1cal_EPSK_interRampData_T)
1194#define NVRAM_EF_L1_EPSK_INTERSLOT_RAMP_PCS1900_TOTAL 1
1195
1196#endif /* defined(__EPSK_TX__) */
1197
1198#if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__)
1199#define NVRAM_EF_L1_SAR_TX_BACKOFF_DB_CUSTOM_PARAMES_SIZE sizeof(L1D_CUSTOM_SAR_TX_BACKOFF_DB_NVRAM_T)
1200#define NVRAM_EF_L1_SAR_TX_BACKOFF_DB_CUSTOM_PARAMES_TOTAL 1
1201#endif
1202
1203#ifdef __cplusplus
1204}
1205#endif
1206
1207#endif /* __L1_NVRAM_DEF_H__ */