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192.168.1.100 / T800_MD / 6c1fd8fba87d5723e0e5614ae30b4258b603cb70 / . / mcu / service / sst / include / SST_intrCtrl.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame^]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * SST_intrCtrl.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * Header file for non-release version of interrupt control.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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328 *============================================================================
329 ****************************************************************************/
330#ifndef __SST_INTRCTRL_H__
331#define __SST_INTRCTRL_H__
332
333#include "us_timer.h"
334#include "reg_base.h"
335
336#if defined(__MD93__)
337 #if !defined(__FPGA__)
338 #define __QBIT_TIME_CHECK__ // use Qbit for timing check, else use microsecond
339 #define __HARD_REAL_TIME_CHECK__ //SW timing check
340 //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
341 //#define __DEADLOCK_DETECTION__
342 //#define __HARD_REAL_TIME_CHECK_LOG_LEVEL__
343 #else /* else of !defined(__FPGA__)*/
344 #define __QBIT_TIME_CHECK__ // use Qbit for timing check, else use microsecond
345 //#define __HARD_REAL_TIME_CHECK__ //SW timing check
346 //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
347 //#define __DEADLOCK_DETECTION__
348 #endif
349#elif defined(__MD95__) /* else if of defined(__MD93__)*/
350 #if !defined(__FPGA__)
351 #define __HARD_REAL_TIME_CHECK__ //SW timing check
352 //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
353 //#define __DEADLOCK_DETECTION__
354 //#define __HARD_REAL_TIME_CHECK_LOG_LEVEL__
355 #else /* else of !defined(__FPGA__)*/
356 //#define __HARD_REAL_TIME_CHECK__ //SW timing check
357 //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
358 //#define __DEADLOCK_DETECTION__
359 #endif
360#elif defined(__MD97__) /* else if of defined(__MD95__)*/
361 #if !defined(__FPGA__)
362 #define __HARD_REAL_TIME_CHECK__ //SW timing check
363 //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
364 //#define __DEADLOCK_DETECTION__
365 //#define __HARD_REAL_TIME_CHECK_LOG_LEVEL__
366 #else /* else of !defined(__FPGA__)*/
367 //#define __HARD_REAL_TIME_CHECK__ //SW timing check
368 //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
369 //#define __DEADLOCK_DETECTION__
370 #endif
371#elif defined(__MD97P__) /* else if of defined(__MD97__)*/
372 #if !defined(__FPGA__)
373 #define __HARD_REAL_TIME_CHECK__ //SW timing check
374 //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
375 //#define __DEADLOCK_DETECTION__
376 //#define __HARD_REAL_TIME_CHECK_LOG_LEVEL__
377 #else /* else of !defined(__FPGA__)*/
378 #define __HARD_REAL_TIME_CHECK__ //SW timing check
379 //#define __MDCIRQ_TIMING_CHECK_EN__ //HW timing check
380 //#define __DEADLOCK_DETECTION__
381 #endif
382#else /* else of defined(__MD93__)*/
383 #error "no chip definition match"
384#endif
385
386#if defined(__DEADLOCK_DETECTION__) && defined(__MDCIRQ_TIMING_CHECK_EN__)
387#error "deadlock detection and HW timing check cannot use together"
388#endif
389#if defined(__MDCIRQ_TIMING_CHECK_EN__) && !defined(__HARD_REAL_TIME_CHECK__)
390#error "We also need SW timing check for normal domain calling ITC APIs although HW timing check is enable"
391#endif
392
393
394#if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__) && !defined(__HARD_REAL_TIME_CHECK__)
395#error "Qbits check is not enable!! Qbits check fail logging cannot enable standalone!!"
396#endif
397
398
399#if defined(__MD93__)
400 #define SST_HR_DUR_HRT (45)
401 #define SST_HR_DUR_NON_HRT (1000)
402 #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
403 #define SST_HR_DUR_HRT_LOG (55)
404 #endif
405#elif defined(__MD95__) /* else if of defined(__MD93__)*/
406#if defined (__KTEST__)
407 #define SST_HR_DUR_HRT (20000000)
408 #define SST_HR_DUR_NON_HRT (20000000)
409 #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
410 #define SST_HR_DUR_HRT_LOG (20000000)
411 #endif
412#else
413 #define SST_HR_DUR_HRT (50)
414 #define SST_HR_DUR_NON_HRT (1000)
415 #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
416 #define SST_HR_DUR_HRT_LOG (50)
417 #endif
418#endif // #if defined (__KTEST__)
419#elif defined(__MD97__) /* else if of defined(__MD95__)*/
420#if defined (__KTEST__)
421 #define SST_HR_DUR_HRT (200000000)
422 #define SST_HR_DUR_NON_HRT (200000000)
423 #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
424 #define SST_HR_DUR_HRT_LOG (200000000)
425 #endif
426#else
427 #define SST_HR_DUR_HRT (80)
428 #define SST_HR_DUR_NON_HRT (1000)
429 #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
430 #define SST_HR_DUR_HRT_LOG (80)
431 #endif
432#endif // #if defined (__KTEST__)
433#elif defined(__MD97P__) /* else if of defined(__MD97__)*/
434#if defined (__KTEST__)
435 #define SST_HR_DUR_HRT (200000000)
436 #define SST_HR_DUR_NON_HRT (200000000)
437 #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
438 #define SST_HR_DUR_HRT_LOG (200000000)
439 #endif
440#else
441 #define SST_HR_DUR_HRT (60)
442 #define SST_HR_DUR_NON_HRT (1000)
443 #if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
444 #define SST_HR_DUR_HRT_LOG (200)
445 #endif
446#endif // #if defined (__KTEST__)
447#else /* else of defined(__MD93__)*/
448 #error "no chip definition match"
449#endif
450
451#if defined(__FPGA__)
452#define SST_HR_DUR_HRT_WD (2000*1000)
453#define SST_HR_DUR_NON_HRT_WD (2000*1000)
454#else
455#define SST_HR_DUR_HRT_WD (2000)
456#define SST_HR_DUR_NON_HRT_WD (2000)
457
458#endif
459
460#define SST_IRQ_MASK (0x00000001)
461
462#if defined(__HW_US_TIMER_SUPPORT__) /* !__CR4__ */
463
464#define GET_AND_SAVED_TIME(v, vpe_num) do{\
465 IRQMaskCounter[vpe_num] = ust_get_current_time();\
466 IRQMaskValue[vpe_num] = v;\
467 }while(0)
468
469#define GET_AND_SAVED_TIME_HRT(vpe_num) do{\
470 HRTQbitCounter[vpe_num] = ust_get_current_time();\
471 }while(0)
472
473#define GET_CURRENT_TIME(v) do{\
474 v = ust_get_current_time();\
475 }while(0)
476
477#define GET_SAVED_TIME(v,vpe_num) do{\
478 v = IRQMaskCounter[vpe_num];\
479 }while(0)
480
481#define GET_SAVED_TIME_HRT(v,vpe_num) do{\
482 v = HRTQbitCounter[vpe_num];\
483 }while(0)
484
485#define GET_DURATION(d,t1,t2) do{\
486 d = ((t2) >= (t1)) ? ((t2) - (t1)) : (USCNT_WRAP - (t1) + (t2) + 1);\
487 }while(0)
488
489#define TRANS_TO_QBIT(d,s) do{\
490 d = (((s)*13)/12);\
491 }while(0)
492
493#if defined(__FPGA__) && !defined(__KTEST__)
494 /* Check us directly instead of qbits in gen95/gen97 */
495 #if !defined(__QBIT_TIME_CHECK__)
496 #define IRQ_DISABLE_MAX_DURATION_HRT (SST_HR_DUR_HRT*1000)
497 #define IRQ_DISABLE_MAX_DURATION_NON_HRT (SST_HR_DUR_NON_HRT*1000)
498 #else
499 #define IRQ_DISABLE_MAX_DURATION_HRT ((SST_HR_DUR_HRT*12)/13*1000)
500 #define IRQ_DISABLE_MAX_DURATION_NON_HRT ((SST_HR_DUR_NON_HRT*12)/13*1000)
501 #endif
502#else
503 /* Check us directly instead of qbits in gen95/gen97 */
504 #if !defined(__QBIT_TIME_CHECK__)
505 #define IRQ_DISABLE_MAX_DURATION_HRT (SST_HR_DUR_HRT)
506 #define IRQ_DISABLE_MAX_DURATION_NON_HRT (SST_HR_DUR_NON_HRT)
507 #else
508 #define IRQ_DISABLE_MAX_DURATION_HRT ((SST_HR_DUR_HRT*12)/13)
509 #define IRQ_DISABLE_MAX_DURATION_NON_HRT ((SST_HR_DUR_NON_HRT*12)/13)
510 #endif
511#endif
512
513#if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
514 /* Check us directly instead of qbits in gen95/gen97 */
515 #if !defined(__QBIT_TIME_CHECK__)
516 #define IRQ_DISABLE_MAX_DURATION_HRT_LOG (SST_HR_DUR_HRT_LOG)
517 #else
518 #define IRQ_DISABLE_MAX_DURATION_HRT_LOG ((SST_HR_DUR_HRT_LOG*12)/13)
519 #endif
520#endif
521
522#if defined(__HARD_REAL_TIME_CHECK_LOG_LEVEL__)
523typedef struct{
524 kal_uint32 violationAddress;
525 kal_uint32 violationDuration;
526} HRTQbitFailLogStruct;
527#define HRTQbitFailLogSize 32
528#endif
529
530#else /* !__HW_US_TIMER_SUPPORT__ */
531
532#error "No timing check counter support!"
533
534#endif /* __HW_US_TIMER_SUPPORT__ */
535
536kal_uint32 query_Qbits_criteria_nonHRT(void);
537kal_uint32 query_Qbits_criteria_nonHRT_us(void);
538kal_uint32 query_Qbits_criteria_HRT(void);
539kal_uint32 query_Qbits_criteria_HRT_us(void);
540
541#endif /* __SST_INTRCTRL_H__ */