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192.168.1.100 / T800_MD / 6c1fd8fba87d5723e0e5614ae30b4258b603cb70 / . / mcu / service / sst / include / dsp_control.h
blob: f32128db5105120bf5199e406bd1c5ee6b815fa9 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame^]1#ifndef _DSP_CONTROL_H_
2#define _DSP_CONTROL_H_
3
4#if defined(__MD97__) || defined(__MD97P__)
5
6#include "kal_public_api.h"
7#include "dsp_control_public.h"
8#include "dsp_module_based_api_public.h"
9#include "usip_api_public.h"
10#include "rake_api_public.h"
11#include "reg_base.h"
12
13#include "dsp_header_define_cuif_inner_brp.h"
14#include "dsp_header_define_cuif_fec_wbrp.h"
15#include "dsp_header_define_cuif_speech.h"
16#include "dsp_header_define_cmif.h"
17
18/************************************/
19/************* Common ***************/
20/************************************/
21/***** Function Utility *****/
22typedef enum{
23 DSP_CTRL_FALSE,
24 DSP_CTRL_TRUE
25} DSP_CTRL_FALSE_TRUE;
26
27typedef struct{
28 kal_uint32 usip_pc;
29 kal_uint32 usip_status;
30 kal_uint32 usip_tbuf_pointer;
31 kal_uint32 usip_halt;
32} DSP_CTRL_PWR_CHECK_MEMBER;
33
34/***** Pattern Macro *****/
35#define DSP_DEACTIVE_DONE 0x62933926
36#define DSP_DEACTIVE_INIT 0x0
37#define ALL_USER_ARE_DEACTIVE DSP_CTRL_FALSE
38#define DSP_CTRL_ENABLE_CORE_INIT_VALUE 0xECECECEC
39#define DUTY_USER_INIT_PATTERN 0x10101010
40#define FIRSTBOOT_CHECK_CUIF_CONNECT_CNT_PATTERN 0x1F
41#define API_CALL_STATUS_INIT_PATTERN 0x0
42
43// uSIP debug ctrl(SW/HW CLK)
44#define USIP_TH0_PERI_CK_DIS 0x4
45#define USIP_TH0_FORCE_CK_DIS 0xC
46#define USIP_TH0_PERI_CK 0x1
47#define USIP_TH0_FORCE_CK 0xFF
48#define USIP_TH0_PERI_CK_SW_MODE_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_TH0_PERI_CK_DIS)
49#define USIP_TH0_FORCE_CK_SW_MODE_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_TH0_FORCE_CK_DIS)
50
51/***** DCM IDLE MASK*****/
52#define USIP_MASK_L1_DCM_IDLE 0x48
53#define USIP_DCM_MASK 0x793
54#define USIP_DCM_MASK_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_MASK_L1_DCM_IDLE)
55
56/***** HW Signal Access Macro *****/
57#define USIP_STATUS_CG_CHECK_MASK 0x00000001
58#define USIP_STATUS_WAITE_CHECK_MASK 0x000F0000
59#define USIP_STATUS_PWR_CHECK_BIT_OFFSET 0x00000100
60
61// SCq16 PWR CTRL COMMON
62#define BASE_SCQ16_0_CR BASE_MADDR_BRAM_SCQ0_VU_CR
63#define BASE_SCQ16_1_CR BASE_MADDR_BRAM_SCQ1_VU_CR
64#define SCQ16_MD32_WAITE_OFFSET 0x24
65#define SCQ16_CORE_FETCH_OFFSET 0x0
66
67// SCq16_0 PWR CTRL
68#define SCQ16_0_MD32_WAITE_ADDR ((volatile kal_uint32*)(BASE_SCQ16_0_CR + SCQ16_MD32_WAITE_OFFSET))
69#define SCQ16_0_MD32_WAITE *((volatile kal_uint32*)(BASE_SCQ16_0_CR + SCQ16_MD32_WAITE_OFFSET))
70#define SCQ16_0_CORE_FETCH *((volatile kal_uint32*)(BASE_SCQ16_0_CR + SCQ16_CORE_FETCH_OFFSET))
71
72// SCq16_1 PWR CTRL
73#define SCQ16_1_MD32_WAITE_ADDR ((volatile kal_uint32*)(BASE_SCQ16_1_CR + SCQ16_MD32_WAITE_OFFSET))
74#define SCQ16_1_MD32_WAITE *((volatile kal_uint32*)(BASE_SCQ16_1_CR + SCQ16_MD32_WAITE_OFFSET))
75#define SCQ16_1_CORE_FETCH *((volatile kal_uint32*)(BASE_SCQ16_1_CR + SCQ16_CORE_FETCH_OFFSET))
76
77// uSIP PWR CTRL COMMON
78#define USIP_MON_PC_OFFSET 0x20010
79#define USIP_MON_TBUF_WPTR_OFFSET 0x20014
80#define USIP_STATUS_OFFSET 0x20018
81
82// uSIP0 PWR CTRL
83#define USIP0_MON_PC_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_PC_OFFSET))
84#define USIP0_MON_PC *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_PC_OFFSET))
85#define USIP0_PWR_CTRL_CHECK_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_STATUS_OFFSET))
86#define USIP0_PWR_CTRL_CHECK *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_STATUS_OFFSET))
87
88#define USIP0_MON_TBUF_WPTR_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
89#define USIP0_MON_TBUF_WPTR *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
90
91// uSIP1 PWR CTRL
92#define USIP1_MON_PC_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_PC_OFFSET))
93#define USIP1_MON_PC *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_PC_OFFSET))
94#define USIP1_PWR_CTRL_CHECK_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_STATUS_OFFSET))
95#define USIP1_PWR_CTRL_CHECK *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_STATUS_OFFSET))
96
97#define USIP1_MON_TBUF_WPTR_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
98#define USIP1_MON_TBUF_WPTR *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
99
100// RAKE BOOTSLAVE
101#define RAKE_BOOTSLAVE_OFFSET 0xC
102#define RAKE_BOOTSLAVE_ADDR ((volatile kal_uint32*)(BASE_MADDR_RAKESYS_PERICTRL + RAKE_BOOTSLAVE_OFFSET))
103#define RAKE_BOOTSLAVE *((volatile kal_uint32*)(BASE_MADDR_RAKESYS_PERICTRL + RAKE_BOOTSLAVE_OFFSET))
104
105// USIP sram type setting
106
107#define USIP_SRAM_TYPE_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF))
108#define USIP_SRAM_TYPE *((volatile kal_uint32*)(BASE_MADDR_MDPERI_MDSYS_CONFIG_ADR_IF))
109#define USIP_SRAM_TYPE_MASK 0x3
110
111
112//SCQ sram type setting
113#define SCQ_SRAM_TYPE_OFFSET 0x4
114#define SCQ_SRAM_TYPE_ADDR ((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + SCQ_SRAM_TYPE_OFFSET))
115#define SCQ_SRAM_TYPE *((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + SCQ_SRAM_TYPE_OFFSET))
116#define SCQ_SRAM_TYPE_MASK 0x7FF
117
118//RAKE sram type setting
119#define RAKE_SRAM_TYPE_OFFSET 0x10
120#define RAKE_SRAM_TYPE_ADDR ((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + RAKE_SRAM_TYPE_OFFSET))
121#define RAKE_SRAM_TYPE *((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + RAKE_SRAM_TYPE_OFFSET))
122#define RAKE_SRAM_TYPE_MASK 0xFF
123/***** Function Macro *****/
124
125/***** Enum *****/
126typedef enum{
127 DSP_CTRL_ABORT,
128 DSP_CTRL_DORMANT
129} DSP_CTRL_IRQ_TYPE;
130
131typedef enum{
132 DSP_CTRL_ACTIVATE_ACTION = 0x0,
133 DSP_CTRL_ACTIVATE_ACTION_AFTER_HWITC = 0x1,
134 DSP_CTRL_ACTIVATE_CHECK_ACTION = 0x4,
135 DSP_CTRL_DEACTIVATE_ACTION = 0x8,
136 DSP_CTRL_DEACTIVATE_ACTION_AFTER_HWITC = 0x9,
137 DSP_CTRL_DEACTIVATE_CHECK_ACTION = 0xC,
138 DSP_CTRL_ACTION_NUM = 0x4
139} DSP_CTRL_ACTION_CODE;
140
141#define DSP_CTRL_ACTIVATE_ACTION_BIT (1 << DSP_CTRL_ACTIVATE_ACTION)
142#define DSP_CTRL_ACTIVATE_CHECK_ACTION_BIT (1 << DSP_CTRL_ACTIVATE_CHECK_ACTION)
143#define DSP_CTRL_DEACTIVATE_ACTION_BIT (1 << DSP_CTRL_DEACTIVATE_ACTION)
144#define DSP_CTRL_DEACTIVATE_CHECK_ACTION_BIT (1 << DSP_CTRL_DEACTIVATE_CHECK_ACTION)
145
146
147#define USIP_TH0_PERI_CK_EN_OFFSET (0x0)
148#define USIP_TH0_PERI_CK_DIS_OFFSET (0x4)
149#define USIP_TH0_FORCE_CK_EN_OFFSET (0x8)
150#define USIP_TH0_FORCE_CK_DIS_OFFSET (0xC)
151
152
153/************************************/
154/************* uSIP *****************/
155/************************************/
156
157/*****cosim only API****/
158void usip_boot(void);
159void usip_power_aware(void);
160void usip_peripheral_clock_enable(kal_uint32);
161void usip_peripheral_clock_disable(kal_uint32);
162void usip_peripheral_clock_force_enable(kal_uint32);
163void usip_peripheral_clock_force_disable(kal_uint32);
164
165DSP_CONTROL_STATUS usip0_thread0_boot_done_check(void);
166DSP_CONTROL_STATUS usip0_thread1_boot_done_check(void);
167DSP_CONTROL_STATUS usip1_thread0_boot_done_check(void);
168
169void rake_ungate(void);
170DSP_CONTROL_STATUS rake_boot_done_check(void);
171
172
173
174/************************************/
175/************* RAKE *****************/
176/************************************/
177#define RAKE_CMIF_BASE_ADDR BASE_MADDR_RAKESYS_CMIF
178#define RAKE_WFI_MASK_OFFSET 0x4
179
180/***** Common API *****/
181
182
183
184
185/************************************/
186/********* module-based APIs ********/
187/************************************/
188#undef L1_MODULE_REGISTER
189#define L1_MODULE_REGISTER(name, wfi, firmware, cb) extern void cb(void);
190
191 #include "L1_module_registration.h"
192
193#undef L1_MODULE_REGISTER
194
195void usip_activate_by_module(DSP_CDIF_CORE_ENUM, L1_MODULE_REGISTRATION, kal_uint32);
196void rake_activate_by_module(L1_MODULE_REGISTRATION, kal_uint32);
197DSP_CONTROL_STATUS usip_activate_done_check_by_module(DSP_CDIF_CORE_ENUM, L1_MODULE_REGISTRATION);
198DSP_CONTROL_STATUS rake_activate_done_check_by_module(L1_MODULE_REGISTRATION);
199void usip_deactivate_by_module(DSP_CDIF_CORE_ENUM, L1_MODULE_REGISTRATION, kal_uint32);
200void rake_deactivate_by_module(L1_MODULE_REGISTRATION, kal_uint32);
201DSP_CONTROL_STATUS usip_deactivate_done_check_by_module(DSP_CDIF_CORE_ENUM, L1_MODULE_REGISTRATION);
202DSP_CONTROL_STATUS rake_deactivate_done_check_by_module(L1_MODULE_REGISTRATION);
203DSP_CONTROL_IDLE_FLAG_STATUS usip_check_idle_flag_by_module(DSP_CDIF_CORE_ENUM, DSP_FIRMWARE_REGISTRATION);
204DSP_CONTROL_IDLE_FLAG_STATUS rake_check_idle_flag_by_module(DSP_CDIF_CORE_ENUM, DSP_FIRMWARE_REGISTRATION);
205void execute_deactivate_irq_cb(L1_MODULE_REGISTRATION);
206
207void dsp_firstboot_activate_by_module(kal_uint32);
208void dsp_activate_by_module(kal_uint32);
209DSP_CONTROL_STATUS dsp_activate_done_check_by_module(kal_uint32);
210void dsp_deactivate_by_module(kal_uint32);
211DSP_CONTROL_STATUS dsp_deactivate_done_check_by_module(kal_uint32);
212kal_uint32 dsp_check_idle_flag_by_module(kal_uint32);
213kal_uint32 dsp_check_idle_flag_by_firmware(kal_uint32);
214
215#else //defined(__MD97__) || defined(__MD97P__)
216/************************************__MD95__*********************************/
217
218#include "kal_public_api.h"
219#include "dsp_control_public.h"
220#include "usip_api_public.h"
221#include "rake_api_public.h"
222#include "reg_base.h"
223
224#include "dsp_header_define_cuif_inner_brp.h"
225#include "dsp_header_define_cuif_fec_wbrp.h"
226#include "dsp_header_define_cuif_speech.h"
227#include "dsp_header_define_cmif.h"
228
229/************************************/
230/************* Common ***************/
231/************************************/
232/***** Function Utility *****/
233typedef enum{
234 DSP_CTRL_FALSE,
235 DSP_CTRL_TRUE
236} DSP_CTRL_FALSE_TRUE;
237
238typedef struct{
239 kal_uint32 usip_pc;
240 kal_uint32 usip_status;
241 kal_uint32 usip_tbuf_pointer;
242 kal_uint32 usip_halt;
243} DSP_CTRL_PWR_CHECK_MEMBER;
244
245/***** Pattern Macro *****/
246#define DSP_DEACTIVE_DONE 0x62933926
247#define DSP_DEACTIVE_INIT 0x0
248#define ALL_USER_ARE_DEACTIVE DSP_CTRL_FALSE
249#define DSP_CTRL_ENABLE_CORE_INIT_VALUE 0xECECECEC
250#define DUTY_USER_INIT_PATTERN 0x10101010
251#define FIRSTBOOT_CHECK_CUIF_CONNECT_CNT_PATTERN 0x1F
252#define API_CALL_STATUS_INIT_PATTERN 0x0
253
254// uSIP debug ctrl(SW/HW CLK)
255#define USIP_TH0_PERI_CK_DIS 0x4
256#define USIP_TH0_FORCE_CK_DIS 0xC
257#define USIP_TH0_FORCE_CK_EN 0x8
258#define USIP_TH0_PERI_CK 0x1
259#define USIP_TH0_FORCE_CK 0xFF
260#define USIP_DISABLE_ALL_FORCE_ON_CK 0xFFFF
261#define USIP_ENABLE_FORCE_ON_CK 0xFC1C
262#define USIP_TH0_PERI_CK_SW_MODE_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_TH0_PERI_CK_DIS)
263#define USIP_TH0_FORCE_CK_SW_MODE_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_TH0_FORCE_CK_DIS)
264#define USIP_ENABLE_FORCE_ON_CK_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_TH0_FORCE_CK_EN)
265
266/***** DCM IDLE MASK*****/
267#define USIP_MASK_L1_DCM_IDLE 0x48
268#if defined(__MD93__)
269#define USIP_DCM_MASK 0x19f
270#elif defined(__MD95__)
271#define USIP_DCM_MASK 0x193
272#else
273#error "not support chip!! Please porting for it!!"
274#endif
275#define USIP_DCM_MASK_REG *(kal_uint32*)(BASE_MADDR_USIP_CONFG + USIP_MASK_L1_DCM_IDLE)
276
277/***** HW Signal Access Macro *****/
278#define USIP_STATUS_CG_CHECK_MASK 0x00000001
279#define USIP_STATUS_WAITE_CHECK_MASK 0x000F0000
280#define USIP_STATUS_PWR_CHECK_BIT_OFFSET 0x00000100
281
282// SCq16 PWR CTRL COMMON
283#define BASE_SCQ16_0_CR BASE_MADDR_BRAM_SCQ0_VU_CR
284#define BASE_SCQ16_1_CR BASE_MADDR_BRAM_SCQ1_VU_CR
285#define SCQ16_MD32_WAITE_OFFSET 0x24
286#define SCQ16_CORE_FETCH_OFFSET 0x0
287
288// SCq16_0 PWR CTRL
289#define SCQ16_0_MD32_WAITE_ADDR ((volatile kal_uint32*)(BASE_SCQ16_0_CR + SCQ16_MD32_WAITE_OFFSET))
290#define SCQ16_0_MD32_WAITE *((volatile kal_uint32*)(BASE_SCQ16_0_CR + SCQ16_MD32_WAITE_OFFSET))
291#define SCQ16_0_CORE_FETCH *((volatile kal_uint32*)(BASE_SCQ16_0_CR + SCQ16_CORE_FETCH_OFFSET))
292
293// SCq16_1 PWR CTRL
294#define SCQ16_1_MD32_WAITE_ADDR ((volatile kal_uint32*)(BASE_SCQ16_1_CR + SCQ16_MD32_WAITE_OFFSET))
295#define SCQ16_1_MD32_WAITE *((volatile kal_uint32*)(BASE_SCQ16_1_CR + SCQ16_MD32_WAITE_OFFSET))
296#define SCQ16_1_CORE_FETCH *((volatile kal_uint32*)(BASE_SCQ16_1_CR + SCQ16_CORE_FETCH_OFFSET))
297
298// uSIP PWR CTRL COMMON
299#define USIP_MON_PC_OFFSET 0x20010
300#define USIP_MON_TBUF_WPTR_OFFSET 0x20014
301#define USIP_STATUS_OFFSET 0x20018
302
303// uSIP0 PWR CTRL
304#define USIP0_MON_PC_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_PC_OFFSET))
305#define USIP0_MON_PC *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_PC_OFFSET))
306#define USIP0_PWR_CTRL_CHECK_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_STATUS_OFFSET))
307#define USIP0_PWR_CTRL_CHECK *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_STATUS_OFFSET))
308
309#define USIP0_MON_TBUF_WPTR_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
310#define USIP0_MON_TBUF_WPTR *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
311
312// uSIP1 PWR CTRL
313#define USIP1_MON_PC_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_PC_OFFSET))
314#define USIP1_MON_PC *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_PC_OFFSET))
315#define USIP1_PWR_CTRL_CHECK_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_STATUS_OFFSET))
316#define USIP1_PWR_CTRL_CHECK *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_STATUS_OFFSET))
317
318#define USIP1_MON_TBUF_WPTR_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
319#define USIP1_MON_TBUF_WPTR *((volatile kal_uint32*)(BASE_MADDR_MDMCU_USIP1_INT_DBG + USIP_MON_TBUF_WPTR_OFFSET))
320
321// RAKE BOOTSLAVE
322#define RAKE_BOOTSLAVE_OFFSET 0xC
323#define RAKE_BOOTSLAVE_ADDR ((volatile kal_uint32*)(BASE_MADDR_RAKESYS_PERICTRL + RAKE_BOOTSLAVE_OFFSET))
324#define RAKE_BOOTSLAVE *((volatile kal_uint32*)(BASE_MADDR_RAKESYS_PERICTRL + RAKE_BOOTSLAVE_OFFSET))
325
326// USIP sram type setting
327#define USIP_SRAM_TYPE_ADDR ((volatile kal_uint32*)(BASE_MADDR_MDPERI_USIP0_MEM_CONFIG))
328#define USIP_SRAM_TYPE *((volatile kal_uint32*)(BASE_MADDR_MDPERI_USIP0_MEM_CONFIG))
329#define USIP_SRAM_TYPE_MASK 0x3
330
331//SCQ sram type setting
332#define SCQ_SRAM_TYPE_OFFSET 0x4
333#define SCQ_SRAM_TYPE_ADDR ((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + SCQ_SRAM_TYPE_OFFSET))
334#define SCQ_SRAM_TYPE *((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + SCQ_SRAM_TYPE_OFFSET))
335#define SCQ_SRAM_TYPE_MASK 0x7FF
336
337//RAKE sram type setting
338#define RAKE_SRAM_TYPE_OFFSET 0x10
339#define RAKE_SRAM_TYPE_ADDR ((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + RAKE_SRAM_TYPE_OFFSET))
340#define RAKE_SRAM_TYPE *((volatile kal_uint32*)(BASE_MADDR_MODEML1_AO_MDRX_P2P_TX + RAKE_SRAM_TYPE_OFFSET))
341#define RAKE_SRAM_TYPE_MASK 0xFF
342/***** Function Macro *****/
343
344/***** Enum *****/
345typedef enum{
346 DSP_CTRL_ABORT,
347 DSP_CTRL_DORMANT
348} DSP_CTRL_IRQ_TYPE;
349
350typedef enum{
351 DSP_CTRL_ACTIVATE_ACTION = 0x0,
352 DSP_CTRL_ACTIVATE_ACTION_AFTER_HWITC = 0x1,
353 DSP_CTRL_ACTIVATE_CHECK_ACTION = 0x4,
354 DSP_CTRL_DEACTIVATE_ACTION = 0x8,
355 DSP_CTRL_DEACTIVATE_ACTION_AFTER_HWITC = 0x9,
356 DSP_CTRL_DEACTIVATE_CHECK_ACTION = 0xC,
357 DSP_CTRL_ACTION_NUM = 0x4
358} DSP_CTRL_ACTION_CODE;
359
360#define DSP_CTRL_ACTIVATE_ACTION_BIT (1 << DSP_CTRL_ACTIVATE_ACTION)
361#define DSP_CTRL_ACTIVATE_CHECK_ACTION_BIT (1 << DSP_CTRL_ACTIVATE_CHECK_ACTION)
362#define DSP_CTRL_DEACTIVATE_ACTION_BIT (1 << DSP_CTRL_DEACTIVATE_ACTION)
363#define DSP_CTRL_DEACTIVATE_CHECK_ACTION_BIT (1 << DSP_CTRL_DEACTIVATE_CHECK_ACTION)
364
365/************************************/
366/************* uSIP *****************/
367/************************************/
368
369/***** Common API *****/
370DSP_CONTROL_IDLE_FLAG_STATUS usip_check_idle_flag(DSP_CDIF_CORE_ENUM, kal_uint32);
371
372/***** Activate Relatives *****/
373void usip_activate(DSP_CDIF_CORE_ENUM, kal_uint32);
374
375/***** Deactivate Relatives *****/
376void usip_deactivate(DSP_CDIF_CORE_ENUM, kal_uint32);
377USIP_CONTROL_STATUS usip_deactive_done_check(DSP_CDIF_CORE_ENUM, kal_uint32);
378
379
380/************************************/
381/************* RAKE *****************/
382/************************************/
383#define RAKE_CMIF_BASE_ADDR BASE_MADDR_RAKESYS_CMIF
384#define RAKE_WFI_MASK_OFFSET 0x4
385
386/***** Common API *****/
387DSP_CONTROL_IDLE_FLAG_STATUS rake_check_idle_flag(RAKE_API_USER);
388
389/***** Activate Relatives *****/
390void rake_activate(RAKE_API_USER);
391
392/***** Deactivate Relatives *****/
393void rake_deactivate(RAKE_API_USER, CMIFZI_CTRL);
394RAKE_CONTROL_STATUS rake_deactive_done_check(RAKE_API_USER);
395
396/* Check Boot Done API*/
397RAKE_BOOTDONECHECK_RETVALUE RAKE_BootDoneCheck(RAKE_API_USER);
398
399#endif //defined(__MD97__) || defined(__MD97P__)
400#endif
401