| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame^] | 1 | #ifndef _SST_DEFS_H |
| 2 | #define _SST_DEFS_H |
| 3 | |
| 4 | #include "reg_base.h" |
| 5 | #include <ex_mem_manager.h> |
| 6 | |
| 7 | #define EX_STACK_SIZE (8*1024) |
| 8 | #define EX_DOR_EXCP_AREA_SIZE_PER_VPE (4*8) /*sizeof(EX_CPU_MIN_REG_T)*/ |
| 9 | |
| 10 | |
| 11 | #if defined(BASE_MADDR_PCCIF0_MD) |
| 12 | #define BASE_MADDR_CCIF0_MD_REG_BASE BASE_MADDR_PCCIF0_MD |
| 13 | #elif defined(BASE_MADDR_CCIF0_MD) |
| 14 | #define BASE_MADDR_CCIF0_MD_REG_BASE BASE_MADDR_CCIF0_MD |
| 15 | #else |
| 16 | //TO FIX: #error "no ccif base define!!" __MD97__ |
| 17 | #define BASE_MADDR_CCIF0_MD_REG_BASE 0x0 |
| 18 | #endif |
| 19 | |
| 20 | //information from ccif owner: 0x100-> CCIF SRAM offset, 512-> SRAM size, 72-> last 72 bytes reserved for bootup trace |
| 21 | #define MDCCIF_BOOTTRC_DATA (BASE_MADDR_CCIF0_MD_REG_BASE + 0x100 + 512 - 72) |
| 22 | |
| 23 | #define g_EMM_MAIN_BUFF_MAGIC_ADDR (MDCCIF_BOOTTRC_DATA + 0x4*15) |
| 24 | #define g_EMM_MAIN_BUFF_MAGIC 0x7274626E |
| 25 | |
| 26 | #define g_EMM_MAIN_BUFF_ADDR_PTR (MDCCIF_BOOTTRC_DATA + 0x4*16) |
| 27 | #define g_EMM_MAIN_BUFF_SIZE_PTR (MDCCIF_BOOTTRC_DATA + 0x4*17) |
| 28 | |
| 29 | #define HS1_BOOT_TRACE_OFFSET EMM_EXRECORD_LEN |
| 30 | #endif /* _SST_DEFS_H */ |