| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | #ifndef __REG_BASE_ESL_H__ |
| 2 | #define __REG_BASE_ESL_H__ |
| 3 | |
| 4 | #if defined(MT6763) || defined(__MD97__) |
| 5 | #if defined(__MD97__) |
| 6 | #define ESL_REG_BANK 0xD0000000 |
| 7 | #endif |
| 8 | |
| 9 | #undef BASE_ADDR_MDCIRQ |
| 10 | #undef BASE_MADDR_MDCIRQ |
| 11 | |
| 12 | #undef BASE_NADDR_MML2_QP_APB |
| 13 | #undef BASE_NADDR_MML2_QP_MEM |
| 14 | #undef BASE_NADDR_MML2_META_APB |
| 15 | #undef BASE_NADDR_MML2_META_MEM |
| 16 | #undef BASE_NADDR_MML2_VRB_MANAGER |
| 17 | #undef BASE_NADDR_MML2_MMU |
| 18 | #undef BASE_NADDR_MML2_DMA_RD |
| 19 | #undef BASE_NADDR_MML2_DMA_WR |
| 20 | #undef BASE_NADDR_MML2_LHIF |
| 21 | #undef BASE_NADDR_MML2_CIPHER |
| 22 | #undef BASE_NADDR_MML2_DL_LMAC |
| 23 | #undef BASE_NADDR_MML2_HARQ_CTRL |
| 24 | #undef BASE_NADDR_MML2_SRAM_WRAP |
| 25 | #undef BASE_NADDR_MML2_CFG_TOP |
| 26 | #undef BASE_NADDR_MML2_BYC |
| 27 | #undef BASE_MADDR_MML2_QP_APB |
| 28 | #undef BASE_MADDR_MML2_QP_MEM |
| 29 | #undef BASE_MADDR_MML2_META_APB |
| 30 | #undef BASE_MADDR_MML2_META_MEM |
| 31 | #undef BASE_MADDR_MML2_VRB_MANAGER |
| 32 | #undef BASE_MADDR_MML2_MMU |
| 33 | #undef BASE_MADDR_MML2_DMA_RD |
| 34 | #undef BASE_MADDR_MML2_DMA_WR |
| 35 | #undef BASE_MADDR_MML2_LHIF |
| 36 | #undef BASE_MADDR_MML2_CIPHER |
| 37 | #undef BASE_MADDR_MML2_DL_LMAC |
| 38 | #undef BASE_MADDR_MML2_HARQ_CTRL |
| 39 | #undef BASE_MADDR_MML2_SRAM_WRAP |
| 40 | #undef BASE_MADDR_MML2_CFG_TOP |
| 41 | #undef BASE_MADDR_MML2_BYC |
| 42 | |
| 43 | #define BASE_ADDR_MDCIRQ (ESL_REG_BANK + 0x7000000) |
| 44 | #define BASE_MADDR_MDCIRQ (ESL_REG_BANK + 0x7000000) |
| 45 | |
| 46 | #define BASE_USCOUNTER (ESL_REG_BANK + 0x1000000) |
| 47 | #define BASE_GLOBAL_TS (ESL_REG_BANK + 0x1000010) |
| 48 | |
| 49 | #define BASE_MADDR_MML2_QP_APB (ESL_REG_BANK + 0x0600000) |
| 50 | #define BASE_MADDR_MML2_QP_MEM (ESL_REG_BANK + 0x0600800) |
| 51 | #define BASE_MADDR_MML2_META_APB (ESL_REG_BANK + 0x0601000) |
| 52 | #define BASE_MADDR_MML2_META_MEM (ESL_REG_BANK + 0x0601800) |
| 53 | #define BASE_MADDR_MML2_VRB_MANAGER (ESL_REG_BANK + 0x0602000) |
| 54 | #define BASE_MADDR_MML2_MMU (ESL_REG_BANK + 0x0603000) |
| 55 | #define BASE_MADDR_MML2_DMA_RD (ESL_REG_BANK + 0x0604000) |
| 56 | #define BASE_MADDR_MML2_DMA_WR (ESL_REG_BANK + 0x0605000) |
| 57 | #define BASE_MADDR_MML2_LHIF (ESL_REG_BANK + 0x0606000) |
| 58 | #define BASE_MADDR_MML2_CIPHER (ESL_REG_BANK + 0x0607000) |
| 59 | #define BASE_MADDR_MML2_DL_LMAC (ESL_REG_BANK + 0x0608000) |
| 60 | #define BASE_MADDR_MML2_HARQ_CTRL (ESL_REG_BANK + 0x0609000) |
| 61 | #define BASE_MADDR_MML2_SRAM_WRAP (ESL_REG_BANK + 0x060A000) |
| 62 | #define BASE_MADDR_MML2_CFG_TOP (ESL_REG_BANK + 0x060B000) |
| 63 | #define BASE_MADDR_MML2_BYC (ESL_REG_BANK + 0x060C000) |
| 64 | |
| 65 | #define BASE_NADDR_MML2_QP_APB BASE_MADDR_MML2_QP_APB |
| 66 | #define BASE_NADDR_MML2_QP_MEM BASE_MADDR_MML2_QP_MEM |
| 67 | #define BASE_NADDR_MML2_META_APB BASE_MADDR_MML2_META_APB |
| 68 | #define BASE_NADDR_MML2_META_MEM BASE_MADDR_MML2_META_MEM |
| 69 | #define BASE_NADDR_MML2_VRB_MANAGER BASE_MADDR_MML2_VRB_MANAGER |
| 70 | #define BASE_NADDR_MML2_MMU BASE_MADDR_MML2_MMU |
| 71 | #define BASE_NADDR_MML2_DMA_RD BASE_MADDR_MML2_DMA_RD |
| 72 | #define BASE_NADDR_MML2_DMA_WR BASE_MADDR_MML2_DMA_WR |
| 73 | #define BASE_NADDR_MML2_LHIF BASE_MADDR_MML2_LHIF |
| 74 | #define BASE_NADDR_MML2_CIPHER BASE_MADDR_MML2_CIPHER |
| 75 | #define BASE_NADDR_MML2_DL_LMAC BASE_MADDR_MML2_DL_LMAC |
| 76 | #define BASE_NADDR_MML2_HARQ_CTRL BASE_MADDR_MML2_HARQ_CTRL |
| 77 | #define BASE_NADDR_MML2_SRAM_WRAP BASE_MADDR_MML2_SRAM_WRAP |
| 78 | #define BASE_NADDR_MML2_CFG_TOP BASE_MADDR_MML2_CFG_TOP |
| 79 | #define BASE_NADDR_MML2_BYC BASE_MADDR_MML2_BYC |
| 80 | |
| 81 | |
| 82 | |
| 83 | |
| 84 | #endif /* ELBRUS */ |
| 85 | |
| 86 | #endif /* end of __REG_BASE_ELBRUS_H__ */ |