rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | #ifndef _CUSTOM_PORT_H_ |
| 2 | #define _CUSTOM_PORT_H_ |
| 3 | |
| 4 | #include "kal_public_api.h" |
| 5 | #include "kal_public_defs.h" |
| 6 | |
| 7 | // |
| 8 | #define PORT_MODE_BITS (3) |
| 9 | #define PORT_MODE_MASK ((1 << PORT_MODE_BITS) - 1) |
| 10 | #define PORT_MODE_SHIFT (29) |
| 11 | |
| 12 | #define PORT_MODE_NONE (0) //slave mode NONE |
| 13 | #define PORT_MODE_USB (1) //slave mode USB |
| 14 | #define PORT_MODE_PCIE (2) //slave mode PCIE |
| 15 | #define PORT_MODE_USB_AND_PCIE (3) //slave mode USB & PCIE |
| 16 | #define PORT_MODE_AP (7) //master mode |
| 17 | |
| 18 | // |
| 19 | #define PORT_DIPC_MODE_BITS (3) |
| 20 | #define PORT_DIPC_MODE_MASK ((1 << PORT_DIPC_MODE_BITS) - 1) |
| 21 | #define PORT_DIPC_MODE_SHIFT (8) |
| 22 | |
| 23 | #define PORT_DIPC_MODE_NOT_SUPPORT (0) |
| 24 | #define PORT_DIPC_MODE_PCIE_ONLY (1) |
| 25 | #define PORT_DIPC_MODE_PCIE_ADVANCE (2) |
| 26 | #define PORT_DIPC_MODE_DUAL_IPC (3) |
| 27 | #define PORT_DIPC_MODE_USB_ONLY (4) |
| 28 | |
| 29 | //only valid when PCIE only mode |
| 30 | #define PORT_PCIE_ENABLE_BITS (1) |
| 31 | #define PORT_PCIE_ENABLE_MASK ((1 << PORT_PCIE_ENABLE_BITS) - 1) |
| 32 | #define PORT_PCIE_ENABLE_SHIFT (1) |
| 33 | |
| 34 | #define PORT_PCIE_DISABLE (0) //port is not enabled on PCIE |
| 35 | #define PORT_PCIE_ENABLE (1) //port is enabled on PCIE |
| 36 | |
| 37 | // |
| 38 | #define PORT_PCIE_STATUS_BITS (1) |
| 39 | #define PORT_PCIE_STATUS_MASK ((1 << PORT_PCIE_STATUS_BITS) - 1) |
| 40 | #define PORT_PCIE_STATUS_SHIFT (0) |
| 41 | |
| 42 | #define PORT_PCIE_STATUS_LINK_DOWN (0) //pcie link is down (if no PCIE, it's default) |
| 43 | #define PORT_PCIE_STATUS_LINK_UP (1) //pcie link is up |
| 44 | |
| 45 | #define CUSTOM_PORT_GET_MODE(x) ((custom_port(x) >> PORT_MODE_SHIFT) & PORT_MODE_MASK) |
| 46 | #define CUSTOM_PORT_GET_DIPC_MODE(x) ((custom_port(x) >> PORT_DIPC_MODE_SHIFT) & PORT_DIPC_MODE_MASK) |
| 47 | #define CUSTOM_PORT_GET_PCIE_ENABLE(x) ((custom_port(x) >> PORT_PCIE_ENABLE_SHIFT) & PORT_PCIE_ENABLE_MASK) |
| 48 | #define CUSTOM_PORT_GET_PCIE_STATUS(x) ((custom_port(x) >> PORT_PCIE_STATUS_SHIFT) & PORT_PCIE_STATUS_MASK) |
| 49 | |
| 50 | typedef enum { |
| 51 | CUSTOM_PORT_USER_UNKNOWN = 0, |
| 52 | CUSTOM_PORT_USER_LOG = 1, |
| 53 | CUSTOM_PORT_USER_META = 2, |
| 54 | CUSTOM_PORT_USER_MIPC = 3, |
| 55 | CUSTOM_PORT_USER_BINARY_TOOL = 4, |
| 56 | CUSTOM_PORT_USER_MBIM = 5, |
| 57 | CUSTOM_PORT_USER_AT = 6, |
| 58 | CUSTOM_PORT_USER_MAX |
| 59 | } custom_port_user_enum; |
| 60 | |
| 61 | kal_uint32 custom_port(custom_port_user_enum port); |
| 62 | |
| 63 | //defintions from AP |
| 64 | #define DIPC_CONFIG_PATH "V:\\dipc_config" |
| 65 | |
| 66 | #define KEY_DUAL_IPC_MODE "dual_ipc_mode" |
| 67 | #define KEY_MD_LOGGING_INTERFACE "md_logging_interface" |
| 68 | #define KEY_MD_AT_INTERFACE "md_at_interface" |
| 69 | #define KEY_MD_PCIE_PORT_CONFIG "md_pcie_port_config" |
| 70 | |
| 71 | #define DIPC_CONFIG_PORT_START (uint32_t)0x00000001 |
| 72 | |
| 73 | // MD Ports |
| 74 | typedef enum { |
| 75 | DIPC_CONFIG_MD_PORT_LOGGING = (DIPC_CONFIG_PORT_START << 0), |
| 76 | DIPC_CONFIG_MD_PORT_META = (DIPC_CONFIG_PORT_START << 1), |
| 77 | DIPC_CONFIG_MD_PORT_BINARY_TOOL = (DIPC_CONFIG_PORT_START << 2), |
| 78 | DIPC_CONFIG_MD_PORT_AT = (DIPC_CONFIG_PORT_START << 3), |
| 79 | } dipc_config_md_port_enum; |
| 80 | |
| 81 | typedef enum { |
| 82 | DIPC_MODE_NOT_CONFIG, |
| 83 | DIPC_MODE_PCIE_ADV, |
| 84 | DIPC_MODE_PCIE_ONLY, |
| 85 | DIPC_MODE_DUAL_IPC, |
| 86 | DIPC_MODE_USB_ONLY, |
| 87 | DIPC_MODE_END = DIPC_MODE_DUAL_IPC, |
| 88 | } dipc_mode_enum; |
| 89 | |
| 90 | typedef enum { |
| 91 | DIPC_INTF_NOT_CONFIG, |
| 92 | DIPC_INTF_USB, |
| 93 | DIPC_INTF_PCIE, |
| 94 | DIPC_INTF_USB_AND_PCIE, |
| 95 | DIPC_INTF_CLOSED, |
| 96 | } dipc_port_intf_enum; |
| 97 | |
| 98 | |
| 99 | |
| 100 | #endif |