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192.168.1.100 / T800_MD / b0f5b85a5b9d69cbfa1dd990d559a4a9c7d8f2a6 / . / mcu / driver / audio / src / v1 / vm.c
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*******************************************************************************
37 *
38 * Filename:
39 * ---------
40 * vm.c
41 *
42 * Project:
43 * --------
44 * MAUI
45 *
46 * Description:
47 * ------------
48 * VM recording/playback
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *==============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
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270 *------------------------------------------------------------------------------
271 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
272 *==============================================================================
273 *******************************************************************************/
274
275#include "kal_public_api.h"
276#include "kal_general_types.h"
277#include "string.h"
278#include "reg_base.h"
279#include "kal_trace.h"
280
281#include "speech_def.h"
282#include "l1aud_common_def.h"
283#include "l1audio.h"
284#include "l1audio_trace_utmd.h"
285#include "l1audio_voc_utmd.h"
286#include "sp_drv.h"
287#include "pcm4way.h"
288#include "am.h"
289#include "media.h"
290#include "afe.h"
291#include "l1sp_trc.h"
292#include "l1audio_sph_trc.h"
293#include "sal_exp.h"
294#include "sal_def.h"
295#include "vm.h"
296#include "gmss_public.h"
297
298/* ------------------------------------------------------------------------------ */
299#define VM_4G_G_SERIAL_DEBUG
300
301#if defined( __UMTS_RAT__ )
302#define _EXTRA_LOG_FOR_BIT_TRUE_
303#endif
304
305#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
306extern kal_bool g_bNeedExtraLog;
307#endif
308
309/* ------------------------------------------------------------------------------ */
310#define VM_STATE_RECORD 0x1
311#define VM_STATE_STOP 0x10
312#define VM_STATE_RECORD_STOP 0x20 // entering vmStop
313
314#define VM_VM_MAGIC_HEADER 0xBB88
315
316#define VM_VM_CTRL_UL_ON 0x0001
317#define VM_VM_CTRL_DL_ON 0x0001
318
319#define VM_EPL_1STSET_RECORD_FLAG 0x0001
320#define VM_EPL_2NDSET_RECORD_FLAG 0x0002
321#define VM_VM_RECORD_FLAG 0x0004
322#define VM_EPL_REFMIC_RECORD_FLAG 0x0008
323#define VM_EPL_ECHOREF_RECORD_FLAG 0x0010
324#define VM_EPL_3RDMIC_RECORD_FLAG 0x0020
325#define VM_EPL_2NDECHOREF_RECORD_FLAG 0x0040
326#define VM_EPL_ALL_RECORD_FLAG (VM_EPL_1STSET_RECORD_FLAG + VM_EPL_2NDSET_RECORD_FLAG + VM_EPL_REFMIC_RECORD_FLAG + VM_EPL_ECHOREF_RECORD_FLAG + VM_EPL_3RDMIC_RECORD_FLAG + VM_EPL_2NDECHOREF_RECORD_FLAG)
327
328#define VM_EPL_BAND_UL0_SHIFT 0
329#define VM_EPL_BAND_UL1_SHIFT 2
330#define VM_EPL_BAND_DL0_SHIFT 4
331#define VM_EPL_BAND_DL1_SHIFT 6
332#define VM_EPL_BAND_UL2_SHIFT 8
333#define VM_EPL_BAND_UL4_SHIFT 10
334#define VM_EPL_BAND_UL3_SHIFT 12
335#define VM_EPL_BAND_UL5_SHIFT 14
336
337#define VM_VM_HEADER_SIZE 6
338#define VM_VM_CONTROL_SIZE 10
339#define VM_VM_MAX_HB_WORD_SIZE ((160+2)*3) // EVS_128000: 2560 bits = 160 words, UL + DL + DL2
340
341#define VM_VM_SCH_DBGINFO_SIZE 100
342#define VM_VM_ENH_DBGINFO_SIZE 160
343#define VM_VM_DRV_DBGINFO_SIZE 20
344#define VM_VM_SVC_DBGINFO_SIZE 20
345#define VM_VM_DBGINFO_TOTAL_SIZE (VM_VM_SCH_DBGINFO_SIZE + VM_VM_ENH_DBGINFO_SIZE + VM_VM_DRV_DBGINFO_SIZE + VM_VM_SVC_DBGINFO_SIZE)
346
347#define VM_VM_BUFFER_SIZE (VM_VM_HEADER_SIZE + VM_VM_CONTROL_SIZE + VM_VM_MAX_HB_WORD_SIZE + VM_VM_DBGINFO_TOTAL_SIZE)
348
349#define VM_EPL_1STSET_SIZE (SAL_FB_PCM_SIZE + SAL_FB_PCM_SIZE + 2)
350#define VM_EPL_2NDSET_SIZE (SAL_FB_PCM_SIZE + SAL_FB_PCM_SIZE + 2)
351#define VM_EPL_REFMIC_SIZE (SAL_FB_PCM_SIZE + 2 + 2)
352#define VM_EPL_ECHOREF_SIZE (SAL_FB_PCM_SIZE + 2)
353#define VM_EPL_3RDMIC_SIZE (SAL_FB_PCM_SIZE + 2)
354#define VM_EPL_2NDECHOREF_SIZE (SAL_FB_PCM_SIZE + 2)
355
356#define VM_EPL_PCM_BUFFER_SIZE VM_EPL_1STSET_SIZE
357#define VM_EPL_TOTAL_SIZE (VM_EPL_1STSET_SIZE + VM_EPL_2NDSET_SIZE + VM_EPL_REFMIC_SIZE + VM_EPL_ECHOREF_SIZE + VM_EPL_3RDMIC_SIZE + VM_EPL_2NDECHOREF_SIZE)
358
359#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
360#define G_CODEC_UL_INFO_HEADER_MAGIC_NUMBER (0x6666)
361#define G_CODEC_DL_INFO_HEADER_MAGIC_NUMBER (0x6667)
362//G.722 bitstream 20ms 160byte
363//G.711 bitstream 10ms 80byte
364//store max 4frame
365#define G_CODEC_MAX_FRAME_NUMBER (4)
366//stream_size+stream
367#define G_CODEC_BITSTREAM_BUFFER_BYTE_SIZE (1*2+80)
368//lost_info + system_time + codec + codec_parameters
369#define G_CODEC_UL_INFO_BYTE_SIZE (4*2)
370//lost_info + system_time + codec + codec_parameters + DL_PCM_buffer_size
371#define G_CODEC_DL_INFO_BYTE_SIZE (5*2)
372//header_magic_number+info_size+info_struct
373#define G_CODEC_UL_INFO_TOTAL_BYTE_SIZE (2*2+G_CODEC_UL_INFO_BYTE_SIZE)
374//header_magic_number+info_size+info_struct
375#define G_CODEC_DL_INFO_TOTAL_BYTE_SIZE (2*2+G_CODEC_DL_INFO_BYTE_SIZE)
376//total byte size
377#define G_CODEC_UL_BITSTREAM_TOTAL_BYTE_SIZE ((G_CODEC_UL_INFO_TOTAL_BYTE_SIZE+G_CODEC_BITSTREAM_BUFFER_BYTE_SIZE)*G_CODEC_MAX_FRAME_NUMBER)
378#define G_CODEC_DL_BITSTREAM_TOTAL_BYTE_SIZE ((G_CODEC_DL_INFO_TOTAL_BYTE_SIZE+G_CODEC_BITSTREAM_BUFFER_BYTE_SIZE)*G_CODEC_MAX_FRAME_NUMBER)
379#endif //#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
380
381#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
382#define G_CODEC_MAX_HB_WORD_SIZE (((G_CODEC_UL_BITSTREAM_TOTAL_BYTE_SIZE+1)>>1) + ((G_CODEC_DL_BITSTREAM_TOTAL_BYTE_SIZE+1)>>1))
383//#define VMREC_OUTPUT_BUF_SIZE (2 * (VM_VM_BUFFER_SIZE + VM_EPL_TOTAL_SIZE + G_CODEC_MAX_HB_WORD_SIZE))
384#define VMREC_OUTPUT_BUF_SIZE 8000 // [REMIND] Please notify AP speech owner when vm buffer change
385#else
386//#define VMREC_OUTPUT_BUF_SIZE (2 * (VM_VM_BUFFER_SIZE + VM_EPL_TOTAL_SIZE))
387#define VMREC_OUTPUT_BUF_SIZE 8000 // [REMIND] Please notify AP speech owner when vm buffer change
388#endif
389
390#define VM_3G_NETWORK_INFO_LEN 7
391
392/* ------------------------------------------------------------------------------ */
393static struct
394{
395 kal_spinlockid lockId;
396 void (*vm_hdlr)(void); // callback function for vm logging
397 bool isVocOn; // only use under call AM_IsSpeechOn()
398 bool isVmLOn; // only use under call AM_IsSpeechOn()
399 bool isMosaic;
400
401 uint16 audId;
402 uint16 state; // record DSP runnning status (including 2 hisr)
403
404 uint16 record_info; // record flag, only use to control EPL record though it also has VM record flag
405
406 uint16 control_1;
407 uint16 control_2;
408 uint16 control_3;
409 uint16 control_4;
410 uint16 control_5;
411 uint16 control_6;
412 uint16 control_7;
413 uint16 control_8;
414 uint16 control_9;
415 uint16 control_10;
416
417 uint16 evs_cur_sd_mode;
418 uint16 sc_len;
419 uint16 sd_len; // sd1_len + sd2_len
420
421 uint16 vm_lost_count; // For record EPL dummy
422 uint16 pcm_lost_count; // For record EPL dummy
423 uint16 vm_counter; // For record EPL dummy
424
425 uint16 *vmBuf; // point to buffer for VM
426 uint16 *pcmBuf; // point to temp buffer to get EPL from DSP in N times
427
428 // related to 'vmRecOutputBuf', which is cycular buffer use to buffer formatted vm data from dsp
429 uint16 pOutputBufWrite;
430 uint16 pOutputBufRead;
431 uint16 outputBufSize;
432} vm;
433
434uint16 vm3GNetworkInfo[VM_3G_NETWORK_INFO_LEN];
435
436static kal_uint16 vmBuffer[VM_VM_BUFFER_SIZE];
437static kal_uint16 vmEPLPCMInputBuf[VM_EPL_PCM_BUFFER_SIZE];
438static kal_uint16 vmRecOutputBuf[VMREC_OUTPUT_BUF_SIZE];
439
440#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
441static kal_uint32 vmGCodecULBitstreamBuf[(G_CODEC_UL_BITSTREAM_TOTAL_BYTE_SIZE + 3) / sizeof(kal_uint32)];
442static kal_uint32 vmGCodecDLBitstreamBuf[(G_CODEC_DL_BITSTREAM_TOTAL_BYTE_SIZE + 3) / sizeof(kal_uint32)];
443static kal_uint32 vmGCodecULBufWritePos;
444static kal_uint32 vmGCodecDLBufWritePos;
445static kal_uint32 vmGCodecULBufLastHeaderPos;
446static kal_uint32 vmGCodecDLBufLastHeaderPos;
447static kal_uint16 *p16vmGCodecULBitstreamBuf;
448static kal_uint16 *p16vmGCodecDLBitstreamBuf;
449#endif
450
451/* ------------------------------------------------------------------------------ */
452#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
453void vmInitGCodecULBuf(void)
454{
455 //memset(vmGCodecULBitstreamBuf, 0, sizeof(vmGCodecULBitstreamBuf));
456 p16vmGCodecULBitstreamBuf = (kal_uint16 *)vmGCodecULBitstreamBuf;
457 vmGCodecULBufWritePos = 0;
458 vmGCodecULBufLastHeaderPos = 0;
459}
460
461void vmInitGCodecDLBuf(void)
462{
463 //memset(vmGCodecDLBitstreamBuf, 0, sizeof(vmGCodecDLBitstreamBuf));
464 p16vmGCodecDLBitstreamBuf = (kal_uint16 *)vmGCodecDLBitstreamBuf;
465 vmGCodecDLBufWritePos = 0;
466 vmGCodecDLBufLastHeaderPos = 0;
467}
468#endif //#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
469
470void vmStoreGCodecULStream(vmGCodecULInfo *pstvmGCodecULInfo, kal_uint16 u16StreamSize, kal_uint8 *pu8StreamData)
471{
472#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
473 kal_uint32 u32TotalBufferSize = sizeof(vmGCodecULBitstreamBuf) >> 1;
474 //bytesize: G_CODEC_UL_INFO_TOTAL_BYTE_SIZE + stream_size + stream_data[]
475 //>>1 => 2byte size
476 kal_uint32 u32NeedSize = (G_CODEC_UL_INFO_TOTAL_BYTE_SIZE + 2 + u16StreamSize + 1) >> 1;
477 kal_uint32 i, j;
478 kal_uint16 u16tempData;
479
480#ifdef VM_4G_G_SERIAL_DEBUG
481 MD_TRC_VM_GFORM_ULSTREAM_ENTER();
482#endif //#ifdef VM_4G_G_SERIAL_DEBUG
483
484 // dsp status check
485 if (vm.state != VM_STATE_RECORD)
486 {
487 return;
488 }
489
490 // application status check
491 if ( (false == vm.isVocOn) && (false == vm.isVmLOn)) // (false == vm.isIdleVmOn) &&
492 {
493 return;
494 }
495
496#ifdef VM_4G_G_SERIAL_DEBUG
497 MD_TRC_VM_GFORM_ULSTREAM_INFO1(u32TotalBufferSize, vmGCodecULBufWritePos, ((u16StreamSize + 1) >> 1), u16StreamSize);
498#endif //#ifdef VM_4G_G_SERIAL_DEBUG
499
500 if ( (u32TotalBufferSize - vmGCodecULBufWritePos) >= u32NeedSize )
501 {
502 vmGCodecULBufLastHeaderPos = vmGCodecULBufWritePos;
503
504 p16vmGCodecULBitstreamBuf[vmGCodecULBufWritePos] = G_CODEC_UL_INFO_HEADER_MAGIC_NUMBER;
505 vmGCodecULBufWritePos++;
506 p16vmGCodecULBitstreamBuf[vmGCodecULBufWritePos] = G_CODEC_UL_INFO_BYTE_SIZE >> 1;
507 vmGCodecULBufWritePos++;
508 p16vmGCodecULBitstreamBuf[vmGCodecULBufWritePos] = pstvmGCodecULInfo->drop_info;
509 vmGCodecULBufWritePos++;
510 p16vmGCodecULBitstreamBuf[vmGCodecULBufWritePos] = (kal_uint16)(ust_get_current_time() / 1000); //ust_get_current_time(): unit is micro second (us) => ust_get_current_time()/1000: unit is ms
511 vmGCodecULBufWritePos++;
512 p16vmGCodecULBitstreamBuf[vmGCodecULBufWritePos] = pstvmGCodecULInfo->codec;
513 vmGCodecULBufWritePos++;
514 p16vmGCodecULBitstreamBuf[vmGCodecULBufWritePos] = pstvmGCodecULInfo->codec_parameters;
515 vmGCodecULBufWritePos++;
516 p16vmGCodecULBitstreamBuf[vmGCodecULBufWritePos] = u16StreamSize;
517 vmGCodecULBufWritePos++;
518 j = 0;
519 for (i = 0; i < (u16StreamSize >> 1); i++)
520 {
521 u16tempData = pu8StreamData[j];
522 j++;
523 u16tempData = (u16tempData << 8) | pu8StreamData[j];
524 j++;
525 p16vmGCodecULBitstreamBuf[vmGCodecULBufWritePos] = u16tempData;
526 vmGCodecULBufWritePos++;
527 }
528 if (u16StreamSize & 0x01)
529 {
530 u16tempData = pu8StreamData[j];
531 u16tempData = (u16tempData << 8) | u16tempData;
532 p16vmGCodecULBitstreamBuf[vmGCodecULBufWritePos] = u16tempData;
533 vmGCodecULBufWritePos++;
534 }
535 }
536 else
537 {
538 MD_TRC_VM_GFORM_ULSTREAM_INFO2(u32NeedSize, u32TotalBufferSize - vmGCodecULBufWritePos);
539 if (vmGCodecULBufWritePos != 0)
540 {
541 p16vmGCodecULBitstreamBuf[vmGCodecULBufLastHeaderPos + 2] += 0x0100;
542 }
543 else
544 {
545 MD_TRC_VM_GFORM_ULSTREAM_INFO3(u32NeedSize, u32TotalBufferSize);
546 }
547 }
548
549#ifdef VM_4G_G_SERIAL_DEBUG
550 MD_TRC_VM_GFORM_ULSTREAM_EXIT();
551#endif //#ifdef VM_4G_G_SERIAL_DEBUG
552#endif //#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
553}
554
555void vmStoreGCodecDLStream(vmGCodecDLInfo *pstvmGCodecDLInfo, kal_uint16 u16StreamSize, kal_uint8 *pu8StreamData)
556{
557#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
558 kal_uint32 u32TotalBufferSize = sizeof(vmGCodecDLBitstreamBuf) >> 1;
559 //bytesize: G_CODEC_DL_INFO_TOTAL_BYTE_SIZE + stream_size + stream_data[]
560 //>>1 => 2byte size
561 kal_uint32 u32NeedSize = (G_CODEC_DL_INFO_TOTAL_BYTE_SIZE + 2 + u16StreamSize + 1) >> 1;
562 kal_uint32 i, j;
563 kal_uint16 u16tempData;
564
565#ifdef VM_4G_G_SERIAL_DEBUG
566 MD_TRC_VM_GFORM_DLSTREAM_ENTER();
567#endif //#ifdef VM_4G_G_SERIAL_DEBUG
568
569 // dsp status check
570 if (vm.state != VM_STATE_RECORD)
571 {
572 return;
573 }
574
575 // application status check
576 if ( (false == vm.isVocOn) && (false == vm.isVmLOn)) // (false == vm.isIdleVmOn) &&
577 {
578 return;
579 }
580
581#ifdef VM_4G_G_SERIAL_DEBUG
582 MD_TRC_VM_GFORM_DLSTREAM_INFO1(u32TotalBufferSize, vmGCodecDLBufWritePos, ((u16StreamSize + 1) >> 1), u16StreamSize);
583#endif //#ifdef VM_4G_G_SERIAL_DEBUG
584
585 if ( (u32TotalBufferSize - vmGCodecDLBufWritePos) >= u32NeedSize )
586 {
587 vmGCodecDLBufLastHeaderPos = vmGCodecDLBufWritePos;
588
589 p16vmGCodecDLBitstreamBuf[vmGCodecDLBufWritePos] = G_CODEC_DL_INFO_HEADER_MAGIC_NUMBER;
590 vmGCodecDLBufWritePos++;
591 p16vmGCodecDLBitstreamBuf[vmGCodecDLBufWritePos] = G_CODEC_DL_INFO_BYTE_SIZE >> 1;
592 vmGCodecDLBufWritePos++;
593 p16vmGCodecDLBitstreamBuf[vmGCodecDLBufWritePos] = pstvmGCodecDLInfo->drop_info;
594 vmGCodecDLBufWritePos++;
595 p16vmGCodecDLBitstreamBuf[vmGCodecDLBufWritePos] = (kal_uint16)(ust_get_current_time() / 1000); //ust_get_current_time(): unit is micro second (us) => ust_get_current_time()/1000: unit is ms
596 vmGCodecDLBufWritePos++;
597 p16vmGCodecDLBitstreamBuf[vmGCodecDLBufWritePos] = pstvmGCodecDLInfo->codec;
598 vmGCodecDLBufWritePos++;
599 p16vmGCodecDLBitstreamBuf[vmGCodecDLBufWritePos] = pstvmGCodecDLInfo->codec_parameters;
600 vmGCodecDLBufWritePos++;
601 p16vmGCodecDLBitstreamBuf[vmGCodecDLBufWritePos] = pstvmGCodecDLInfo->DL_PCM_size;
602 vmGCodecDLBufWritePos++;
603 p16vmGCodecDLBitstreamBuf[vmGCodecDLBufWritePos] = u16StreamSize;
604 vmGCodecDLBufWritePos++;
605 j = 0;
606 for (i = 0; i < (u16StreamSize >> 1); i++)
607 {
608 u16tempData = pu8StreamData[j];
609 j++;
610 u16tempData = (u16tempData << 8) | pu8StreamData[j];
611 j++;
612 p16vmGCodecDLBitstreamBuf[vmGCodecDLBufWritePos] = u16tempData;
613 vmGCodecDLBufWritePos++;
614 }
615 if (u16StreamSize & 0x01)
616 {
617 u16tempData = pu8StreamData[j];
618 u16tempData = (u16tempData << 8) | u16tempData;
619 p16vmGCodecDLBitstreamBuf[vmGCodecDLBufWritePos] = u16tempData;
620 vmGCodecDLBufWritePos++;
621 }
622 }
623 else
624 {
625 MD_TRC_VM_GFORM_DLSTREAM_INFO2(u32NeedSize, u32TotalBufferSize - vmGCodecDLBufWritePos);
626 if (vmGCodecDLBufWritePos != 0)
627 {
628 p16vmGCodecDLBitstreamBuf[vmGCodecDLBufLastHeaderPos + 2] += 0x0100;
629 }
630 else
631 {
632 MD_TRC_VM_GFORM_DLSTREAM_INFO3(u32NeedSize, u32TotalBufferSize);
633 }
634 }
635
636#ifdef VM_4G_G_SERIAL_DEBUG
637 MD_TRC_VM_GFORM_DLSTREAM_EXIT();
638#endif //#ifdef VM_4G_G_SERIAL_DEBUG
639#endif //#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
640}
641
642void vmSet3GNetworkInfo( uint32 *l1_info, uint16 crc_result, uint16 buf_status, uint8 dl_count )
643{
644 kal_int16 tpc_SIR_lta, dpdch_SIR_lta, TFCI_max_corr, I;
645 uint32 l1Info, s_value;
646 if ( l1_info == NULL ) {
647 l1Info = 0;
648 tpc_SIR_lta = 0;
649 dpdch_SIR_lta = 0;
650 TFCI_max_corr = 0;
651 s_value = 0;
652 } else {
653 l1Info = l1_info[1];
654 tpc_SIR_lta = l1_info[4];
655 dpdch_SIR_lta = l1_info[5];
656 TFCI_max_corr = l1_info[6];
657 s_value = l1_info[3];
658 }
659 I = (uint16)(l1Info & 0xFFFF);
660 vm3GNetworkInfo[4] = I;
661
662 I = (uint16)(l1Info >> 16);
663 vm3GNetworkInfo[5] = I;
664
665 vm3GNetworkInfo[3] = crc_result;
666
667
668 vm3GNetworkInfo[6] = (uint16)((s_value >= 32767) ? 32767 : s_value); //s_value
669
670 vm3GNetworkInfo[0] = (uint16)tpc_SIR_lta;
671 vm3GNetworkInfo[1] = (uint16)dpdch_SIR_lta;
672 vm3GNetworkInfo[2] = (uint16)TFCI_max_corr;
673}
674
675static uint16 vmEPLBandSet(uint16 u2EPLBufLen, uint16 u2EPLBufShift)
676{
677 uint16 u2vmEPLBand = 0;
678 if (u2EPLBufLen == SAL_NB_PCM_SIZE)
679 {
680 u2vmEPLBand = SAL_NB;
681 }
682 else if (u2EPLBufLen == SAL_WB_PCM_SIZE)
683 {
684 u2vmEPLBand = SAL_WB;
685 }
686 else if (u2EPLBufLen == SAL_SWB_PCM_SIZE)
687 {
688 u2vmEPLBand = SAL_SWB;
689 }
690 else if (u2EPLBufLen == SAL_FB_PCM_SIZE)
691 {
692 u2vmEPLBand = SAL_FB;
693 }
694 return u2vmEPLBand << u2EPLBufShift;
695}
696
697bool VM_CodIsAMR(uint16 codec_mode)
698{
699 if ((codec_mode <= SAL_COD_AMR475 && codec_mode >= SAL_COD_AMR122) ||
700 (codec_mode >= SAL_COD_AWB660 && codec_mode <= SAL_COD_AWB2385))
701 {
702 return true;
703 }
704 return false;
705}
706
707bool VM_CodIsEVS(uint16 codec_mode)
708{
709 if ((codec_mode >= SAL_COD_EVSMIN && codec_mode <= SAL_COD_EVSMAX))
710 {
711 return true;
712 }
713 return false;
714}
715
716/* ------------------------------------------------------------------------------ */
717#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
718void vmFormatter_gseries(uint16 *vmBuf, Sal_VM_Frame *vmfrm)
719{
720 volatile uint16 *addr;
721 uint16 I, sc_mode, sd_mode, sc_len, sd_len;
722 uint32 J;
723
724 sc_mode = SAL_COD_AMR122;
725 sd_mode = SAL_COD_AMR122;
726
727 sc_len = AM_GetSpeechPatternLength(sc_mode);
728 //ASSERT_REBOOT( sc_len > 0 );
729 sd_len = AM_GetSpeechPatternLength(sd_mode);
730 //ASSERT_REBOOT( sd_len > 0 );
731
732 //[0:0]: UL on
733 //[6:1]: UL mode
734 //[10:7]: TX type
735 //[11:11]: (no use) SP flag
736 //[13:12]: Call mode
737 I = 0; // Tx: NO_DATA
738 vm.control_1 = (I << 7) | (sc_mode << 1) | (vm.control_1 & 1);
739
740 // if Call mode = 2G, vm.control_1 = vm.control_1 | 0x0000;
741 if (L1SP_GetState() == L1SP_STATE_4G_SPEECH_ON)
742 vm.control_1 = vm.control_1 | 0x3000; // Call mode = 4G
743 else if (SAL_3G_Mode())
744 vm.control_1 = vm.control_1 | 0x1000; // Call mode = 3G
745
746 //[0:0]: DL on
747 //[6:1]: DL mode
748 //[10:7]: RX type
749 //[15:11]: (no use) [12:11] SID flag, [13] TAF, [14] UFI, [15] BFI
750 I = 0; // Rx: NO_DATA
751 vm.control_2 = (I << 7) | (sd_mode << 1) | (vm.control_2 & 1);
752
753 kal_prompt_trace(MOD_L1SP, "vmBuf head %x", vmBuf);
754
755 *vmBuf++ = VM_VM_MAGIC_HEADER;
756 J = L1SP_GetState();
757 I = (uint16)( ( VM_VM_DBGINFO_TOTAL_SIZE << 3 ) | J);
758 *vmBuf++ = I;
759 *vmBuf++ = VM_VM_RECORD_FLAG;
760 *vmBuf++ = 0; //reset EPL band
761 J = fma_get_glb_ts() & 0xFFFFFFFF;
762#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
763 if ( g_bNeedExtraLog )
764 MD_TRC_VM_SP3G_VM_L1T(J);
765#endif
766 I = (uint16)(J & 0xFFFF);
767 *vmBuf++ = I;
768 I = (uint16)(J >> 16);
769 *vmBuf++ = I;
770 vm.vm_counter++;
771
772 //Chip ID
773 vm.control_3 = VM_CHIP_ID;
774
775 //[1:0]: DL frm cnt
776 //[7:2]: DL2 mode
777 //[11:8]: DL2 RX type
778 //[13:12]: Codec band
779 //[15:14]: Expert mode (By VLP)
780 vm.control_4 = (vmfrm->dec_frm_num & 0x3) | ((sd_mode & 0x3F) << 2) | ((vmfrm->dec_hdr_1 & 0xE) << 8) | ((SAL_VM_Get_CodBand() & 0x3) << 12);
781
782 //[15:0]: TS control
783 vm.control_5 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_CTRL);
784
785 //[7:0]: TS target scale
786 //[12:8]: TS max scale
787 vm.control_6 = (SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_TARGET_SCALE) & 0xFF) | ((SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_MAX_SCALE) & 0x1F) << 8);
788
789 //[10:0]: TS output size 1
790 vm.control_7 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_OUTPUT_SIZE_1);
791
792 //[10:0]: TS output size 2
793 vm.control_8 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_OUTPUT_SIZE_2);
794
795 // record vm control value
796 *vmBuf++ = vm.control_1;
797 *vmBuf++ = vm.control_2;
798 *vmBuf++ = vm.control_3;
799 *vmBuf++ = vm.control_4;
800 *vmBuf++ = vm.control_5;
801 *vmBuf++ = vm.control_6;
802 *vmBuf++ = vm.control_7;
803 *vmBuf++ = vm.control_8;
804 *vmBuf++ = vm.control_9;
805 *vmBuf++ = vm.control_10;
806
807 // record UL data
808 vm.sc_len = 0;
809 if ( vm.control_1 & 1 )
810 {
811 addr = vmfrm->enc_hb_addr;
812 for ( I = 0; I < sc_len; I++ )
813 {
814 *vmBuf++ = *addr++;
815 if (L1SP_GetState() == L1SP_STATE_2G_SPEECH_ON)
816 addr++;
817 }
818 vm.sc_len += sc_len;
819 }
820
821 // record DL data
822 vm.sd_len = 0;
823 if ( vm.control_2 & 1 )
824 {
825 addr = vmfrm->dec_hb_addr;
826 for ( I = 0; I < sd_len; I++ )
827 {
828 *vmBuf++ = *addr++;
829 if (L1SP_GetState() == L1SP_STATE_2G_SPEECH_ON)
830 addr++;
831 }
832 vm.sd_len += sd_len;
833
834 if (vmfrm->dec_frm_num == 2)
835 {
836 addr = vmfrm->dec_hb_addr_1;
837 for ( I = 0; I < sd_len; I++ )
838 {
839 *vmBuf++ = *addr++;
840 if (L1SP_GetState() == L1SP_STATE_2G_SPEECH_ON)
841 addr++;
842 }
843 vm.sd_len += sd_len;
844 }
845 }
846
847 kal_prompt_trace(MOD_L1SP, "Formatter_GSeries SC Len= %d, SD Len= %d, Dec_Cnt= %d", vm.sc_len, vm.sd_len, vmfrm->dec_frm_num);
848
849 // Debug info
850 addr = vmfrm->dbgInfo_addr;
851 for ( I = 0; I < VM_VM_SCH_DBGINFO_SIZE; I++ )
852 *vmBuf++ = *addr++;
853
854 addr = vmfrm->enh_dbgInfo_addr;
855 for ( I = 0; I < VM_VM_ENH_DBGINFO_SIZE; I++ )
856 *vmBuf++ = *addr++;
857
858 for (I = 0; I < VM_VM_DRV_DBGINFO_SIZE; I++)
859 {
860 if (I < VM_3G_NETWORK_INFO_LEN)
861 *vmBuf++ = vm3GNetworkInfo[I];
862 else
863 *vmBuf++ = 0;
864 }
865
866 addr = vmfrm->svc_dbgInfo_addr;
867 for ( I = 0; I < VM_VM_SVC_DBGINFO_SIZE; I++ )
868 *vmBuf++ = *addr++;
869
870 kal_prompt_trace(MOD_L1SP, "vmBuf tail %x", vmBuf);
871}
872#endif //#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
873
874#if defined(__EVS_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
875EVS_VM_ID VM_EVS_Get_Codec_ID(SP4G_Codec EVSCod)
876{
877 EVS_VM_ID VM_Codec_ID = 0;
878 switch (EVSCod)
879 {
880 case SP4G_CODEC_EVS_08K_005_9:
881 case SP4G_CODEC_EVS_16K_005_9:
882 case SP4G_CODEC_EVS_32K_005_9:
883 case SP4G_CODEC_EVS_48K_005_9:
884 VM_Codec_ID = EVS_PRI590;
885 break;
886
887 case SP4G_CODEC_EVS_AWB_06_60:
888 VM_Codec_ID = EVS_AWB660;
889 break;
890
891 case SP4G_CODEC_EVS_08K_007_2:
892 case SP4G_CODEC_EVS_16K_007_2:
893 case SP4G_CODEC_EVS_32K_007_2:
894 case SP4G_CODEC_EVS_48K_007_2:
895 VM_Codec_ID = EVS_PRI720;
896 break;
897
898 case SP4G_CODEC_EVS_08K_008_0:
899 case SP4G_CODEC_EVS_16K_008_0:
900 case SP4G_CODEC_EVS_32K_008_0:
901 case SP4G_CODEC_EVS_48K_008_0:
902 VM_Codec_ID = EVS_PRI800;
903 break;
904
905 case SP4G_CODEC_EVS_AWB_08_85:
906 VM_Codec_ID = EVS_AWB885;
907 break;
908
909 case SP4G_CODEC_EVS_08K_009_6:
910 case SP4G_CODEC_EVS_16K_009_6:
911 case SP4G_CODEC_EVS_32K_009_6:
912 case SP4G_CODEC_EVS_48K_009_6:
913 VM_Codec_ID = EVS_PRI960;
914 break;
915
916 case SP4G_CODEC_EVS_AWB_12_65:
917 VM_Codec_ID = EVS_AWB1265;
918 break;
919
920 case SP4G_CODEC_EVS_08K_013_2:
921 case SP4G_CODEC_EVS_16K_013_2:
922 case SP4G_CODEC_EVS_32K_013_2:
923 case SP4G_CODEC_EVS_48K_013_2:
924 VM_Codec_ID = EVS_PRI1320;
925 break;
926
927 case SP4G_CODEC_EVS_AWB_14_25:
928 VM_Codec_ID = EVS_AWB1425;
929 break;
930
931 case SP4G_CODEC_EVS_AWB_15_85:
932 VM_Codec_ID = EVS_AWB1585;
933 break;
934
935 case SP4G_CODEC_EVS_08K_016_4:
936 case SP4G_CODEC_EVS_16K_016_4:
937 case SP4G_CODEC_EVS_32K_016_4:
938 case SP4G_CODEC_EVS_48K_016_4:
939 VM_Codec_ID = EVS_PRI1640;
940 break;
941
942 case SP4G_CODEC_EVS_AWB_18_25:
943 VM_Codec_ID = EVS_AWB1825;
944 break;
945
946 case SP4G_CODEC_EVS_AWB_19_85:
947 VM_Codec_ID = EVS_AWB1985;
948 break;
949
950 case SP4G_CODEC_EVS_AWB_23_05:
951 VM_Codec_ID = EVS_AWB2305;
952 break;
953
954 case SP4G_CODEC_EVS_AWB_23_85:
955 VM_Codec_ID = EVS_AWB2385;
956 break;
957
958 case SP4G_CODEC_EVS_08K_024_4:
959 case SP4G_CODEC_EVS_16K_024_4:
960 case SP4G_CODEC_EVS_32K_024_4:
961 case SP4G_CODEC_EVS_48K_024_4:
962 VM_Codec_ID = EVS_PRI2440;
963 break;
964
965 case SP4G_CODEC_EVS_08K_032_0:
966 case SP4G_CODEC_EVS_16K_032_0:
967 case SP4G_CODEC_EVS_32K_032_0:
968 case SP4G_CODEC_EVS_48K_032_0:
969 VM_Codec_ID = EVS_PRI3200;
970 break;
971
972 case SP4G_CODEC_EVS_08K_048_0:
973 case SP4G_CODEC_EVS_16K_048_0:
974 case SP4G_CODEC_EVS_32K_048_0:
975 case SP4G_CODEC_EVS_48K_048_0:
976 VM_Codec_ID = EVS_PRI4800;
977 break;
978
979 case SP4G_CODEC_EVS_08K_064_0:
980 case SP4G_CODEC_EVS_16K_064_0:
981 case SP4G_CODEC_EVS_32K_064_0:
982 case SP4G_CODEC_EVS_48K_064_0:
983 VM_Codec_ID = EVS_PRI6400;
984 break;
985
986 case SP4G_CODEC_EVS_08K_096_0:
987 case SP4G_CODEC_EVS_16K_096_0:
988 case SP4G_CODEC_EVS_32K_096_0:
989 case SP4G_CODEC_EVS_48K_096_0:
990 VM_Codec_ID = EVS_PRI9600;
991 break;
992
993 case SP4G_CODEC_EVS_08K_128_0:
994 case SP4G_CODEC_EVS_16K_128_0:
995 case SP4G_CODEC_EVS_32K_128_0:
996 case SP4G_CODEC_EVS_48K_128_0:
997 VM_Codec_ID = EVS_PRI12800;
998 break;
999
1000 case SP4G_CODEC_EVS_08K_002_4_SID:
1001 case SP4G_CODEC_EVS_08K_000_0_REV:
1002 case SP4G_CODEC_EVS_08K_000_0_LOST:
1003 case SP4G_CODEC_EVS_08K_000_0_NODATA:
1004
1005 case SP4G_CODEC_EVS_16K_002_4_SID:
1006 case SP4G_CODEC_EVS_16K_000_0_REV:
1007 case SP4G_CODEC_EVS_16K_000_0_LOST:
1008 case SP4G_CODEC_EVS_16K_000_0_NODATA:
1009
1010 case SP4G_CODEC_EVS_32K_002_4_SID:
1011 case SP4G_CODEC_EVS_32K_000_0_REV:
1012 case SP4G_CODEC_EVS_32K_000_0_LOST:
1013 case SP4G_CODEC_EVS_32K_000_0_NODATA:
1014
1015 case SP4G_CODEC_EVS_48K_002_4_SID:
1016 case SP4G_CODEC_EVS_48K_000_0_REV:
1017 case SP4G_CODEC_EVS_48K_000_0_LOST:
1018 case SP4G_CODEC_EVS_48K_000_0_NODATA:
1019
1020 case SP4G_CODEC_EVS_AWB_02_00_SID:
1021 case SP4G_CODEC_EVS_AWB_00_00_REV0:
1022 case SP4G_CODEC_EVS_AWB_00_00_REV1:
1023 case SP4G_CODEC_EVS_AWB_00_00_REV2:
1024 case SP4G_CODEC_EVS_AWB_00_00_REV3:
1025 case SP4G_CODEC_EVS_AWB_00_00_LOST:
1026 case SP4G_CODEC_EVS_AWB_00_00_NODATA:
1027 VM_Codec_ID = EVS_SID_LOST_NODATA;
1028 break;
1029
1030 default:
1031 VM_Codec_ID = EVS_UNDEF;
1032 break;
1033 }
1034 return VM_Codec_ID;
1035}
1036
1037void vmFormatter_evs(uint16 *vmBuf, Sal_VM_Frame *vmfrm)
1038{
1039 volatile uint16 *addr;
1040 uint16 I, sc_mode, sd_mode, sc_len, sd_len;
1041 uint32 J;
1042 uint16 sc_mode_invalid = 0, sd_mode_invalid = 0;
1043
1044 sc_mode = VM_EVS_Get_Codec_ID(SAL_EVS_Get_Codec_Mode(SAL_EVS_TX_CODEC_MODE));
1045
1046 if (sc_mode == EVS_UNDEF)
1047 {
1048 sc_mode_invalid = 1;
1049 sc_mode = EVS_PRI1640;
1050 }
1051
1052 sd_mode = VM_EVS_Get_Codec_ID(SAL_EVS_Get_Codec_Mode(SAL_EVS_RX_CODEC_MODE));
1053
1054 if (sd_mode == EVS_SID_LOST_NODATA) // DL only, For EVS Codec ID: REV and LOST
1055 {
1056 if (vm.evs_cur_sd_mode == EVS_UNDEF)
1057 sd_mode = VM_EVS_Get_Codec_ID(SAL_Get_DL_CodecMode()); //Codec mode of call open
1058 else
1059 sd_mode = vm.evs_cur_sd_mode;
1060 }
1061
1062 if (sd_mode == EVS_UNDEF)
1063 {
1064 sd_mode_invalid = 1;
1065 sd_mode = EVS_PRI1640;
1066 }
1067
1068 vm.evs_cur_sd_mode = sd_mode;
1069
1070 sc_len = AM_GetSpeechPatternLength(sc_mode);
1071 //ASSERT_REBOOT( sc_len > 0 );
1072 sd_len = AM_GetSpeechPatternLength(sd_mode);
1073 //ASSERT_REBOOT( sd_len > 0 );
1074
1075 //[0:0]: UL on
1076 //[6:1]: UL mode
1077 //[10:7]: (no use) TX type
1078 //[11:11]: (no use) SP flag
1079 //[13:12]: Call mode
1080 vm.control_1 = (sc_mode << 1) | (vm.control_1 & 1);
1081 vm.control_1 = vm.control_1 | 0x3000; // Call mode = 4G
1082
1083 //[0:0]: DL on
1084 //[6:1]: DL mode
1085 //[10:7]: (no use) RX type
1086 //[15:11]: (no use) [12:11] SID flag, [13] TAF, [14] UFI, [15] BFI
1087 vm.control_2 = (sd_mode << 1) | (vm.control_2 & 1);
1088
1089 kal_prompt_trace(MOD_L1SP, "vmBuf head %x", vmBuf);
1090
1091 *vmBuf++ = VM_VM_MAGIC_HEADER;
1092 J = L1SP_GetState();
1093 I = (uint16)( ( VM_VM_DBGINFO_TOTAL_SIZE << 3 ) | J);
1094 *vmBuf++ = I;
1095 *vmBuf++ = VM_VM_RECORD_FLAG;
1096 *vmBuf++ = 0; //reset EPL band
1097 J = fma_get_glb_ts() & 0xFFFFFFFF;
1098#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1099 if ( g_bNeedExtraLog )
1100 MD_TRC_VM_SP3G_VM_L1T(J);
1101#endif
1102 I = (uint16)(J & 0xFFFF);
1103 *vmBuf++ = I;
1104 I = (uint16)(J >> 16);
1105 *vmBuf++ = I;
1106 vm.vm_counter++;
1107
1108 //Chip ID
1109 vm.control_3 = VM_CHIP_ID;
1110
1111 //[1:0]: DL frm cnt
1112 //[7:2]: DL2 mode
1113 //[11:8]: DL2 RX type
1114 //[13:12]: Codec band
1115 //[15:14]: Expert mode (By VLP)
1116 vm.control_4 = (vmfrm->dec_frm_num & 0x3) | ((sd_mode & 0x3F) << 2) | ((vmfrm->dec_hdr_1 & 0xE) << 8) | ((SAL_VM_Get_CodBand() & 0x3) << 12);
1117
1118 //[15:0]: TS control
1119 vm.control_5 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_CTRL);
1120
1121 //[7:0]: TS target scale
1122 //[12:8]: TS max scale
1123 vm.control_6 = (SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_TARGET_SCALE) & 0xFF) | ((SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_MAX_SCALE) & 0x1F) << 8);
1124
1125 //[10:0]: TS output size 1
1126 vm.control_7 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_OUTPUT_SIZE_1);
1127
1128 //[10:0]: TS output size 2
1129 vm.control_8 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_OUTPUT_SIZE_2);
1130
1131 // record vm control value
1132 *vmBuf++ = vm.control_1;
1133 *vmBuf++ = vm.control_2;
1134 *vmBuf++ = vm.control_3;
1135 *vmBuf++ = vm.control_4;
1136 *vmBuf++ = vm.control_5;
1137 *vmBuf++ = vm.control_6;
1138 *vmBuf++ = vm.control_7;
1139 *vmBuf++ = vm.control_8;
1140 *vmBuf++ = vm.control_9;
1141 *vmBuf++ = vm.control_10;
1142
1143 // record UL data
1144 vm.sc_len = 0;
1145 if ( vm.control_1 & 1 )
1146 {
1147 if (sc_mode_invalid)
1148 {
1149 *vmBuf++ = SAL_EVS_SPEECH_GOOD_FRAME;
1150 *vmBuf++ = 328; //EVS 16.4 HB Len
1151 }
1152 else
1153 {
1154 *vmBuf++ = SAL_EVS_Get_Enc_BFI();
1155 *vmBuf++ = SAL_EVS_Get_Enc_HBLen();
1156 }
1157
1158 addr = vmfrm->enc_hb_addr;
1159 for ( I = 0; I < (sc_len - 2); I++ )
1160 {
1161 if (sc_mode_invalid)
1162 *vmBuf++ = 0;
1163 else
1164 *vmBuf++ = *addr++;
1165 }
1166 vm.sc_len += sc_len;
1167 }
1168
1169 // record DL data
1170 vm.sd_len = 0;
1171 if ( vm.control_2 & 1 )
1172 {
1173 if (sd_mode_invalid)
1174 {
1175 *vmBuf++ = SAL_EVS_SPEECH_GOOD_FRAME;
1176 *vmBuf++ = 328; //EVS 16.4 HB Len
1177 }
1178 else
1179 {
1180 *vmBuf++ = SAL_EVS_Get_Dec_BFI(SAL_4G_RX_FIRST_FRM);
1181 *vmBuf++ = SAL_EVS_Get_Dec_HBLen(SAL_4G_RX_FIRST_FRM);
1182 }
1183
1184 addr = vmfrm->dec_hb_addr;
1185 for ( I = 0; I < (sd_len - 2); I++ )
1186 {
1187 if (sd_mode_invalid)
1188 *vmBuf++ = 0;
1189 else
1190 *vmBuf++ = *addr++;
1191 }
1192 vm.sd_len += sd_len;
1193
1194 if (vmfrm->dec_frm_num == 2)
1195 {
1196 if (sd_mode_invalid)
1197 {
1198 *vmBuf++ = SAL_EVS_SPEECH_GOOD_FRAME;
1199 *vmBuf++ = 328; //EVS 16.4 HB Len
1200 }
1201 else
1202 {
1203 *vmBuf++ = SAL_EVS_Get_Dec_BFI(SAL_4G_RX_SECOND_FRM);
1204 *vmBuf++ = SAL_EVS_Get_Dec_HBLen(SAL_4G_RX_SECOND_FRM);
1205 }
1206
1207 addr = vmfrm->dec_hb_addr_1;
1208 for ( I = 0; I < (sd_len - 2); I++ )
1209 {
1210 if (sd_mode_invalid)
1211 *vmBuf++ = 0;
1212 else
1213 *vmBuf++ = *addr++;
1214 }
1215 vm.sd_len += sd_len;
1216 }
1217 }
1218
1219 kal_prompt_trace(MOD_L1SP, "Formatter_EVS SC Len= %d, SD Len= %d, Dec_Cnt= %d", vm.sc_len, vm.sd_len, vmfrm->dec_frm_num);
1220
1221 // Debug info
1222 // SCH Dbg Info 0
1223 addr = vmfrm->dbgInfo_addr;
1224 *vmBuf = (*addr) & 0xEA;
1225 *vmBuf = *vmBuf | (SAL_EVS_SPEECH_BAD_FRAME == SAL_EVS_Get_Enc_BFI()) | ((SAL_EVS_SPEECH_BAD_FRAME == SAL_EVS_Get_Dec_BFI(SAL_4G_RX_FIRST_FRM)) << 2);
1226 vmBuf++;
1227
1228 // SCH Dbg Info 1
1229 *vmBuf = (SAL_EVS_Get_PCMBW()) | ((SAL_EVS_Get_PCMBW()) << 2) | ((SAL_EVS_Get_Enc_MaxRate()) << 4);
1230 *vmBuf = *vmBuf | ((SAL_EVS_Get_Enc_CA_Enable()) << 6) | ((SAL_EVS_Get_Enc_CA_RF_FEC_Indicator()) << 7) | ((SAL_EVS_Get_Enc_CA_RF_FEC_Offset()) << 8);
1231 *vmBuf = *vmBuf | ((SAL_EVS_Get_Dec_CA_FrmMode(SAL_4G_RX_FIRST_FRM)) << 11) | ((SAL_EVS_Get_Dec_CA_FrmMode(SAL_4G_RX_SECOND_FRM)) << 13);
1232 vmBuf++;
1233
1234 // SCH Dbg Info 2
1235 *vmBuf++ = SAL_EVS_Get_Enc_HBLen();
1236
1237 // SCH Dbg Info 3
1238 *vmBuf++ = SAL_EVS_Get_Dec_HBLen(SAL_4G_RX_FIRST_FRM);
1239
1240 // SCH Dbg Info 4
1241 *vmBuf++ = SAL_EVS_Get_Dec_HBLen(SAL_4G_RX_SECOND_FRM);
1242
1243 // SCH Dbg Info reserved
1244 addr = vmfrm->dbgInfo_addr + 5;
1245 for ( I = 0; I < (VM_VM_SCH_DBGINFO_SIZE - 5); I++ )
1246 *vmBuf++ = *addr++;
1247
1248 addr = vmfrm->enh_dbgInfo_addr;
1249 for ( I = 0; I < VM_VM_ENH_DBGINFO_SIZE; I++ )
1250 *vmBuf++ = *addr++;
1251
1252 for (I = 0; I < VM_VM_DRV_DBGINFO_SIZE; I++)
1253 {
1254 if (I < VM_3G_NETWORK_INFO_LEN)
1255 *vmBuf++ = vm3GNetworkInfo[I];
1256 else
1257 *vmBuf++ = 0;
1258 }
1259
1260 addr = vmfrm->svc_dbgInfo_addr;
1261 for ( I = 0; I < VM_VM_SVC_DBGINFO_SIZE; I++ )
1262 *vmBuf++ = *addr++;
1263
1264 kal_prompt_trace(MOD_L1SP, "vmBuf tail %x", vmBuf);
1265}
1266#endif
1267
1268void vmFormatter_amr(uint16 *vmBuf, Sal_VM_Frame *vmfrm)
1269{
1270 volatile uint16 *addr;
1271 uint16 I, sc_mode, sd_mode, sc_len, sd_len;
1272 uint32 J;
1273 uint16 sc_mode_invalid = 0;
1274
1275 sc_mode = vmfrm->enc_mode;
1276 sd_mode = vmfrm->dec_mode;
1277 if ((VM_CodIsAMR(sc_mode)) == false)
1278 {
1279 sc_mode = sd_mode;
1280 sc_mode_invalid = 1;
1281 }
1282
1283 sc_len = AM_GetSpeechPatternLength(sc_mode);
1284 //ASSERT_REBOOT( sc_len > 0 );
1285 sd_len = AM_GetSpeechPatternLength(sd_mode);
1286 //ASSERT_REBOOT( sd_len > 0 );
1287
1288 //[0:0]: UL on
1289 //[6:1]: UL mode
1290 //[10:7]: TX type
1291 //[11:11]: (no use) SP flag
1292 //[13:12]: Call mode
1293 if (sc_mode_invalid)
1294 {
1295 I = 0; // Tx: NO_DATA
1296 }
1297 else
1298 {
1299 I = vmfrm->enc_hdr & 0x3; // Tx: bit0, bit1
1300 }
1301 vm.control_1 = (I << 7) | (sc_mode << 1) | (vm.control_1 & 1);
1302
1303 // if Call mode = 2G, vm.control_1 = vm.control_1 | 0x0000;
1304 if (L1SP_GetState() == L1SP_STATE_4G_SPEECH_ON)
1305 vm.control_1 = vm.control_1 | 0x3000; // Call mode = 4G
1306 else if (SAL_3G_Mode())
1307 vm.control_1 = vm.control_1 | 0x1000; // Call mode = 3G
1308
1309 //[0:0]: DL on
1310 //[6:1]: DL mode
1311 //[10:7]: RX type
1312 //[15:11]: (no use) [12:11] SID flag, [13] TAF, [14] UFI, [15] BFI
1313 I = (vmfrm->dec_hdr & 0xE) >> 1; // Rx: bit1, bit2, bit3
1314 vm.control_2 = (I << 7) | (sd_mode << 1) | (vm.control_2 & 1);
1315
1316 kal_prompt_trace(MOD_L1SP, "vmBuf head %x", vmBuf);
1317
1318 *vmBuf++ = VM_VM_MAGIC_HEADER;
1319 J = L1SP_GetState();
1320 I = (uint16)( ( VM_VM_DBGINFO_TOTAL_SIZE << 3 ) | J);
1321 *vmBuf++ = I;
1322 *vmBuf++ = VM_VM_RECORD_FLAG;
1323 *vmBuf++ = 0; //reset EPL band
1324 J = fma_get_glb_ts() & 0xFFFFFFFF;
1325#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1326 if ( g_bNeedExtraLog )
1327 MD_TRC_VM_SP3G_VM_L1T(J);
1328#endif
1329 I = (uint16)(J & 0xFFFF);
1330 *vmBuf++ = I;
1331 I = (uint16)(J >> 16);
1332 *vmBuf++ = I;
1333 vm.vm_counter++;
1334
1335 //Chip ID
1336 vm.control_3 = VM_CHIP_ID;
1337
1338 //[1:0]: DL frm cnt
1339 //[7:2]: DL2 mode
1340 //[11:8]: DL2 RX type
1341 //[13:12]: Codec band
1342 //[15:14]: Expert mode (By VLP)
1343 vm.control_4 = (vmfrm->dec_frm_num & 0x3) | ((sd_mode & 0x3F) << 2) | ((vmfrm->dec_hdr_1 & 0xE) << 8) | ((SAL_VM_Get_CodBand() & 0x3) << 12);
1344
1345 //[15:0]: TS control
1346 vm.control_5 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_CTRL);
1347
1348 //[7:0]: TS target scale
1349 //[12:8]: TS max scale
1350 vm.control_6 = (SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_TARGET_SCALE) & 0xFF) | ((SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_MAX_SCALE) & 0x1F) << 8);
1351
1352 //[10:0]: TS output size 1
1353 vm.control_7 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_OUTPUT_SIZE_1);
1354
1355 //[10:0]: TS output size 2
1356 vm.control_8 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_OUTPUT_SIZE_2);
1357
1358 // record vm control value
1359 *vmBuf++ = vm.control_1;
1360 *vmBuf++ = vm.control_2;
1361 *vmBuf++ = vm.control_3;
1362 *vmBuf++ = vm.control_4;
1363 *vmBuf++ = vm.control_5;
1364 *vmBuf++ = vm.control_6;
1365 *vmBuf++ = vm.control_7;
1366 *vmBuf++ = vm.control_8;
1367 *vmBuf++ = vm.control_9;
1368 *vmBuf++ = vm.control_10;
1369
1370 // record UL data
1371 vm.sc_len = 0;
1372 if ( vm.control_1 & 1 )
1373 {
1374 addr = vmfrm->enc_hb_addr;
1375 for ( I = 0; I < sc_len; I++ )
1376 {
1377 *vmBuf++ = *addr++;
1378 if (L1SP_GetState() == L1SP_STATE_2G_SPEECH_ON)
1379 addr++;
1380 }
1381 vm.sc_len += sc_len;
1382 }
1383
1384 // record DL data
1385 vm.sd_len = 0;
1386 if ( vm.control_2 & 1 )
1387 {
1388 addr = vmfrm->dec_hb_addr;
1389 for ( I = 0; I < sd_len; I++ )
1390 {
1391 *vmBuf++ = *addr++;
1392 if (L1SP_GetState() == L1SP_STATE_2G_SPEECH_ON)
1393 addr++;
1394 }
1395 vm.sd_len += sd_len;
1396
1397 if (vmfrm->dec_frm_num == 2)
1398 {
1399 addr = vmfrm->dec_hb_addr_1;
1400 for ( I = 0; I < sd_len; I++ )
1401 {
1402 *vmBuf++ = *addr++;
1403 if (L1SP_GetState() == L1SP_STATE_2G_SPEECH_ON)
1404 addr++;
1405 }
1406 vm.sd_len += sd_len;
1407 }
1408 }
1409
1410 kal_prompt_trace(MOD_L1SP, "Formatter_AMR SC Len= %d, SD Len= %d, Dec_Cnt= %d", vm.sc_len, vm.sd_len, vmfrm->dec_frm_num);
1411
1412 // Debug info
1413 addr = vmfrm->dbgInfo_addr;
1414 for ( I = 0; I < VM_VM_SCH_DBGINFO_SIZE; I++ )
1415 *vmBuf++ = *addr++;
1416
1417 addr = vmfrm->enh_dbgInfo_addr;
1418 for ( I = 0; I < VM_VM_ENH_DBGINFO_SIZE; I++ )
1419 *vmBuf++ = *addr++;
1420
1421 for (I = 0; I < VM_VM_DRV_DBGINFO_SIZE; I++)
1422 {
1423 if (I < VM_3G_NETWORK_INFO_LEN)
1424 *vmBuf++ = vm3GNetworkInfo[I];
1425 else
1426 *vmBuf++ = 0;
1427 }
1428
1429 addr = vmfrm->svc_dbgInfo_addr;
1430 for ( I = 0; I < VM_VM_SVC_DBGINFO_SIZE; I++ )
1431 *vmBuf++ = *addr++;
1432
1433 kal_prompt_trace(MOD_L1SP, "vmBuf tail %x", vmBuf);
1434}
1435
1436void vmFormatter_4g(uint16 *vmBuf, Sal_VM_Frame *vmfrm)
1437{
1438#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
1439 if ( SP4G_IsGCodecMode() )
1440 {
1441 vmFormatter_gseries(vmBuf, vmfrm);
1442 return;
1443 }
1444#endif
1445
1446#if defined(__EVS_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
1447 if (VM_CodIsEVS(vmfrm->dec_mode) == true)
1448 {
1449 vmFormatter_evs(vmBuf, vmfrm);
1450 return;
1451 }
1452#endif
1453
1454 vmFormatter_amr(vmBuf, vmfrm);
1455}
1456
1457void vmFormatter_c2k(uint16 *vmBuf, Sal_VM_Frame *vmfrm)
1458{
1459 volatile uint16 *addr;
1460 uint16 I, sc_mode, sd_mode, sc_len, sd_len;
1461 uint32 J;
1462 uint16 sc_mode_invalid = 0;
1463
1464 sc_mode = vmfrm->enc_mode;
1465 sd_mode = vmfrm->dec_mode;
1466 if (sc_mode != sd_mode)
1467 {
1468 sc_mode = sd_mode;
1469 sc_mode_invalid = 1;
1470 }
1471
1472 sc_len = AM_GetSpeechPatternLength(sc_mode);
1473 //ASSERT_REBOOT( sc_len > 0 );
1474 sd_len = AM_GetSpeechPatternLength(sd_mode);
1475 //ASSERT_REBOOT( sd_len > 0 );
1476
1477 //[0:0]: UL on
1478 //[6:1]: UL mode
1479 //[10:7]: TX type
1480 //[11:11]: (no use) SP flag
1481 //[13:12]: Call mode
1482 if (sc_mode_invalid)
1483 {
1484 I = 0; // Tx: NO_DATA
1485 }
1486 else
1487 {
1488 I = vmfrm->enc_hdr; // Tx
1489 }
1490 vm.control_1 = (I << 7) | (sc_mode << 1) | (vm.control_1 & 1);
1491 vm.control_1 = vm.control_1 | 0x2000; // Call mode = C2K
1492
1493 //[0:0]: DL on
1494 //[6:1]: DL mode
1495 //[10:7]: RX type
1496 //[15:11]: (no use) [12:11] SID flag, [13] TAF, [14] UFI, [15] BFI
1497 I = vmfrm->dec_hdr; // Rx
1498 vm.control_2 = (I << 7) | (sd_mode << 1) | (vm.control_2 & 1);
1499
1500 kal_prompt_trace(MOD_L1SP, "vmBuf head %x", vmBuf);
1501
1502 *vmBuf++ = VM_VM_MAGIC_HEADER;
1503 J = L1SP_GetState();
1504 I = (uint16)( ( VM_VM_DBGINFO_TOTAL_SIZE << 3 ) | J);
1505 *vmBuf++ = I;
1506 *vmBuf++ = VM_VM_RECORD_FLAG;
1507 *vmBuf++ = 0; //reset EPL band
1508 J = fma_get_glb_ts() & 0xFFFFFFFF;
1509#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1510 // TODO: c2k [trace]
1511#endif
1512 I = (uint16)(J & 0xFFFF);
1513 *vmBuf++ = I;
1514 I = (uint16)(J >> 16);
1515 *vmBuf++ = I;
1516 vm.vm_counter++;
1517
1518 //Chip ID
1519 vm.control_3 = VM_CHIP_ID;
1520
1521 //[1:0]: DL frm cnt
1522 //[7:2]: DL2 mode
1523 //[11:8]: DL2 RX type
1524 //[13:12]: Codec band
1525 //[15:14]: Expert mode (By VLP)
1526 vm.control_4 = (vmfrm->dec_frm_num & 0x3) | ((sd_mode & 0x3F) << 2) | ((vmfrm->dec_hdr_1 & 0xE) << 8) | ((SAL_VM_Get_CodBand() & 0x3) << 12);
1527
1528 //[15:0]: TS control
1529 vm.control_5 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_CTRL);
1530
1531 //[7:0]: TS target scale
1532 //[12:8]: TS max scale
1533 vm.control_6 = (SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_TARGET_SCALE) & 0xFF) | ((SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_MAX_SCALE) & 0x1F) << 8);
1534
1535 //[10:0]: TS output size 1
1536 vm.control_7 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_OUTPUT_SIZE_1);
1537
1538 //[10:0]: TS output size 2
1539 vm.control_8 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_OUTPUT_SIZE_2);
1540
1541 // record vm control value
1542 *vmBuf++ = vm.control_1;
1543 *vmBuf++ = vm.control_2;
1544 *vmBuf++ = vm.control_3;
1545 *vmBuf++ = vm.control_4;
1546 *vmBuf++ = vm.control_5;
1547 *vmBuf++ = vm.control_6;
1548 *vmBuf++ = vm.control_7;
1549 *vmBuf++ = vm.control_8;
1550 *vmBuf++ = vm.control_9;
1551 *vmBuf++ = vm.control_10;
1552
1553 // record UL data
1554 vm.sc_len = 0;
1555 if ( vm.control_1 & 1 )
1556 {
1557 addr = vmfrm->enc_hb_addr;
1558 for ( I = 0; I < sc_len; I++ )
1559 {
1560 *vmBuf++ = *addr++;
1561 }
1562 vm.sc_len += sc_len;
1563 }
1564
1565 // record DL data
1566 vm.sd_len = 0;
1567 if ( vm.control_2 & 1 )
1568 {
1569 addr = vmfrm->dec_hb_addr;
1570 for ( I = 0; I < sd_len; I++ )
1571 {
1572 *vmBuf++ = *addr++;
1573 }
1574 vm.sd_len += sd_len;
1575
1576 if (vmfrm->dec_frm_num == 2)
1577 {
1578 addr = vmfrm->dec_hb_addr_1;
1579 for ( I = 0; I < sd_len; I++ )
1580 {
1581 *vmBuf++ = *addr++;
1582 }
1583 vm.sd_len += sd_len;
1584 }
1585 }
1586
1587 kal_prompt_trace(MOD_L1SP, "Formatter_C2K SC Len= %d, SD Len= %d, Dec_Cnt= %d", vm.sc_len, vm.sd_len, vmfrm->dec_frm_num);
1588
1589 // Debug info
1590 addr = vmfrm->dbgInfo_addr;
1591 for ( I = 0; I < VM_VM_SCH_DBGINFO_SIZE; I++ )
1592 *vmBuf++ = *addr++;
1593
1594 addr = vmfrm->enh_dbgInfo_addr;
1595 for ( I = 0; I < VM_VM_ENH_DBGINFO_SIZE; I++ )
1596 *vmBuf++ = *addr++;
1597
1598 for (I = 0; I < VM_VM_DRV_DBGINFO_SIZE; I++)
1599 {
1600 if (I < VM_3G_NETWORK_INFO_LEN)
1601 *vmBuf++ = vm3GNetworkInfo[I];
1602 else
1603 *vmBuf++ = 0;
1604 }
1605
1606 addr = vmfrm->svc_dbgInfo_addr;
1607 for ( I = 0; I < VM_VM_SVC_DBGINFO_SIZE; I++ )
1608 *vmBuf++ = *addr++;
1609
1610 kal_prompt_trace(MOD_L1SP, "vmBuf tail %x", vmBuf);
1611}
1612
1613void vmFormatter_standby(uint16 *vmBuf, Sal_VM_Frame *vmfrm)
1614{
1615 volatile uint16 *addr;
1616 uint16 I, sc_mode, sd_mode, sc_len, sd_len;
1617 uint32 J;
1618 uint16 sc_mode_invalid = 0;
1619
1620 sc_mode = vmfrm->enc_mode;
1621 sd_mode = vmfrm->dec_mode;
1622 if ((VM_CodIsAMR(sc_mode)) == false)
1623 {
1624 sc_mode = sd_mode;
1625 sc_mode_invalid = 1;
1626 }
1627
1628 sc_len = AM_GetSpeechPatternLength(sc_mode);
1629 //ASSERT_REBOOT( sc_len > 0 );
1630 sd_len = AM_GetSpeechPatternLength(sd_mode);
1631 //ASSERT_REBOOT( sd_len > 0 );
1632
1633 //[0:0]: UL on
1634 //[6:1]: UL mode
1635 //[10:7]: TX type
1636 //[11:11]: (no use) SP flag
1637 //[13:12]: Call mode
1638 if (sc_mode_invalid)
1639 {
1640 I = 0; // Tx: NO_DATA
1641 }
1642 else
1643 {
1644 I = vmfrm->enc_hdr & 0x3; // Tx: bit0, bit1
1645 }
1646 vm.control_1 = (I << 7) | (sc_mode << 1) | (vm.control_1 & 1);
1647 vm.control_1 = vm.control_1 | 0x1000; // Call mode = 3G
1648
1649 //[0:0]: DL on
1650 //[6:1]: DL mode
1651 //[10:7]: RX type
1652 //[15:11]: (no use) [12:11] SID flag, [13] TAF, [14] UFI, [15] BFI
1653 I = (vmfrm->dec_hdr & 0xE) >> 1; // Rx: bit1, bit2, bit3
1654 vm.control_2 = (I << 7) | (sd_mode << 1) | (vm.control_2 & 1);
1655
1656 kal_prompt_trace(MOD_L1SP, "vmBuf head %x", vmBuf);
1657
1658 *vmBuf++ = VM_VM_MAGIC_HEADER;
1659 J = L1SP_GetState();
1660 I = (uint16)( ( VM_VM_DBGINFO_TOTAL_SIZE << 3 ) | J);
1661 *vmBuf++ = I;
1662 *vmBuf++ = VM_VM_RECORD_FLAG;
1663 *vmBuf++ = 0; //reset EPL band
1664 J = fma_get_glb_ts() & 0xFFFFFFFF;
1665#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
1666 if ( g_bNeedExtraLog )
1667 MD_TRC_VM_SP3G_VM_L1T(J);
1668#endif
1669 I = (uint16)(J & 0xFFFF);
1670 *vmBuf++ = I;
1671 I = (uint16)(J >> 16);
1672 *vmBuf++ = I;
1673 vm.vm_counter++;
1674
1675 //Chip ID
1676 vm.control_3 = VM_CHIP_ID;
1677
1678 //[1:0]: DL frm cnt
1679 //[7:2]: DL2 mode
1680 //[11:8]: DL2 RX type
1681 //[13:12]: Codec band
1682 //[15:14]: Expert mode (By VLP)
1683 vm.control_4 = (vmfrm->dec_frm_num & 0x3) | ((sd_mode & 0x3F) << 2) | ((vmfrm->dec_hdr_1 & 0xE) << 8) | ((SAL_VM_Get_CodBand() & 0x3) << 12);
1684
1685 //[15:0]: TS control
1686 vm.control_5 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_CTRL);
1687
1688 //[7:0]: TS target scale
1689 //[12:8]: TS max scale
1690 vm.control_6 = (SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_TARGET_SCALE) & 0xFF) | ((SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_MAX_SCALE) & 0x1F) << 8);
1691
1692 //[10:0]: TS output size 1
1693 vm.control_7 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_OUTPUT_SIZE_1);
1694
1695 //[10:0]: TS output size 2
1696 vm.control_8 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_OUTPUT_SIZE_2);
1697
1698 // record vm control value
1699 *vmBuf++ = vm.control_1;
1700 *vmBuf++ = vm.control_2;
1701 *vmBuf++ = vm.control_3;
1702 *vmBuf++ = vm.control_4;
1703 *vmBuf++ = vm.control_5;
1704 *vmBuf++ = vm.control_6;
1705 *vmBuf++ = vm.control_7;
1706 *vmBuf++ = vm.control_8;
1707 *vmBuf++ = vm.control_9;
1708 *vmBuf++ = vm.control_10;
1709
1710 // record UL data
1711 vm.sc_len = 0;
1712 if ( vm.control_1 & 1 )
1713 {
1714 addr = vmfrm->enc_hb_addr;
1715 for ( I = 0; I < sc_len; I++ )
1716 {
1717 *vmBuf++ = *addr++;
1718 }
1719 vm.sc_len += sc_len;
1720 }
1721
1722 // record DL data
1723 vm.sd_len = 0;
1724 if ( vm.control_2 & 1 )
1725 {
1726 addr = vmfrm->dec_hb_addr;
1727 for ( I = 0; I < sd_len; I++ )
1728 {
1729 *vmBuf++ = *addr++;
1730 }
1731 vm.sd_len += sd_len;
1732
1733 if (vmfrm->dec_frm_num == 2)
1734 {
1735 addr = vmfrm->dec_hb_addr_1;
1736 for ( I = 0; I < sd_len; I++ )
1737 {
1738 *vmBuf++ = *addr++;
1739 }
1740 vm.sd_len += sd_len;
1741 }
1742 }
1743
1744 kal_prompt_trace(MOD_L1SP, "Formatter_Standby SC Len= %d, SD Len= %d, Dec_Cnt= %d", vm.sc_len, vm.sd_len, vmfrm->dec_frm_num);
1745
1746 // Debug info
1747 addr = vmfrm->dbgInfo_addr;
1748 for ( I = 0; I < VM_VM_SCH_DBGINFO_SIZE; I++ )
1749 *vmBuf++ = *addr++;
1750
1751 addr = vmfrm->enh_dbgInfo_addr;
1752 for ( I = 0; I < VM_VM_ENH_DBGINFO_SIZE; I++ )
1753 *vmBuf++ = *addr++;
1754
1755 for (I = 0; I < VM_VM_DRV_DBGINFO_SIZE; I++)
1756 {
1757 if (I < VM_3G_NETWORK_INFO_LEN)
1758 *vmBuf++ = vm3GNetworkInfo[I];
1759 else
1760 *vmBuf++ = 0;
1761 }
1762
1763 addr = vmfrm->svc_dbgInfo_addr;
1764 for ( I = 0; I < VM_VM_SVC_DBGINFO_SIZE; I++ )
1765 *vmBuf++ = *addr++;
1766
1767 kal_prompt_trace(MOD_L1SP, "vmBuf tail %x", vmBuf);
1768}
1769
1770void vmFormatter_vm(uint16 *vmBuf, Sal_VM_Frame *vmfrm)
1771{
1772 volatile uint16 *addr;
1773 uint16 I, sc_mode, sd_mode, sc_len, sd_len;
1774 uint32 J;
1775 uint16 sc_mode_invalid = 0;
1776
1777 sc_mode = vmfrm->enc_mode;
1778 sd_mode = vmfrm->dec_mode;
1779 if (sc_mode != sd_mode)
1780 {
1781 sc_mode = sd_mode;
1782 sc_mode_invalid = 1;
1783 }
1784
1785 sc_len = AM_GetSpeechPatternLength(sc_mode);
1786 //ASSERT_REBOOT( sc_len > 0 );
1787 sd_len = AM_GetSpeechPatternLength(sd_mode);
1788 //ASSERT_REBOOT( sd_len > 0 );
1789
1790 //[0:0]: UL on
1791 //[6:1]: UL mode
1792 //[10:7]: (no use) TX type
1793 //[11:11]: SP flag
1794 //[13:12]: Call mode
1795 if (sc_mode_invalid)
1796 {
1797 I = 0; // sp_flag: Silence
1798 }
1799 else
1800 {
1801 I = (vmfrm->enc_hdr & 0x2) >> 1; // sp_flag: bit1
1802 }
1803 vm.control_1 = (I << 11) | (sc_mode << 1) | (vm.control_1 & 1);
1804 // if Call mode = 2G, vm.control_1 = vm.control_1 | 0x0000;
1805
1806 //[0:0]: DL on
1807 //[6:1]: DL mode
1808 //[10:7]: (no use) RX type
1809 //[15:11]: [12:11] SID flag, [13] TAF, [14] UFI, [15] BFI
1810 I = (vmfrm->dec_hdr & 0x3E) >> 1; // BFI, UFI, TAF, SID
1811 vm.control_2 = (I << 11) | (sd_mode << 1) | (vm.control_2 & 1);
1812
1813 kal_prompt_trace(MOD_L1SP, "vmBuf head %x", vmBuf);
1814
1815 *vmBuf++ = VM_VM_MAGIC_HEADER;
1816 J = L1SP_GetState();
1817 I = (uint16)( ( VM_VM_DBGINFO_TOTAL_SIZE << 3 ) | J);
1818 *vmBuf++ = I;
1819 *vmBuf++ = VM_VM_RECORD_FLAG;
1820 *vmBuf++ = 0; //reset EPL band
1821 J = fma_get_glb_ts() & 0xFFFFFFFF;
1822 I = (uint16)(J & 0xFFFF);
1823 *vmBuf++ = I;
1824 I = (uint16)(J >> 16);
1825 *vmBuf++ = I;
1826 vm.vm_counter++;
1827
1828 //Chip ID
1829 vm.control_3 = VM_CHIP_ID;
1830
1831 //[1:0]: DL frm cnt
1832 //[7:2]: DL2 mode
1833 //[11:8]: DL2 RX type
1834 //[13:12]: Codec band
1835 //[15:14]: Expert mode (By VLP)
1836 vm.control_4 = (vmfrm->dec_frm_num & 0x3) | ((sd_mode & 0x3F) << 2) | ((vmfrm->dec_hdr_1 & 0xE) << 8) | ((SAL_VM_Get_CodBand() & 0x3) << 12);
1837
1838 //[15:0]: TS control
1839 vm.control_5 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_CTRL);
1840
1841 //[7:0]: TS target scale
1842 //[12:8]: TS max scale
1843 vm.control_6 = (SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_TARGET_SCALE) & 0xFF) | ((SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_MAX_SCALE) & 0x1F) << 8);
1844
1845 //[10:0]: TS output size 1
1846 vm.control_7 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_OUTPUT_SIZE_1);
1847
1848 //[10:0]: TS output size 2
1849 vm.control_8 = SAL_VM_Get_TS_Info(SAL_VM_TS_INFO_OUTPUT_SIZE_2);
1850
1851 // record vm control value
1852 *vmBuf++ = vm.control_1;
1853 *vmBuf++ = vm.control_2;
1854 *vmBuf++ = vm.control_3;
1855 *vmBuf++ = vm.control_4;
1856 *vmBuf++ = vm.control_5;
1857 *vmBuf++ = vm.control_6;
1858 *vmBuf++ = vm.control_7;
1859 *vmBuf++ = vm.control_8;
1860 *vmBuf++ = vm.control_9;
1861 *vmBuf++ = vm.control_10;
1862
1863 // record UL data
1864 vm.sc_len = 0;
1865 if ( vm.control_1 & 1 )
1866 {
1867 addr = vmfrm->enc_hb_addr;
1868 for ( I = 0; I < sc_len; I++ )
1869 {
1870 *vmBuf++ = *addr++;
1871 if (L1SP_GetState() == L1SP_STATE_2G_SPEECH_ON)
1872 addr++;
1873 }
1874 vm.sc_len += sc_len;
1875 }
1876
1877 // record DL data
1878 vm.sd_len = 0;
1879 if ( vm.control_2 & 1 )
1880 {
1881 addr = vmfrm->dec_hb_addr;
1882 for ( I = 0; I < sd_len; I++ )
1883 {
1884 *vmBuf++ = *addr++;
1885 if (L1SP_GetState() == L1SP_STATE_2G_SPEECH_ON)
1886 addr++;
1887 }
1888 vm.sd_len += sd_len;
1889
1890 if (vmfrm->dec_frm_num == 2)
1891 {
1892 addr = vmfrm->dec_hb_addr_1;
1893 for ( I = 0; I < sd_len; I++ )
1894 {
1895 *vmBuf++ = *addr++;
1896 if (L1SP_GetState() == L1SP_STATE_2G_SPEECH_ON)
1897 addr++;
1898 }
1899 vm.sd_len += sd_len;
1900 }
1901 }
1902
1903 kal_prompt_trace(MOD_L1SP, "Formatter_VM SC Len= %d, SD Len= %d, Dec_Cnt= %d", vm.sc_len, vm.sd_len, vmfrm->dec_frm_num);
1904
1905 // Debug info
1906 addr = vmfrm->dbgInfo_addr;
1907 for ( I = 0; I < VM_VM_SCH_DBGINFO_SIZE; I++ )
1908 *vmBuf++ = *addr++;
1909
1910 addr = vmfrm->enh_dbgInfo_addr;
1911 for ( I = 0; I < VM_VM_ENH_DBGINFO_SIZE; I++ )
1912 *vmBuf++ = *addr++;
1913
1914 for (I = 0; I < VM_VM_DRV_DBGINFO_SIZE; I++)
1915 {
1916 if (I < VM_3G_NETWORK_INFO_LEN)
1917 *vmBuf++ = vm3GNetworkInfo[I];
1918 else
1919 *vmBuf++ = 0;
1920 }
1921
1922 addr = vmfrm->svc_dbgInfo_addr;
1923 for ( I = 0; I < VM_VM_SVC_DBGINFO_SIZE; I++ )
1924 *vmBuf++ = *addr++;
1925
1926 kal_prompt_trace(MOD_L1SP, "vmBuf tail %x", vmBuf);
1927}
1928
1929void vmFormatter_2g(uint16 *vmBuf, Sal_VM_Frame *vmfrm)
1930{
1931 if (VM_CodIsAMR(vmfrm->dec_mode) == true)
1932 {
1933 vmFormatter_amr(vmBuf, vmfrm);
1934 }
1935 else
1936 {
1937 vmFormatter_vm(vmBuf, vmfrm);
1938 }
1939}
1940
1941/* ------------------------------------------------------------------------------ */
1942/**
1943 @buf1: pointer to pcm buf1,
1944 @len1:length of buf1, unit is word(2byte)
1945 @buf2:pointer to pcm buf2
1946 @len2: length of buf2. unit is word(2byte)
1947*/
1948void VmRec_GetReadBufs(kal_uint32 *add1, kal_uint16 *len1, kal_uint32 *add2, kal_uint16 *len2)
1949{
1950 if (vm.pOutputBufWrite >= vm.pOutputBufRead) // write > read, 1 buf segment
1951 {
1952 *add1 = (kal_uint32)(&vmRecOutputBuf[vm.pOutputBufRead]);
1953 *len1 = (vm.pOutputBufWrite - vm.pOutputBufRead);
1954 *add2 = 0;
1955 *len2 = 0;
1956 }
1957 else //write < read, 2 buf segment
1958 {
1959 *add1 = (kal_uint32)(&vmRecOutputBuf[vm.pOutputBufRead]);
1960 *len1 = (vm.outputBufSize - vm.pOutputBufRead);
1961 *add2 = (kal_uint32)(vmRecOutputBuf);
1962 *len2 = (vm.pOutputBufWrite);
1963 }
1964}
1965
1966/**
1967 @len: unit is word
1968*/
1969void VmRec_ReadDataDone(uint16 len)
1970{
1971 vm.pOutputBufRead += len;
1972 if ( vm.pOutputBufRead >= vm.outputBufSize)
1973 vm.pOutputBufRead = vm.pOutputBufRead - vm.outputBufSize;
1974}
1975
1976//use this function instead of Media_WriteDataDone to avoid media.waiting false usage
1977int32 vmRec_queryOutputBufFreeSpace(void)
1978{
1979 int32 count;
1980
1981 count = vm.pOutputBufRead + vm.outputBufSize - vm.pOutputBufWrite - 1;
1982
1983 if ( count >= vm.outputBufSize )
1984 count -= vm.outputBufSize;
1985 return count;
1986}
1987
1988void vmRec_getWriteBuffer(uint16 **buffer, uint32 *bufLen)
1989{
1990 int32 count;
1991
1992 if ( vm.pOutputBufRead > vm.pOutputBufWrite )
1993 count = vm.pOutputBufRead - vm.pOutputBufWrite - 1;
1994 else if ( vm.pOutputBufRead == 0 )
1995 count = vm.outputBufSize - vm.pOutputBufWrite - 1;
1996 else
1997 count = vm.outputBufSize - vm.pOutputBufWrite;
1998
1999 *buffer = &vmRecOutputBuf[vm.pOutputBufWrite];
2000 *bufLen = (uint32)count;
2001}
2002
2003static void vmRec_writeDataDone(uint32 len)
2004{
2005 vm.pOutputBufWrite += len;
2006 if ( vm.pOutputBufWrite >= vm.outputBufSize)
2007 vm.pOutputBufWrite = vm.pOutputBufWrite - vm.outputBufSize;
2008}
2009
2010static void vocWriteVocToCatcher(uint16 vmLen, uint16 *vmBuf)
2011{
2012 uint32 len = vmLen * 2;
2013 uint16 *buf = vmBuf;
2014
2015 while (len > 1000)
2016 {
2017 tst_vc_response(TVCI_VM_LOGGING, (const kal_uint8*)buf, 1000);
2018 buf += 500;
2019 len -= 1000;
2020 }
2021 tst_vc_response(TVCI_VM_LOGGING, (const kal_uint8*)buf, len);
2022}
2023
2024static void vmRec_writeVmToOutputBuf(uint16 vmLen, uint16 *vmBuf) // a frame of VM must be written to MB
2025{
2026 uint16 *toPtr;
2027 uint32 segment, I;
2028
2029 vmRec_getWriteBuffer( &toPtr, &segment );
2030
2031 if (segment > vmLen)
2032 segment = vmLen;
2033
2034 for ( I = segment ; I > 0 ; I-- ) {
2035 *toPtr++ = *vmBuf++;
2036 }
2037
2038 vmRec_writeDataDone( segment );
2039
2040 // second segment
2041 vmLen -= segment; // unprocess length
2042 if (vmLen > 0 )
2043 {
2044 vmRec_getWriteBuffer( &toPtr, &segment );
2045
2046 if (segment > vmLen)
2047 segment = vmLen;
2048
2049 for ( I = segment ; I > 0 ; I-- ) {
2050 *toPtr++ = *vmBuf++;
2051 }
2052 vmRec_writeDataDone( segment );
2053 }
2054 return;
2055}
2056
2057static void voc4WayPcmRecord( volatile uint16* ul_addr, uint16 ul_len, volatile uint16* dl_addr, uint16 dl_len)
2058{
2059 uint16 *buf;
2060
2061 buf = vm.pcmBuf;
2062 // header for record 1st set of UL-DL PCM data
2063 *buf++ = (vm.vm_lost_count << 8) + vm.pcm_lost_count;
2064 *buf++ = vm.vm_counter ;
2065
2066 // make it interleave
2067 // Uplink
2068 EMI_ReadFromDSP((uint16*)buf, ul_addr, ul_len);
2069 buf += ul_len;
2070
2071 // Downlink
2072 EMI_ReadFromDSP((uint16*)buf, dl_addr, dl_len);
2073
2074 buf = vm.pcmBuf;
2075
2076 vocWriteVocToCatcher(ul_len + dl_len + 2, buf);
2077}
2078
2079static void vm4WayPcmRecord(volatile uint16 *ul_addr, uint16 ul_len, volatile uint16 *dl_addr, uint16 dl_len)
2080{
2081 uint32 I, tmp = 0;
2082 uint16 *buf, *mBuf;
2083 uint16 logsize;
2084
2085 logsize = ul_len + dl_len + 2;
2086
2087 buf = vm.pcmBuf;
2088 // header for record 1st set of UL-DL PCM data
2089 *buf++ = (vm.vm_lost_count << 8) + vm.pcm_lost_count;
2090 *buf++ = vm.vm_counter ;
2091
2092 // Uplink
2093 EMI_ReadFromDSP((uint16*)buf, ul_addr, ul_len);
2094 buf += ul_len;
2095
2096 // Downlink
2097 EMI_ReadFromDSP((uint16*)buf, dl_addr, dl_len);
2098
2099 buf = vm.pcmBuf;
2100
2101 vmRec_getWriteBuffer( &mBuf, &tmp );
2102 if ( tmp > logsize )
2103 tmp = logsize;
2104 //for( I = tmp ; I > 0 ; I-- ) {
2105 // *mBuf++ = *buf++;
2106 //}
2107 kal_mem_cpy(mBuf, buf, tmp << 1);
2108 buf += tmp;
2109 mBuf += tmp;
2110
2111 vmRec_writeDataDone(tmp);
2112
2113 tmp = logsize - tmp; // tmp is size did not write to Buffer
2114 if ( (int32)tmp > 0 )
2115 {
2116 vmRec_getWriteBuffer( &mBuf, &I );
2117
2118 if (I >= tmp)
2119 {
2120 //for( I = tmp ; I > 0 ; I--) {
2121 // *mBuf++ = *buf++;
2122 //}
2123 kal_mem_cpy(mBuf, buf, tmp << 1);
2124 buf += tmp;
2125 mBuf += tmp;
2126
2127 vmRec_writeDataDone( tmp );
2128 }
2129 else
2130 {
2131 MD_TRC_VM_REC_HISR_PCM_DATA_LOST(0);
2132 }
2133 }
2134}
2135
2136static void vmRefMic_AGC_PcmRecord( bool isToVoc, volatile uint16 *addr, uint16 len )
2137{
2138 uint32 I, tmp = 0;
2139 uint16 *buf, *mBuf;
2140 uint16 logsize;
2141
2142 logsize = len + 2 + 2;
2143
2144 buf = vm.pcmBuf;
2145 *buf++ = (vm.vm_lost_count << 8) + vm.pcm_lost_count;
2146 *buf++ = vm.vm_counter ;
2147
2148 { //RefMic
2149 EMI_ReadFromDSP((uint16*)buf, addr, len);
2150 buf += len;
2151 *buf++ = SAL_AGC_GetSWGain(0);
2152 *buf = SAL_AGC_GetSWGain(1);
2153 }
2154
2155 buf = vm.pcmBuf;
2156
2157 if (isToVoc)
2158 {
2159 vocWriteVocToCatcher(logsize, buf);
2160 }
2161 else // normal vm process
2162 {
2163 vmRec_getWriteBuffer( &mBuf, &tmp );
2164 if ( tmp > logsize )
2165 tmp = logsize;
2166 kal_mem_cpy(mBuf, buf, tmp << 1);
2167 buf += tmp;
2168 mBuf += tmp;
2169
2170 vmRec_writeDataDone(tmp);
2171
2172 tmp = logsize - tmp;
2173 if ( (int32)tmp > 0 )
2174 {
2175 vmRec_getWriteBuffer( &mBuf, &I );
2176 if (I >= tmp)
2177 {
2178 kal_mem_cpy(mBuf, buf, tmp << 1);
2179 buf += tmp;
2180 mBuf += tmp;
2181 vmRec_writeDataDone(tmp);
2182 }
2183 else
2184 {
2185 MD_TRC_VM_REC_HISR_PCM_DATA_LOST(0);
2186 }
2187 }
2188 }
2189}
2190
2191static void vmEchoRefPcmRecord( bool isToVoc, volatile uint16 *addr, uint16 len )
2192{
2193 uint32 I, tmp = 0;
2194 uint16 *buf, *mBuf;
2195 uint16 logsize;
2196
2197 logsize = len + 2;
2198
2199 buf = vm.pcmBuf;
2200 *buf++ = (vm.vm_lost_count << 8) + vm.pcm_lost_count;
2201 *buf++ = vm.vm_counter ;
2202
2203 EMI_ReadFromDSP((uint16*)buf, addr, len);
2204 buf = vm.pcmBuf;
2205
2206 if (isToVoc)
2207 {
2208 vocWriteVocToCatcher(logsize, buf);
2209 }
2210 else // normal vm process
2211 {
2212 vmRec_getWriteBuffer( &mBuf, &tmp );
2213 if ( tmp > logsize )
2214 tmp = logsize;
2215 kal_mem_cpy(mBuf, buf, tmp << 1);
2216 buf += tmp;
2217 mBuf += tmp;
2218
2219 vmRec_writeDataDone(tmp);
2220
2221 tmp = logsize - tmp;
2222 if ( (int32)tmp > 0 )
2223 {
2224 vmRec_getWriteBuffer( &mBuf, &I );
2225 if (I >= tmp)
2226 {
2227 kal_mem_cpy(mBuf, buf, tmp << 1);
2228 buf += tmp;
2229 mBuf += tmp;
2230 vmRec_writeDataDone(tmp);
2231 }
2232 else
2233 {
2234 MD_TRC_VM_REC_HISR_PCM_DATA_LOST(0);
2235 }
2236 }
2237 }
2238}
2239
2240/* ------------------------------------------------------------------------------ */
2241void vmTchPcmRecordHisr(void *param)
2242{
2243 uint16 u2VM_total_size; // VM + EPL_PCM + EPL_dummy
2244 uint16 u2VM_buffer_size; // VM
2245 uint16 u2VM_size; // Dbg Info size + EPL PCM size
2246 uint16 u2EPL_PCM_size = 0;
2247 uint16 u2EPL_dummy_size = 0;
2248 uint16 *buf;
2249 Sal_EPL_Frame eplfrm_t;
2250
2251 if (KAL_SPINLOCK_NOT_AVAILABLE == kal_take_spinlock(vm.lockId, KAL_NO_WAIT))
2252 {
2253 MD_TRC_VM_HISR_LOCK_NOT_AVALIABLE(2);
2254 goto leaveEplHisr;
2255 }
2256
2257 // dsp status check
2258 if ( vm.state != VM_STATE_RECORD )
2259 {
2260 goto leaveEplProc;
2261 }
2262
2263 // application status check
2264 if ( (false == vm.isVocOn) && (false == vm.isVmLOn))
2265 {
2266 goto leaveEplProc;
2267 }
2268
2269 SAL_EPL_GetFrame(&eplfrm_t);
2270
2271 if (vm.record_info & VM_EPL_1STSET_RECORD_FLAG) {
2272 u2EPL_PCM_size += eplfrm_t.ul_pre_len + eplfrm_t.dl_pre_len;
2273 u2EPL_dummy_size += 2;
2274 }
2275 if (vm.record_info & VM_EPL_2NDSET_RECORD_FLAG) {
2276 u2EPL_PCM_size += eplfrm_t.ul_pos_len + eplfrm_t.dl_pos_len;
2277 u2EPL_dummy_size += 2;
2278 }
2279 if (vm.record_info & VM_EPL_REFMIC_RECORD_FLAG) {
2280 u2EPL_PCM_size += eplfrm_t.ul2_pos_len;
2281 u2EPL_dummy_size += 4;
2282 }
2283 if (vm.record_info & VM_EPL_ECHOREF_RECORD_FLAG) {
2284 u2EPL_PCM_size += eplfrm_t.ul4_pos_len;
2285 u2EPL_dummy_size += 2;
2286 }
2287 if (vm.record_info & VM_EPL_3RDMIC_RECORD_FLAG) {
2288 u2EPL_PCM_size += eplfrm_t.ul3_pos_len;
2289 u2EPL_dummy_size += 2;
2290 }
2291 if (vm.record_info & VM_EPL_2NDECHOREF_RECORD_FLAG) {
2292 u2EPL_PCM_size += eplfrm_t.ul5_pos_len;
2293 u2EPL_dummy_size += 2;
2294 }
2295
2296 // handing the total size u2VM_total_size (vm + pcm buffer) in word(2byte)
2297 buf = vm.vmBuf;
2298
2299 if (buf[0] == VM_VM_MAGIC_HEADER) //already buffer VM, (normal case)
2300 {
2301 u2VM_size = VM_VM_DBGINFO_TOTAL_SIZE + u2EPL_PCM_size;
2302 u2VM_buffer_size = VM_VM_HEADER_SIZE + VM_VM_CONTROL_SIZE + vm.sc_len + vm.sd_len + VM_VM_DBGINFO_TOTAL_SIZE;
2303 kal_prompt_trace(MOD_L1SP, "TchPcmRecordHisr SC Len= %d, SD Len= %d", vm.sc_len, vm.sd_len);
2304 }
2305 else // case when previous vmbufer is missing! Save the pcm data with empty vm
2306 {
2307 u2VM_size = u2EPL_PCM_size;
2308 u2VM_buffer_size = VM_VM_HEADER_SIZE;
2309 }
2310 u2VM_total_size = u2VM_buffer_size + u2EPL_PCM_size + u2EPL_dummy_size;
2311
2312 buf[3] |= vmEPLBandSet(eplfrm_t.ul_pre_len, VM_EPL_BAND_UL0_SHIFT);
2313 buf[3] |= vmEPLBandSet(eplfrm_t.ul_pos_len, VM_EPL_BAND_UL1_SHIFT);
2314 buf[3] |= vmEPLBandSet(eplfrm_t.dl_pre_len, VM_EPL_BAND_DL0_SHIFT);
2315 buf[3] |= vmEPLBandSet(eplfrm_t.dl_pos_len, VM_EPL_BAND_DL1_SHIFT);
2316 buf[3] |= vmEPLBandSet(eplfrm_t.ul2_pos_len, VM_EPL_BAND_UL2_SHIFT);
2317 buf[3] |= vmEPLBandSet(eplfrm_t.ul4_pos_len, VM_EPL_BAND_UL4_SHIFT);
2318 buf[3] |= vmEPLBandSet(eplfrm_t.ul3_pos_len, VM_EPL_BAND_UL3_SHIFT);
2319 buf[3] |= vmEPLBandSet(eplfrm_t.ul5_pos_len, VM_EPL_BAND_UL5_SHIFT);
2320
2321 kal_prompt_trace(MOD_L1SP, "UL_PRE %d, UL_POS %d, DL_PRE %d, DL_POS %d, UL2 %d, UL3 %d, UL4 %d, UL5 %d", eplfrm_t.ul_pre_len, eplfrm_t.ul_pos_len, eplfrm_t.dl_pre_len, eplfrm_t.dl_pos_len, eplfrm_t.ul2_pos_len, eplfrm_t.ul3_pos_len, eplfrm_t.ul4_pos_len, eplfrm_t.ul5_pos_len);
2322 kal_prompt_trace(MOD_L1SP, "Band %x", buf[3]);
2323
2324 //when vm logging and VOC are both on, only send the data to vm logging to reduce log size
2325 if (vm.isVmLOn)
2326 {
2327 if (vmRec_queryOutputBufFreeSpace() < u2VM_total_size)
2328 {
2329 // drop this log and add counter
2330 vm.pcm_lost_count++;
2331 MD_TRC_VM_REC_HISR_VM_DATA_LOST(vm.vm_lost_count, 1);
2332 goto leaveEplProc;
2333 }
2334 else
2335 {
2336 uint32 timestamp;
2337 buf[0] = VM_VM_MAGIC_HEADER;
2338 buf[1] = (u2VM_size << 3) | (L1SP_GetState()) ;
2339 buf[2] |= (vm.record_info & VM_EPL_ALL_RECORD_FLAG);
2340 // buf[3] is set in previous
2341 timestamp = fma_get_glb_ts() & 0xFFFFFFFF;
2342 buf[4] = (uint16)(timestamp & 0xFFFF); // Lo
2343 buf[5] = (uint16)(timestamp >> 16); // High
2344
2345 vmRec_writeVmToOutputBuf(u2VM_buffer_size, buf);
2346
2347 //pcm bufs
2348 if (vm.record_info & VM_EPL_1STSET_RECORD_FLAG)
2349 vm4WayPcmRecord(eplfrm_t.ul_pre_buf, eplfrm_t.ul_pre_len, eplfrm_t.dl_pre_buf, eplfrm_t.dl_pre_len);
2350
2351 if (vm.record_info & VM_EPL_2NDSET_RECORD_FLAG)
2352 vm4WayPcmRecord(eplfrm_t.ul_pos_buf, eplfrm_t.ul_pos_len, eplfrm_t.dl_pos_buf, eplfrm_t.dl_pos_len);
2353
2354 if (vm.record_info & VM_EPL_REFMIC_RECORD_FLAG)
2355 vmRefMic_AGC_PcmRecord(false, eplfrm_t.ul2_pos_buf, eplfrm_t.ul2_pos_len);
2356
2357 if (vm.record_info & VM_EPL_ECHOREF_RECORD_FLAG)
2358 vmEchoRefPcmRecord(false, eplfrm_t.ul4_pos_buf, eplfrm_t.ul4_pos_len);
2359
2360 if (vm.record_info & VM_EPL_3RDMIC_RECORD_FLAG)
2361 vmEchoRefPcmRecord(false, eplfrm_t.ul3_pos_buf, eplfrm_t.ul3_pos_len);
2362
2363 if (vm.record_info & VM_EPL_2NDECHOREF_RECORD_FLAG)
2364 vmEchoRefPcmRecord(false, eplfrm_t.ul5_pos_buf, eplfrm_t.ul5_pos_len);
2365 }
2366 }
2367 else // VOC
2368 {
2369 // fill vm buffer header
2370 uint32 timestamp;
2371 buf[0] = VM_VM_MAGIC_HEADER;
2372 buf[1] = (u2VM_size << 3) | (L1SP_GetState()) ;
2373 buf[2] |= (vm.record_info & VM_EPL_ALL_RECORD_FLAG);
2374 // buf[3] is set in previous
2375 timestamp = fma_get_glb_ts() & 0xFFFFFFFF;
2376 buf[4] = (uint16)(timestamp & 0xFFFF); // Lo
2377 buf[5] = (uint16)(timestamp >> 16); // High
2378
2379 vocWriteVocToCatcher(u2VM_buffer_size, buf);
2380
2381 if (vm.record_info & VM_EPL_1STSET_RECORD_FLAG)
2382 voc4WayPcmRecord(eplfrm_t.ul_pre_buf, eplfrm_t.ul_pre_len, eplfrm_t.dl_pre_buf, eplfrm_t.dl_pre_len);
2383
2384 if (vm.record_info & VM_EPL_2NDSET_RECORD_FLAG)
2385 voc4WayPcmRecord(eplfrm_t.ul_pos_buf, eplfrm_t.ul_pos_len, eplfrm_t.dl_pos_buf, eplfrm_t.dl_pos_len);
2386
2387 if (vm.record_info & VM_EPL_REFMIC_RECORD_FLAG)
2388 vmRefMic_AGC_PcmRecord(true, eplfrm_t.ul2_pos_buf, eplfrm_t.ul2_pos_len);
2389
2390 if (vm.record_info & VM_EPL_ECHOREF_RECORD_FLAG)
2391 vmEchoRefPcmRecord(true, eplfrm_t.ul4_pos_buf, eplfrm_t.ul4_pos_len);
2392
2393 if (vm.record_info & VM_EPL_3RDMIC_RECORD_FLAG)
2394 vmEchoRefPcmRecord(true, eplfrm_t.ul3_pos_buf, eplfrm_t.ul3_pos_len);
2395
2396 if (vm.record_info & VM_EPL_2NDECHOREF_RECORD_FLAG)
2397 vmEchoRefPcmRecord(true, eplfrm_t.ul5_pos_buf, eplfrm_t.ul5_pos_len);
2398 }
2399
2400 vm.pcm_lost_count = 0;
2401 buf[0] = 0;
2402 buf[1] = 0;
2403 buf[2] = 0;
2404 buf[3] = 0;
2405
2406leaveEplProc:
2407 kal_give_spinlock(vm.lockId);
2408
2409 if (vm.vm_hdlr) {
2410 vm.vm_hdlr();
2411 }
2412
2413leaveEplHisr:
2414 return;
2415}
2416
2417void vmTchRecordHisr(void *param)
2418{
2419 uint16 u2VM_buffer_size;
2420 uint16 *vmBuf;
2421 uint8 sp_state = L1SP_GetState();
2422
2423 if (KAL_SPINLOCK_NOT_AVAILABLE == kal_take_spinlock(vm.lockId, KAL_NO_WAIT))
2424 {
2425 MD_TRC_VM_HISR_LOCK_NOT_AVALIABLE(1);
2426 goto leaveHisr;
2427 }
2428
2429 // check dsp status
2430 if ( vm.state != VM_STATE_RECORD )
2431 {
2432 goto leaveProc;
2433 }
2434
2435 // check application status
2436 if ( (false == vm.isVocOn) && (false == vm.isVmLOn))
2437 {
2438 goto leaveProc;
2439 }
2440
2441 // just logging
2442#if defined(__MA_L1__)
2443 if (!(L1SP_GetState() == L1SP_STATE_3G_SPEECH_ON || L1SP_GetState() == L1SP_STATE_3G324M_SPEECH_ON))
2444 {
2445 uint8 rx_type, tx_type, BFI;
2446 uint16 rx_debug;
2447 rx_debug = *DSP_RX_TCH_S(0, 0);
2448 tx_type = *DSP_RX_TCH_S(0, 0) & 0x3;
2449 rx_type = (rx_debug >> 1) & 0x7;
2450 BFI = (rx_debug >> 5) & 0x1; //speechBFI
2451 if ( rx_type < 3 ) //non-amr
2452 rx_type = 8 + (rx_type << 1) + BFI;
2453 BFI = (rx_debug >> 8) & 0xFF; //BER
2454 MD_TRC_L1Audio_Msg_SPEECH_FRAME( L1SP_Speech_TX_Type(tx_type), L1SP_Speech_RX_Type(rx_type), BFI);
2455 MD_TRC_L1Audio_Msg_VM_DEBUG( DP2_3G_debug_info0, DP2_3G_debug_info1, DP2_3G_debug_info7 );
2456 }
2457#endif
2458
2459 // process previous buffer
2460 vmBuf = vm.vmBuf;
2461
2462 if (vmBuf[0] == VM_VM_MAGIC_HEADER) //already buffer VM
2463 {
2464 u2VM_buffer_size = VM_VM_HEADER_SIZE + VM_VM_CONTROL_SIZE + vm.sc_len + vm.sd_len + VM_VM_DBGINFO_TOTAL_SIZE;
2465 kal_prompt_trace(MOD_L1SP, "TchRecordHisr SC Len= %d, SD Len= %d", vm.sc_len, vm.sd_len);
2466
2467 //when vm logging and VOC are both on, only send the data to vm logging to reduce log size
2468 if (vm.isVmLOn)
2469 {
2470 if (vmRec_queryOutputBufFreeSpace() < u2VM_buffer_size)
2471 {
2472 // drop this log and add counter
2473 vm.vm_lost_count++;
2474 MD_TRC_VM_REC_HISR_VM_DATA_LOST(vm.vm_lost_count, 2);
2475 goto leaveProc;
2476 }
2477 else
2478 {
2479 vmRec_writeVmToOutputBuf(u2VM_buffer_size, vmBuf);
2480 }
2481 }
2482 else
2483 {
2484 vocWriteVocToCatcher(u2VM_buffer_size, vmBuf);
2485 }
2486
2487 vm.vm_lost_count = 0;
2488 vmBuf[0] = 0;
2489 vmBuf[1] = 0;
2490 vmBuf[2] = 0;
2491 vmBuf[3] = 0;
2492 }
2493
2494 // formatting
2495 Sal_VM_Frame vmfrm_t;
2496
2497 switch (sp_state)
2498 {
2499 case L1SP_STATE_4G_SPEECH_ON:
2500 SAL_VM_GetFrame3G(&vmfrm_t);
2501 vmFormatter_4g(vmBuf, &vmfrm_t);
2502 break;
2503 case L1SP_STATE_3G_SPEECH_ON:
2504 case L1SP_STATE_3G324M_SPEECH_ON:
2505 SAL_VM_GetFrame3G(&vmfrm_t);
2506 vmFormatter_amr(vmBuf, &vmfrm_t);
2507 break;
2508 case L1SP_STATE_C2K_SPEECH_ON:
2509 SAL_VM_GetFrameC2K(&vmfrm_t);
2510 vmFormatter_c2k(vmBuf, &vmfrm_t);
2511 break;
2512 default:
2513 if (L1SP_Get_isStandByMode() || pcmEx_isRunInIdleMode())
2514 {
2515 SAL_VM_GetFrame3G(&vmfrm_t);
2516 vmFormatter_standby(vmBuf, &vmfrm_t);
2517 }
2518 else
2519 {
2520 SAL_VM_GetFrame2G(&vmfrm_t);
2521 vmFormatter_2g(vmBuf, &vmfrm_t);
2522 }
2523 break;
2524 }
2525
2526leaveProc:
2527 kal_give_spinlock(vm.lockId);
2528
2529 if (vm.vm_hdlr)
2530 {
2531 vm.vm_hdlr();
2532 }
2533
2534leaveHisr:
2535 SP_updateEmCodecEvent();
2536 return;
2537}
2538
2539void VM_Init(void)
2540{
2541 vm.lockId = kal_create_spinlock("VM_LOCK");
2542}
2543
2544void VMREC_ConfigEpl(void)
2545{
2546 // only support phone call VM record dynamic change from AP side
2547 if (vm.isVocOn || vm.isVmLOn)
2548 {
2549 kal_uint16 recordInfo = L1Audio_GetDebugInfo(VM_DEBUG_INFO);
2550
2551 if (ChkL1ClsFltr_L1Audio_VoC_TRACE_EPL())
2552 {
2553 recordInfo |= (VM_EPL_1STSET_RECORD_FLAG + VM_EPL_2NDSET_RECORD_FLAG);
2554 recordInfo |= VM_EPL_REFMIC_RECORD_FLAG;
2555 recordInfo |= VM_EPL_ECHOREF_RECORD_FLAG;
2556 recordInfo |= VM_EPL_3RDMIC_RECORD_FLAG;
2557 recordInfo |= VM_EPL_2NDECHOREF_RECORD_FLAG;
2558 }
2559
2560 MD_TRC_VM_REC_DEBUG_INFO(recordInfo);
2561
2562 // config to open, and did not open yet
2563 if (((recordInfo & (VM_EPL_1STSET_RECORD_FLAG + VM_EPL_2NDSET_RECORD_FLAG)) != 0)
2564 && ((vm.record_info & (VM_EPL_1STSET_RECORD_FLAG + VM_EPL_2NDSET_RECORD_FLAG)) == 0))
2565 {
2566 //EPL open
2567 recordInfo |= VM_EPL_REFMIC_RECORD_FLAG;
2568 recordInfo |= VM_EPL_ECHOREF_RECORD_FLAG;
2569 recordInfo |= VM_EPL_3RDMIC_RECORD_FLAG;
2570 recordInfo |= VM_EPL_2NDECHOREF_RECORD_FLAG;
2571
2572 // Initial
2573 vm.record_info = recordInfo;
2574 vm.vm_lost_count = 0;
2575 vm.pcm_lost_count = 0;
2576 vm.vm_counter = 0;
2577
2578 vm.pcmBuf = vmEPLPCMInputBuf;
2579 memset(vmEPLPCMInputBuf, 0, sizeof(uint16)*VM_EPL_PCM_BUFFER_SIZE);
2580
2581 // Enable EPL
2582 L1Audio_HookHisrHandler(DP_D2C_VMEPL_REC_INT, (L1Audio_EventHandler)vmTchPcmRecordHisr, 0);
2583 AM_PCM8K_RecordOn(AM_PCM8KREC_APP_TYPE_VMEPL, 0);
2584 }
2585 }
2586}
2587
2588/**
2589 @vm_hdlr: handler
2590 @isVoc: is call from vm over catcher.
2591*/
2592void VMREC_Start(void (*vm_hdlr)(void), bool isVoc)
2593{
2594 if (AM_IsAmInSpeechState())
2595 {
2596 //decide the open
2597 bool isAlreadyOn = (vm.isVocOn || vm.isVmLOn);
2598
2599 if (isVoc)
2600 {
2601 //ASSERT(!vm.isVocOn); // prevent re-entry
2602 vm.isVocOn = true;
2603 }
2604 else // normal vm
2605 {
2606 //ASSERT(!vm.isVmLOn); // prevent re-entry
2607 vm.isVmLOn = true;
2608 vm.vm_hdlr = vm_hdlr;
2609 }
2610
2611#ifdef __SENSITIVE_DATA_MOSAIC__
2612 if (dhl_mask_sensitive_trace_on())
2613 {
2614 vm.isMosaic = true;
2615 return;
2616 }
2617 else
2618 {
2619 vm.isMosaic = false;
2620 }
2621#endif
2622
2623 //already on
2624 if (isAlreadyOn)
2625 {
2626 VMREC_ConfigEpl();
2627 return;
2628 }
2629 else
2630 {
2631 // Initial
2632 vm.audId = L1Audio_GetAudioID();
2633 L1Audio_SetFlag(vm.audId); //Be careful.Before Locking SleepMode, to access DSP sherrif tasks much time. So access DSP must be after SetFlag
2634
2635 vm.state = VM_STATE_RECORD;
2636
2637 vm.control_1 = VM_VM_CTRL_UL_ON;
2638 vm.control_2 = VM_VM_CTRL_DL_ON;
2639 vm.control_3 = VM_CHIP_ID;
2640 vm.control_4 = 0;
2641 vm.control_5 = 0;
2642 vm.control_6 = 0;
2643 vm.control_7 = 0;
2644 vm.control_8 = 0;
2645 vm.control_9 = 0;
2646 vm.control_10 = 0;
2647
2648 vm.evs_cur_sd_mode = EVS_UNDEF;
2649 vm.sc_len = 0;
2650 vm.sd_len = 0;
2651
2652 //vm buffer initital
2653 vm.vmBuf = vmBuffer;
2654 memset(vm.vmBuf, 0, sizeof(uint16)*VM_VM_BUFFER_SIZE);
2655
2656 // output buffer initial
2657 vm.pOutputBufWrite = 0;
2658 vm.pOutputBufRead = 0;
2659 vm.outputBufSize = VMREC_OUTPUT_BUF_SIZE;
2660 memset(vmRecOutputBuf, 0, sizeof(uint16)*VMREC_OUTPUT_BUF_SIZE);
2661
2662 VMREC_ConfigEpl();
2663
2664#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
2665 //G-serial codec buffer initial
2666 {
2667 vmInitGCodecULBuf();
2668 vmInitGCodecDLBuf();
2669 }
2670#endif
2671
2672#if defined(__UMTS_RAT__)
2673#if defined(_EXTRA_LOG_FOR_BIT_TRUE_)
2674 //TDD load need to reduce trace
2675 if (SP_3G_SIM_FDD_ACTIVE == L1SP_GetSIMStatus() &&
2676 (((int)L1Audio_GetDebugInfo(SPH_DEBUGINFO))& SPH_DEBUGINFO12_BIT1))
2677 {
2678 g_bNeedExtraLog = KAL_TRUE;
2679 }
2680#endif
2681#endif
2682 // enalbe normal VM record
2683 L1Audio_HookHisrHandler(DP_D2C_VM_REC_INT, (L1Audio_EventHandler)vmTchRecordHisr, 0);
2684 AM_VMRecordOn();
2685 }
2686 }
2687}
2688
2689/**
2690 @isVoc: is call from voice over cater. true is yes; false is no.
2691*/
2692void VMREC_Stop( bool isVoc)
2693{
2694 // check voc & vm are both closed.
2695 if (AM_IsAmInSpeechState())
2696 {
2697 if (isVoc)
2698 {
2699 //ASSERT(vm.isVocOn == true);
2700 kal_take_spinlock(vm.lockId, KAL_INFINITE_WAIT);
2701 vm.isVocOn = false;
2702 kal_give_spinlock(vm.lockId);
2703
2704 if (vm.isVmLOn) //still another need vm
2705 {
2706 return;
2707 }
2708 }
2709 else //record vm from media
2710 {
2711 //ASSERT(vm.isVmLOn == true);
2712 kal_take_spinlock(vm.lockId, KAL_INFINITE_WAIT);
2713 vm.isVmLOn = false;
2714 vm.vm_hdlr = NULL;
2715 kal_give_spinlock(vm.lockId);
2716
2717 if (vm.isVocOn) //still another need vm
2718 {
2719 return;
2720 }
2721 }
2722
2723#ifdef __SENSITIVE_DATA_MOSAIC__
2724 {
2725 if (vm.isMosaic)
2726 {
2727 return;
2728 }
2729 }
2730#endif
2731
2732 if (VM_STATE_RECORD == vm.state)
2733 {
2734 kal_take_spinlock(vm.lockId, KAL_INFINITE_WAIT);
2735 vm.state = VM_STATE_RECORD_STOP;
2736 kal_give_spinlock(vm.lockId);
2737
2738 if (vm.record_info & (VM_EPL_1STSET_RECORD_FLAG + VM_EPL_2NDSET_RECORD_FLAG))
2739 {
2740 AM_PCM8K_RecordOff(false, AM_PCM8KREC_APP_TYPE_VMEPL);
2741 L1Audio_UnhookHisrHandler(DP_D2C_VMEPL_REC_INT); // EPL record unhook
2742
2743 vm.pcmBuf = NULL;
2744 }
2745
2746 AM_VMRecordOff();
2747 L1Audio_UnhookHisrHandler(DP_D2C_VM_REC_INT); // vm record unhook
2748
2749 vm.vmBuf = NULL;
2750 vm.state = VM_STATE_STOP;
2751 vm.record_info = 0;
2752
2753 // output buffer clean
2754 vm.pOutputBufWrite = 0;
2755 vm.pOutputBufRead = 0;
2756 vm.outputBufSize = 0;
2757 memset(vmRecOutputBuf, 0, sizeof(uint16)*VMREC_OUTPUT_BUF_SIZE);
2758
2759#if defined(__G_CODEC_SUPPORT__) && defined(__VOLTE_SUPPORT__)
2760 //G-serial codec buffer initial
2761 {
2762 vmInitGCodecULBuf();
2763 vmInitGCodecDLBuf();
2764 }
2765#endif
2766
2767 // release sleep mode
2768 L1Audio_ClearFlag(vm.audId);
2769 L1Audio_FreeAudioID(vm.audId);
2770 }
2771 }
2772}