| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2012 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * drvdrv_common.c |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * Tataka_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This Module defines device driver common functions. |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
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| 1659 | *------------------------------------------------------------------------------ |
| 1660 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 1661 | *============================================================================ |
| 1662 | ****************************************************************************/ |
| 1663 | #include "drv_features.h" |
| 1664 | #include "kal_general_types.h" |
| 1665 | #include "kal_public_defs.h" |
| 1666 | #include "kal_public_api.h" |
| 1667 | #include "drv_comm.h" |
| 1668 | #include "kal_public_defs.h" //MSBB change #include "stack_config.h" |
| 1669 | #include "reg_base.h" |
| 1670 | #include "intrCtrl.h" |
| 1671 | |
| 1672 | #include "kal_trace.h" |
| 1673 | #include "system_trc.h" |
| 1674 | #include "init_trc_api.h" |
| 1675 | #include "init.h" |
| 1676 | #include "dcl.h" |
| 1677 | #include "drv_cmif.h" |
| 1678 | #include "cuif_l1core_public.h" |
| 1679 | #include "prbm.h" |
| 1680 | |
| 1681 | #if defined(MT6297) |
| 1682 | #include "d2d_public.h" |
| 1683 | #endif |
| 1684 | |
| 1685 | #if defined(__MD97__) |
| 1686 | #include "csif_l1core_public_api.h" |
| 1687 | #endif |
| 1688 | |
| 1689 | #ifdef __MTK_TARGET__ |
| 1690 | #include "ex_public.h" |
| 1691 | #ifdef __MULTI_BOOT__ |
| 1692 | #include "multiboot_config.h" |
| 1693 | #endif /* __MULTI_BOOT__ */ |
| 1694 | #endif /* __MTK_TARGET__ */ |
| 1695 | |
| 1696 | #if defined(__RESOURCE_MANAGER__) |
| 1697 | #include "rm.h" |
| 1698 | #endif //__RESOURCE_MANAGER__ |
| 1699 | |
| 1700 | #include "us_timer.h" |
| 1701 | #include "drv_hisr.h" |
| 1702 | |
| 1703 | #ifdef DRV_HIF_SUPPORT |
| 1704 | #include "hif_hal.h" |
| 1705 | #endif |
| 1706 | |
| 1707 | #ifdef __HIF_CCCI_SUPPORT__ |
| 1708 | #include "ccci_if.h" |
| 1709 | #endif |
| 1710 | |
| 1711 | #ifdef __HIF_PCCIF4_SUPPORT__ |
| 1712 | #include "pccif4_if.h" |
| 1713 | #endif |
| 1714 | |
| 1715 | #ifdef __HIF_PCCIF5_SUPPORT__ |
| 1716 | #include "pccif5_if.h" |
| 1717 | #endif |
| 1718 | |
| 1719 | #if defined(__SMART_PHONE_MODEM__) |
| 1720 | #include "ccci.h" |
| 1721 | |
| 1722 | #endif /* __SMART_PHONE_MODEM__ */ |
| 1723 | |
| 1724 | #if defined(DRV_MISC_TDMA_L1_MACRO) || defined(DRV_MISC_TOPSM_32K_RTC) |
| 1725 | #include "RM_public.h" |
| 1726 | #endif |
| 1727 | |
| 1728 | #if defined(__SCC_SIB_SUPPORT__) |
| 1729 | #include "scc.h" |
| 1730 | #include "Drv_mtad.h" |
| 1731 | #endif |
| 1732 | |
| 1733 | #if defined(__HIF_PCIE_SUPPORT__) |
| 1734 | #include "hif_pcie.h" |
| 1735 | #endif |
| 1736 | |
| 1737 | #if defined(__HIF_MHCCIF_SUPPORT__) |
| 1738 | #include "mhccif_if.h" |
| 1739 | #endif |
| 1740 | #if defined(DRV_EMIMPU) |
| 1741 | extern void emimpu_init(void); |
| 1742 | #endif /* DRV_EMIMPU */ |
| 1743 | |
| 1744 | //extern void DRVPDN_ini(void); |
| 1745 | //extern void DMA_Ini(void); |
| 1746 | extern void WDT_init(void); |
| 1747 | //extern void spi_init(void); |
| 1748 | extern void custom_drv_init(void); |
| 1749 | extern void GCU_Disable_ReverseBit(void); |
| 1750 | extern void UART_PDN_Enable(UART_PORT port); |
| 1751 | //extern void USB2UART_init(void); |
| 1752 | /* comment unused code after annouce at 2016/02/02 */ |
| 1753 | //extern void Visual_Init(void); |
| 1754 | |
| 1755 | //extern void che_hw_init(void); |
| 1756 | //extern void lpwr_init(void); |
| 1757 | #if !defined(DCL_MSDC_INTERFACE) |
| 1758 | extern void MSDC_Initialize(); |
| 1759 | #if defined(__MSDC2_SD_MMC__) || defined(__MSDC2_SD_SDIO__) |
| 1760 | extern void MSDC_Initialize2(); |
| 1761 | #endif//defined(__MSDC2_SD_MMC__) || defined(__MSDC2_SD_SDIO__) |
| 1762 | #endif//!defined(DCL_MSDC_INTERFACE) |
| 1763 | |
| 1764 | /* comment unused code after annouce at 2016/02/02 */ |
| 1765 | //#ifdef __WIFI_SUPPORT__ |
| 1766 | //extern void wndrv_HWinit(void); |
| 1767 | //#endif |
| 1768 | |
| 1769 | extern void custom_drv_deinit(void); |
| 1770 | |
| 1771 | /* comment unused code after annouce at 2016/02/02 */ |
| 1772 | //#if defined(ISP_SUPPORT) |
| 1773 | //extern void CalInit(void); |
| 1774 | //#endif |
| 1775 | |
| 1776 | #if defined(DRV_UART_SWITCHABLE_BETWEEN_PROCESSORS) |
| 1777 | extern kal_uint8 UartPortOwnedByMD[3]; |
| 1778 | #endif // #if defined(DRV_UART_SWITCHABLE_BETWEEN_PROCESSORS) |
| 1779 | //extern kal_bool INT_QueryExceptionStatus(void); |
| 1780 | //Remove old extern function announcement & add new header file due to WCS/MDD/DE5 Kari Suvanto's request |
| 1781 | #include <ex_public.h> |
| 1782 | |
| 1783 | /*lint -e552*/ |
| 1784 | boot_mode_type system_boot_mode = UNKNOWN_BOOT_MODE; |
| 1785 | /*lint +e552*/ |
| 1786 | extern kal_uint16 INT_BootMode(void); |
| 1787 | |
| 1788 | #ifdef IC_MODULE_TEST |
| 1789 | extern void IC_ModuleTest_Start(void); |
| 1790 | #endif /*IC_MODULE_TEST*/ |
| 1791 | |
| 1792 | #if defined(IC_BURNIN_TEST) || defined(DRV_MISC_GPT1_AS_OS_TICK) |
| 1793 | extern void INT_Timer_Interrupt(void); |
| 1794 | #endif //IC_BURNIN_TEST |
| 1795 | |
| 1796 | typedef void (* MEMCPY_FUNC)(const void *srcaddr, void *dstaddr, kal_uint32 len); |
| 1797 | #ifdef DRV_MISC_DMA_NO_MEMCPY |
| 1798 | void (* DRV_MEMCPY)(const void *srcaddr, void *dstaddr, kal_uint32 len); |
| 1799 | #elif defined(DRV_MISC_DMA_MEMCPY) |
| 1800 | extern kal_bool DMA_memcpy(const void *src, const void *dst, kal_uint32 length); |
| 1801 | void (* DRV_MEMCPY_PTR)(const void *srcaddr, void *dstaddr, kal_uint32 len); |
| 1802 | void DRV_MEMCPY(const void *srcaddr, void *dstaddr, kal_uint32 len); |
| 1803 | #endif /**/ |
| 1804 | |
| 1805 | //#if defined(__IRDA_SUPPORT__) && !defined(__MEUT__) && !defined(__MEIT__) |
| 1806 | /*TY adds this 2004/10/27*/ |
| 1807 | //extern UartDriver_strcut ircomm_uart_api; |
| 1808 | //#endif |
| 1809 | |
| 1810 | #if defined(__BTMTK__) && (defined(__BT_SPP_PROFILE__) || defined(__BT_HFG_PROFILE__)) |
| 1811 | extern Seriport_HANDLER_T SPPA_Uart_Drv_Handler; |
| 1812 | extern void bchs_host_controller_power_off(void); |
| 1813 | #elif defined __CMUX_SUPPORT__ |
| 1814 | extern Seriport_HANDLER_T CmuxUart_Drv_Handler; |
| 1815 | #endif |
| 1816 | |
| 1817 | #ifdef __SWDBG_SUPPORT__ |
| 1818 | extern kal_uint8 SWDBG_Profile; |
| 1819 | #endif /* _SWDBG_SUPPORT__ */ |
| 1820 | |
| 1821 | /* comment unused code after annouce at 2016/02/02 */ |
| 1822 | //#ifdef __BTMODULE_MT6601__ |
| 1823 | //extern void BT_Radio_Shutdown(void); |
| 1824 | //#endif |
| 1825 | |
| 1826 | #if (defined( DRV_MULTIPLE_SIM) && (!defined(DRV_2_SIM_CONTROLLER))) |
| 1827 | extern void sim_MT6302_init(void); |
| 1828 | #endif |
| 1829 | |
| 1830 | extern void EINT_Setting_Init(void); |
| 1831 | |
| 1832 | extern void SOE_Drv_Init(void); |
| 1833 | |
| 1834 | extern void OSTD_register_ccci_callback(void); |
| 1835 | |
| 1836 | #if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_MISC_REG_DBG__) |
| 1837 | #define DRV_MISC_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data) |
| 1838 | #define DRV_MISC_Reg(addr) DRV_DBG_Reg(addr) |
| 1839 | #define DRV_MISC_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data) |
| 1840 | #define DRV_MISC_Reg32(addr) DRV_DBG_Reg32(addr) |
| 1841 | #define DRV_MISC_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data) |
| 1842 | #define DRV_MISC_Reg8(addr) DRV_DBG_Reg8(addr) |
| 1843 | #define DRV_MISC_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data) |
| 1844 | #define DRV_MISC_SetBits(addr,data) DRV_DBG_SetBits(addr,data) |
| 1845 | #define DRV_MISC_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value) |
| 1846 | #define DRV_MISC_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data) |
| 1847 | #define DRV_MISC_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data) |
| 1848 | #define DRV_MISC_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value) |
| 1849 | #define DRV_MISC_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data) |
| 1850 | #define DRV_MISC_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data) |
| 1851 | #define DRV_MISC_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value) |
| 1852 | #else |
| 1853 | #define DRV_MISC_WriteReg(addr,data) DRV_WriteReg(addr,data) |
| 1854 | #define DRV_MISC_Reg(addr) DRV_Reg(addr) |
| 1855 | #define DRV_MISC_WriteReg32(addr,data) DRV_WriteReg32(addr,data) |
| 1856 | #define DRV_MISC_Reg32(addr) DRV_Reg32(addr) |
| 1857 | #define DRV_MISC_WriteReg8(addr,data) DRV_WriteReg8(addr,data) |
| 1858 | #define DRV_MISC_Reg8(addr) DRV_Reg8(addr) |
| 1859 | #define DRV_MISC_ClearBits(addr,data) DRV_ClearBits(addr,data) |
| 1860 | #define DRV_MISC_SetBits(addr,data) DRV_SetBits(addr,data) |
| 1861 | #define DRV_MISC_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value) |
| 1862 | #define DRV_MISC_ClearBits32(addr,data) DRV_ClearBits32(addr,data) |
| 1863 | #define DRV_MISC_SetBits32(addr,data) DRV_SetBits32(addr,data) |
| 1864 | #define DRV_MISC_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value) |
| 1865 | #define DRV_MISC_ClearBits8(addr,data) DRV_ClearBits8(addr,data) |
| 1866 | #define DRV_MISC_SetBits8(addr,data) DRV_SetBits8(addr,data) |
| 1867 | #define DRV_MISC_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value) |
| 1868 | #endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_MISC_REG_DBG__) |
| 1869 | |
| 1870 | #ifdef __DRV_COMM_REG_DBG__ |
| 1871 | DRV_REG_DBG_STRUCT DRV_REG_DBG_INFO_DATA; |
| 1872 | |
| 1873 | static void drv_reg_dbg_trace(kal_uint8 write, kal_uint16 line, kal_uint32 addr, kal_uint32 value) |
| 1874 | { |
| 1875 | DRV_REG_DBG_INFO_DATA.dbg_data[DRV_REG_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_COMM_REG_DBG_INFO_SIZE - 1)].write_flag = write; |
| 1876 | DRV_REG_DBG_INFO_DATA.dbg_data[DRV_REG_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_COMM_REG_DBG_INFO_SIZE - 1)].line_number = line; |
| 1877 | DRV_REG_DBG_INFO_DATA.dbg_data[DRV_REG_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_COMM_REG_DBG_INFO_SIZE - 1)].reg_addr = addr; |
| 1878 | DRV_REG_DBG_INFO_DATA.dbg_data[DRV_REG_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_COMM_REG_DBG_INFO_SIZE - 1)].reg_value = value; |
| 1879 | DRV_REG_DBG_INFO_DATA.dbg_data[DRV_REG_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_COMM_REG_DBG_INFO_SIZE - 1)].time_log = drv_get_current_time(); |
| 1880 | DRV_REG_DBG_INFO_DATA.dbg_data_idx++; |
| 1881 | } |
| 1882 | |
| 1883 | void drv_reg_dbg_trace_write16(kal_uint16 line, kal_uint32 addr, kal_uint32 data) |
| 1884 | { |
| 1885 | kal_uint32 savedMask; |
| 1886 | |
| 1887 | savedMask = SaveAndSetIRQMask(); |
| 1888 | ((*(volatile kal_uint16 *)(addr)) = (kal_uint16)(data)); |
| 1889 | drv_reg_dbg_trace(1, line, addr, data); |
| 1890 | RestoreIRQMask(savedMask); |
| 1891 | return; |
| 1892 | } |
| 1893 | |
| 1894 | void drv_reg_dbg_trace_write32(kal_uint16 line, kal_uint32 addr, kal_uint32 data) |
| 1895 | { |
| 1896 | kal_uint32 savedMask; |
| 1897 | |
| 1898 | savedMask = SaveAndSetIRQMask(); |
| 1899 | ((*(volatile kal_uint32 *)(addr)) = (kal_uint32)(data)); |
| 1900 | drv_reg_dbg_trace(1, line, addr, data); |
| 1901 | RestoreIRQMask(savedMask); |
| 1902 | return; |
| 1903 | } |
| 1904 | |
| 1905 | void drv_reg_dbg_trace_write8(kal_uint16 line, kal_uint32 addr, kal_uint32 data) |
| 1906 | { |
| 1907 | kal_uint32 savedMask; |
| 1908 | |
| 1909 | savedMask = SaveAndSetIRQMask(); |
| 1910 | ((*(volatile kal_uint8 *)(addr)) = (kal_uint8)(data)); |
| 1911 | drv_reg_dbg_trace(1, line, addr, data); |
| 1912 | RestoreIRQMask(savedMask); |
| 1913 | return; |
| 1914 | } |
| 1915 | |
| 1916 | kal_uint16 drv_reg_dbg_trace_read16(kal_uint16 line, kal_uint32 addr) |
| 1917 | { |
| 1918 | kal_uint16 value; |
| 1919 | kal_uint32 savedMask; |
| 1920 | |
| 1921 | savedMask = SaveAndSetIRQMask(); |
| 1922 | value = DRV_Reg(addr); |
| 1923 | drv_reg_dbg_trace(0, line, addr, value); |
| 1924 | RestoreIRQMask(savedMask); |
| 1925 | return value; |
| 1926 | } |
| 1927 | |
| 1928 | kal_uint32 drv_reg_dbg_trace_read32(kal_uint16 line, kal_uint32 addr) |
| 1929 | { |
| 1930 | kal_uint32 value; |
| 1931 | kal_uint32 savedMask; |
| 1932 | |
| 1933 | savedMask = SaveAndSetIRQMask(); |
| 1934 | value = DRV_Reg32(addr); |
| 1935 | drv_reg_dbg_trace(0, line, addr, value); |
| 1936 | RestoreIRQMask(savedMask); |
| 1937 | return value; |
| 1938 | } |
| 1939 | |
| 1940 | kal_uint32 drv_reg_dbg_trace_read8(kal_uint16 line, kal_uint32 addr) |
| 1941 | { |
| 1942 | kal_uint8 value; |
| 1943 | kal_uint32 savedMask; |
| 1944 | |
| 1945 | savedMask = SaveAndSetIRQMask(); |
| 1946 | value = DRV_Reg8(addr); |
| 1947 | drv_reg_dbg_trace(0, line, addr, value); |
| 1948 | RestoreIRQMask(savedMask); |
| 1949 | return value; |
| 1950 | } |
| 1951 | |
| 1952 | #endif //__DRV_COMM_REG_DBG__ |
| 1953 | |
| 1954 | #if defined(__MTK_TARGET__) |
| 1955 | /* bb reg dump setting */ |
| 1956 | EX_BBREG_DUMP devdrv_dump; |
| 1957 | const kal_uint32 devdrv_dump_regions[] = { |
| 1958 | #if defined(MT6763)||defined(MT6739)||defined(MT6771)||defined(MT6765) |
| 1959 | /*Base Address, length, type(0/1=byte access, 2=16-bit access, 4=32-bit access) */ |
| 1960 | BASE_ADDR_MDGPTM, 0x0070, 4, /*GPT */ |
| 1961 | BASE_MADDR_MDMCU_BUSMON, 0x0C18, 4, |
| 1962 | BASE_MADDR_MDINFRABUSMON, 0x0C18, 4, |
| 1963 | BASE_MADDR_MDINFRAMISC, 0x0210, 4, |
| 1964 | BASE_MADDR_LOGTOP, 0x0200, 4, |
| 1965 | BASE_ADDR_MML2_QP_APB, 0x0084, 4, |
| 1966 | (BASE_ADDR_MML2_QP_APB+0x100), 0x00BC, 4, |
| 1967 | (BASE_ADDR_MML2_QP_APB+0x200), 0x0024, 4, |
| 1968 | BASE_ADDR_MML2_QP_MEM, 0x0148, 4, |
| 1969 | BASE_ADDR_MML2_META_APB, 0x0170, 4, |
| 1970 | (BASE_ADDR_MML2_META_APB+0x200), 0x0058, 4, |
| 1971 | BASE_ADDR_MML2_META_MEM, 0x0198, 4, |
| 1972 | BASE_ADDR_MML2_VRB_MANAGER, 0x0114, 4, |
| 1973 | (BASE_ADDR_MML2_VRB_MANAGER+0x200),0x0314, 4, |
| 1974 | (BASE_ADDR_MML2_VRB_MANAGER+0x700),0x0114, 4, |
| 1975 | BASE_ADDR_MML2_MMU, 0x004C, 4, |
| 1976 | (BASE_ADDR_MML2_MMU+0x80), 0x0004, 4, |
| 1977 | (BASE_ADDR_MML2_MMU+0x100), 0x0014, 4, |
| 1978 | (BASE_ADDR_MML2_MMU+0x200), 0x00C4, 4, |
| 1979 | (BASE_ADDR_MML2_MMU+0x300), 0x0044, 4, |
| 1980 | (BASE_ADDR_MML2_MMU+0x400), 0x0084, 4, |
| 1981 | BASE_ADDR_MML2_DMA_RD, 0x00C8, 4, |
| 1982 | BASE_ADDR_MML2_DMA_WR, 0x0090, 4, |
| 1983 | (BASE_ADDR_MML2_DMA_WR+0x100), 0x00C8, 4, |
| 1984 | (BASE_ADDR_MML2_DMA_WR+0x200), 0x00C8, 4, |
| 1985 | (BASE_ADDR_MML2_DMA_WR+0x300), 0x00C8, 4, |
| 1986 | BASE_ADDR_MML2_LHIF, 0x003C, 4, |
| 1987 | BASE_ADDR_MML2_CIPHER, 0x00EC, 4, |
| 1988 | (BASE_ADDR_MML2_CIPHER+0x800), 0x013C, 4, |
| 1989 | BASE_ADDR_MML2_DL_LMAC, 0x0058, 4, |
| 1990 | BASE_ADDR_MML2_HARQ_CTRL, 0x0028, 4, |
| 1991 | (BASE_ADDR_MML2_HARQ_CTRL+0x800), 0x0220, 4, |
| 1992 | BASE_ADDR_MML2_SRAM_WRAP, 0x0020, 4, |
| 1993 | BASE_ADDR_MML2_CFG_TOP, 0x0060, 4, |
| 1994 | (BASE_ADDR_MML2_CFG_TOP+0x800), 0x0008, 4, |
| 1995 | BASE_ADDR_MML2_BYC, 0x0030, 4, |
| 1996 | BASE_ADDR_MCUMMU_MMU, 0x004C, 4, |
| 1997 | (BASE_ADDR_MCUMMU_MMU+0x080), 0x0004, 4, |
| 1998 | (BASE_ADDR_MCUMMU_MMU+0x100), 0x0014, 4, |
| 1999 | (BASE_ADDR_MCUMMU_MMU+0x200), 0x00C4, 4, |
| 2000 | (BASE_ADDR_MCUMMU_MMU+0x300), 0x0044, 4, |
| 2001 | (BASE_ADDR_MCUMMU_MMU+0x400), 0x0084, 4, |
| 2002 | BASE_ADDR_MCUMMU_VRB, 0x0024, 4, |
| 2003 | (BASE_ADDR_MCUMMU_VRB+0x100), 0x0014, 4, |
| 2004 | (BASE_ADDR_MCUMMU_VRB+0x200), 0x0014, 4, |
| 2005 | (BASE_ADDR_MCUMMU_VRB+0x300), 0x0014, 4, |
| 2006 | (BASE_ADDR_MCUMMU_VRB+0x400), 0x0014, 4, |
| 2007 | (BASE_ADDR_MCUMMU_VRB+0x500), 0x0014, 4, |
| 2008 | (BASE_ADDR_MCUMMU_VRB+0x700), 0x0014, 4, |
| 2009 | BASE_ADDR_MCUMMU, 0x0178, 4, |
| 2010 | (BASE_MADDR_MDMCU_PDAMON+0x800), 0x00A0, 4, |
| 2011 | BASE_ADDR_MCUSYS_ELM_EMI, 0x0480, 4, |
| 2012 | BASE_ADDR_MDINFRA_ELM, 0x0480, 4, |
| 2013 | (0x1f010060), 0x0060, 4, |
| 2014 | (BASE_ADDR_MDPERIMISC+0x70), 0x0010, 4, |
| 2015 | (BASE_MADDR_USIP_DSPLOG), 0x0100, 4, |
| 2016 | (BASE_MADDR_USIP_DSPLOG+0x100), 0x0100, 4, |
| 2017 | (BASE_MADDR_USIP_DSPLOG+0x200), 0x0100, 4, |
| 2018 | (BASE_MADDR_USIP_DSPLOG+0x300), 0x0100, 4, |
| 2019 | BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB, 0x0100, 4, |
| 2020 | BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB, 0x0100, 4, |
| 2021 | BASE_MADDR_RAKESYS_DSP_SW_LOGGER, 0x0100, 4, |
| 2022 | BASE_MADDR_MDTOP_PLLMIXED, 0x0700, 4, /* PLLMIXED */ |
| 2023 | (BASE_MADDR_MDTOP_PLLMIXED+0xC00), 0x0320, 4, /* PLLMIXED */ |
| 2024 | BASE_MADDR_MDTOP_CLKSW, 0x0220, 4, /* CLKSW */ |
| 2025 | (BASE_MADDR_MDTOP_CLKSW+0xF00), 0x10, 4, /* CLKSW */ |
| 2026 | L1_BASE_ADDR_IDC_CTRL, 0x0308, 4, /*IDC_CTRL*/ |
| 2027 | L1_BASE_ADDR_IDC_UART, 0x00FC, 1, /*IDC_UART*/ |
| 2028 | #elif defined(MT6295M) || defined(MT3967) || defined(MT6779) |
| 2029 | /*Base Address, length, type(0/1=byte access, 2=16-bit access, 4=32-bit access) */ |
| 2030 | BASE_ADDR_MDGPTM, 0x00D0, 4, /*GPT */ |
| 2031 | BASE_MADDR_MDMCU_BUSMON, 0x0C18, 4, |
| 2032 | BASE_MADDR_MDINFRABUSMON, 0x0C18, 4, |
| 2033 | BASE_MADDR_MDINFRAMISC, 0x0210, 4, |
| 2034 | BASE_MADDR_LOGTOP, 0x0200, 4, |
| 2035 | BASE_ADDR_MML2_QP_APB, 0x0220, 4, |
| 2036 | BASE_ADDR_MML2_DLCH_QP_APB, 0x0220, 4, |
| 2037 | BASE_ADDR_MML2_QP_MEM, 0x0148, 4, |
| 2038 | BASE_ADDR_MML2_META_APB, 0x0170, 4, |
| 2039 | (BASE_ADDR_MML2_META_APB+0x200), 0x0058, 4, |
| 2040 | BASE_ADDR_MML2_META_MEM, 0x01B0, 4, |
| 2041 | BASE_ADDR_MML2_VRB_MANAGER, 0x008C, 4, |
| 2042 | (BASE_ADDR_MML2_VRB_MANAGER+0x100), 0x0014, 4, |
| 2043 | (BASE_ADDR_MML2_VRB_MANAGER+0x140), 0x0014, 4, |
| 2044 | (BASE_ADDR_MML2_VRB_MANAGER+0x180), 0x0014, 4, |
| 2045 | (BASE_ADDR_MML2_VRB_MANAGER+0x1C0), 0x0014, 4, |
| 2046 | (BASE_ADDR_MML2_VRB_MANAGER+0x200), 0x0014, 4, |
| 2047 | (BASE_ADDR_MML2_VRB_MANAGER+0x240), 0x0014, 4, |
| 2048 | (BASE_ADDR_MML2_VRB_MANAGER+0x280), 0x0014, 4, |
| 2049 | (BASE_ADDR_MML2_VRB_MANAGER+0x2C0), 0x0014, 4, |
| 2050 | (BASE_ADDR_MML2_VRB_MANAGER+0x300), 0x0014, 4, |
| 2051 | (BASE_ADDR_MML2_VRB_MANAGER+0x340), 0x0014, 4, |
| 2052 | BASE_ADDR_MML2_MMU, 0x004C, 4, |
| 2053 | (BASE_ADDR_MML2_MMU+0x80), 0x0004, 4, |
| 2054 | (BASE_ADDR_MML2_MMU+0x100), 0x0014, 4, |
| 2055 | (BASE_ADDR_MML2_MMU+0x200), 0x0018, 4, |
| 2056 | (BASE_ADDR_MML2_MMU+0x2C0), 0x0004, 4, |
| 2057 | (BASE_ADDR_MML2_MMU+0x300), 0x0010, 4, |
| 2058 | (BASE_ADDR_MML2_MMU+0x400), 0x0130, 4, |
| 2059 | (BASE_ADDR_MML2_MMU+0x600), 0x0130, 4, |
| 2060 | BASE_ADDR_MML2_DMA_RD, 0x00C8, 4, |
| 2061 | BASE_ADDR_MML2_DLCH_RDMA, 0x00c8, 4, |
| 2062 | BASE_ADDR_MML2_DMA_WR, 0x0030, 4, |
| 2063 | (BASE_ADDR_MML2_DMA_WR+0x80), 0x0010, 4, |
| 2064 | (BASE_ADDR_MML2_DMA_WR+0x100), 0x0030, 4, |
| 2065 | (BASE_ADDR_MML2_DMA_WR+0x1C0), 0x0010, 4, |
| 2066 | (BASE_ADDR_MML2_DMA_WR+0x200), 0x0020, 4, |
| 2067 | (BASE_ADDR_MML2_DMA_WR+0x2C0), 0x0010, 4, |
| 2068 | (BASE_ADDR_MML2_DMA_WR+0x300), 0x0024, 4, |
| 2069 | (BASE_ADDR_MML2_DMA_WR+0x3C0), 0x0010, 4, |
| 2070 | BASE_ADDR_MML2_LHIF, 0x0068, 4, |
| 2071 | BASE_ADDR_MML2_CIPHER, 0x00F4, 4, |
| 2072 | (BASE_ADDR_MML2_CIPHER+0x800), 0x0150, 4, |
| 2073 | BASE_ADDR_MML2_DLCH_CIPHER, 0x00F4, 4, |
| 2074 | (BASE_ADDR_MML2_DLCH_CIPHER+0x800), 0x0150, 4, |
| 2075 | BASE_ADDR_MML2_DL_LMAC, 0x0058, 4, |
| 2076 | BASE_ADDR_MML2_HARQ_CTRL, 0x0028, 4, |
| 2077 | (BASE_ADDR_MML2_HARQ_CTRL+0x800), 0x0550, 4, |
| 2078 | BASE_ADDR_MML2_SRAM_WRAP, 0x0020, 4, |
| 2079 | BASE_ADDR_MML2_CFG_TOP, 0x0060, 4, |
| 2080 | (BASE_ADDR_MML2_CFG_TOP+0x80), 0x0008, 4, |
| 2081 | BASE_ADDR_MML2_BYC, 0x0030, 4, |
| 2082 | BASE_ADDR_MCUMMU_MMU, 0x004C, 4, |
| 2083 | (BASE_ADDR_MCUMMU_MMU+0x080), 0x0004, 4, |
| 2084 | (BASE_ADDR_MCUMMU_MMU+0x100), 0x0014, 4, |
| 2085 | (BASE_ADDR_MCUMMU_MMU+0x200), 0x0018, 4, |
| 2086 | (BASE_ADDR_MCUMMU_MMU+0x2C0), 0x0004, 4, |
| 2087 | (BASE_ADDR_MCUMMU_MMU+0x300), 0x0010, 4, |
| 2088 | (BASE_ADDR_MCUMMU_MMU+0x400), 0x0130, 4, |
| 2089 | (BASE_ADDR_MCUMMU_MMU+0x600), 0x0130, 4, |
| 2090 | (BASE_ADDR_MCUMMU_VRB+0x100), 0x0010, 4, |
| 2091 | (BASE_ADDR_MCUMMU_VRB+0x200), 0x0010, 4, |
| 2092 | (BASE_ADDR_MCUMMU_VRB+0x300), 0x0010, 4, |
| 2093 | (BASE_ADDR_MCUMMU_VRB+0x400), 0x0010, 4, |
| 2094 | (BASE_ADDR_MCUMMU_VRB+0x500), 0x0010, 4, |
| 2095 | BASE_ADDR_MCUMMU, 0x0094, 4, |
| 2096 | BASE_MADDR_MML2_ROHC, 0x004C, 4, |
| 2097 | BASE_NADDR_MML2_IPF_UL, 0x00B0, 4, |
| 2098 | BASE_NADDR_MML2_IPF_DL, 0x00D0, 4, |
| 2099 | BASE_NADDR_MML2_IPF_PN, 0x0030, 4, |
| 2100 | BASE_NADDR_MML2_IPF_HPCNAT, 0x00B0, 4, |
| 2101 | BASE_NADDR_MML2_IPF_SRAM, 0x0C00, 4, |
| 2102 | (BASE_MADDR_MDMCU_PDAMON+0x1000), 0x00A0, 4, |
| 2103 | BASE_ADDR_MCUSYS_ELM_EMI, 0x0480, 4, |
| 2104 | BASE_ADDR_MDINFRA_ELM, 0x0480, 4, |
| 2105 | (0x1f010060), 0x0060, 4, |
| 2106 | (BASE_ADDR_MDPERIMISC+0x70), 0x0010, 4, |
| 2107 | (BASE_MADDR_USIP_DSPLOG), 0x0100, 4, |
| 2108 | (BASE_MADDR_USIP_DSPLOG+0x100), 0x0100, 4, |
| 2109 | (BASE_MADDR_USIP_DSPLOG+0x200), 0x0100, 4, |
| 2110 | (BASE_MADDR_USIP_DSPLOG+0x300), 0x0100, 4, |
| 2111 | BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB, 0x0100, 4, |
| 2112 | BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB, 0x0100, 4, |
| 2113 | BASE_MADDR_RAKESYS_DSP_SW_LOGGER, 0x0100, 4, |
| 2114 | BASE_MADDR_MDTOP_PLLMIXED, 0x0700, 4, /* PLLMIXED */ |
| 2115 | (BASE_MADDR_MDTOP_PLLMIXED+0xC00), 0x0320, 4, /* PLLMIXED */ |
| 2116 | BASE_MADDR_MDTOP_CLKSW, 0x0220, 4, /* CLKSW */ |
| 2117 | (BASE_MADDR_MDTOP_CLKSW+0xF00), 0x10, 4, /* CLKSW */ |
| 2118 | L1_BASE_ADDR_IDC_CTRL, 0x0308, 4, /*IDC_CTRL*/ |
| 2119 | L1_BASE_ADDR_IDC_UART, 0x00FC, 1, /*IDC_UART*/ |
| 2120 | #elif defined(__MD97__) |
| 2121 | /*Base Address, length, type(0/1=byte access, 2=16-bit access, 4=32-bit access) */ |
| 2122 | BASE_ADDR_MDGPTM, 0x00D0, 4, /*GPT */ |
| 2123 | //BASE_MADDR_MDMCU_BUSMON, 0x0C18, 4, |
| 2124 | //BASE_MADDR_MDINFRABUSMON, 0x0C18, 4, |
| 2125 | BASE_MADDR_MDINFRAMISC, 0x0210, 4, |
| 2126 | BASE_MADDR_LOGTOP, 0x0600, 4, |
| 2127 | //Start of NRL2 |
| 2128 | BASE_NADDR_NRL2_NRL2_TOP_CFG, 0x128, 4, |
| 2129 | BASE_NADDR_NRL2_ROHC, 0x10C, 4, |
| 2130 | (BASE_NADDR_NRL2_NRL2_QP_UL_LHIF+0x800), 0x1B4, 4, |
| 2131 | BASE_NADDR_NRL2_NRL2_QP_UL_NR, 0x688, 4, |
| 2132 | BASE_NADDR_NRL2_NRL2_METADATA_MNG, 0x700, 4, |
| 2133 | (BASE_NADDR_NRL2_NRL2_METADATA_MNG+0x800), 0x66C, 4, |
| 2134 | (BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB+0x100), 0x188, 4, |
| 2135 | BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB, 0x6F0, 4, |
| 2136 | BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI, 0x118, 4, |
| 2137 | BASE_NADDR_NRL2_LTEDL_LMAC, 0x88, 4, |
| 2138 | BASE_NADDR_NRL2_LTEDL_HARQ, 0x2C, 4, |
| 2139 | (BASE_NADDR_NRL2_LTEDL_HARQ+0x400), 0x640, 4, |
| 2140 | (BASE_NADDR_NRL2_LTEDL_HARQ+0xA40), 0x64, 4, |
| 2141 | BASE_NADDR_NRL2_NRL2_LHIF, 0x70, 4, |
| 2142 | BASE_NADDR_NRL2_NRL2_IPF_UL, 0xB0, 4, |
| 2143 | BASE_NADDR_NRL2_NRL2_IPF_DL, 0x15C, 4, |
| 2144 | BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH, 0x90, 4, |
| 2145 | BASE_NADDR_NRL2_NRL2_IPF_HPCNAT, 0xB0, 4, |
| 2146 | BASE_NADDR_NRL2_NRL2_IPF_RULE, 0x800, 4, |
| 2147 | (BASE_NADDR_NRL2_NRL2_IPF_RULE+0x800), 0x400, 4, |
| 2148 | BASE_NADDR_NRL2_NRL2_IPF_LOG, 0x400, 4, |
| 2149 | BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL, 0x300, 4, |
| 2150 | BASE_NADDR_NRL2_GEN95_QP, 0x240, 4, |
| 2151 | BASE_NADDR_NRL2_NRL2_DL_UPP, 0x728, 4, |
| 2152 | (BASE_NADDR_NRL2_NRL2_DL_UPP+0x870), 0x54, 4, |
| 2153 | (BASE_NADDR_NRL2_NRL2_DL_UPP+0xA00), 0x244, 4, |
| 2154 | (BASE_NADDR_NRL2_NRL2_DL_UPP+0xEF8), 0x8, 4, |
| 2155 | BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0, 0xFD8, 4, |
| 2156 | BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1, 0x68, 4, |
| 2157 | BASE_NADDR_NRL2_NRL2_CPHR_NR, 0xED0, 4, |
| 2158 | BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC, 0x148, 4, |
| 2159 | BASE_NADDR_NRL2_NRL2_WDMA_GEN95, 0x148, 4, |
| 2160 | BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF, 0x148, 4, |
| 2161 | BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX, 0x148, 4, |
| 2162 | BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0, 0x148, 4, |
| 2163 | BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1, 0x148, 4, |
| 2164 | BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR, 0x148, 4, |
| 2165 | BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP, 0x148, 4, |
| 2166 | BASE_NADDR_NRL2_VRB_MNG, 0x3D4, 4, |
| 2167 | BASE_NADDR_NRL2_NRL2_QP_UL_RETX, 0x22C, 4, |
| 2168 | BASE_NADDR_NRL2_NRL2_QP_UL_LHIF, 0x22C, 4, |
| 2169 | BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0, 0x8, 4, |
| 2170 | BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1, 0x8, 4, |
| 2171 | BASE_NADDR_NRL2_NRL2_SRAM_WRAP, 0x100, 4, |
| 2172 | BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP, 0xC8, 4, |
| 2173 | BASE_NADDR_NRL2_DLSYS_5GPL_RDMA, 0xC8, 4, |
| 2174 | BASE_NADDR_NRL2_DLSYS_4GPL_RDMA, 0xC8, 4, |
| 2175 | BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0, 0xC8, 4, |
| 2176 | BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1, 0xC8, 4, |
| 2177 | BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX, 0xC8, 4, |
| 2178 | BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF, 0xC8, 4, |
| 2179 | BASE_NADDR_NRL2_GEN95_RDMA, 0xC8, 4, |
| 2180 | BASE_NADDR_NRL2_NRL2_PPHY, 0x1C, 4, |
| 2181 | BASE_NADDR_NRL2_NRL2_MMU, 0x84, 4, |
| 2182 | (BASE_NADDR_NRL2_NRL2_MMU+0x100), 0x18, 4, |
| 2183 | (BASE_NADDR_NRL2_NRL2_MMU+0x200), 0xd0, 4, |
| 2184 | (BASE_NADDR_NRL2_NRL2_MMU+0x300), 0xC, 4, |
| 2185 | (BASE_NADDR_NRL2_NRL2_MMU+0x400), 0x180, 4, |
| 2186 | (BASE_NADDR_NRL2_NRL2_MMU+0x600), 0x170, 4, |
| 2187 | BASE_NADDR_NRL2_GEN95_CPHR, 0xF4, 4, |
| 2188 | (BASE_NADDR_NRL2_GEN95_CPHR+0x800), 0x148, 4, |
| 2189 | BASE_NADDR_NRL2_GEN95_BYC, 0x30, 4, |
| 2190 | BASE_NADDR_NRL2_DLSYS_COPRO_ARB, 0x7C, 4, |
| 2191 | (BASE_NADDR_NRL2_DLSYS_COPRO_ARB+0x120), 0xE8, 4, |
| 2192 | BASE_NADDR_NRL2_DLSYS_5GPL_QP, 0x44, 4, |
| 2193 | (BASE_NADDR_NRL2_DLSYS_5GPL_QP+0x104), 0x128, 4, |
| 2194 | BASE_NADDR_NRL2_DLSYS_4GPL_QP, 0x44, 4, |
| 2195 | (BASE_NADDR_NRL2_DLSYS_4GPL_QP+0x104), 0x128, 4, |
| 2196 | (BASE_NADDR_NRL2_NRL2_BUS_SMI+0x100), 0x148, 4, |
| 2197 | (BASE_NADDR_NRL2_NRL2_BUS_SMI+0x300), 0xCC, 4, |
| 2198 | (BASE_NADDR_NRL2_NRL2_BUS_SMI+0x400), 0x48, 4, |
| 2199 | (BASE_NADDR_NRL2_NRL2_BUS_SMI+0x500), 0x2C, 4, |
| 2200 | //End of NRL2 |
| 2201 | (BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER+0x1C00), 0x00F0, 4, |
| 2202 | BASE_ADDR_MCUSYS_ELM_EMI, 0x0720, 4, |
| 2203 | BASE_ADDR_MDINFRA_ELM, 0x0720, 4, |
| 2204 | #if defined(MT6297) |
| 2205 | BASE_ADDR_MDINFRA_ELM_B, 0x0600, 4, |
| 2206 | #endif |
| 2207 | (0x1f010060), 0x0060, 4, |
| 2208 | (BASE_ADDR_MDPERIMISC+0x70), 0x0010, 4, |
| 2209 | (BASE_MADDR_USIP_DSPLOG), 0x0100, 4, |
| 2210 | (BASE_MADDR_USIP_DSPLOG+0x100), 0x0100, 4, |
| 2211 | (BASE_MADDR_USIP_DSPLOG+0x200), 0x0100, 4, |
| 2212 | (BASE_MADDR_USIP_DSPLOG+0x300), 0x0100, 4, |
| 2213 | // 20180315 mark DSPLOG_1PB related regiester due to MT6297 FPGA load build fail |
| 2214 | /* |
| 2215 | BASE_MADDR_BRAM_SCQ0_DSPLOG_1PB, 0x0100, 4, |
| 2216 | BASE_MADDR_BRAM_SCQ1_DSPLOG_1PB, 0x0100, 4, |
| 2217 | */ |
| 2218 | BASE_MADDR_RAKESYS_DSP_SW_LOGGER, 0x0100, 4, |
| 2219 | BASE_MADDR_MDTOP_PLLMIXED, 0x550, 4, /* PLLMIXED */ |
| 2220 | (BASE_MADDR_MDTOP_PLLMIXED+0x800), 0x50, 4, /* PLLMIXED */ |
| 2221 | (BASE_MADDR_MDTOP_PLLMIXED+0xC00), 0x50, 4, /* PLLMIXED */ |
| 2222 | (BASE_MADDR_MDTOP_PLLMIXED+0xD00), 0x10, 4, /* PLLMIXED */ |
| 2223 | (BASE_MADDR_MDTOP_PLLMIXED+0xF00), 0x20, 4, /* PLLMIXED */ |
| 2224 | BASE_MADDR_MDTOP_CLKSW, 0x150, 4, /* CLKSW */ |
| 2225 | (BASE_MADDR_MDTOP_CLKSW+0x200), 0x30, 4, /* CLKSW */ |
| 2226 | (BASE_MADDR_MDTOP_CLKSW+0x300), 0x10, 4, /* CLKSW */ |
| 2227 | (BASE_MADDR_MDTOP_CLKSW+0x400), 0x20, 4, /* CLKSW */ |
| 2228 | (BASE_MADDR_MDTOP_CLKSW+0x500), 0x10, 4, /* CLKSW */ |
| 2229 | (BASE_MADDR_MDTOP_CLKSW+0xF00), 0x10, 4, /* CLKSW */ |
| 2230 | L1_BASE_ADDR_IDC_CTRL, 0x040C, 4, /*IDC_CTRL*/ /* 20191104 Grass request to enlarge */ |
| 2231 | L1_BASE_ADDR_IDC_UART, 0x0218, 1, /*IDC_UART*/ /* 20191104 Grass request to enlarge */ |
| 2232 | BASE_MADDR_CLK_CTRL, 0x20, 4, |
| 2233 | L1_BASE_MADDR_AO_CONFG, 0x60, 4, |
| 2234 | |
| 2235 | #elif defined(__MD97P__) |
| 2236 | /*Base Address, length, type(0/1=byte access, 2=16-bit access, 4=32-bit access) */ |
| 2237 | BASE_ADDR_MDGPTM, 0x00D0, 4, /*GPT */ |
| 2238 | BASE_MADDR_MDMCU_BUSMON, 0x0C18, 4, |
| 2239 | BASE_MADDR_MDINFRABUSMON, 0x0C18, 4, |
| 2240 | /* BASE_MADDR_MDINFRAMISC, 0x0210, 4, 20190805 marked it for avoid build error */ |
| 2241 | BASE_MADDR_LOGTOP, 0x0600, 4, |
| 2242 | |
| 2243 | // 20190717 for solve build error & FPGA usage , mark most register first |
| 2244 | /* |
| 2245 | //Start of NRL2 |
| 2246 | BASE_NADDR_NRL2_NRL2_TOP_CFG, 0x128, 4, |
| 2247 | BASE_NADDR_NRL2_ROHC, 0x10C, 4, |
| 2248 | (BASE_NADDR_NRL2_NRL2_QP_UL_LHIF+0x800), 0x1B4, 4, |
| 2249 | BASE_NADDR_NRL2_NRL2_QP_UL_NR, 0x688, 4, |
| 2250 | BASE_NADDR_NRL2_NRL2_METADATA_MNG, 0x700, 4, |
| 2251 | (BASE_NADDR_NRL2_NRL2_METADATA_MNG+0x800), 0x66C, 4, |
| 2252 | (BASE_NADDR_MDCORESYS_MML2_MCU_MMU_VRB+0x100), 0x188, 4, |
| 2253 | BASE_NADDR_MDCORESYS_MML2_MCU_MMU_TLB, 0x6F0, 4, |
| 2254 | BASE_NADDR_MDCORESYS_MML2_MCU_MMU_AXI, 0x118, 4, |
| 2255 | BASE_NADDR_NRL2_LTEDL_LMAC, 0x88, 4, |
| 2256 | BASE_NADDR_NRL2_LTEDL_HARQ, 0x2C, 4, |
| 2257 | (BASE_NADDR_NRL2_LTEDL_HARQ+0x400), 0x640, 4, |
| 2258 | (BASE_NADDR_NRL2_LTEDL_HARQ+0xA40), 0x64, 4, |
| 2259 | BASE_NADDR_NRL2_NRL2_LHIF, 0x70, 4, |
| 2260 | BASE_NADDR_NRL2_NRL2_IPF_UL, 0xB0, 4, |
| 2261 | BASE_NADDR_NRL2_NRL2_IPF_DL, 0x15C, 4, |
| 2262 | BASE_NADDR_NRL2_NRL2_IPF_PN_MATCH, 0x90, 4, |
| 2263 | BASE_NADDR_NRL2_NRL2_IPF_HPCNAT, 0xB0, 4, |
| 2264 | BASE_NADDR_NRL2_NRL2_IPF_RULE, 0x800, 4, |
| 2265 | (BASE_NADDR_NRL2_NRL2_IPF_RULE+0x800), 0x400, 4, |
| 2266 | BASE_NADDR_NRL2_NRL2_IPF_LOG, 0x400, 4, |
| 2267 | BASE_NADDR_NRL2_NRL2_IPF_RQ_TBL, 0x300, 4, |
| 2268 | BASE_NADDR_NRL2_GEN95_QP, 0x240, 4, |
| 2269 | BASE_NADDR_NRL2_NRL2_DL_UPP, 0x728, 4, |
| 2270 | (BASE_NADDR_NRL2_NRL2_DL_UPP+0x870), 0x54, 4, |
| 2271 | (BASE_NADDR_NRL2_NRL2_DL_UPP+0xA00), 0x244, 4, |
| 2272 | (BASE_NADDR_NRL2_NRL2_DL_UPP+0xEF8), 0x8, 4, |
| 2273 | BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_0, 0xFD8, 4, |
| 2274 | BASE_NADDR_NRL2_NRL2_DL_UPP_TB_MAP_1, 0x68, 4, |
| 2275 | BASE_NADDR_NRL2_NRL2_CPHR_NR, 0xED0, 4, |
| 2276 | BASE_NADDR_NRL2_NRL2_WDMA_DL_LMAC, 0x148, 4, |
| 2277 | BASE_NADDR_NRL2_NRL2_WDMA_GEN95, 0x148, 4, |
| 2278 | BASE_NADDR_NRL2_NRL2_WDMA_UL_LHIF, 0x148, 4, |
| 2279 | BASE_NADDR_NRL2_NRL2_WDMA_UL_RETX, 0x148, 4, |
| 2280 | BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC0, 0x148, 4, |
| 2281 | BASE_NADDR_NRL2_NRL2_WDMA_UL_NR_CC1, 0x148, 4, |
| 2282 | BASE_NADDR_NRL2_NRL2_WDMA_DL_DECPHR, 0x148, 4, |
| 2283 | BASE_NADDR_NRL2_NRL2_WDMA_DL_UPP, 0x148, 4, |
| 2284 | BASE_NADDR_NRL2_VRB_MNG, 0x3D4, 4, |
| 2285 | BASE_NADDR_NRL2_NRL2_QP_UL_RETX, 0x22C, 4, |
| 2286 | BASE_NADDR_NRL2_NRL2_QP_UL_LHIF, 0x22C, 4, |
| 2287 | BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_0, 0x8, 4, |
| 2288 | BASE_NADDR_MODEML1_AO_MML2_TXBRP_TB_CTRL_1, 0x8, 4, |
| 2289 | BASE_NADDR_NRL2_NRL2_SRAM_WRAP, 0x100, 4, |
| 2290 | BASE_NADDR_NRL2_NRL2_RDMA_DL_UPP, 0xC8, 4, |
| 2291 | BASE_NADDR_NRL2_DLSYS_5GPL_RDMA, 0xC8, 4, |
| 2292 | BASE_NADDR_NRL2_DLSYS_4GPL_RDMA, 0xC8, 4, |
| 2293 | BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC0, 0xC8, 4, |
| 2294 | BASE_NADDR_NRL2_NRL2_RDMA_UL_NR_CC1, 0xC8, 4, |
| 2295 | BASE_NADDR_NRL2_NRL2_RDMA_UL_RETX, 0xC8, 4, |
| 2296 | BASE_NADDR_NRL2_NRL2_RDMA_UL_LHIF, 0xC8, 4, |
| 2297 | BASE_NADDR_NRL2_GEN95_RDMA, 0xC8, 4, |
| 2298 | BASE_NADDR_NRL2_NRL2_PPHY, 0x1C, 4, |
| 2299 | BASE_NADDR_NRL2_NRL2_MMU, 0x84, 4, |
| 2300 | (BASE_NADDR_NRL2_NRL2_MMU+0x100), 0x18, 4, |
| 2301 | (BASE_NADDR_NRL2_NRL2_MMU+0x200), 0xd0, 4, |
| 2302 | (BASE_NADDR_NRL2_NRL2_MMU+0x300), 0xC, 4, |
| 2303 | (BASE_NADDR_NRL2_NRL2_MMU+0x400), 0x180, 4, |
| 2304 | (BASE_NADDR_NRL2_NRL2_MMU+0x600), 0x170, 4, |
| 2305 | BASE_NADDR_NRL2_GEN95_CPHR, 0xF4, 4, |
| 2306 | (BASE_NADDR_NRL2_GEN95_CPHR+0x800), 0x148, 4, |
| 2307 | BASE_NADDR_NRL2_GEN95_BYC, 0x30, 4, |
| 2308 | BASE_NADDR_NRL2_DLSYS_COPRO_ARB, 0x7C, 4, |
| 2309 | (BASE_NADDR_NRL2_DLSYS_COPRO_ARB+0x120), 0xE8, 4, |
| 2310 | BASE_NADDR_NRL2_DLSYS_5GPL_QP, 0x44, 4, |
| 2311 | (BASE_NADDR_NRL2_DLSYS_5GPL_QP+0x104), 0x128, 4, |
| 2312 | BASE_NADDR_NRL2_DLSYS_4GPL_QP, 0x44, 4, |
| 2313 | (BASE_NADDR_NRL2_DLSYS_4GPL_QP+0x104), 0x128, 4, |
| 2314 | (BASE_NADDR_NRL2_NRL2_BUS_SMI+0x100), 0x148, 4, |
| 2315 | (BASE_NADDR_NRL2_NRL2_BUS_SMI+0x300), 0xCC, 4, |
| 2316 | (BASE_NADDR_NRL2_NRL2_BUS_SMI+0x400), 0x48, 4, |
| 2317 | (BASE_NADDR_NRL2_NRL2_BUS_SMI+0x500), 0x2C, 4, |
| 2318 | //End of NRL2 |
| 2319 | (BASE_MADDR_MDMCU_SHAOLIN__MDMCU_PDA_MONITER+0x1C00), 0x00F0, 4, |
| 2320 | BASE_ADDR_MCUSYS_ELM_EMI, 0x0480, 4, |
| 2321 | BASE_ADDR_MDINFRA_ELM, 0x0480, 4, |
| 2322 | #if defined(MT6297) |
| 2323 | BASE_ADDR_MDINFRA_ELM_B, 0x0480, 4, |
| 2324 | #endif |
| 2325 | (0x1f010060), 0x0060, 4, |
| 2326 | (BASE_ADDR_MDPERIMISC+0x70), 0x0010, 4, |
| 2327 | (BASE_MADDR_USIP_DSPLOG), 0x0100, 4, |
| 2328 | (BASE_MADDR_USIP_DSPLOG+0x100), 0x0100, 4, |
| 2329 | (BASE_MADDR_USIP_DSPLOG+0x200), 0x0100, 4, |
| 2330 | (BASE_MADDR_USIP_DSPLOG+0x300), 0x0100, 4, |
| 2331 | */ |
| 2332 | |
| 2333 | |
| 2334 | BASE_MADDR_RAKESYS_DSP_SW_LOGGER, 0x0100, 4, |
| 2335 | BASE_MADDR_MDTOP_PLLMIXED, 0x550, 4, /* PLLMIXED */ |
| 2336 | (BASE_MADDR_MDTOP_PLLMIXED+0x800), 0x50, 4, /* PLLMIXED */ |
| 2337 | (BASE_MADDR_MDTOP_PLLMIXED+0xC00), 0x50, 4, /* PLLMIXED */ |
| 2338 | (BASE_MADDR_MDTOP_PLLMIXED+0xD00), 0x10, 4, /* PLLMIXED */ |
| 2339 | (BASE_MADDR_MDTOP_PLLMIXED+0xF00), 0x20, 4, /* PLLMIXED */ |
| 2340 | BASE_MADDR_MDTOP_CLKSW, 0x150, 4, /* CLKSW */ |
| 2341 | (BASE_MADDR_MDTOP_CLKSW+0x200), 0x30, 4, /* CLKSW */ |
| 2342 | (BASE_MADDR_MDTOP_CLKSW+0x300), 0x10, 4, /* CLKSW */ |
| 2343 | (BASE_MADDR_MDTOP_CLKSW+0x400), 0x20, 4, /* CLKSW */ |
| 2344 | (BASE_MADDR_MDTOP_CLKSW+0x500), 0x10, 4, /* CLKSW */ |
| 2345 | (BASE_MADDR_MDTOP_CLKSW+0xF00), 0x10, 4, /* CLKSW */ |
| 2346 | L1_BASE_ADDR_IDC_CTRL, 0x050C, 4, /*IDC_CTRL*/ |
| 2347 | L1_BASE_ADDR_IDC_UART, 0x0218, 1, /*IDC_UART*/ |
| 2348 | BASE_MADDR_CLK_CTRL, 0x20, 4, |
| 2349 | L1_BASE_MADDR_AO_CONFG, 0x60, 4, |
| 2350 | |
| 2351 | /* end of MD97P */ |
| 2352 | |
| 2353 | #else /* MT6290 */ |
| 2354 | #error "Unsupported Chip" |
| 2355 | // 0, 0, 0 |
| 2356 | #endif/* MT6290 */ |
| 2357 | }; |
| 2358 | #endif /* __MTK_TARGET__ */ |
| 2359 | |
| 2360 | |
| 2361 | /*To get all customized data*/ |
| 2362 | void Drv_Customize_Init(void) |
| 2363 | { |
| 2364 | DCL_HANDLE chr_usb_det_handle; |
| 2365 | |
| 2366 | chr_usb_det_handle = Dcl_Chr_Det_Open(DCL_CHR_USB_DET, FLAGS_NONE); |
| 2367 | Dcl_Chr_Det_Control(chr_usb_det_handle, CHR_DET_CMD_REGISTER_CHR_USB_EINT, NULL); |
| 2368 | Dcl_Chr_Det_Close(chr_usb_det_handle); |
| 2369 | } |
| 2370 | |
| 2371 | /************************************************************************* |
| 2372 | * FUNCTION |
| 2373 | * Drv_query_boot_mode |
| 2374 | * |
| 2375 | * DESCRIPTION |
| 2376 | * Return boot mode. |
| 2377 | * |
| 2378 | * PARAMETERS |
| 2379 | * |
| 2380 | * RETURNS |
| 2381 | * FACTORY_BOOT, NORMAL_BOOT and USBMS_BOOT |
| 2382 | * |
| 2383 | * GLOBALS AFFECTED |
| 2384 | * |
| 2385 | *************************************************************************/ |
| 2386 | boot_mode_type Drv_query_boot_mode(void) |
| 2387 | { |
| 2388 | |
| 2389 | #ifdef __MULTI_BOOT__ |
| 2390 | |
| 2391 | |
| 2392 | if( FACTORY_BOOT == kal_query_boot_mode() ) |
| 2393 | return FACTORY_BOOT; |
| 2394 | |
| 2395 | |
| 2396 | #endif /* __MULTI_BOOT__ */ |
| 2397 | |
| 2398 | return NORMAL_BOOT; |
| 2399 | } |
| 2400 | |
| 2401 | /************************************************************************* |
| 2402 | * FUNCTION |
| 2403 | * Drv_query_boot_mode_at_init |
| 2404 | * |
| 2405 | * DESCRIPTION |
| 2406 | * Return boot mode at init stage. |
| 2407 | * Due to Seamless META feature, we will never into META mode at init stage. |
| 2408 | * |
| 2409 | * PARAMETERS |
| 2410 | * |
| 2411 | * RETURNS |
| 2412 | * NORMAL_BOOT and USBMS_BOOT |
| 2413 | * |
| 2414 | * GLOBALS AFFECTED |
| 2415 | * |
| 2416 | *************************************************************************/ |
| 2417 | boot_mode_type Drv_query_boot_mode_at_init(void) |
| 2418 | { |
| 2419 | |
| 2420 | #ifdef __MULTI_BOOT__ |
| 2421 | |
| 2422 | |
| 2423 | |
| 2424 | #endif /* __MULTI_BOOT__ */ |
| 2425 | |
| 2426 | return NORMAL_BOOT; |
| 2427 | } |
| 2428 | |
| 2429 | /************************************************************************* |
| 2430 | * FUNCTION |
| 2431 | * Drv_PW_Init |
| 2432 | * |
| 2433 | * DESCRIPTION |
| 2434 | * PW initialization |
| 2435 | * |
| 2436 | * PARAMETERS |
| 2437 | * |
| 2438 | * RETURNS |
| 2439 | * |
| 2440 | * GLOBALS AFFECTED |
| 2441 | * |
| 2442 | *************************************************************************/ |
| 2443 | void Drv_PW_Init(void) |
| 2444 | { |
| 2445 | |
| 2446 | //DclBMT_Initialize(); |
| 2447 | |
| 2448 | #ifndef __L1_STANDALONE__ |
| 2449 | #ifdef PMIC_PRESENT |
| 2450 | INT_Trace_Enter(INIT_DRV1_PW); |
| 2451 | { |
| 2452 | DCL_HANDLE handle; |
| 2453 | Dcl_Chr_Det_Initialize(); |
| 2454 | handle=DclPW_Open(DCL_PW, FLAGS_NONE); |
| 2455 | DclPW_Control(handle, PW_CMD_POWER_INIT, NULL); |
| 2456 | DclPW_Close(handle); |
| 2457 | } |
| 2458 | INT_Trace_Exit(INIT_DRV1_PW); |
| 2459 | |
| 2460 | #if defined(DRV_BMT_HW_PRECC_WORKAROUND) |
| 2461 | { |
| 2462 | PW_CTRL_GET_POWERON_REASON CtrlVal; |
| 2463 | DCL_HANDLE pmu_handle; |
| 2464 | pmu_handle = DclPW_Open(DCL_PW, FLAGS_NONE); |
| 2465 | DclPW_Control(pmu_handle, PW_CMD_GET_POWERON_REASON, (DCL_CTRL_DATA_T *)&CtrlVal); |
| 2466 | if(CtrlVal.powerOnReason == CHRPWRON || CtrlVal.powerOnReason == USBPWRON_WDT || |
| 2467 | CtrlVal.powerOnReason == USBPWRON) |
| 2468 | { |
| 2469 | // For Pre-cc 3.2~3.3V VCore Drop Issue |
| 2470 | DclPW_Control(pmu_handle, PW_CMD_POWERON, NULL); |
| 2471 | } |
| 2472 | DclPW_Close(pmu_handle); |
| 2473 | } |
| 2474 | |
| 2475 | #endif |
| 2476 | |
| 2477 | { |
| 2478 | DCL_HANDLE handle; |
| 2479 | |
| 2480 | handle=DclPW_Open(DCL_PW, FLAGS_NONE); |
| 2481 | DclPW_Control(handle,PW_CMD_POWERON,NULL); |
| 2482 | DclPW_Close(handle); |
| 2483 | } |
| 2484 | |
| 2485 | /* |
| 2486 | if(BMT.PWRon == PWRKEYPWRON) |
| 2487 | GPTI_BusyWait(Custom_Keypress_Period); |
| 2488 | */ |
| 2489 | #else /*PMIC_PRESENT*/ |
| 2490 | DCL_HANDLE handle; |
| 2491 | |
| 2492 | handle=DclPW_Open(DCL_PW, FLAGS_NONE); |
| 2493 | DclPW_Control(handle,PW_CMD_POWERON,NULL); |
| 2494 | DclPW_Close(handle); |
| 2495 | #endif /*PMIC_PRESENT*/ |
| 2496 | #else /*__L1_STANDALONE__*/ |
| 2497 | { |
| 2498 | DCL_HANDLE handle; |
| 2499 | |
| 2500 | handle=DclPW_Open(DCL_PW, FLAGS_NONE); |
| 2501 | DclPW_Control(handle,PW_CMD_POWERON,NULL); |
| 2502 | DclPW_Close(handle); |
| 2503 | } |
| 2504 | #endif /*__L1_STANDALONE__*/ |
| 2505 | } |
| 2506 | |
| 2507 | /* |
| 2508 | * FUNCTION |
| 2509 | * Drv_Init_Phase1 |
| 2510 | * |
| 2511 | * DESCRIPTION |
| 2512 | * This function is the NFB phase1 (Primary ROM) initial function for |
| 2513 | * all device drivers. |
| 2514 | * This function is called once to initialize the device driver. |
| 2515 | * |
| 2516 | * CALLS |
| 2517 | * |
| 2518 | * PARAMETERS |
| 2519 | * None |
| 2520 | * |
| 2521 | * RETURNS |
| 2522 | * None |
| 2523 | * |
| 2524 | * GLOBALS AFFECTED |
| 2525 | * external_global |
| 2526 | * |
| 2527 | * NOTE XXX |
| 2528 | * All sub functions reference by this function should be placed on |
| 2529 | * Primary ROM for NFB projects. Or it cannot boot up because Drv_Init() |
| 2530 | * executed before Secondary ROM loaded. |
| 2531 | * Please make sure all sub-functions under custom.lib that referenced by |
| 2532 | * Drv_Init() list in NFB scatter file. |
| 2533 | */ |
| 2534 | |
| 2535 | void Drv_Init_Phase1(void) |
| 2536 | { |
| 2537 | #if defined(MT6297) |
| 2538 | d2d_init(); |
| 2539 | #endif |
| 2540 | |
| 2541 | #if defined(__MD97__) |
| 2542 | #if defined(__MD97__) |
| 2543 | csif_init(); |
| 2544 | #endif |
| 2545 | #endif //defined(__MD97__) |
| 2546 | |
| 2547 | #if defined (__FPGA__) |
| 2548 | |
| 2549 | /**/ |
| 2550 | /* =========== Below is Init Flow of FPGA =============== */ |
| 2551 | /**/ |
| 2552 | |
| 2553 | DCL_HANDLE uart_handle; |
| 2554 | DCL_CTRL_DATA_T data; |
| 2555 | extern Seriport_HANDLER_T Uart_Drv_Handler; |
| 2556 | |
| 2557 | #if defined(__SCC_SIB_SUPPORT__) |
| 2558 | // Init SIB Related IP Driver |
| 2559 | scc_init(); |
| 2560 | #endif |
| 2561 | |
| 2562 | CMIF_Init(); |
| 2563 | CUIF_Init(); |
| 2564 | /* TTY initialization */ |
| 2565 | INT_Trace_Enter(INIT_DRV1_TTY); |
| 2566 | DclSerialPort_Initialize(); |
| 2567 | INT_Trace_Exit(INIT_DRV1_TTY); |
| 2568 | |
| 2569 | //int gpt module |
| 2570 | INT_Trace_Enter(INIT_DRV1_GPTI); |
| 2571 | DclSGPT_Initialize(); |
| 2572 | INT_Trace_Exit(INIT_DRV1_GPTI); |
| 2573 | |
| 2574 | //init uart1 |
| 2575 | INT_Trace_Enter(INIT_DRV1_UART1); |
| 2576 | uart_handle = DclSerialPort_Open(uart_port1, 0); |
| 2577 | DclSerialPort_DrvRegisterCb(uart_handle, &Uart_Drv_Handler); |
| 2578 | DclSerialPort_DrvAttach(uart_handle); |
| 2579 | DclSerialPort_Control(uart_handle,SIO_CMD_INIT,&data); |
| 2580 | INT_Trace_Exit(INIT_DRV1_UART1); |
| 2581 | |
| 2582 | // VoLTE core will use UART2 (share UART0) |
| 2583 | //init uart2 |
| 2584 | INT_Trace_Enter(INIT_DRV1_UART2); |
| 2585 | uart_handle = DclSerialPort_Open(uart_port2, 0); |
| 2586 | DclSerialPort_DrvRegisterCb(uart_handle, &Uart_Drv_Handler); |
| 2587 | DclSerialPort_DrvAttach(uart_handle); |
| 2588 | DclSerialPort_Control(uart_handle,SIO_CMD_INIT,&data); |
| 2589 | INT_Trace_Exit(INIT_DRV1_UART2); |
| 2590 | |
| 2591 | #ifdef __HIF_CCCI_SUPPORT__ |
| 2592 | INT_Trace_Enter(INIT_DRV1_CCCI); |
| 2593 | lte_ccci_hal_init(); |
| 2594 | INT_Trace_Exit(INIT_DRV1_CCCI); |
| 2595 | #endif |
| 2596 | |
| 2597 | #ifdef __HIF_PCCIF4_SUPPORT__ |
| 2598 | INT_Trace_Enter(INIT_DRV1_PCCIF4); |
| 2599 | pccif4_isr_init(); |
| 2600 | INT_Trace_Exit(INIT_DRV1_PCCIF4); |
| 2601 | #endif |
| 2602 | |
| 2603 | #ifdef __HIF_PCCIF5_SUPPORT__ |
| 2604 | INT_Trace_Enter(INIT_DRV1_PCCIF5); |
| 2605 | pccif5_isr_init(); |
| 2606 | INT_Trace_Exit(INIT_DRV1_PCCIF5); |
| 2607 | #endif |
| 2608 | |
| 2609 | /* update the system boot mode */ |
| 2610 | /*lint -e552*/ |
| 2611 | system_boot_mode = Drv_query_boot_mode_at_init(); |
| 2612 | /*lint +e552*/ |
| 2613 | print_boot_mode(); |
| 2614 | |
| 2615 | // 2016/07/26 request by Chi-Yen Yu |
| 2616 | #if !defined(__TCM_ONLY_LOAD__) && !defined(__FLAVOR_BASIC__) |
| 2617 | prbm_init(); |
| 2618 | #endif |
| 2619 | /**/ |
| 2620 | /* =========== Above is Init Flow of FPGA =============== */ |
| 2621 | /**/ |
| 2622 | |
| 2623 | #else /* Not __FPGA__, means ASIC */ |
| 2624 | |
| 2625 | /**/ |
| 2626 | /* =========== Below is Init Flow of ASIC =============== */ |
| 2627 | /**/ |
| 2628 | |
| 2629 | |
| 2630 | #if defined(DRV_GPT_GPT3) && (!defined(__LTE_RAT__)) |
| 2631 | DCL_HANDLE gpt_handle; |
| 2632 | #endif //defined(DRV_GPT_GPT3) |
| 2633 | #ifndef DRV_RTC_NOT_EXIST |
| 2634 | DCL_HANDLE rtc_handler; |
| 2635 | #endif //#ifndef DRV_RTC_NOT_EXIST |
| 2636 | |
| 2637 | DCL_HANDLE uart_handle; |
| 2638 | DCL_CTRL_DATA_T data; |
| 2639 | extern Seriport_HANDLER_T Uart_Drv_Handler; |
| 2640 | |
| 2641 | #if defined(__MTK_TARGET__) |
| 2642 | /* register bb reg dump */ |
| 2643 | devdrv_dump.regions = (kal_uint32*)devdrv_dump_regions; |
| 2644 | devdrv_dump.num = sizeof(devdrv_dump_regions) / (sizeof(kal_uint32) * 3); |
| 2645 | devdrv_dump.bbreg_dump_callback = NULL; |
| 2646 | EX_REGISTER_BBREG_DUMP(&devdrv_dump); |
| 2647 | #endif /* __MTK_TARGET__ */ |
| 2648 | |
| 2649 | #ifdef __BACKUP_DOWNLOAD_RESTORE_WITHOUT_BATTERY__ |
| 2650 | if (INT_GetSysStaByCmd(CHK_USB_META_WO_BAT, NULL)==KAL_TRUE) |
| 2651 | { |
| 2652 | |
| 2653 | #if !defined(CHIP10992) |
| 2654 | DCL_HANDLE handle; |
| 2655 | DclPMU_Initialize(); |
| 2656 | handle = DclPMU_Open(DCL_PMU, FLAGS_NONE); |
| 2657 | DclPMU_Control(handle, CHR_SET_CHARGE_WITHOUT_BATTERY, NULL); |
| 2658 | DclPMU_Close(handle); |
| 2659 | #endif |
| 2660 | |
| 2661 | } |
| 2662 | #endif //#ifdef __BACKUP_DOWNLOAD_RESTORE_WITHOUT_BATTERY__ |
| 2663 | |
| 2664 | #if defined(__SCC_SIB_SUPPORT__) |
| 2665 | // Init SIB Related IP Driver |
| 2666 | scc_init(); |
| 2667 | #endif |
| 2668 | |
| 2669 | CMIF_Init(); |
| 2670 | CUIF_Init(); |
| 2671 | /* TTY initialization */ |
| 2672 | INT_Trace_Enter(INIT_DRV1_TTY); |
| 2673 | DclSerialPort_Initialize(); |
| 2674 | INT_Trace_Exit(INIT_DRV1_TTY); |
| 2675 | |
| 2676 | /* 20160921 : according to WCT1_CD2_DSD Chun-Hsien Lu's requirement, remove MTAD relate code */ |
| 2677 | /* attach MTAD driver to TTYcore, if SIB was enabled */ |
| 2678 | //#if defined(__SCC_SIB_SUPPORT__) |
| 2679 | // mtad_driver_attach_to_tty(); |
| 2680 | //#endif |
| 2681 | |
| 2682 | #if defined(__DSP_FCORE4__) |
| 2683 | INT_Trace_Enter(INIT_DRV1_MDCIHW); |
| 2684 | mdci_hw_init(1,0x0); |
| 2685 | INT_Trace_Exit(INIT_DRV1_MDCIHW); |
| 2686 | #endif |
| 2687 | |
| 2688 | #ifdef __HIF_CCCI_SUPPORT__ |
| 2689 | INT_Trace_Enter(INIT_DRV1_CCCI); |
| 2690 | lte_ccci_hal_init(); |
| 2691 | INT_Trace_Exit(INIT_DRV1_CCCI); |
| 2692 | |
| 2693 | INT_Trace_Enter(INIT_DRV1_OSTD_CCCI_CALLBACK); |
| 2694 | OSTD_register_ccci_callback(); |
| 2695 | INT_Trace_Exit(ININIT_DRV1_OSTD_CCCI_CALLBACK); |
| 2696 | #endif |
| 2697 | |
| 2698 | #ifdef __HIF_PCCIF4_SUPPORT__ |
| 2699 | INT_Trace_Enter(INIT_DRV1_PCCIF4); |
| 2700 | pccif4_isr_init(); |
| 2701 | INT_Trace_Exit(INIT_DRV1_PCCIF4); |
| 2702 | #endif |
| 2703 | |
| 2704 | #ifdef __HIF_PCCIF5_SUPPORT__ |
| 2705 | INT_Trace_Enter(INIT_DRV1_PCCIF5); |
| 2706 | pccif5_isr_init(); |
| 2707 | INT_Trace_Exit(INIT_DRV1_PCCIF5); |
| 2708 | #endif |
| 2709 | |
| 2710 | #ifdef __HIF_MHCCIF_SUPPORT__ |
| 2711 | INT_Trace_Enter(INIT_DRV1_MHCCIF); |
| 2712 | mhccif_init(); |
| 2713 | INT_Trace_Exit(INIT_DRV1_MHCCIF); |
| 2714 | #endif |
| 2715 | |
| 2716 | #ifdef __HIF_PCIE_SUPPORT__ |
| 2717 | INT_Trace_Enter(INIT_DRV1_PCIE); |
| 2718 | hifpcie_init(); |
| 2719 | INT_Trace_Exit(INIT_DRV1_PCIE); |
| 2720 | #endif |
| 2721 | |
| 2722 | #if defined(DRV_EMIMPU) |
| 2723 | INT_Trace_Enter(INIT_DRV1_EMIMPU); |
| 2724 | emimpu_init(); |
| 2725 | INT_Trace_Exit(INIT_DRV1_EMIMPU); |
| 2726 | #endif /* DRV_EMIMPU */ |
| 2727 | |
| 2728 | #ifndef DRV_PWM_NOT_EXIST |
| 2729 | INT_Trace_Enter(INIT_DRV1_PWM); |
| 2730 | DclPWM_Initialize(); |
| 2731 | INT_Trace_Exit(INIT_DRV1_PWM); |
| 2732 | #endif |
| 2733 | |
| 2734 | /*To get all customized data*/ |
| 2735 | INT_Trace_Enter(INIT_DRV1_CUSTOM); |
| 2736 | |
| 2737 | Drv_Customize_Init(); |
| 2738 | custom_drv_init(); |
| 2739 | |
| 2740 | INT_Trace_Exit(INIT_DRV1_CUSTOM); |
| 2741 | |
| 2742 | #if defined(DRV_GPT_GPT3) && (!defined(__LTE_RAT__)) |
| 2743 | INT_Trace_Enter(INIT_DRV1_GPT3); |
| 2744 | /*turn on gpt3 to count powen on period*/ |
| 2745 | DclFGPT_Initialize(); |
| 2746 | gpt_handle=DclFGPT_Open(DCL_GPT_FreeRUN3,0); |
| 2747 | DclFGPT_Control(gpt_handle,FGPT_CMD_START,0); |
| 2748 | DclFGPT_Close(gpt_handle); |
| 2749 | INT_Trace_Exit(INIT_DRV1_GPT3); |
| 2750 | #endif |
| 2751 | |
| 2752 | #if 0 /* comment unused code after annouce at 2016/02/02 */ |
| 2753 | #if defined(MULTI_MEDIA_EXIST) |
| 2754 | /* under construction !*/ |
| 2755 | /* under construction !*/ |
| 2756 | /* under construction !*/ |
| 2757 | #endif /* defined(MULTI_MEDIA_EXIST)*/ |
| 2758 | #endif |
| 2759 | |
| 2760 | #ifdef DRV_MISC_DMA_NO_MEMCPY |
| 2761 | DRV_MEMCPY = (MEMCPY_FUNC)0x48000150; |
| 2762 | #elif defined(DRV_MISC_DMA_MEMCPY) |
| 2763 | DRV_MEMCPY_PTR = (MEMCPY_FUNC)0x48000134; |
| 2764 | #endif |
| 2765 | |
| 2766 | INT_Trace_Enter(INIT_DRV1_GPTI); |
| 2767 | DclSGPT_Initialize(); |
| 2768 | INT_Trace_Exit(INIT_DRV1_GPTI); |
| 2769 | |
| 2770 | INT_Trace_Enter(INIT_DRV1_WDT); |
| 2771 | WDT_init(); |
| 2772 | INT_Trace_Exit(INIT_DRV1_WDT); |
| 2773 | |
| 2774 | |
| 2775 | { |
| 2776 | // F32K HW init |
| 2777 | DCL_HANDLE F32K_handle; |
| 2778 | F32K_handle = DclF32K_Open(DCL_F32K_CLK, FLAGS_NONE); |
| 2779 | DclF32K_Control(F32K_handle, F32K_CLK_CMD_HW_INIT, (DCL_CTRL_DATA_T *)NULL); |
| 2780 | DclF32K_Close(F32K_handle); |
| 2781 | } |
| 2782 | |
| 2783 | #ifndef DRV_RTC_NOT_EXIST |
| 2784 | // need to set XOSC earlier |
| 2785 | INT_Trace_Enter(INIT_DRV1_XOSC); |
| 2786 | rtc_handler = DclRTC_Open(DCL_RTC,FLAGS_NONE); |
| 2787 | DclRTC_Control(rtc_handler, RTC_CMD_SETXOSC, (DCL_CTRL_DATA_T *)NULL); |
| 2788 | INT_Trace_Exit(INIT_DRV1_XOSC); |
| 2789 | #endif /*DRV_RTC_NOT_EXIST*/ |
| 2790 | |
| 2791 | |
| 2792 | #if 0 /* comment unused code after annouce at 2016/02/02 */ |
| 2793 | #ifdef __DRV_EXT_ACCESSORY_DETECTION__ |
| 2794 | /* under construction !*/ |
| 2795 | /* under construction !*/ |
| 2796 | /* under construction !*/ |
| 2797 | /* under construction !*/ |
| 2798 | /* under construction !*/ |
| 2799 | /* under construction !*/ |
| 2800 | #endif // #ifdef __DRV_EXT_ACCESSORY_DETECTION__ |
| 2801 | #endif |
| 2802 | |
| 2803 | #if 0 /* comment unused code after annouce at 2016/02/02 */ |
| 2804 | #if defined(__RESOURCE_MANAGER__) |
| 2805 | /* under construction !*/ |
| 2806 | /* under construction !*/ |
| 2807 | /* under construction !*/ |
| 2808 | #endif //__RESOURCE_MANAGER__ |
| 2809 | #endif |
| 2810 | |
| 2811 | #ifndef DRV_RTC_NOT_EXIST |
| 2812 | #ifdef DRV_RTC_HW_CALI |
| 2813 | print_bootup_trace_enter(SST_INIT_DRV1_RTCHW); |
| 2814 | DclRTC_Control(rtc_handler, RTC_CMD_HW_INIT, (DCL_CTRL_DATA_T *)NULL); |
| 2815 | print_bootup_trace_exit(SST_INIT_DRV1_RTCHW); |
| 2816 | #endif |
| 2817 | #endif /*DRV_RTC_NOT_EXIST*/ |
| 2818 | //DclPW_Initialize(); |
| 2819 | |
| 2820 | DclSPMI_Initialize(); |
| 2821 | |
| 2822 | #if !defined(CHIP10992) |
| 2823 | DclPMU_Initialize(); |
| 2824 | #endif |
| 2825 | |
| 2826 | Drv_PW_Init(); |
| 2827 | |
| 2828 | /* update the system boot mode */ |
| 2829 | /*lint -e552*/ |
| 2830 | system_boot_mode = Drv_query_boot_mode_at_init(); |
| 2831 | /*lint +e552*/ |
| 2832 | print_boot_mode(); |
| 2833 | |
| 2834 | INT_Trace_Enter(INIT_DRV1_UART1); |
| 2835 | uart_handle = DclSerialPort_Open(uart_port1, 0); |
| 2836 | DclSerialPort_DrvRegisterCb(uart_handle, &Uart_Drv_Handler); |
| 2837 | DclSerialPort_DrvAttach(uart_handle); |
| 2838 | |
| 2839 | // Initialization |
| 2840 | |
| 2841 | DclSerialPort_Control(uart_handle,SIO_CMD_INIT,&data); |
| 2842 | INT_Trace_Exit(INIT_DRV1_UART1); |
| 2843 | |
| 2844 | #if defined(__ANDROID_MODEM__) && !defined(__X_BOOTING__) |
| 2845 | //in Router product. SUART0 is AP own, so it should not be init here. |
| 2846 | UART_PDN_Enable(uart_port2); |
| 2847 | #else |
| 2848 | // Register the callback function |
| 2849 | INT_Trace_Enter(INIT_DRV1_UART2); |
| 2850 | uart_handle = DclSerialPort_Open(uart_port2, 0); |
| 2851 | DclSerialPort_DrvRegisterCb(uart_handle, &Uart_Drv_Handler); |
| 2852 | DclSerialPort_DrvAttach(uart_handle); |
| 2853 | |
| 2854 | // Initialization |
| 2855 | DclSerialPort_Control(uart_handle,SIO_CMD_INIT,&data); |
| 2856 | INT_Trace_Exit(INIT_DRV1_UART2); |
| 2857 | #endif |
| 2858 | #ifdef __UART3_SUPPORT__ |
| 2859 | INT_Trace_Enter(INIT_DRV1_UART3); |
| 2860 | // Register the callback function |
| 2861 | uart_handle = DclSerialPort_Open(uart_port3, 0); |
| 2862 | DclSerialPort_DrvRegisterCb(uart_handle, &Uart_Drv_Handler); |
| 2863 | DclSerialPort_DrvAttach(uart_handle); |
| 2864 | DclSerialPort_Control(uart_handle,SIO_CMD_INIT,(DCL_CTRL_DATA_T *)&data_init); |
| 2865 | INT_Trace_Exit(INIT_DRV1_UART3); |
| 2866 | #endif |
| 2867 | |
| 2868 | // 2016/07/26 request by Chi-Yen Yu |
| 2869 | #if (!defined(__TCM_ONLY_LOAD__) && !defined(__FLAVOR_BASIC__)) || defined(ATEST_DPCOPRO_EN) |
| 2870 | prbm_init(); |
| 2871 | #endif |
| 2872 | /**/ |
| 2873 | /* =========== Above is Init Flow of ASIC =============== */ |
| 2874 | /**/ |
| 2875 | |
| 2876 | #endif |
| 2877 | } |
| 2878 | |
| 2879 | /* |
| 2880 | * FUNCTION |
| 2881 | * Drv_Init_Phase2 |
| 2882 | * |
| 2883 | * DESCRIPTION |
| 2884 | * This function is the NFB phase2 (Secondary ROM) initial function for |
| 2885 | * all device drivers. |
| 2886 | * This function is called once to initialize the device driver. |
| 2887 | * |
| 2888 | * CALLS |
| 2889 | * |
| 2890 | * PARAMETERS |
| 2891 | * None |
| 2892 | * |
| 2893 | * RETURNS |
| 2894 | * None |
| 2895 | * |
| 2896 | * GLOBALS AFFECTED |
| 2897 | * external_global |
| 2898 | * |
| 2899 | * NOTE XXX |
| 2900 | * All sub functions reference by this function should be placed on |
| 2901 | * Secondary ROM for NFB projects. |
| 2902 | */ |
| 2903 | void Drv_Init_Phase2(void) |
| 2904 | { |
| 2905 | |
| 2906 | #if defined (__FPGA__) |
| 2907 | |
| 2908 | /**/ |
| 2909 | /* =========== Below is Init Flow of FPGA =============== */ |
| 2910 | /**/ |
| 2911 | |
| 2912 | |
| 2913 | #if defined(__CMUX_SUPPORT__) || (defined(__BTMTK__) && (defined(__BT_SPP_PROFILE__) || defined(__BT_HFG_PROFILE__))) |
| 2914 | DCL_HANDLE uart_handle; |
| 2915 | #endif /* __CMUX_SUPPORT__ || (__BTMTK__ && (__BT_SPP_PROFILE__ || __BT_HFG_PROFILE__)) */ |
| 2916 | |
| 2917 | #if defined(__BTMTK__) && (defined(__BT_SPP_PROFILE__) || defined(__BT_HFG_PROFILE__)) |
| 2918 | { |
| 2919 | kal_uint16 i; |
| 2920 | for(i = (kal_uint16)start_of_virtual_port; i < (kal_uint16)end_of_virtual_port + 1; i++) |
| 2921 | { |
| 2922 | uart_handle = DclSerialPort_Open((DCL_DEV)i, 0); |
| 2923 | DclSerialPort_RegisterCallback(uart_handle, &SPPA_Uart_Drv_Handler); |
| 2924 | } |
| 2925 | } |
| 2926 | #elif defined __CMUX_SUPPORT__ |
| 2927 | { |
| 2928 | kal_uint16 i; |
| 2929 | for(i = (kal_uint16)start_of_virtual_port; i < (kal_uint16)end_of_virtual_port + 1; i++) |
| 2930 | { |
| 2931 | uart_handle = DclSerialPort_Open((DCL_DEV)i, 0); |
| 2932 | DclSerialPort_DrvRegisterCb(uart_handle, &CmuxUart_Drv_Handler); |
| 2933 | DclSerialPort_DrvAttach(uart_handle); |
| 2934 | } |
| 2935 | } |
| 2936 | #endif |
| 2937 | |
| 2938 | #ifdef __SIM_DRV_MULTI_DRV_ARCH__ |
| 2939 | INT_Trace_Enter(INIT_DRV2_SIM); |
| 2940 | DclSIM_Initialize(); |
| 2941 | INT_Trace_Exit(INIT_DRV2_SIM); |
| 2942 | #endif |
| 2943 | |
| 2944 | |
| 2945 | /**/ |
| 2946 | /* =========== Above is Init Flow of FPGA =============== */ |
| 2947 | /**/ |
| 2948 | |
| 2949 | #else /* Not __FPGA__, means ASIC */ |
| 2950 | |
| 2951 | /**/ |
| 2952 | /* =========== Below is Init Flow of ASIC =============== */ |
| 2953 | /**/ |
| 2954 | |
| 2955 | #if defined(__CMUX_SUPPORT__) || (defined(__BTMTK__) && (defined(__BT_SPP_PROFILE__) || defined(__BT_HFG_PROFILE__))) |
| 2956 | DCL_HANDLE uart_handle; |
| 2957 | #endif /* __CMUX_SUPPORT__ || (__BTMTK__ && (__BT_SPP_PROFILE__ || __BT_HFG_PROFILE__)) */ |
| 2958 | |
| 2959 | #ifndef DRV_RTC_NOT_EXIST |
| 2960 | DCL_HANDLE rtc_handler; |
| 2961 | #endif /*DRV_RTC_NOT_EXIST*/ |
| 2962 | |
| 2963 | #if defined(IC_BURNIN_TEST) || defined(DRV_MISC_GPT1_AS_OS_TICK) |
| 2964 | /*AB: Enable GPT1 for OS tick in the burn-in test load*/ |
| 2965 | extern void GPT_init(kal_uint8 timerNum, void (*GPT_Callback)(void)); |
| 2966 | extern void GPT_ResetTimer(kal_uint8 timerNum,kal_uint16 countValue,kal_bool autoReload); |
| 2967 | extern void GPT_Start(kal_uint8 timerNum); |
| 2968 | GPT_init(1, INT_Timer_Interrupt); |
| 2969 | GPT_ResetTimer(1, 4, KAL_TRUE); |
| 2970 | GPT_Start(1); |
| 2971 | #endif //IC_BURNIN_TEST |
| 2972 | |
| 2973 | #if defined(__BTMTK__) && (defined(__BT_SPP_PROFILE__) || defined(__BT_HFG_PROFILE__)) |
| 2974 | { |
| 2975 | kal_uint16 i; |
| 2976 | for(i = (kal_uint16)start_of_virtual_port; i < (kal_uint16)end_of_virtual_port + 1; i++) |
| 2977 | { |
| 2978 | uart_handle = DclSerialPort_Open((DCL_DEV)i, 0); |
| 2979 | DclSerialPort_RegisterCallback(uart_handle, &SPPA_Uart_Drv_Handler); |
| 2980 | } |
| 2981 | } |
| 2982 | #elif defined __CMUX_SUPPORT__ |
| 2983 | { |
| 2984 | kal_uint16 i; |
| 2985 | for(i = (kal_uint16)start_of_virtual_port; i < (kal_uint16)end_of_virtual_port + 1; i++) |
| 2986 | { |
| 2987 | uart_handle = DclSerialPort_Open((DCL_DEV)i, 0); |
| 2988 | DclSerialPort_DrvRegisterCb(uart_handle, &CmuxUart_Drv_Handler); |
| 2989 | DclSerialPort_DrvAttach(uart_handle); |
| 2990 | } |
| 2991 | } |
| 2992 | #endif |
| 2993 | |
| 2994 | #if 0 /* comment unused code after annouce at 2016/02/02 */ |
| 2995 | #ifndef DRV_KBD_NOT_EXIST |
| 2996 | /* under construction !*/ |
| 2997 | /* under construction !*/ |
| 2998 | /* under construction !*/ |
| 2999 | #endif /*DRV_KBD_NOT_EXIST*/ |
| 3000 | #endif |
| 3001 | |
| 3002 | #ifndef DRV_RTC_NOT_EXIST |
| 3003 | INT_Trace_Enter(INIT_DRV2_RTCSW); |
| 3004 | rtc_handler = DclRTC_Open(DCL_RTC,FLAGS_NONE); |
| 3005 | DclRTC_Control(rtc_handler, RTC_CMD_INIT_TC_AL_INTR, (DCL_CTRL_DATA_T *)NULL); |
| 3006 | INT_Trace_Exit(INIT_DRV2_RTCSW); |
| 3007 | #endif /*DRV_RTC_NOT_EXIST*/ |
| 3008 | |
| 3009 | #ifdef __SIM_DRV_MULTI_DRV_ARCH__ |
| 3010 | INT_Trace_Enter(INIT_DRV2_SIM); |
| 3011 | DclSIM_Initialize(); |
| 3012 | INT_Trace_Exit(INIT_DRV2_SIM); |
| 3013 | #endif |
| 3014 | |
| 3015 | #if (defined( DRV_MULTIPLE_SIM) && (!defined(DRV_2_SIM_CONTROLLER))) |
| 3016 | INT_Trace_Enter(INIT_DRV2_SIMMT6302); |
| 3017 | sim_MT6302_init(); |
| 3018 | INT_Trace_Exit(INIT_DRV2_SIMMT6302); |
| 3019 | #endif |
| 3020 | |
| 3021 | #if defined(ATEST_DRV_ENABLE) && !defined(ATEST_DRV_MSDC) |
| 3022 | |
| 3023 | #else //defined(ATEST_DRV_ENABLE) && !defined(ATEST_DRV_MSDC) |
| 3024 | |
| 3025 | #if defined(__MSDC_SD_MMC__) |
| 3026 | INT_Trace_Enter(INIT_DRV2_MSDC); |
| 3027 | #if !defined(DCL_MSDC_INTERFACE) |
| 3028 | MSDC_Initialize(); |
| 3029 | #else |
| 3030 | DclSD_Initialize(); |
| 3031 | #endif//!defined(DCL_MSDC_INTERFACE) |
| 3032 | INT_Trace_Exit(INIT_DRV2_MSDC); |
| 3033 | #endif // defined(__MSDC_SD_MMC__) |
| 3034 | |
| 3035 | #if defined(__MSDC2_SD_MMC__) || defined(__MSDC2_SD_SDIO__) |
| 3036 | INT_Trace_Enter(INIT_DRV2_MSDC2); |
| 3037 | #if !defined(DCL_MSDC_INTERFACE) |
| 3038 | MSDC_Initialize2(); |
| 3039 | #endif//!defined(DCL_MSDC_INTERFACE) |
| 3040 | INT_Trace_Exit(INIT_DRV2_MSDC2); |
| 3041 | #endif//defined(__MSDC2_SD_MMC__) || defined(__MSDC2_SD_SDIO__) |
| 3042 | #endif //defined(ATEST_DRV_ENABLE) && !defined(ATEST_DRV_MSDC) |
| 3043 | |
| 3044 | #ifdef IC_MODULE_TEST |
| 3045 | IC_ModuleTest_Start(); |
| 3046 | #endif /*IC_MODULE_TEST*/ |
| 3047 | |
| 3048 | #ifdef MT6218B/*only 6218B has this */ |
| 3049 | GCU_Disable_ReverseBit(); |
| 3050 | #endif |
| 3051 | #ifdef __SWDBG_SUPPORT__ |
| 3052 | |
| 3053 | /* initialize SWDBG */ |
| 3054 | INT_Trace_Enter(INIT_DRV2_SWDBG); |
| 3055 | swdbg_init(); |
| 3056 | INT_Trace_Exit(INIT_DRV2_SWDBG); |
| 3057 | |
| 3058 | #endif /* __SWDBG_SUPPORT__ */ |
| 3059 | |
| 3060 | #if 0 /* comment unused code after annouce at 2016/02/02 */ |
| 3061 | /* under construction !*/ |
| 3062 | #if defined(ISP_SUPPORT) |
| 3063 | /* under construction !*/ |
| 3064 | /* under construction !*/ |
| 3065 | /* under construction !*/ |
| 3066 | #endif |
| 3067 | #endif |
| 3068 | |
| 3069 | #if 0 /* comment unused code after annouce at 2016/02/02 */ |
| 3070 | #ifdef __WIFI_SUPPORT__ |
| 3071 | /* under construction !*/ |
| 3072 | /* under construction !*/ |
| 3073 | /* under construction !*/ |
| 3074 | #endif |
| 3075 | #endif |
| 3076 | |
| 3077 | #if 0 //There is no I2C driver request for MT6290 |
| 3078 | /* under construction !*/ |
| 3079 | #if defined(DRV_I2C_25_SERIES) |
| 3080 | /* under construction !*/ |
| 3081 | /* under construction !*/ |
| 3082 | /* under construction !*/ |
| 3083 | #endif |
| 3084 | #endif |
| 3085 | |
| 3086 | #if 0 /* comment unused code after annouce at 2016/02/02 */ |
| 3087 | /* under construction !*/ |
| 3088 | /* under construction !*/ |
| 3089 | #if defined(__PXS_ENABLE__) && !defined(IC_MODULE_TEST) && !defined(IC_BURNIN_TEST) |
| 3090 | /* under construction !*/ |
| 3091 | #endif // #if defined(__PXS_ENABLE__) && !defined(IC_MODULE_TEST) && !defined(IC_BURNIN_TEST) |
| 3092 | #endif |
| 3093 | |
| 3094 | #if 0 /* comment unused code after annouce at 2016/02/02 */ |
| 3095 | #ifdef CAS_SMD_SUPPORT |
| 3096 | /* under construction !*/ |
| 3097 | /* under construction !*/ |
| 3098 | /* under construction !*/ |
| 3099 | #endif |
| 3100 | #endif |
| 3101 | |
| 3102 | #if 0 // Init BTIF_HWInit_VFIFO(); in bluetooth module |
| 3103 | #if defined(__BTMODULE_MT6236__) |
| 3104 | /* under construction !*/ |
| 3105 | /* under construction !*/ |
| 3106 | /* under construction !*/ |
| 3107 | #elif defined(__BTMODULE_MT6256__) || defined(__BTMODULE_MT6276__) |
| 3108 | /* under construction !*/ |
| 3109 | #endif |
| 3110 | /* under construction !*/ |
| 3111 | #endif // 0 |
| 3112 | |
| 3113 | //#ifdef DRV_HIF_SUPPORT |
| 3114 | //hif_init(); |
| 3115 | //#endif |
| 3116 | //#ifdef DRV_SPI_SUPPORT |
| 3117 | //spi_init(); |
| 3118 | //#endif |
| 3119 | #if defined(__TOUCH_PANEL_CAPACITY__) |
| 3120 | DclSTS_Initialize(); |
| 3121 | #endif |
| 3122 | |
| 3123 | #if defined(MOTION_SENSOR_SUPPORT) |
| 3124 | INT_Trace_Enter(INIT_DRV2_MSENS); |
| 3125 | motion_sensor_init(); |
| 3126 | INT_Trace_Exit(INIT_DRV2_MSENS); |
| 3127 | #endif |
| 3128 | |
| 3129 | INT_Trace_Enter(INIT_DRV2_ADC); |
| 3130 | DclHADC_Initialize(); |
| 3131 | DclSADC_Initialize(); |
| 3132 | INT_Trace_Exit(INIT_DRV2_ADC); |
| 3133 | |
| 3134 | INT_Trace_Enter(INIT_DRV2_SOE); |
| 3135 | SOE_Drv_Init(); |
| 3136 | INT_Trace_Exit(INIT_DRV2_SOE); |
| 3137 | |
| 3138 | EINT_Setting_Init(); |
| 3139 | |
| 3140 | #ifdef __HIF_PCIE_SUPPORT__ |
| 3141 | /* Must init after EINT */ |
| 3142 | INT_Trace_Enter(INIT_DRV2_PCIE2); |
| 3143 | hifpcie_init_2(); |
| 3144 | INT_Trace_Exit(INIT_DRV2_PCIE2); |
| 3145 | #endif |
| 3146 | |
| 3147 | /**/ |
| 3148 | /* =========== Above is Init Flow of ASIC =============== */ |
| 3149 | /**/ |
| 3150 | |
| 3151 | #endif |
| 3152 | } |
| 3153 | |
| 3154 | /* |
| 3155 | * FUNCTION |
| 3156 | * Drv_Deinit |
| 3157 | * |
| 3158 | * DESCRIPTION |
| 3159 | * This function is the deinitial function for all device drivers. |
| 3160 | * This function is called once to deinitialize the device driver. |
| 3161 | * |
| 3162 | * CALLS |
| 3163 | * |
| 3164 | * PARAMETERS |
| 3165 | * None |
| 3166 | * |
| 3167 | * RETURNS |
| 3168 | * None |
| 3169 | * |
| 3170 | * GLOBALS AFFECTED |
| 3171 | * external_global |
| 3172 | */ |
| 3173 | void Drv_Deinit(void) |
| 3174 | { |
| 3175 | /* Don't do driver deinit when still in system initialization stage. |
| 3176 | Otherwise it may cause problem in NFI booting. */ |
| 3177 | if (KAL_FALSE == kal_query_systemInit()) |
| 3178 | { |
| 3179 | custom_drv_deinit(); |
| 3180 | #if 0 /* comment unused code after annouce at 2016/02/02 */ |
| 3181 | #ifdef __BTMODULE_MT6601__ |
| 3182 | /* under construction !*/ |
| 3183 | #endif |
| 3184 | #endif |
| 3185 | } |
| 3186 | |
| 3187 | { |
| 3188 | DCL_HANDLE usb_hcd; |
| 3189 | |
| 3190 | usb_hcd = DclUSB_HCD_Open(DCL_USB, FLAGS_NONE); |
| 3191 | DclUSB_HCD_Control(usb_hcd, USB_HCD_CMD_USB_HCD_VBUS_OFF, NULL); // turn off Vbus 5V |
| 3192 | DclUSB_HCD_Close(usb_hcd); |
| 3193 | } |
| 3194 | } |
| 3195 | |
| 3196 | #if defined(DRV_MISC_DMA_MEMCPY) |
| 3197 | void DRV_MEMCPY(const void *srcaddr, void *dstaddr, kal_uint32 len) |
| 3198 | { |
| 3199 | if (!DMA_memcpy(srcaddr,dstaddr,len)) |
| 3200 | DRV_MEMCPY_PTR(srcaddr,dstaddr,len); |
| 3201 | } |
| 3202 | #endif /*DRV_MISC_DMA_MEMCPY*/ |
| 3203 | |
| 3204 | |
| 3205 | kal_bool Drv_WriteReg(kal_uint32 addr, kal_uint16 data) |
| 3206 | { |
| 3207 | #ifdef __LTE_RAT__ |
| 3208 | if (addr < 0xB0000000) |
| 3209 | return KAL_FALSE; |
| 3210 | #else |
| 3211 | if (addr < 0x70000000) |
| 3212 | return KAL_FALSE; |
| 3213 | #endif |
| 3214 | |
| 3215 | DRV_MISC_WriteReg(addr,data); |
| 3216 | return KAL_TRUE; |
| 3217 | } |
| 3218 | |
| 3219 | kal_bool Drv_ReadReg(kal_uint32 addr, kal_uint16 *data) |
| 3220 | { |
| 3221 | #ifdef __LTE_RAT__ |
| 3222 | if (addr < 0xB0000000) |
| 3223 | return KAL_FALSE; |
| 3224 | #else |
| 3225 | if (addr < 0x70000000) |
| 3226 | return KAL_FALSE; |
| 3227 | #endif |
| 3228 | |
| 3229 | *data = DRV_MISC_Reg(addr); |
| 3230 | return KAL_TRUE; |
| 3231 | } |
| 3232 | |
| 3233 | kal_uint32 drv_get_current_time(void) |
| 3234 | { |
| 3235 | |
| 3236 | #if defined(DRV_MISC_TDMA_NO_TIME) |
| 3237 | ASSERT(0); |
| 3238 | #endif /*DRV_MISC_TDMA_NO_TIME*/ |
| 3239 | |
| 3240 | #if defined(DRV_MISC_TDMA_TIME_BASE) |
| 3241 | return (DRV_MISC_Reg32(TDMA_base+0x0230)); |
| 3242 | #elif defined(DRV_MISC_TDMA_TIME_BASE_8200) |
| 3243 | return (DRV_MISC_Reg32(0x82000230)); |
| 3244 | #elif defined(DRV_MISC_TDMA_TIME_BASE_8020) |
| 3245 | return (DRV_MISC_Reg32(0x80200230)); |
| 3246 | #elif defined(DRV_MISC_TDMA_TIME_BASE_8406) |
| 3247 | return (DRV_MISC_Reg32(0x84060230)); |
| 3248 | #elif defined(DRV_MISC_TDMA_L1_MACRO) |
| 3249 | //return (HW_TDMA_GET_32KCNT()); |
| 3250 | // 2014/12/04 , replace 32KCNT function by request of TH Yeh & Hsiao-Hsien Chen |
| 3251 | return RM_GetF32k(); |
| 3252 | #elif defined(DRV_MISC_TOPSM_32K_RTC) /* Get 32K ticks */ |
| 3253 | // 2016/09/01, change to use 32K Tick API provide by low-power team (Owen Ho) |
| 3254 | //return DRV_MISC_Reg32(BASE_ADDR_MDTOPSM+0x0104); |
| 3255 | return MD_TOPSM_Get_F32K_Cnt(); |
| 3256 | #else |
| 3257 | return 0; |
| 3258 | #endif |
| 3259 | |
| 3260 | } |
| 3261 | |
| 3262 | kal_uint32 drv_get_duration_tick(kal_uint32 previous_time, kal_uint32 current_time) |
| 3263 | { |
| 3264 | kal_uint32 result=0; |
| 3265 | #if defined(DRV_MISC_TDMA_NO_TIME) |
| 3266 | ASSERT(0); |
| 3267 | #endif /*DRV_MISC_TDMA_NO_TIME*/ |
| 3268 | |
| 3269 | if (previous_time > current_time) |
| 3270 | { |
| 3271 | //#if defined(DRV_MISC_TDMA_TIME_MAX_80000) |
| 3272 | #if defined(DRV_MISC_TDMA_TIME_MAX_19BITS) |
| 3273 | result = 0x80000 - previous_time + current_time; |
| 3274 | #elif defined(DRV_MISC_TDMA_TIME_MAX_24BITS) |
| 3275 | result = 0x1000000 - previous_time + current_time; |
| 3276 | #elif defined(DRV_MISC_TDMA_TIME_MAX_32BITS) || defined(DRV_MISC_TOPSM_32K_RTC) |
| 3277 | result = 0xFFFFFFFF - previous_time + current_time + 1; |
| 3278 | #else /* use us_counter=>Qbit as tick*/ |
| 3279 | result = 0; |
| 3280 | #endif |
| 3281 | } |
| 3282 | else |
| 3283 | { |
| 3284 | result = current_time - previous_time; |
| 3285 | } |
| 3286 | return result; |
| 3287 | } |
| 3288 | |
| 3289 | kal_uint32 drv_get_duration_ms(kal_uint32 previous_time) |
| 3290 | { |
| 3291 | kal_uint32 result; |
| 3292 | kal_uint32 current_time; |
| 3293 | kal_uint64 temp_value; |
| 3294 | |
| 3295 | current_time = drv_get_current_time(); |
| 3296 | result = drv_get_duration_tick(previous_time, current_time); |
| 3297 | /* X ms = result x 1000/32K = (result x 125)>>12 */ |
| 3298 | temp_value = (kal_uint64)(((kal_uint64) result)*125); |
| 3299 | result = (kal_uint32)(temp_value>>12); |
| 3300 | return result; |
| 3301 | } |
| 3302 | |
| 3303 | #ifdef DRV_MEMORY_TRACE_DEBUG |
| 3304 | DRV_DBG_STRUCT DRV_DBG_INFO_DATA; |
| 3305 | /*drv_dbg_trace(NAND_READ_START,drv_get_current_time(),0,0);*/ |
| 3306 | void drv_dbg_trace(kal_uint16 index, kal_uint32 time, kal_uint32 data1, kal_uint32 data2) |
| 3307 | { |
| 3308 | kal_uint32 savedMask; |
| 3309 | savedMask = SaveAndSetIRQMask(); |
| 3310 | { |
| 3311 | DRV_DBG_INFO_DATA.dbg_data[DRV_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_DBG_INFO_SIZE-1)].tag = index; |
| 3312 | DRV_DBG_INFO_DATA.dbg_data[DRV_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_DBG_INFO_SIZE-1)].time = time; |
| 3313 | DRV_DBG_INFO_DATA.dbg_data[DRV_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_DBG_INFO_SIZE-1)].data1 = data1; |
| 3314 | DRV_DBG_INFO_DATA.dbg_data[DRV_DBG_INFO_DATA.dbg_data_idx&(MAX_DRV_DBG_INFO_SIZE-1)].data2 = data2; |
| 3315 | DRV_DBG_INFO_DATA.dbg_data_idx++; |
| 3316 | } |
| 3317 | RestoreIRQMask(savedMask); |
| 3318 | } |
| 3319 | #endif /*DRV_MEMORY_TRACE_DEBUG*/ |
| 3320 | |
| 3321 | /************************************************************************* |
| 3322 | APIs for driver debugging |
| 3323 | *************************************************************************/ |
| 3324 | #if 0 //#if defined(__TST_MODULE__) |
| 3325 | #if (!defined(MTK_KAL_MNT))&&(!defined(KAL_ON_OSCAR))&&(!defined(MCD_DLL_EXPORT))&&(!defined(L1_SIM))&&(!defined(__FUE__)) |
| 3326 | /* under construction !*/ |
| 3327 | /* under construction !*/ |
| 3328 | /* under construction !*/ |
| 3329 | /* under construction !*/ |
| 3330 | /* under construction !*/ |
| 3331 | /* under construction !*/ |
| 3332 | /* under construction !*/ |
| 3333 | /* under construction !*/ |
| 3334 | /* under construction !*/ |
| 3335 | /* under construction !*/ |
| 3336 | /* under construction !*/ |
| 3337 | /* under construction !*/ |
| 3338 | /* under construction !*/ |
| 3339 | /* under construction !*/ |
| 3340 | /* under construction !*/ |
| 3341 | /* under construction !*/ |
| 3342 | /* under construction !*/ |
| 3343 | /* under construction !*/ |
| 3344 | /* under construction !*/ |
| 3345 | /* under construction !*/ |
| 3346 | /* under construction !*/ |
| 3347 | /* under construction !*/ |
| 3348 | /* under construction !*/ |
| 3349 | /* under construction !*/ |
| 3350 | /* under construction !*/ |
| 3351 | /* under construction !*/ |
| 3352 | /* under construction !*/ |
| 3353 | /* under construction !*/ |
| 3354 | /* under construction !*/ |
| 3355 | /* under construction !*/ |
| 3356 | /* under construction !*/ |
| 3357 | /* under construction !*/ |
| 3358 | /* under construction !*/ |
| 3359 | /* under construction !*/ |
| 3360 | /* under construction !*/ |
| 3361 | /* under construction !*/ |
| 3362 | /* under construction !*/ |
| 3363 | /* under construction !*/ |
| 3364 | /* under construction !*/ |
| 3365 | /* under construction !*/ |
| 3366 | /* under construction !*/ |
| 3367 | /* under construction !*/ |
| 3368 | /* under construction !*/ |
| 3369 | /* under construction !*/ |
| 3370 | /* under construction !*/ |
| 3371 | /* under construction !*/ |
| 3372 | /* under construction !*/ |
| 3373 | /* under construction !*/ |
| 3374 | /* under construction !*/ |
| 3375 | /* under construction !*/ |
| 3376 | /* under construction !*/ |
| 3377 | /* under construction !*/ |
| 3378 | /* under construction !*/ |
| 3379 | /* under construction !*/ |
| 3380 | /* under construction !*/ |
| 3381 | /* under construction !*/ |
| 3382 | /* under construction !*/ |
| 3383 | /* under construction !*/ |
| 3384 | /* under construction !*/ |
| 3385 | /* under construction !*/ |
| 3386 | /* under construction !*/ |
| 3387 | /* under construction !*/ |
| 3388 | /* under construction !*/ |
| 3389 | /* under construction !*/ |
| 3390 | /* under construction !*/ |
| 3391 | /* under construction !*/ |
| 3392 | /* under construction !*/ |
| 3393 | /* under construction !*/ |
| 3394 | /* under construction !*/ |
| 3395 | /* under construction !*/ |
| 3396 | /* under construction !*/ |
| 3397 | /* under construction !*/ |
| 3398 | /* under construction !*/ |
| 3399 | /* under construction !*/ |
| 3400 | /* under construction !*/ |
| 3401 | /* under construction !*/ |
| 3402 | /* under construction !*/ |
| 3403 | /* under construction !*/ |
| 3404 | /* under construction !*/ |
| 3405 | /* under construction !*/ |
| 3406 | #endif /* (!defined(MTK_KAL_MNT))&&(!defined(KAL_ON_OSCAR))&&(!defined(MCD_DLL_EXPORT))&&(!defined(L1_SIM))*/ |
| 3407 | #endif // #if defined(__TST_MODULE__) |
| 3408 | |
| 3409 | kal_uint8 drv_dummy_return(void) |
| 3410 | { |
| 3411 | return 0; |
| 3412 | } |
| 3413 | |