| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | #define D2D_DSP_SEMAPHORESYS_BANK_A_BASE (BASE_MADDR_MCOREPERI_INFRA_DSPSEMAPHORE) |
| 2 | #define D2D_DSP_SEMAPHORESYS_BANK_B_BASE (BASE_NADDR_MCOREPERI_INFRA_DSPSEMAPHORE) |
| 3 | |
| 4 | #define D2D_DSP_SEMAPHORESYS_IDLE_SET_CR_BANK_A_BASE (D2D_DSP_SEMAPHORESYS_BANK_A_BASE + 0x4) |
| 5 | #define D2D_DSP_SEMAPHORESYS_IDLE_SET_CR_BANK_B_BASE (D2D_DSP_SEMAPHORESYS_BANK_A_BASE + 0x4) |
| 6 | |
| 7 | #define D2D_DSP_SEMAPHORESYS_IDLE_STS_CR_BANK_A_BASE (D2D_DSP_SEMAPHORESYS_BANK_B_BASE + 0xC) |
| 8 | #define D2D_DSP_SEMAPHORESYS_IDLE_STS_CR_BANK_B_BASE (D2D_DSP_SEMAPHORESYS_BANK_B_BASE + 0xC) |
| 9 | |
| 10 | volatile kal_uint32 FAIL_MSG[3]; |
| 11 | #define SSDVT_FAIL_MSG(a, b, c) FAIL_MSG[0]=a;FAIL_MSG[1]=b;FAIL_MSG[2]=c;while(1) |
| 12 | #define SSDVT_PASS() FAIL_MSG[0]=6297;FAIL_MSG[1]=6295;FAIL_MSG[2]=6293;while(1) |