| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | #ifndef __EINT_HW_H__ |
| 2 | #define __EINT_HW_H__ |
| 3 | #include "drv_comm.h" |
| 4 | |
| 5 | #define GPIOMUX_BASE_ADDR BASE_MADDR_MDEINT |
| 6 | #define EINT_ADDR_OFFSET 0x1000 |
| 7 | |
| 8 | #define GPIOMUX_EINT_SRC1 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x0)) |
| 9 | //#define GPIOMUX_EINT_SRC2 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x4)) |
| 10 | //#define GPIOMUX_EINT_SRC3 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x8)) |
| 11 | //#define GPIOMUX_EINT_SRC4 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0xC)) |
| 12 | #define GPIOMUX_EINT_DB_EN ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x100)) |
| 13 | #define GPIOMUX_EINT_POL ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x180)) |
| 14 | #define GPIOMUX_EINT_TYPE ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x200)) |
| 15 | #define GPIOMUX_EINT_IRQEN ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x280)) |
| 16 | #define GPIOMUX_EINT_IRQSTS ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x300)) |
| 17 | #define GPIOMUX_EINT_DBNCSTS ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x380)) |
| 18 | #define GPIOMUX_EINT_DUR0 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x400)) |
| 19 | #define GPIOMUX_EINT_DUR1 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x404)) |
| 20 | #define GPIOMUX_EINT_DUR2 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x408)) |
| 21 | #define GPIOMUX_EINT_DUR3 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x40C)) |
| 22 | //#define GPIOMUX_EINT_DUR4 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x410)) |
| 23 | //#define GPIOMUX_EINT_DUR5 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x414)) |
| 24 | //#define GPIOMUX_EINT_DUR6 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x418)) |
| 25 | //#define GPIOMUX_EINT_DUR7 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x41C)) |
| 26 | //#define GPIOMUX_EINT_DUR8 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x420)) |
| 27 | //#define GPIOMUX_EINT_DUR9 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x424)) |
| 28 | //#define GPIOMUX_EINT_DUR10 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x428)) |
| 29 | //#define GPIOMUX_EINT_DUR11 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x42C)) |
| 30 | //#define GPIOMUX_EINT_DUR12 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x430)) |
| 31 | //#define GPIOMUX_EINT_DUR13 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x434)) |
| 32 | //#define GPIOMUX_EINT_DUR14 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x438)) |
| 33 | //#define GPIOMUX_EINT_DUR15 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x43C)) |
| 34 | #define GPIOMUX_EINT_DIRQ0 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x800)) |
| 35 | #define GPIOMUX_EINT_DIRQ1 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x804)) |
| 36 | #define GPIOMUX_EINT_DIRQ2 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x808)) |
| 37 | #define GPIOMUX_EINT_DIRQ3 ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x80C)) |
| 38 | |
| 39 | /* GPIO_MUX part Set and Clear Registers*/ |
| 40 | /* ================================================================= */ |
| 41 | #define GPIOMUX_EINT_DB_EN_SET ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x100 + 0x4)) |
| 42 | #define GPIOMUX_EINT_POL_SET ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x180 + 0x4)) |
| 43 | #define GPIOMUX_EINT_TYPE_SET ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x200 + 0x4)) |
| 44 | #define GPIOMUX_EINT_IRQEN_SET ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x280 + 0x4)) |
| 45 | |
| 46 | |
| 47 | #define GPIOMUX_EINT_DB_EN_CLR ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x100 + 0x8)) |
| 48 | #define GPIOMUX_EINT_POL_CLR ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x180 + 0x8)) |
| 49 | #define GPIOMUX_EINT_TYPE_CLR ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x200 + 0x8)) |
| 50 | #define GPIOMUX_EINT_IRQEN_CLR ((volatile unsigned int*)(GPIOMUX_BASE_ADDR + EINT_ADDR_OFFSET +0x280 + 0x8)) |
| 51 | |
| 52 | #define EINT_L2_STA() REG32(GPIOMUX_EINT_IRQSTS) |
| 53 | #define EINT_L2_ACK(irq) REG32_WRITE(GPIOMUX_EINT_IRQSTS,(1<<irq)) |
| 54 | #endif |