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192.168.1.100 / T800_MD / b0f5b85a5b9d69cbfa1dd990d559a4a9c7d8f2a6 / . / mcu / driver / devdrv / elm / inc / elm.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2012
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * elm.h
41 *
42 * Project:
43 * --------
44 * MOLY
45 *
46 * Description:
47 * ------------
48 * Header file for ELM.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
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219 *------------------------------------------------------------------------------
220 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
221 *============================================================================
222 ****************************************************************************/
223#if !defined(__ELM_H__)
224#define __ELM_H__
225/* ==================== */
226/* CONFIGURATIONS */
227/* ==================== */
228/* ==================== */
229/* INCLUDES */
230/* ==================== */
231#include "reg_base.h"
232#include "kal_general_types.h"
233#include "kal_public_api.h"
234#include "sync_data.h"
235#include "boot.h"
236
237#include "drv_comm.h"
238/*******************************************************************************
239 * Feature Option
240 *******************************************************************************/
241#define ELM_AMIF_ENABLE
242#define ELM_GCR
243#define __ELM_RUNTIME_PROFILE__
244
245
246/* ==================== */
247/* DEFINITIONS */
248/* ==================== */
249#if defined(__MD95__)
250 #define __ELM_MD95__
251 #define ELM_IF_DEF_MD95(def_statement, undef_statement) def_statement
252#elif defined(__MD97__)
253 #define __ELM_MD97__
254#elif defined(__MD97P__)
255 #define __ELM_MD97P__
256#else /* __MCU_DORMANT_MODE__ */
257 #define ELM_IF_DEF_MD95(def_statement, undef_statement) undef_statement
258#endif
259
260#if defined(__ELM_MD95__) || defined(__ELM_MD97__) || defined(__ELM_MD97P__)
261
262#ifdef ELM_GCR
263#define REG_ELM_STAT (GCR_CUSTOM_ADDR + 0x00A0) //0xA0~0xAC, MDMCU, CNT0~CNT3
264#define REG_ELM_WC_STAT (GCR_CUSTOM_ADDR + 0x00B0) //0xB0~0xB4, MDMCU, CNT4~CNT5, only valid in mode0, representing word count
265
266#if defined(MT6297)
267#define REG_INFRA_B_ELM_STAT (GCR_CUSTOM_ADDR + 0x0490) //APOLLO MDINFRA_ELM_B
268#define REG_INFRA_B_ELM_WC_STAT (GCR_CUSTOM_ADDR + 0x04a0) //APOLLO MDINFRA_ELM_B
269
270#define REG_INFRA_ELM_STAT (GCR_CUSTOM_ADDR + 0x060) //APOLLO MDINFRA_ELM_A
271#define REG_INFRA_ELM_WC_STAT (GCR_CUSTOM_ADDR + 0x0B8) //APOLLO MDINFRA_ELM_A
272#else
273#define REG_INFRA_ELM_STAT (GCR_CUSTOM_ADDR + 0x0060) //0x60~0x6C, MDINFRA, CNT0~CNT3
274#define REG_INFRA_ELM_WC_STAT (GCR_CUSTOM_ADDR + 0x00B8) //0xB8~0xBC, MDINFRA, CNT4~CNT5, only valid in mode0, representing word count
275#endif
276
277#else
278#define REG_ELM_STAT (BASE_ADDR_MCUSYS_ELM_EMI + 0x0050)
279#define REG_ELM_WC_STAT (BASE_ADDR_MCUSYS_ELM_EMI + 0x00E0)
280#define REG_INFRA_ELM_STAT (BASE_ADDR_MDINFRA_ELM + 0x0050)
281#define REG_INFRA_ELM_WC_STAT (BASE_ADDR_MDINFRA_ELM + 0x00E0)
282#endif //ifdef ELM_GCR
283#define REG_ELM_STAT_APB (BASE_ADDR_MCUSYS_ELM_EMI + 0x0050)
284#define REG_ELM_WC_STAT_APB (BASE_ADDR_MCUSYS_ELM_EMI + 0x00E0)
285
286#define ELM_GET_WC_CNT(rw, idx, p_cnt) \
287 do {\
288 *p_cnt = DRV_Reg32(REG_ELM_WC_STAT + (rw << 2));\
289 } while(0)
290
291#define ELM_INFRA_GET_WC_CNT(rw, idx, p_cnt) \
292 do {\
293 *p_cnt = DRV_Reg32(REG_INFRA_ELM_WC_STAT + (rw << 2));\
294 } while(0)
295
296#if defined(MT6297)
297#define ELM_INFRA_B_GET_WC_CNT(rw, idx, p_cnt) \
298 do {\
299 *p_cnt = DRV_Reg32(REG_INFRA_B_ELM_WC_STAT + (rw << 2));\
300 } while(0)
301#endif
302
303#else //!__ELM_MD95__
304
305#ifdef ELM_GCR
306#define REG_ELM_STAT (GCR_CUSTOM_ADDR + 0x00B0)
307#define REG_INFRA_ELM_STAT (GCR_CUSTOM_ADDR + 0x0060)
308#else
309#define REG_ELM_STAT (BASE_ADDR_MCUSYS_ELM_EMI + 0x0050)
310#define REG_INFRA_ELM_STAT (BASE_ADDR_MDINFRA_ELM + 0x0050)
311#endif //ifdef ELM_GCR
312#define REG_ELM_STAT_APB (BASE_ADDR_MCUSYS_ELM_EMI + 0x0050)
313
314#define ELM_GET_WC_CNT(rw, idx, p_cnt) \
315 do {\
316 } while(0)
317
318#define ELM_INFRA_GET_WC_CNT(rw, idx, p_cnt) \
319 do {\
320 } while(0)
321
322#endif //ifdef __ELM_MD95__
323
324/* ==================== */
325/* ELM CONTROL API */
326/* ==================== */
327
328// ELM init
329extern void ELM_INIT(void);
330extern void ELM_Config_DormantEnter(void);
331extern void ELM_Config_DormantLeave(void);
332extern kal_bool Set_EMI_ELM_ExceptionType(kal_uint8 exception_type);
333extern kal_bool Set_EMI_ELM_Threshold(kal_uint8 info, kal_uint32 threshold);
334
335#if 0
336/* under construction !*/
337/* under construction !*/
338/* under construction !*/
339/* under construction !*/
340#endif
341// ELM clear
342#define ELM_CLR() \
343 do {\
344 } while(0)
345
346// ELM Start
347#define ELM_START() \
348 do {\
349 } while(0)
350
351// ELM Pause
352#define ELM_PAUSE() \
353 do {\
354 } while(0)
355
356// ELM Counter Selection
357enum {
358 ELM_RD = 0,
359 ELM_WR = 1
360};
361
362enum {
363 ELM_TYPE_TRANS = 0,
364 ELM_TYPE_LATENCY = 1
365};
366
367
368#define ELM_GET_CNT(rw, type, idx, p_cnt) \
369 do {\
370 *p_cnt = DRV_Reg32(REG_ELM_STAT + (((rw ) + (type<< 1)) << 2));\
371 } while(0)
372
373
374#define ELM_INFRA_GET_CNT(rw, type, idx, p_cnt) \
375 do {\
376 *p_cnt = DRV_Reg32(REG_INFRA_ELM_STAT + (((rw ) + (type<< 1)) << 2));\
377 } while(0)
378
379#if defined(MT6297)
380#define ELM_INFRA_B_GET_CNT(rw, type, idx, p_cnt) \
381 do {\
382 *p_cnt = DRV_Reg32(REG_INFRA_B_ELM_STAT + (((rw ) + (type<< 1)) << 2));\
383 } while(0)
384#endif
385
386
387#define ELM_GET_CNT_APB(rw, type, idx, p_cnt) \
388 do {\
389 *p_cnt = DRV_Reg32(REG_ELM_STAT_APB+ (((rw ) + (type<< 1)) << 2));\
390 } while(0)
391
392
393typedef struct _ELM_LOG_T
394{
395 kal_uint32 w_trans;
396 kal_uint32 w_latency;
397 kal_uint32 r_trans;
398 kal_uint32 r_latency;
399} ELM_LOG_T;
400
401typedef struct _ELM_FULL_LOG_T
402{
403 kal_uint32 fma_stamp;
404 kal_uint32 w_trans;
405 kal_uint32 w_latency;
406 kal_uint32 w_wordcount;
407 kal_uint32 r_trans;
408 kal_uint32 r_latency;
409 kal_uint32 r_wordcount;
410 kal_uint32 r_lat_thr;// read latency criteria
411 kal_uint32 w_lat_thr;// write latency criteria
412} ELM_FULL_LOG_T;
413
414typedef struct _ELM_M4PORT_FULL_LOG_T
415{
416 kal_uint32 infra_w_trans;
417 kal_uint32 infra_w_latency;
418 kal_uint32 infra_w_wordcount;
419 kal_uint32 infra_r_trans;
420 kal_uint32 infra_r_latency;
421 kal_uint32 infra_r_wordcount;
422} ELM_M4PORT_FULL_LOG_T;
423
424
425// for spv compatibility
426#define ELM_GET_LOG(c, l) do { \
427 ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).w_trans));\
428 ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).w_latency));\
429 ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).r_trans));\
430 ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).r_latency));\
431 } while (0)
432
433#define ELM_GET_ALL_LOG(c, l) do { \
434 ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).w_trans));\
435 ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).w_latency));\
436 ELM_GET_WC_CNT(ELM_WR, (c), &((l).w_wordcount));\
437 ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).r_trans));\
438 ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).r_latency));\
439 ELM_GET_WC_CNT(ELM_RD, (c), &((l).r_wordcount));\
440 } while (0)
441
442#define ELM_GET_M4PORT_ALL_LOG(c, l) do { \
443 ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).infra_w_trans));\
444 ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).infra_w_latency));\
445 ELM_INFRA_GET_WC_CNT(ELM_WR, (c), &((l).infra_w_wordcount));\
446 ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).infra_r_trans));\
447 ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).infra_r_latency));\
448 ELM_INFRA_GET_WC_CNT(ELM_RD, (c), &((l).infra_r_wordcount));\
449 } while (0)
450
451#if defined(MT6297)
452#define ELM_GET_MDINFRA_B_ALL_LOG(c, l) do { \
453 ELM_INFRA_B_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).infra_w_trans));\
454 ELM_INFRA_B_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).infra_w_latency));\
455 ELM_INFRA_B_GET_WC_CNT(ELM_WR, (c), &((l).infra_w_wordcount));\
456 ELM_INFRA_B_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).infra_r_trans));\
457 ELM_INFRA_B_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).infra_r_latency));\
458 ELM_INFRA_B_GET_WC_CNT(ELM_RD, (c), &((l).infra_r_wordcount));\
459 } while (0)
460#endif
461
462void ELM_GET_FULL_LOG(ELM_FULL_LOG_T* data);
463
464// for profiling ELM log
465typedef enum
466{
467 //When ELM irq happend
468 ELM_NONE = 0, //show trace only
469 ELM_ASSERT, //trigger assert
470 ELM_ASSERT_AT_2nd, //show trace first, twice in 500us then assert
471} elm_exception_type;
472
473typedef struct _ELM_RUNTIME_PROFILE_LAT_T
474{
475 kal_uint32 cur_frc;
476 kal_uint32 int_status;
477 kal_uint32 r_trans;
478 kal_uint32 w_trans;
479 kal_uint32 r_alat;
480 kal_uint32 r_alat_maxost;
481 kal_uint32 w_alat;
482 kal_uint32 w_alat_maxost;
483 kal_uint32 r_l2_tot_lat;
484 kal_uint32 w_l2_tot_lat;
485 kal_uint32 ap_dvfs_tick;
486 kal_uint32 txzq_dvfs_tick;
487 kal_uint32 md_tick;
488#if defined(__MD97__) || defined(__MD97P__)
489 kal_uint32 enter_lisr_frc;
490 kal_uint32 ap_ddren_tick ;
491 kal_uint32 id0_subwindow_status;
492 kal_uint32 id1_subwindow_status;
493 kal_uint32 emi_blocking;
494#endif
495} ELM_RUNTIME_PROFILE_LAT_T;
496
497typedef struct _ELM_RUNTIME_PROFILE_WC_T
498{
499 kal_uint32 cur_frc;
500 kal_uint32 int_status;
501 kal_uint32 r_wc;
502 kal_uint32 w_wc;
503} ELM_RUNTIME_PROFILE_WC_T;
504
505void ELM_MCU_threshold_change(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us);
506void ELM_MCU_threshold_change_lightweight(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us);
507
508#if defined(__MD97__) || defined(__MD97P__)
509typedef struct _ELM_MAX_LOG_T
510{
511 kal_uint32 m3_max_r_word_cnt ;
512 kal_uint32 m3_max_w_word_cnt ;
513 kal_uint32 m4_max_r_word_cnt ;
514 kal_uint32 m4_max_w_word_cnt ;
515#if defined(MT6297)
516 kal_uint32 m4b_max_r_word_cnt ;
517 kal_uint32 m4b_max_w_word_cnt ;
518#endif
519} ELM_MAX_LOG_T;
520
521void EMI_ELM_GET_MAX_LOG(ELM_MAX_LOG_T * tt);
522void EMI_ELM_AMIF_SCENARIO_CHANGE_LOGGING(ELM_MAX_LOG_T t);
523
524#endif
525
526#endif /* !__ELM_H__ */