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192.168.1.100 / T800_MD / b0f5b85a5b9d69cbfa1dd990d559a4a9c7d8f2a6 / . / mcu / driver / devdrv / i2c / inc / drv_i2c.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * i2c.h
41 *
42 *
43 * Description:
44 * ------------
45 * I2C Driver
46 *
47 * Author:
48 * -------
49 * -------
50 *
51 *============================================================================
52 * HISTORY
53 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
54 *------------------------------------------------------------------------------
55 * removed!
56 * removed!
57 * removed!
58 *
59 * removed!
60 * removed!
61 * removed!
62 *
63 * removed!
64 * removed!
65 * removed!
66 * removed!
67 *
68 * removed!
69 * removed!
70 * removed!
71 *
72 * removed!
73 * removed!
74 * removed!
75 *
76 *
77 *------------------------------------------------------------------------------
78 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
79 *============================================================================
80 *****************************************************************************/
81#ifndef __I2C_H__
82#define __I2C_H__
83
84#include "drv_features_i2c.h"
85#include "dcl_i2c_owner.h"
86
87#include "drv_comm.h"
88
89#include "kal_general_types.h"
90#include "reg_base.h"
91
92#ifdef ATEST_DRV_ENABLE
93#define dhl_trace(...)
94#define DRVI2C_PRINTF(x...) \
95do{ \
96 dbg_print(x); \
97 dbg_flush(); \
98}while(0)
99#else /*ATEST_DRV_ENABLE*/
100#include "drv_i2c_trace.h"
101#endif
102
103#ifndef __DRV_DEBUG_I2C_REG_READ_WRITE__
104#define DRV_I2C_ClearBits16(addr, data) DRV_ClearBits(addr,data)
105#define DRV_I2C_SetBits16(addr, data) DRV_SetBits(addr,data)
106#define DRV_I2C_WriteReg16(addr, data) DRV_WriteReg(addr, data)
107#define DRV_I2C_ReadReg16(addr) DRV_Reg(addr)
108#define DRV_I2C_SetData16(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
109#else // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
110#define DRV_I2C_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
111#define DRV_I2C_SetBits16(addr) DRV_DBG_SetBits(addr)
112#define DRV_I2C_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
113#define DRV_I2C_ReadReg16(addr) DRV_DBG_Reg(addr)
114#define DRV_I2C_SetData16(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
115#endif // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
116
117#define SCCB_MAXIMUM_TRANSACTION_LENGTH 8 // SCCB backward compatible
118
119#if defined(MT6885)||defined(MT6873)||defined(MT6853)
120#define I2C_CLOCK_RATE 65000 //65MHz
121#else
122#define I2C_CLOCK_RATE 12000 //12MHz
123#endif
124#define DRV_I2C_FIFO_DEPTH 8
125
126typedef enum
127{
128 I2C_TRANSACTION_COMPLETE,
129 I2C_TRANSACTION_FAIL,
130 I2C_TRANSACTION_IS_BUSY,
131 I2C_TRANSACTION_ACKERR,
132 I2C_TRANSACTION_HS_NACKERR,
133 I2C_TRANSACTION_SUCCESS,
134 I2C_TRANSACTION_TIMEOUT
135}I2C_TRANSACTION_RESULT;
136
137
138typedef enum
139{
140 I2C_IDLE_STATE = 0,
141 I2C_READY_STATE,
142 I2C_BUSY_STATE
143}I2C_STATE;
144
145/* Transaction mode for new SCCB APIs */
146typedef enum
147{
148 I2C_TRANSACTION_FAST_MODE,
149 I2C_TRANSACTION_HIGH_SPEED_MODE
150}I2C_TRANSACTION_MODE;
151
152/* Transaction type for batch transaction */
153typedef enum
154{
155 I2C_TRANSACTION_WRITE,
156 I2C_TRANSACTION_READ,
157 I2C_TRANSACTION_CONT_WRITE,
158 I2C_TRANSACTION_CONT_READ,
159 I2C_TRANSACTION_WRITE_AND_READ
160}I2C_TRANSACTION_TYPE;
161
162typedef struct
163{
164 kal_uint8 *data;
165 kal_uint32 data_len;
166}i2c_single_write_struct, i2c_single_read_struct;
167/* For I2C_CMD_CONT_WRITE, I2C_CMD_CONT_READ command. */
168typedef struct
169{
170 kal_uint8 *data;
171 kal_uint32 data_len;
172 kal_uint32 transfer_num;
173}i2c_cont_write_struct, i2c_cont_read_struct;
174/* For I2C_CMD_WRITE_AND_READ command. */
175typedef struct
176{
177 kal_uint8 *indata;
178 kal_uint32 indata_len;
179 kal_uint8 *outdata;
180 kal_uint32 outdata_len;
181}i2c_write_and_read_struct;
182/* */
183typedef union
184{
185 i2c_single_write_struct single_write;
186 i2c_single_read_struct single_read;
187 i2c_cont_write_struct cont_write;
188 i2c_cont_write_struct cont_read;
189 i2c_write_and_read_struct write_and_read;
190}i2c_transaction_data_struct;
191/* For I2C_CMD_SINGLE_BATCH command. */
192typedef struct
193{
194 I2C_TRANSACTION_TYPE transaction_type;
195 i2c_transaction_data_struct transaction_data;
196}i2c_batch_data_struct;
197
198typedef enum
199{
200 // Module source clock is 15.36Mhz
201 I2C_100KB, //99.74KB
202 I2C_200KB, //196.9KB
203 I2C_300KB, //295.4KB
204 I2C_400KB, //384.0KB
205 /* HS Mode */
206 I2C_960KB, //960.0KB
207 I2C_1280KB, //1280.0KB
208 I2C_1536KB, //1536.0KB
209 I2C_1920KB, //1920.0KB
210 I2C_2560KB, //2560.0KB
211 I2C_3840KB //3840.0KB
212
213}I2C_SPEED_ENUM;
214
215typedef struct
216{
217 //kal_uint8 sccb_mode; // Transaction mode for existing SCCB APIs
218
219 kal_bool get_handle_wait; //When get handle wait until the I2C is avaliable
220
221 kal_uint8 slave_address; //the address of the slave device
222
223 kal_uint8 delay_len; //number of half pulse between transfers in a trasaction
224
225 I2C_TRANSACTION_MODE transaction_mode; //I2C_TRANSACTION_FAST_MODE or I2C_TRANSACTION_HIGH_SPEED_MODE
226
227 kal_uint16 Fast_Mode_Speed; //The speed of I2C fast mode(Kb)
228
229 kal_uint16 HS_Mode_Speed; //The speed of I2C high speed mode(Kb)
230}i2c_config_struct;
231
232typedef struct
233{
234 i2c_config_struct i2c_config;
235
236 kal_uint8 fs_sample_cnt_div; //these two parameters are used to specify I2C clock rate
237 kal_uint8 fs_step_cnt_div; //half pulse width=step_cnt_div*sample_cnt_div*(1/13Mhz)
238
239 kal_uint8 hs_sample_cnt_div; //these two parameters are used to specify I2C clock rate
240 kal_uint8 hs_step_cnt_div; //half pulse width=step_cnt_div*sample_cnt_div*(1/13Mhz)
241
242 I2C_TRANSACTION_RESULT transaction_result; /* The result of the end of transaction
243 (I2C_TRANSACTION_COMPLETE|I2C_TRANSACTION_FAIL) */
244
245}i2c_handle_struct;
246
247typedef struct
248{
249 volatile I2C_STATE state;
250 DCL_I2C_OWNER owner;
251
252 kal_uint8 number_of_read;
253 kal_uint8* read_buffer;
254
255}i2c_status_struct;
256
257
258
259#ifndef DRV_I2C_OFF
260#ifndef BASE_MADDR_MDINFRA_I2C
261#define BASE_MADDR_MDINFRA_I2C 0xA0400000
262#endif
263#define I2C_base BASE_MADDR_MDINFRA_I2C
264/* Register Definitions */
265#define REG_I2C_DATA_PORT (I2C_base + 0x00)
266#define REG_I2C_SLAVE_ADDR (I2C_base + 0x04)
267#define REG_I2C_INT_MASK (I2C_base + 0x08)
268#define REG_I2C_INT_STA (I2C_base + 0x0c)
269#define REG_I2C_CONTROL (I2C_base + 0x10)
270#define REG_I2C_TRANSFER_LEN (I2C_base + 0x14)
271#define REG_I2C_TRANSAC_LEN (I2C_base + 0x18)
272#define REG_I2C_DELAY_LEN (I2C_base + 0x1c)
273#define REG_I2C_TIMING (I2C_base + 0x20)
274#define REG_I2C_START (I2C_base + 0x24)
275#define REG_I2C_FIFO_STAT (I2C_base + 0x30)
276#define REG_I2C_FIFO_THRESH (I2C_base + 0x34)
277#define REG_I2C_FIFO_ADDR_CLR (I2C_base + 0x38)
278#define REG_I2C_IO_CONFIG (I2C_base + 0x40)
279#define REG_I2C_MULTI_MASTER (I2C_base + 0x44)
280#define REG_I2C_HS_MODE (I2C_base + 0x48)
281#define REG_I2C_SOFTRESET (I2C_base + 0x50)
282#define REG_I2C_TRANSFER_LEN_AUX (I2C_base + 0x6C) ///new from MT6256E2
283#define REG_I2C_HW_Version (I2C_base + 0x78)
284#define REG_I2C_DBG_STA (I2C_base + 0x64) //only for debug
285#define REG_I2C_TIMEOUT_TIMING (I2C_base + 0x74) //timeout timing reg
286#define REG_SW_I2C_EN (I2C_base + 0x80)
287#define REG_SW_I2C_SCL_WR (I2C_base + 0x84)
288#define REG_SW_I2C_SDA_WR (I2C_base + 0x88)
289#define REG_SW_I2C_RD (I2C_base + 0x8C)
290
291#endif // DRV_I2C_OFF
292
293/* Register masks */
294#define I2C_1_BIT_MASK 0x01
295#define I2C_3_BIT_MASK 0x07
296#define I2C_4_BIT_MASK 0x0f
297#define I2C_6_BIT_MASK 0x3f
298#define I2C_8_BIT_MASK 0xff
299#define I2C_16_BIT_MASK 0xffff
300
301#define I2C_RX_FIFO_THRESH_MASK 0x0007
302#define I2C_RX_FIFO_THRESH_SHIFT 0
303#define I2C_TX_FIFO_THRESH_MASK 0x0700
304#define I2C_TX_FIFO_THRESH_SHIFT 8
305
306#define I2C_AUX_LEN_MASK 0x1f00
307#define I2C_AUX_LEN_SHIFT 8
308
309#define I2C_SAMPLE_CNT_DIV_MASK 0x0700
310#define I2C_SAMPLE_CNT_DIV_SHIFT 8
311#define I2C_DATA_READ_TIME_MASK 0x7000
312#define I2C_DATA_READ_TIME_SHIFT 12
313
314#define I2C_MASTER_READ 0x01
315#define I2C_MASTER_WRITE 0x00
316
317//#define I2C_CTL_MODE_BIT 0x01
318#define I2C_CTL_RS_STOP_BIT 0x02
319#define I2C_CTL_DMA_EN_BIT 0x04
320#define I2C_CTL_CLK_EXT_EN_BIT 0x08
321#define I2C_CTL_DIR_CHANGE_BIT 0x10
322#define I2C_CTL_ACK_ERR_DET_BIT 0x20
323#define I2C_CTL_TRANSFER_LEN_CHG_BIT 0x40
324
325#define I2C_DATA_READ_ADJ_BIT 0x8000
326
327#define I2C_SCL_MODE_BIT 0x01
328#define I2C_SDA_MODE_BIT 0x02
329#define I2C_BUS_DETECT_EN_BIT 0x04
330
331#define I2C_ARBITRATION_BIT 0x01
332#define I2C_CLOCK_SYNC_BIT 0x02
333#define I2C_BUS_BUSY_DET_BIT 0x04
334
335#define I2C_HS_EN_BIT 0x01
336#define I2C_HS_NACK_ERR_DET_EN_BIT 0x02
337#define I2C_HS_MASTER_CODE_MASK 0x0070
338#define I2C_HS_MASTER_CODE_SHIFT 4
339#define I2C_HS_STEP_CNT_DIV_MASK 0x0700
340#define I2C_HS_STEP_CNT_DIV_SHIFT 8
341#define I2C_HS_SAMPLE_CNT_DIV_MASK 0x7000
342#define I2C_HS_SAMPLE_CNT_DIV_SHIFT 12
343
344/* I2C Status */
345#define I2C_FIFO_FULL_STATUS 0x01
346#define I2C_FIFO_EMPTY_STATUS 0x02
347
348/* Register Settings */
349#define SET_I2C_SLAVE_ADDRESS(n,rw) do{DRV_I2C_SetData16(REG_I2C_SLAVE_ADDR, I2C_8_BIT_MASK, (((n>>1)<<1) + rw));} while(0)
350
351#define DISABLE_I2C_INT do{DRV_I2C_WriteReg16(REG_I2C_INT_MASK, 0);} while(0)
352#define ENABLE_I2C_INT do{DRV_I2C_WriteReg16(REG_I2C_INT_MASK,I2C_1_BIT_MASK);} while(0)
353
354#define CLEAR_I2C_STA do{DRV_I2C_WriteReg16(REG_I2C_INT_STA, I2C_4_BIT_MASK);} while(0)
355
356//#define SET_I2C_FAST_SPEED_MODE REG_I2C_CONTROL &= ~I2C_CTL_MODE_BIT;
357//#define SET_I2C_HIGH_SPEED_MODE REG_I2C_CONTROL |= I2C_CTL_MODE_BIT;
358
359#define SET_I2C_ST_BETWEEN_TRANSFER do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_RS_STOP_BIT);} while(0)
360#define SET_I2C_RS_BETWEEN_TRANSFER do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_RS_STOP_BIT);} while(0)
361#define ENABLE_I2C_DMA_TRANSFER do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_DMA_EN_BIT);} while(0)
362#define ENABLE_I2C_CLOCK_EXTENSION do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_CLK_EXT_EN_BIT);} while(0)
363#define ENABLE_I2C_DIR_CHANGE do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_DIR_CHANGE_BIT);} while(0)
364#define ENABLE_I2C_ACK_ERR_DET do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_ACK_ERR_DET_BIT);} while(0)
365#define ENABLE_I2C_TRANSFER_LEN_CHG do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_TRANSFER_LEN_CHG_BIT);} while(0)
366#define ENABLE_I2C_BUS_BUSY_RESET do{DRV_I2C_SetBits16(REG_I2C_CONTROL, 0x80);} while(0)
367#define ENABLE_I2C_TIMEOUT do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_TIMEOUT);} while(0)
368
369#define DISABLE_I2C_DMA_TRANSFER do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_DMA_EN_BIT);} while(0)
370#define DISABLE_I2C_CLOCK_EXTENSION do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_CLK_EXT_EN_BIT);} while(0)
371#define DISABLE_I2C_DIR_CHANGE do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_DIR_CHANGE_BIT);} while(0)
372#define DISABLE_I2C_ACK_ERR_DET do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_ACK_ERR_DET_BIT);} while(0)
373#define DISABLE_I2C_TRANSFER_LEN_CHG do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_TRANSFER_LEN_CHG_BIT);} while(0)
374#define DISABLE_I2C_BUS_BUSY_RESET do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, 0x80);} while(0)
375#define DISABLE_I2C_TIMEOUT do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_TIMEOUT);} while(0)
376
377#ifdef DRV_I2C_MAX_65535_TRANSFER_LENGTH
378#define SET_I2C_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_16_BIT_MASK, (n));} while(0)
379#define SET_I2C_AUX_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN_AUX, I2C_16_BIT_MASK, (n));} while(0)
380#else
381#define SET_I2C_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_8_BIT_MASK, (n));} while(0)
382#define SET_I2C_AUX_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_AUX_LEN_MASK, ((n)<<I2C_AUX_LEN_SHIFT));} while(0)
383#endif
384
385#define SET_I2C_TRANSACTION_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSAC_LEN, I2C_8_BIT_MASK, (n));} while(0)
386#define SET_I2C_DELAY_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_DELAY_LEN, I2C_8_BIT_MASK, (n));} while(0)
387
388#define SET_I2C_STEP_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_6_BIT_MASK, (n));} while(0)
389#define SET_I2C_SAMPLE_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_SAMPLE_CNT_DIV_MASK, ((n)<<I2C_SAMPLE_CNT_DIV_SHIFT));} while(0)
390#define SET_I2C_DATA_READ_TIME(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_DATA_READ_TIME_MASK, ((n)<<I2C_DATA_READ_TIME_SHIFT));} while(0)
391#define ENABLE_I2C_DATA_READ_ADJ do{DRV_I2C_SetBits16(REG_I2C_TIMING, I2C_DATA_READ_ADJ_BIT);} while(0)
392#define DISABLE_I2C_DATA_READ_ADJ do{DRV_I2C_ClearBits16(REG_I2C_TIMING, I2C_DATA_READ_ADJ_BIT);} while(0)
393
394#define START_I2C_TRANSACTION do{DRV_I2C_WriteReg16(REG_I2C_START, 0x01);} while(0)
395
396// #define I2C_FIFO_FULL ((REG_I2C_FIFO_STAT>>1)&0x01)
397// #define I2C_FIFO_EMPTY (REG_I2C_FIFO_STAT & 0x01)
398
399#define SET_I2C_RX_FIFO_THRESH(n) do{DRV_I2C_SetData16(REG_I2C_FIFO_THRESH, I2C_RX_FIFO_THRESH_MASK, ((n)<< I2C_RX_FIFO_THRESH_SHIFT));} while(0)
400#define SET_I2C_TX_FIFO_THRESH(n) do{DRV_I2C_SetData16(REG_I2C_FIFO_THRESH, I2C_TX_FIFO_THRESH_MASK, ((n)<< I2C_TX_FIFO_THRESH_SHIFT));} while(0)
401
402#define CLEAR_I2C_FIFO do{DRV_I2C_WriteReg16(REG_I2C_FIFO_ADDR_CLR, 0x01);} while(0)
403
404#define SET_I2C_SCL_NORMAL_MODE do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_SCL_MODE_BIT);} while(0)
405#define SET_I2C_SCL_WIRED_AND_MODE do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_SCL_MODE_BIT);} while(0)
406#define SET_I2C_SDA_NORMAL_MODE do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_SDA_MODE_BIT);} while(0)
407#define SET_I2C_SDA_WIRED_AND_MODE do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_SDA_MODE_BIT);} while(0)
408#define ENABLE_I2C_BUS_DETECT do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_BUS_DETECT_EN_BIT);} while(0)
409#define DISABLE_I2C_BUS_DETECT do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_BUS_DETECT_EN_BIT);} while(0)
410
411#define ENABLE_I2C_CLOCK_SYNC do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_ARBITRATION_BIT);} while(0)
412#define ENABLE_DATA_ARBITION do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_CLOCK_SYNC_BIT);} while(0)
413#define ENABLE_I2C_BUS_BUSY_DET do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_BUS_BUSY_DET_BIT);} while(0)
414#define DISABLE_I2C_CLOCK_SYNC do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_ARBITRATION_BIT);} while(0)
415#define DISABLE_DATA_ARBITION do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_CLOCK_SYNC_BIT);} while(0)
416#define DISABLE_I2C_BUS_BUSY_DET do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_BUS_BUSY_DET_BIT);} while(0)
417
418#define SET_I2C_HIGH_SPEED_MODE_800KB do{DRV_I2C_WriteReg16(REG_I2C_HS_MODE, 0x0703);} while(0)
419#define SET_I2C_HIGH_SPEED_MODE_1000KB do{DRV_I2C_WriteReg16(REG_I2C_HS_MODE, 0x0503);} while(0)
420
421#define SET_I2C_FAST_MODE do{DRV_I2C_ClearBits16(REG_I2C_HS_MODE, I2C_HS_EN_BIT);} while(0)
422#define SET_I2C_HS_MODE do{DRV_I2C_SetBits16(REG_I2C_HS_MODE, I2C_HS_EN_BIT);} while(0)
423#define ENABLE_I2C_NAKERR_DET do{DRV_I2C_SetBits16(REG_I2C_HS_MODE, I2C_HS_NACK_ERR_DET_EN_BIT);} while(0)
424#define DISABLE_I2C_NAKERR_DET do{DRV_I2C_ClearBits16(REG_I2C_HS_MODE, I2C_HS_NACK_ERR_DET_EN_BIT);} while(0)
425#define SET_I2C_HS_MASTER_CODE(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_MASTER_CODE_MASK, ((n)<<I2C_HS_MASTER_CODE_SHIFT));} while(0)
426
427#define SET_I2C_HS_STEP_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_STEP_CNT_DIV_MASK, ((n)<<I2C_HS_STEP_CNT_DIV_SHIFT));} while(0)
428#define SET_I2C_HS_SAMPLE_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_SAMPLE_CNT_DIV_MASK, ((n)<<I2C_HS_SAMPLE_CNT_DIV_SHIFT));} while(0)
429
430#define RESET_I2C do{DRV_I2C_WriteReg16(REG_I2C_SOFTRESET, 0x01);} while(0)
431#define SET_I2C_SW_MODE do{DRV_I2C_WriteReg16(REG_SW_I2C_EN, 0x1);}while(0)
432#define SET_I2C_HW_MODE do{DRV_I2C_WriteReg16(REG_SW_I2C_EN, 0x0);}while(0)
433
434
435/****** SW definitions******/
436#define I2C_READ_BIT 0x01
437#define I2C_WRITE_BIT 0x00
438
439#define I2C_TRANSAC_COMPLETE 0x01
440#define I2C_TRANSAC_ACK_ERR 0x02
441#define I2C_HS_NACK_ERR 0x04
442#define I2C_TIMEOUT 0x10
443
444//extern kal_bool dcl_i2c_init_done_flag;
445//extern i2c_handle_struct i2c_handle[DCL_I2C_NUM_OF_OWNER];
446
447void dcl_i2c_init(void);
448void dcl_i2c_deinit(void);
449extern void dcl_i2c_hw_cfg (DCL_I2C_OWNER owner, I2C_TRANSACTION_TYPE type, kal_uint8* write_buffer, kal_uint32 write_len, kal_uint8* read_buffer, kal_uint32 read_len, kal_uint32 transfer_num);
450void dcl_i2c_set_transaction_speed(DCL_I2C_OWNER owner,I2C_TRANSACTION_MODE mode,kal_uint16* Fast_Mode_Speed,kal_uint16* HS_Mode_Speed);
451extern kal_uint32 dcl_i2c_wait_transaction_complete_and_lock(DCL_I2C_OWNER owner);
452void dcl_i2c_wait_transaction_complete(kal_uint32 savedMask);
453
454#endif // #ifndef __I2C_H__
455