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192.168.1.100 / T800_MD / b0f5b85a5b9d69cbfa1dd990d559a4a9c7d8f2a6 / . / mcu / driver / devdrv / iomux / inc / drv_iomux.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2013
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35/*****************************************************************************
36 *
37 * Filename:
38 * ---------
39 * drv_iomux.h
40 *
41 * Project:
42 * --------
43 * drv_iomux
44 *
45 * Description:
46 * ------------
47 * This file is intends for iomux driver.
48 *
49 * Author:
50 * -------
51 * -------
52 *
53 *===========================================================
54 ******************************************************************************/
55
56
57#ifndef IOMUX_HW_H
58#define IOMUX_HW_H
59
60#include "drv_comm.h"
61#include "kal_general_types.h"
62#include "kal_debug.h"
63
64#ifndef BASE_MADDR_IOMUX0
65#define BASE_MADDR_IOMUX0 (0xC3710000)
66#endif
67#ifndef BASE_MADDR_IOMUX1
68#define BASE_MADDR_IOMUX1 (0xC3720000)
69#endif
70#ifndef BASE_MADDR_IOMUX2
71#define BASE_MADDR_IOMUX2 (0xC3730000)
72#endif
73
74#define IOMUX0_CODA_VERSION (BASE_MADDR_IOMUX0+0x0) /* Read only */
75#define IOMUX0_TOP_DUMMY (BASE_MADDR_IOMUX0+0x04)
76#define IOMUX0_TOP_STATUS (BASE_MADDR_IOMUX0+0x08)
77#define IOMUX1_CODA_VERSION (BASE_MADDR_IOMUX1+0x0) /* Read only */
78#define IOMUX1_TOP_DUMMY (BASE_MADDR_IOMUX1+0x04)
79#define IOMUX1_TOP_STATUS (BASE_MADDR_IOMUX1+0x08)
80#define IOMUX2_CODA_VERSION (BASE_MADDR_IOMUX2+0x0) /* Read only */
81#define IOMUX2_TOP_DUMMY (BASE_MADDR_IOMUX2+0x04)
82#define IOMUX2_TOP_STATUS (BASE_MADDR_IOMUX2+0x08)
83
84#define IOMUX0_MODE_SEL_1 (BASE_MADDR_IOMUX0+0x100)
85#define IOMUX0_MODE_SEL_2 (BASE_MADDR_IOMUX0+0x104)
86#define IOMUX0_MODE_SEL_3 (BASE_MADDR_IOMUX0+0x108)
87#define IOMUX1_MODE_SEL_0 (BASE_MADDR_IOMUX1+0x100)
88#define IOMUX1_MODE_SEL_1 (BASE_MADDR_IOMUX1+0x104)
89#define IOMUX2_MODE_SEL_0 (BASE_MADDR_IOMUX2+0x100)
90#define IOMUX2_MODE_SEL_1 (BASE_MADDR_IOMUX2+0x104)
91#define IOMUX2_MODE_SEL_2 (BASE_MADDR_IOMUX2+0x108)
92#define IOMUX2_MODE_SEL_3 (BASE_MADDR_IOMUX2+0x10C)
93#define IOMUX2_MODE_SEL_4 (BASE_MADDR_IOMUX2+0x110)
94#define IOMUX2_MODE_SEL_5 (BASE_MADDR_IOMUX2+0x114)
95
96#define IOMUX_CFG_GLOBAL (BASE_MADDR_IOMUX0+0x110)
97#define IOMUX_CFG_MDUART (BASE_MADDR_IOMUX0+0x120)
98#define IOMUX_CFG_APUART (BASE_MADDR_IOMUX0+0x124)
99#define IOMUX_CFG_SUART0 (BASE_MADDR_IOMUX0+0x128)
100#define IOMUX_CFG_SUART1 (BASE_MADDR_IOMUX0+0x12C)
101#define IOMUX_CFG_SDIO (BASE_MADDR_IOMUX0+0x130)
102#define IOMUX_CFG_MSDC0P_0 (BASE_MADDR_IOMUX0+0x140)
103#define IOMUX_CFG_MSDC0P_1 (BASE_MADDR_IOMUX0+0x144)
104#define IOMUX_CFG_MSDC0P_2 (BASE_MADDR_IOMUX0+0x148)
105#define IOMUX_CFG_MSDC1P (BASE_MADDR_IOMUX0+0x150)
106#define IOMUX_CFG_PMIC_BSI_0 (BASE_MADDR_IOMUX0+0x160)
107#define IOMUX_CFG_PMIC_BSI_1 (BASE_MADDR_IOMUX0+0x164)
108#define IOMUX_CFG_PMIC_BSI_2 (BASE_MADDR_IOMUX0+0x168)
109#define IOMUX_CFG_RFIC2_BSI_0 (BASE_MADDR_IOMUX0+0x170)
110#define IOMUX_CFG_RFIC2_BSI_1 (BASE_MADDR_IOMUX0+0x174)
111#define IOMUX_CFG_CV (BASE_MADDR_IOMUX0+0x180)
112#define IOMUX_CFG_SB (BASE_MADDR_IOMUX0+0x184)
113#define IOMUX_CFG_I2C (BASE_MADDR_IOMUX0+0x190)
114#define IOMUX_CFG_SDIO_INT (BASE_MADDR_IOMUX0+0x1A0)
115#define IOMUX_CFG_MSDC1P_CLK (BASE_MADDR_IOMUX0+0x1B0)
116#define IOMUX_CFG_MSDC1P_CMD (BASE_MADDR_IOMUX0+0x1B4)
117#define IOMUX_CFG_MSDC1P_DATA0 (BASE_MADDR_IOMUX0+0x1B8)
118#define IOMUX_CFG_MSDC1P_DATA1 (BASE_MADDR_IOMUX0+0x1BC)
119#define IOMUX_CFG_MSDC1P_DATA2 (BASE_MADDR_IOMUX0+0x1C0)
120#define IOMUX_CFG_MSDC1P_DATA3 (BASE_MADDR_IOMUX0+0x1C4)
121#define IOMUX_CFG_MSDC1P_RCLK (BASE_MADDR_IOMUX0+0x1C8)
122#define IOMUX0_CFG_BIAS_TUNE (BASE_MADDR_IOMUX0+0x1D0)
123
124#define IOMUX_CFG_RFIC1_BSI (BASE_MADDR_IOMUX1+0x110)
125#define IOMUX_CFG_MISC_BSI_0 (BASE_MADDR_IOMUX1+0x120)
126#define IOMUX_CFG_MISC_BSI_1 (BASE_MADDR_IOMUX1+0x124)
127#define IOMUX_CFG_GPIO_0 (BASE_MADDR_IOMUX1+0x130)
128#define IOMUX_CFG_GPIO_1 (BASE_MADDR_IOMUX1+0x134)
129#define IOMUX_CFG_GPIO_2 (BASE_MADDR_IOMUX1+0x138)
130#define IOMUX_CFG_GPIO_3 (BASE_MADDR_IOMUX1+0x13C)
131#define IOMUX1_CFG_BIAS_TUNE (BASE_MADDR_IOMUX1+0x140)
132
133#define IOMUX_CFG_JTAG (BASE_MADDR_IOMUX2+0x120)
134#define IOMUX_CFG_SPI_0 (BASE_MADDR_IOMUX2+0x130)
135#define IOMUX_CFG_SPI_1 (BASE_MADDR_IOMUX2+0x134)
136#define IOMUX_CFG_NFI_0 (BASE_MADDR_IOMUX2+0x140)
137#define IOMUX_CFG_NFI_1 (BASE_MADDR_IOMUX2+0x144)
138#define IOMUX_CFG_NFI_2 (BASE_MADDR_IOMUX2+0x148)
139#define IOMUX_CFG_NFI_3 (BASE_MADDR_IOMUX2+0x14C)
140#define IOMUX_CFG_NFI_4 (BASE_MADDR_IOMUX2+0x150)
141#define IOMUX_CFG_BPI_0 (BASE_MADDR_IOMUX2+0x160)
142#define IOMUX_CFG_BPI_1 (BASE_MADDR_IOMUX2+0x164)
143#define IOMUX_CFG_BPI_2 (BASE_MADDR_IOMUX2+0x168)
144#define IOMUX_CFG_BPI_3 (BASE_MADDR_IOMUX2+0x16C)
145#define IOMUX_CFG_BPI_4 (BASE_MADDR_IOMUX2+0x170)
146#define IOMUX_CFG_BPI_5 (BASE_MADDR_IOMUX2+0x174)
147#define IOMUX_CFG_BPI_6 (BASE_MADDR_IOMUX2+0x178)
148#define IOMUX_CFG_BPI_7 (BASE_MADDR_IOMUX2+0x17C)
149#define IOMUX_CFG_BPI_8 (BASE_MADDR_IOMUX2+0x180)
150#define IOMUX_CFG_BPI_9 (BASE_MADDR_IOMUX2+0x184)
151#define IOMUX_CFG_BPI_10 (BASE_MADDR_IOMUX2+0x188)
152#define IOMUX_CFG_BPI_11 (BASE_MADDR_IOMUX2+0x18C)
153#define IOMUX_CFG_USIM1 (BASE_MADDR_IOMUX2+0x190)
154#define IOMUX_CFG_USIM2 (BASE_MADDR_IOMUX2+0x194)
155#define IOMUX2_CFG_BIAS_TUNE (BASE_MADDR_IOMUX2+0x1B0)
156
157
158
159/*IOMUX0_MODE_SEL_1*/
160#define S_SDIO0 (0x00)
161#define S_MSDC0P_0 (0x03)
162#define S_MSDC0P_1 (0x06)
163#define S_MSDC0P_2 (0x09)
164#define S_MSDC1P (0x0C)
165#define S_MDUART (0x10)
166#define S_APUART (0x13)
167#define S_SUART0 (0x16)
168#define S_SUART1 (0x19)
169#define S_SUART2 (0x1C)
170
171/*IOMUX0_MODE_SEL_2 */
172#define S_PMIC_BSI_0 (0x00)
173#define S_PMIC_BSI_1 (0x03)
174#define S_PMIC_BSI_2 (0x06)
175#define S_I2C (0x09)
176#define S_RFIC2_BSI_0 (0x0C)
177#define S_RFIC2_BSI_1 (0x10)
178#define S_SDIO_INT (0x13)
179#define S_GLOBAL_0 (0x16)
180#define S_GLOBAL_1 (0x19)
181
182/*IOMUX0_MODE_SEL_3*/
183#define S_C2K_UT0 (0x00)
184#define S_SRCLK_IN (0x03)
185#define S_IDC_RXD (0x06)
186#define S_EXT_FRAME_SYNC (0x09)
187#define S_UIM0_HOTPLUG (0x0C)
188#define S_UIM1_HOTPLUG (0x10)
189#define S_MD2_EINT0 (0x13)
190#define S_MD2_EINT1 (0x16)
191#define S_MD2_EINT2 (0x19)
192
193/*IOMUX1_MODE_SEL_0 */
194#define S_MISC_BSI_0 (0x00)
195#define S_MISC_BSI_1 (0x03)
196/*IOMUX1_MODE_SEL_1 */
197#define S_GPIO_0 (0x00)
198#define S_GPIO_1 (0x03)
199#define S_GPIO_2 (0x06)
200#define S_GPIO_3 (0x09)
201
202/*IOMUX2_MODE_SEL_0 */
203#define S_BPI_0 (0x00)
204#define S_BPI_1 (0x03)
205#define S_BPI_2 (0x06)
206#define S_BPI_3 (0x09)
207#define S_BPI_4 (0x0C)
208#define S_BPI_5 (0x10)
209#define S_BPI_6 (0x13)
210#define S_BPI_7 (0x16)
211#define S_BPI_8 (0x19)
212#define S_BPI_9 (0x1C)
213/*IOMUX2_MODE_SEL_1 */
214#define S_BPI_10 (0x00)
215#define S_BPI_11 (0x03)
216#define S_BPI_12 (0x06)
217
218/*IOMUX2_MODE_SEL_2 */
219#define S_NFI_0 (0x00)
220#define S_NFI_1 (0x03)
221#define S_NFI_2 (0x06)
222#define S_NFI_3 (0x09)
223#define S_NFI_4 (0x0C)
224#define S_NFI_5 (0x10)
225#define S_NFI_6 (0x13)
226#define S_NFI_7 (0x16)
227#define S_NFI_8 (0x19)
228#define S_NFI_9 (0x1C)
229/*IOMUX2_MODE_SEL_3 */
230#define S_NFI_10 (0x00)
231#define S_NFI_11 (0x03)
232#define S_NFI_12 (0x06)
233#define S_NFI_13 (0x09)
234#define S_NFI_14 (0x0C)
235#define S_NFI_15 (0x10)
236#define S_NFI_16 (0x13)
237#define S_NFI_17 (0x16)
238#define S_NFI_18 (0x19)
239#define S_NFI_19 (0x1C)
240/*IOMUX2_MODE_SEL_4 */
241#define S_NFI_20 (0x00)
242#define S_NFI_21 (0x03)
243#define S_NFI_22 (0x06)
244#define S_NFI_23 (0x09)
245
246/*IOMUX2_MODE_SEL_5 */
247#define S_USIM_1 (0x00)
248#define S_USIM_2 (0x03)
249#define S_JTAG (0x06)
250#define S_SPI_0 (0x09)
251#define S_SPI_1 (0x0C)
252
253/*IOMUX2_BIAS_TUNE */
254#define SEL_BPI_BIAS_TUNE (0x00)
255#define SEL_SPI_BIAS_TUNE (0x03)
256#define SEL_SIM0P_BIAS_TUNE (0x06)
257#define SEL_SIM1P_BIAS_TUNE (0x09)
258
259
260#define IOMUX_OK (0)
261#define IOMUX_FAIL (-1)
262#define IOMUX_MEM_SIZE 4096
263
264#define EN_IOMUX_PRINTF 1
265extern void dbg_print(char *fmt,...);
266
267#if EN_IOMUX_PRINTF
268#define IOMUX_PRINT(fmt, var ...) do {dbg_print(fmt"\n\r", ##var);} while (0)
269#define IOMUX_PRINTN(fmt, var ...) do {dbg_print(fmt, ##var);} while (0)
270#define IOMUX_ERR(fmt, var ...) do {IOMUX_PRINT("ERROR [%s:%d]"fmt, __FUNCTION__, __LINE__, ##var);} while (0)
271#define IOMUX_WARN(fmt, var ...) do {IOMUX_PRINT("WARNING [%s:%d]"fmt, __FUNCTION__, __LINE__, ##var);} while (0)
272#else
273#define IOMUX_PRINT(fmt, var ...)
274#define IOMUX_PRINTN(fmt, var ...)
275#define IOMUX_ERR(fmt, var ...)
276#define IOMUX_WARN(fmt, var ...)
277#endif
278
279
280
281typedef enum{
282/*IOMUX0_MODE_SEL_1*/
283SEL_SDIO0 = 0,
284SEL_MSDC0P_0,
285SEL_MSDC0P_1,
286SEL_MSDC0P_2,
287SEL_MSDC1P ,
288SEL_MDUART,
289SEL_SUART0 ,
290SEL_SUART1,
291SEL_SUART2,
292
293/*IOMUX0_MODE_SEL_2 */
294SEL_PMIC_BSI_0,
295SEL_PMIC_BSI_1,
296SEL_PMIC_BSI_2,
297SEL_I2C,
298SEL_RFIC2_BSI_0,
299SEL_RFIC2_BSI_1,
300SEL_SDIO_INT,
301SEL_GLOBAL_0,
302SEL_GLOBAL_1,
303
304/*IOMUX0_MODE_SEL_3*/
305SEL_C2K_UT0,
306SEL_SRCLK_IN,
307SEL_IDC_RXD ,
308SEL_EXT_FRAME_SYNC,
309SEL_UIM0_HOTPLUG,
310SEL_UIM1_HOTPLUG,
311SEL_MD2_EINT0,
312SEL_MD2_EINT1,
313SEL_MD2_EINT2,
314
315/*IOMUX1_MODE_SEL_0 */
316SEL_MISC_BSI_0,
317SEL_MISC_BSI_1,
318/*IOMUX1_MODE_SEL_1 */
319SEL_GPIO_0,
320SEL_GPIO_1,
321SEL_GPIO_2,
322SEL_GPIO_3,
323
324/*IOMUX2_MODE_SEL_0 */
325SEL_BPI_0,
326SEL_BPI_1,
327SEL_BPI_2,
328SEL_BPI_3,
329SEL_BPI_4,
330SEL_BPI_5,
331SEL_BPI_6,
332SEL_BPI_7,
333SEL_BPI_8,
334SEL_BPI_9,
335/*IOMUX2_MODE_SEL_1 */
336SEL_BPI_10,
337SEL_BPI_11,
338SEL_BPI_12,
339
340/*IOMUX2_MODE_SEL_2 */
341SEL_NFI_0,
342SEL_NFI_1,
343SEL_NFI_2,
344SEL_NFI_3,
345SEL_NFI_4,
346SEL_NFI_5,
347SEL_NFI_6,
348SEL_NFI_7,
349SEL_NFI_8,
350SEL_NFI_9,
351/*IOMUX2_MODE_SEL_3 */
352SEL_NFI_10,
353SEL_NFI_11,
354SEL_NFI_12,
355SEL_NFI_13,
356SEL_NFI_14,
357SEL_NFI_15,
358SEL_NFI_16,
359SEL_NFI_17,
360SEL_NFI_18,
361SEL_NFI_19,
362/*IOMUX2_MODE_SEL_4 */
363SEL_NFI_20,
364SEL_NFI_21,
365SEL_NFI_22,
366SEL_NFI_23,
367
368/*IOMUX2_MODE_SEL_5 */
369SEL_USIM_1,
370SEL_USIM_2,
371SEL_JTAG,
372SEL_SPI_0,
373SEL_SPI_1,
374sel_count
375}mod_sel_t;
376
377
378typedef enum{
379CFG_GLOBAL = 0,
380CFG_MDUART ,
381CFG_APUART,
382CFG_SUART0 ,
383CFG_SUART1 ,
384CFG_SDIO ,
385CFG_MSDC0P_0,
386CFG_MSDC0P_1 ,
387CFG_MSDC0P_2 ,
388CFG_MSDC1P ,
389CFG_PMIC_BSI_0 ,
390CFG_PMIC_BSI_1 ,
391CFG_PMIC_BSI_2 ,
392CFG_RFIC2_BSI_0 ,
393CFG_RFIC2_BSI_1 ,
394CFG_CV ,
395CFG_SB ,
396CFG_I2C ,
397CFG_SDIO_INT ,
398CFG_MSDC1P_CLK,
399CFG_MSDC1P_CMD,
400CFG_MSDC1P_DATA0,
401CFG_MSDC1P_DATA1,
402CFG_MSDC1P_DATA2,
403CFG_MSDC1P_DATA3,
404CFG_MSDC1P_RCLK,
405CFG_BIAS_TUNE_0,
406
407CFG_RFIC1_BSI,
408CFG_MISC_BSI_0,
409CFG_MISC_BSI_1,
410CFG_GPIO_0,
411CFG_GPIO_1,
412CFG_GPIO_2,
413CFG_GPIO_3,
414CFG_BIAS_TUNE_1,
415
416CFG_JTAG,
417CFG_SPI_0,
418CFG_SPI_1,
419CFG_NFI_0,
420CFG_NFI_1,
421CFG_NFI_2,
422CFG_NFI_3,
423CFG_NFI_4,
424CFG_BPI_0,
425CFG_BPI_1,
426CFG_BPI_2,
427CFG_BPI_3,
428CFG_BPI_4,
429CFG_BPI_5,
430CFG_BPI_6,
431CFG_BPI_7,
432CFG_BPI_8,
433CFG_BPI_9,
434CFG_BPI_10,
435CFG_BPI_11,
436CFG_USIM1,
437CFG_USIM2,
438CFG_BIAS_TUNE_2,
439cfg_count,
440}config_sel_t;
441
442
443typedef enum{
444 normal = 0,
445 msdc0p,
446 msdc1,
447 sdio,
448 ddrphy,
449 dmcmdphy
450}module_type_t;
451
452
453typedef struct{
454 config_sel_t cfg_sel;
455 module_type_t type;
456 kal_uint32 rdsel;
457 kal_uint32 tdsel;
458 kal_uint32 drive;
459 kal_uint8 r0;
460 kal_uint8 r1;
461 kal_uint8 smt;
462 kal_uint8 sr;
463
464
465}module_conf_t;
466
467
468/*
469 * @brief Set the module IOPAD group driving.
470 * @param
471 * cfg_sel: configure IOPAD group selection, valied value please see enum config_sel_t;
472 * drv_sel: driving value table list. SDIO: 000'b~111'b; Others: 00'b~11'b
473 */
474extern void IOMUX_set_module_driving(config_sel_t cfg_sel, kal_uint32 drv_sel);
475/*
476 * @brief Get the module IOPAD group driving.
477 * @param
478 * cfg_sel: configure IOPAD group selection, valied value please see enum config_sel_t;
479 * @return
480 return the function mode, valid value please check driving table;
481 */
482extern kal_uint32 IOMUX_get_module_driving(config_sel_t cfg_sel );
483/*
484 * @brief Check the function num is valid or not for IOPAD group .
485 * @param
486 * funciton_num: function mode selection valid value 0~5;
487 * module_num: IOPAD group selection, valied value please see enum module_sel;
488 * sip_flag: choose the chip is SIP or Non-SIP.
489 * 0: non-sip ; 1: sip
490 * @return
491 * 0: is valid setting;
492 * 1: invaild funtion setting;
493 */
494
495extern kal_uint32 IOMUX_funcValid_check(kal_uint32 function_num, mod_sel_t mod_num, kal_uint32 sip_flag);
496
497
498/*
499 * @brief set IOPAD group to special funciton mode
500 * @param
501 * funciton_num: function mode selection valid value 0~5;
502 * mod_num: IOPAD group selection, valied value please see enum module_sel;
503 * sip_flag: choose the chip is SIP or Non-SIP.
504 * 0: non-sip ; 1: sip
505 * @return
506 */
507extern void IOMUX_set_module_func( mod_sel_t mod_num, kal_uint32 function_num);
508
509/*
510 * @brief Get the special function mode of the IOPAD group.
511 * @param
512 * mod_num: IOPAD group selection, valied value please see enum module_sel;
513 * @return
514 return the function mode, valid value 0~5;
515 */
516extern kal_uint32 IOMUX_get_module_func(mod_sel_t module_num);
517
518
519/*****************************************************************
520*some fields control the IOPAD behavior when these IOPAD groups operate in non F0 mode.
521*
522******************************************************************/
523
524extern void IOMUX_init(void);
525extern void IOMUX_set_moduleconfig(module_conf_t* cfg);
526extern module_conf_t* IOMUX_get_moduleconfig(config_sel_t cfg_sel, module_type_t type);
527
528#define CONFIG_ADDR(cfg_sel)
529#define IOMUX_set_module_drive(cfg_sel, data)
530#define IOMUX_set_msdc_drive(cfg_sel, data)
531#define IOMUX_set_module_tdsel(cfg_sel, data)
532#define IOMUX_set_msdc_tdsel(cfg_sel, data)
533#define IOMUX_set_module_rdsel(cfg_sel, data)
534#define IOMUX_set_msdc_rdsel(cfg_sel, data)
535#define IOMUX_set_msdc0_smt(cfg_sel, data)
536#define IOMUX_set_msdc0_sr(cfg_sel, data)
537#define IOMUX_set_sdio_r1(cfg_sel, data)
538#define IOMUX_set_sdio_r0(cfg_sel, data)
539#define IOMUX_set_sdio_smt(cfg_sel, data)
540#define IOMUX_set_sdio_sr(cfg_sel, data)
541#define IOMUX_set_ddrphy_cfg(data)
542#define IOMUX_set_dmcmdphy_cfg(data)
543
544
545
546
547#define IOMUX_get_module_drive(cfg_sel)
548#define IOMUX_get_msdc_drive(cfg_sel)
549#define IOMUX_get_module_tdsel(cfg_sel)
550#define IOMUX_get_msdc_tdsel(cfg_sel)
551#define IOMUX_get_module_rdsel(cfg_sel)
552#define IOMUX_get_msdc_rdsel(cfg_sel)
553
554#define IOMUX_get_msdc0_smt(cfg_sel)
555#define IOMUX_get_msdc0_sr(cfg_sel)
556
557
558#define IOMUX_get_sdio_r0(cfg_sel)
559#define IOMUX_get_sdio_r1(cfg_sel)
560#define IOMUX_get_sdio_sr(cfg_sel)
561#define IOMUX_get_sdio_smt(cfg_sel)
562#define IOMUX_get_ddrphy_cfg()
563#define IOMUX_get_dmcmdphy_cfg()
564
565
566#ifndef DRV_SetReg3
567#define DRV_SetReg3(addr,offset,data) DRV_WriteReg32(addr, ((DRV_Reg32(addr) & ~(0x7<<offset))|(data << offset)))
568#endif
569
570
571#endif /*IOMUX_HW_H*/