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192.168.1.100 / T800_MD / b0f5b85a5b9d69cbfa1dd990d559a4a9c7d8f2a6 / . / mcu / driver / devdrv / pmic / src / dcl_pmic6355.c
blob: 11ac04cc057aeb20e4b983dce71a037b770e9920 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2013
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * dcl_pmic6355_37.c
41 *
42 * Project:
43 * --------
44 * MOLY Software
45 *
46 * Description:
47 * ------------
48 * This file is for PMIC 6355
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * removed!
59 * removed!
60 * removed!
61 *
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63 * removed!
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66 *
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76 * removed!
77 * removed!
78 * removed!
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80 *
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82 * removed!
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85 *
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87 * removed!
88 * removed!
89 * removed!
90 *
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92 * removed!
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95 *
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100 * removed!
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103 * removed!
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105 * removed!
106 *
107 * removed!
108 * removed!
109 *
110 * removed!
111 *------------------------------------------------------------------------------
112 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
113 *============================================================================
114 ****************************************************************************/
115
116#if defined(FPGA_CTP)
117#include <common.h>
118#endif
119
120#include "reg_base.h"
121#include "drv_comm.h"
122#include "init.h"
123#include "dcl.h"
124#include "dcl_pmu_sw.h"
125#include "pmic_wrap.h"
126#include "kal_public_api.h"
127#include "us_timer.h"
128
129#if defined(PMIC_6355_REG_API)
130
131// Start PMIC_UNIT_TEST
132//#define PMIC_UNIT_TEST
133// ARM Section RW/RO/ZI Use Internal SRAM
134#define PMIC_INTERNAL_SRAM
135
136#if !defined(__FUE__)
137#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
138#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
139#else /*defined(__FUE__)*/
140#define SAVEANDSETIRQMASK() 0
141#define RESTOREIRQMASK(mask) {}
142#endif /*defined(__FUE__)*/
143
144#define PMIC_MAX_REG_NUM 0x3a00 // 0x0000~0x3a00
145
146//////////////////////////////////////////////////
147// Exported APIs //
148//////////////////////////////////////////////////
149
150extern DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr);
151extern DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr);
152extern void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val);
153extern void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val);
154extern DCL_BOOL dcl_pmic_init_done_query(void);
155typedef enum
156{
157 AUXADC_READ_INIT = 0,
158 AUXADC_READ_REQUEST = 1,
159 AUXADC_READ_READY = 2,
160 AUXADC_READ_BUSY = 3,
161 AUXADC_READ_DATA = 4
162}AUXADC_FSM;
163
164typedef struct
165{
166 kal_uint32 command_flag;
167 kal_uint32 reg_before_write;
168 kal_uint32 write_value;
169 kal_uint32 address_offset;
170 kal_uint32 reg_mask;
171 kal_uint32 reg_shift;
172 kal_uint32 reg_addr;
173 kal_uint32 reg_data;
174}PMIC_REG_LOG;
175
176AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
177PMIC_REG_LOG pmic_reg_log;
178
179#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
180__attribute__ ((zero_init))
181#endif /* __MTK_TARGET__ */
182
183kal_uint8 pmic_hw_version;
184kal_uint8 pmic_sw_version;
185kal_uint16 pmic_reg[PMIC_MAX_REG_NUM];
186DCL_BOOL pmic_init_done = DCL_FALSE;
187
188kal_spinlockid dcl_pmic_access_spinlock;
189extern kal_spinlockid dcl_pmic_control_spinlock;
190
191const PMIC_FLAG_TABLE_ENTRY pmic_flags_table[] =
192{
193 {PMIC_HWCID, PMIC_HWCID_MASK, PMIC_HWCID_SHIFT, },
194 {PMIC_SWCID, PMIC_SWCID_MASK, PMIC_SWCID_SHIFT, },
195 {PMIC_TOP_CON, PMIC_RG_SRCLKEN_IN0_EN_MASK, PMIC_RG_SRCLKEN_IN0_EN_SHIFT, },
196 {PMIC_TOP_CON, PMIC_RG_SRCLKEN_IN1_EN_MASK, PMIC_RG_SRCLKEN_IN1_EN_SHIFT, },
197 {PMIC_TOP_CON, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT, },
198 {PMIC_TOP_CON, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT, },
199 {PMIC_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_EN_MASK, PMIC_RG_BUCK_VMODEM_EN_SHIFT, },
200 {PMIC_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_LP_MASK, PMIC_RG_BUCK_VMODEM_LP_SHIFT, },
201 {PMIC_BUCK_VMODEM_CON1, PMIC_RG_BUCK_VMODEM_VOSEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT, },
202 {PMIC_BUCK_VMODEM_CON2, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
203 {PMIC_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT, },
204 {PMIC_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT, },
205 {PMIC_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT, },
206 {PMIC_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT, },
207 {PMIC_BUCK_VMODEM_OP_EN_SET, PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT, },
208 {PMIC_BUCK_VMODEM_OP_EN_CLR, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT, },
209 {PMIC_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT, },
210 {PMIC_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT, },
211 {PMIC_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT, },
212 {PMIC_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_ON_OP_MASK, PMIC_RG_BUCK_VMODEM_ON_OP_SHIFT, },
213 {PMIC_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_LP_OP_MASK, PMIC_RG_BUCK_VMODEM_LP_OP_SHIFT, },
214 {PMIC_BUCK_VMODEM_OP_CFG_SET, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT, },
215 {PMIC_BUCK_VMODEM_OP_CFG_CLR, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT, },
216 {PMIC_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_MASK, PMIC_DA_VMODEM_VOSEL_SHIFT, },
217 {PMIC_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_GRAY_MASK, PMIC_DA_VMODEM_VOSEL_GRAY_SHIFT, },
218 {PMIC_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_EN_MASK, PMIC_DA_VMODEM_EN_SHIFT, },
219 {PMIC_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_STB_MASK, PMIC_DA_VMODEM_STB_SHIFT, },
220 {PMIC_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_VSLEEP_SEL_MASK, PMIC_DA_VMODEM_VSLEEP_SEL_SHIFT, },
221 {PMIC_BUCK_VS1_VOTER, PMIC_RG_BUCK_VS1_VOTER_EN_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SHIFT, },
222 {PMIC_BUCK_VS1_VOTER_SET, PMIC_RG_BUCK_VS1_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SET_SHIFT, },
223 {PMIC_BUCK_VS1_VOTER_CLR, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_SHIFT, },
224 {PMIC_BUCK_VS1_VOTER_CFG, PMIC_RG_BUCK_VS1_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS1_VOTER_VOSEL_SHIFT, },
225 {PMIC_BUCK_VS2_VOTER, PMIC_RG_BUCK_VS2_VOTER_EN_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SHIFT, },
226 {PMIC_BUCK_VS2_VOTER_SET, PMIC_RG_BUCK_VS2_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SET_SHIFT, },
227 {PMIC_BUCK_VS2_VOTER_CLR, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_SHIFT, },
228 {PMIC_BUCK_VS2_VOTER_CFG, PMIC_RG_BUCK_VS2_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOTER_VOSEL_SHIFT, },
229 {PMIC_BUCK_VPA_CON0, PMIC_RG_BUCK_VPA_EN_MASK, PMIC_RG_BUCK_VPA_EN_SHIFT, },
230 {PMIC_BUCK_VPA_CON1, PMIC_RG_BUCK_VPA_VOSEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_SHIFT, },
231 {PMIC_SMPS_ANA_CON4, PMIC_RG_VMODEM_SLEEP_VOLTAGE_MASK, PMIC_RG_VMODEM_SLEEP_VOLTAGE_SHIFT, },
232 {PMIC_SMPS_ANA_CON14, PMIC_RG_VSRAM_MD_SLEEP_VOLTAGE_MASK, PMIC_RG_VSRAM_MD_SLEEP_VOLTAGE_SHIFT, },
233 {PMIC_VPA_ANA_CON0, PMIC_RG_VPA_MODESET_MASK, PMIC_RG_VPA_MODESET_SHIFT, },
234 {PMIC_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_EN_MASK, PMIC_RG_LDO_VSIM1_EN_SHIFT, },
235 {PMIC_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_LP_MASK, PMIC_RG_LDO_VSIM1_LP_SHIFT, },
236 {PMIC_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM1_SW_OP_EN_SHIFT, },
237 {PMIC_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_EN_SHIFT, },
238 {PMIC_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_EN_SHIFT, },
239 {PMIC_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_EN_SHIFT, },
240 {PMIC_LDO_VSIM1_OP_EN_SET, PMIC_RG_LDO_VSIM1_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM1_OP_EN_SET_SHIFT, },
241 {PMIC_LDO_VSIM1_OP_EN_CLR, PMIC_RG_LDO_VSIM1_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_EN_CLR_SHIFT, },
242 {PMIC_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_SHIFT, },
243 {PMIC_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_SHIFT, },
244 {PMIC_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_SHIFT, },
245 {PMIC_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_ON_OP_MASK, PMIC_RG_LDO_VSIM1_ON_OP_SHIFT, },
246 {PMIC_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_LP_OP_MASK, PMIC_RG_LDO_VSIM1_LP_OP_SHIFT, },
247 {PMIC_LDO_VSIM1_OP_CFG_SET, PMIC_RG_LDO_VSIM1_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_SET_SHIFT, },
248 {PMIC_LDO_VSIM1_OP_CFG_CLR, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_SHIFT, },
249 {PMIC_LDO_VSIM1_CON2, PMIC_RG_LDO_VSIM1_OCFB_EN_MASK, PMIC_RG_LDO_VSIM1_OCFB_EN_SHIFT, },
250 {PMIC_LDO_VSIM1_CON2, PMIC_DA_QI_VSIM1_OCFB_EN_MASK, PMIC_DA_QI_VSIM1_OCFB_EN_SHIFT, },
251 {PMIC_DLDO_ANA_CON2, PMIC_RG_VSIM1_VOSEL_MASK, PMIC_RG_VSIM1_VOSEL_SHIFT, },
252 {PMIC_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_EN_MASK, PMIC_RG_LDO_VSIM2_EN_SHIFT, },
253 {PMIC_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_LP_MASK, PMIC_RG_LDO_VSIM2_LP_SHIFT, },
254 {PMIC_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM2_SW_OP_EN_SHIFT, },
255 {PMIC_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_EN_SHIFT, },
256 {PMIC_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_EN_SHIFT, },
257 {PMIC_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_EN_SHIFT, },
258 {PMIC_LDO_VSIM2_OP_EN_SET, PMIC_RG_LDO_VSIM2_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM2_OP_EN_SET_SHIFT, },
259 {PMIC_LDO_VSIM2_OP_EN_CLR, PMIC_RG_LDO_VSIM2_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_EN_CLR_SHIFT, },
260 {PMIC_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_SHIFT, },
261 {PMIC_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_SHIFT, },
262 {PMIC_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_SHIFT, },
263 {PMIC_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_ON_OP_MASK, PMIC_RG_LDO_VSIM2_ON_OP_SHIFT, },
264 {PMIC_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_LP_OP_MASK, PMIC_RG_LDO_VSIM2_LP_OP_SHIFT, },
265 {PMIC_LDO_VSIM2_OP_CFG_SET, PMIC_RG_LDO_VSIM2_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_SET_SHIFT, },
266 {PMIC_LDO_VSIM2_OP_CFG_CLR, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_SHIFT, },
267 {PMIC_LDO_VSIM2_CON2, PMIC_RG_LDO_VSIM2_OCFB_EN_MASK, PMIC_RG_LDO_VSIM2_OCFB_EN_SHIFT, },
268 {PMIC_LDO_VSIM2_CON2, PMIC_DA_QI_VSIM2_OCFB_EN_MASK, PMIC_DA_QI_VSIM2_OCFB_EN_SHIFT, },
269 {PMIC_DLDO_ANA_CON4, PMIC_RG_VSIM2_VOSEL_MASK, PMIC_RG_VSIM2_VOSEL_SHIFT, },
270 {PMIC_LDO_VMIPI_CON0, PMIC_RG_LDO_VMIPI_EN_MASK, PMIC_RG_LDO_VMIPI_EN_SHIFT, },
271 {PMIC_LDO_VMIPI_CON0, PMIC_RG_LDO_VMIPI_LP_MASK, PMIC_RG_LDO_VMIPI_LP_SHIFT, },
272 {PMIC_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_SW_OP_EN_MASK, PMIC_RG_LDO_VMIPI_SW_OP_EN_SHIFT, },
273 {PMIC_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_HW0_OP_EN_MASK, PMIC_RG_LDO_VMIPI_HW0_OP_EN_SHIFT, },
274 {PMIC_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_HW1_OP_EN_MASK, PMIC_RG_LDO_VMIPI_HW1_OP_EN_SHIFT, },
275 {PMIC_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_HW2_OP_EN_MASK, PMIC_RG_LDO_VMIPI_HW2_OP_EN_SHIFT, },
276 {PMIC_LDO_VMIPI_OP_EN_SET, PMIC_RG_LDO_VMIPI_OP_EN_SET_MASK, PMIC_RG_LDO_VMIPI_OP_EN_SET_SHIFT, },
277 {PMIC_LDO_VMIPI_OP_EN_CLR, PMIC_RG_LDO_VMIPI_OP_EN_CLR_MASK, PMIC_RG_LDO_VMIPI_OP_EN_CLR_SHIFT, },
278 {PMIC_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_HW0_OP_CFG_MASK, PMIC_RG_LDO_VMIPI_HW0_OP_CFG_SHIFT, },
279 {PMIC_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_HW1_OP_CFG_MASK, PMIC_RG_LDO_VMIPI_HW1_OP_CFG_SHIFT, },
280 {PMIC_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_HW2_OP_CFG_MASK, PMIC_RG_LDO_VMIPI_HW2_OP_CFG_SHIFT, },
281 {PMIC_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_ON_OP_MASK, PMIC_RG_LDO_VMIPI_ON_OP_SHIFT, },
282 {PMIC_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_LP_OP_MASK, PMIC_RG_LDO_VMIPI_LP_OP_SHIFT, },
283 {PMIC_LDO_VMIPI_OP_CFG_SET, PMIC_RG_LDO_VMIPI_OP_CFG_SET_MASK, PMIC_RG_LDO_VMIPI_OP_CFG_SET_SHIFT, },
284 {PMIC_LDO_VMIPI_OP_CFG_CLR, PMIC_RG_LDO_VMIPI_OP_CFG_CLR_MASK, PMIC_RG_LDO_VMIPI_OP_CFG_CLR_SHIFT, },
285 {PMIC_LDO_VMIPI_CON1, PMIC_DA_QI_VMIPI_MODE_MASK, PMIC_DA_QI_VMIPI_MODE_SHIFT, },
286 {PMIC_LDO_VMIPI_CON1, PMIC_DA_QI_VMIPI_EN_MASK, PMIC_DA_QI_VMIPI_EN_SHIFT, },
287 {PMIC_LDO_VMIPI_CON2, PMIC_RG_LDO_VMIPI_OCFB_EN_MASK, PMIC_RG_LDO_VMIPI_OCFB_EN_SHIFT, },
288 {PMIC_LDO_VMIPI_CON2, PMIC_DA_QI_VMIPI_OCFB_EN_MASK, PMIC_DA_QI_VMIPI_OCFB_EN_SHIFT, },
289 {PMIC_LDO_VTCXO24_CON0, PMIC_RG_LDO_VTCXO24_EN_MASK, PMIC_RG_LDO_VTCXO24_EN_SHIFT, },
290 {PMIC_LDO_VTCXO24_CON0, PMIC_RG_LDO_VTCXO24_LP_MASK, PMIC_RG_LDO_VTCXO24_LP_SHIFT, },
291 {PMIC_LDO_VTCXO24_OP_EN, PMIC_RG_LDO_VTCXO24_SW_OP_EN_MASK, PMIC_RG_LDO_VTCXO24_SW_OP_EN_SHIFT, },
292 {PMIC_LDO_VTCXO24_OP_EN, PMIC_RG_LDO_VTCXO24_HW0_OP_EN_MASK, PMIC_RG_LDO_VTCXO24_HW0_OP_EN_SHIFT, },
293 {PMIC_LDO_VTCXO24_OP_EN, PMIC_RG_LDO_VTCXO24_HW1_OP_EN_MASK, PMIC_RG_LDO_VTCXO24_HW1_OP_EN_SHIFT, },
294 {PMIC_LDO_VTCXO24_OP_EN, PMIC_RG_LDO_VTCXO24_HW2_OP_EN_MASK, PMIC_RG_LDO_VTCXO24_HW2_OP_EN_SHIFT, },
295 {PMIC_LDO_VTCXO24_OP_EN_SET, PMIC_RG_LDO_VTCXO24_OP_EN_SET_MASK, PMIC_RG_LDO_VTCXO24_OP_EN_SET_SHIFT, },
296 {PMIC_LDO_VTCXO24_OP_EN_CLR, PMIC_RG_LDO_VTCXO24_OP_EN_CLR_MASK, PMIC_RG_LDO_VTCXO24_OP_EN_CLR_SHIFT, },
297 {PMIC_LDO_VTCXO24_OP_CFG, PMIC_RG_LDO_VTCXO24_HW0_OP_CFG_MASK, PMIC_RG_LDO_VTCXO24_HW0_OP_CFG_SHIFT, },
298 {PMIC_LDO_VTCXO24_OP_CFG, PMIC_RG_LDO_VTCXO24_HW1_OP_CFG_MASK, PMIC_RG_LDO_VTCXO24_HW1_OP_CFG_SHIFT, },
299 {PMIC_LDO_VTCXO24_OP_CFG, PMIC_RG_LDO_VTCXO24_HW2_OP_CFG_MASK, PMIC_RG_LDO_VTCXO24_HW2_OP_CFG_SHIFT, },
300 {PMIC_LDO_VTCXO24_OP_CFG, PMIC_RG_LDO_VTCXO24_ON_OP_MASK, PMIC_RG_LDO_VTCXO24_ON_OP_SHIFT, },
301 {PMIC_LDO_VTCXO24_OP_CFG, PMIC_RG_LDO_VTCXO24_LP_OP_MASK, PMIC_RG_LDO_VTCXO24_LP_OP_SHIFT, },
302 {PMIC_LDO_VTCXO24_OP_CFG_SET, PMIC_RG_LDO_VTCXO24_OP_CFG_SET_MASK, PMIC_RG_LDO_VTCXO24_OP_CFG_SET_SHIFT, },
303 {PMIC_LDO_VTCXO24_OP_CFG_CLR, PMIC_RG_LDO_VTCXO24_OP_CFG_CLR_MASK, PMIC_RG_LDO_VTCXO24_OP_CFG_CLR_SHIFT, },
304 {PMIC_LDO_VTCXO24_CON1, PMIC_DA_QI_VTCXO24_MODE_MASK, PMIC_DA_QI_VTCXO24_MODE_SHIFT, },
305 {PMIC_LDO_VTCXO24_CON1, PMIC_DA_QI_VTCXO24_EN_MASK, PMIC_DA_QI_VTCXO24_EN_SHIFT, },
306 {PMIC_LDO_VTCXO24_CON2, PMIC_RG_LDO_VTCXO24_OCFB_EN_MASK, PMIC_RG_LDO_VTCXO24_OCFB_EN_SHIFT, },
307 {PMIC_LDO_VTCXO24_CON2, PMIC_DA_QI_VTCXO24_OCFB_EN_MASK, PMIC_DA_QI_VTCXO24_OCFB_EN_SHIFT, },
308 {PMIC_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_EN_MASK, PMIC_RG_LDO_VFE28_EN_SHIFT, },
309 {PMIC_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_LP_MASK, PMIC_RG_LDO_VFE28_LP_SHIFT, },
310 {PMIC_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_SW_OP_EN_MASK, PMIC_RG_LDO_VFE28_SW_OP_EN_SHIFT, },
311 {PMIC_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW0_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW0_OP_EN_SHIFT, },
312 {PMIC_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW1_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW1_OP_EN_SHIFT, },
313 {PMIC_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW2_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW2_OP_EN_SHIFT, },
314 {PMIC_LDO_VFE28_OP_EN_SET, PMIC_RG_LDO_VFE28_OP_EN_SET_MASK, PMIC_RG_LDO_VFE28_OP_EN_SET_SHIFT, },
315 {PMIC_LDO_VFE28_OP_EN_CLR, PMIC_RG_LDO_VFE28_OP_EN_CLR_MASK, PMIC_RG_LDO_VFE28_OP_EN_CLR_SHIFT, },
316 {PMIC_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW0_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW0_OP_CFG_SHIFT, },
317 {PMIC_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW1_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW1_OP_CFG_SHIFT, },
318 {PMIC_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW2_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW2_OP_CFG_SHIFT, },
319 {PMIC_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_ON_OP_MASK, PMIC_RG_LDO_VFE28_ON_OP_SHIFT, },
320 {PMIC_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_LP_OP_MASK, PMIC_RG_LDO_VFE28_LP_OP_SHIFT, },
321 {PMIC_LDO_VFE28_OP_CFG_SET, PMIC_RG_LDO_VFE28_OP_CFG_SET_MASK, PMIC_RG_LDO_VFE28_OP_CFG_SET_SHIFT, },
322 {PMIC_LDO_VFE28_OP_CFG_CLR, PMIC_RG_LDO_VFE28_OP_CFG_CLR_MASK, PMIC_RG_LDO_VFE28_OP_CFG_CLR_SHIFT, },
323 {PMIC_LDO_VFE28_CON1, PMIC_DA_QI_VFE28_MODE_MASK, PMIC_DA_QI_VFE28_MODE_SHIFT, },
324 {PMIC_LDO_VFE28_CON1, PMIC_DA_QI_VFE28_EN_MASK, PMIC_DA_QI_VFE28_EN_SHIFT, },
325 {PMIC_LDO_VFE28_CON2, PMIC_RG_LDO_VFE28_OCFB_EN_MASK, PMIC_RG_LDO_VFE28_OCFB_EN_SHIFT, },
326 {PMIC_LDO_VFE28_CON2, PMIC_DA_QI_VFE28_OCFB_EN_MASK, PMIC_DA_QI_VFE28_OCFB_EN_SHIFT, },
327 {PMIC_LDO_VRF18_1_CON0, PMIC_RG_LDO_VRF18_1_EN_MASK, PMIC_RG_LDO_VRF18_1_EN_SHIFT, },
328 {PMIC_LDO_VRF18_1_CON0, PMIC_RG_LDO_VRF18_1_LP_MASK, PMIC_RG_LDO_VRF18_1_LP_SHIFT, },
329 {PMIC_LDO_VRF18_1_OP_EN, PMIC_RG_LDO_VRF18_1_SW_OP_EN_MASK, PMIC_RG_LDO_VRF18_1_SW_OP_EN_SHIFT, },
330 {PMIC_LDO_VRF18_1_OP_EN, PMIC_RG_LDO_VRF18_1_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF18_1_HW0_OP_EN_SHIFT, },
331 {PMIC_LDO_VRF18_1_OP_EN, PMIC_RG_LDO_VRF18_1_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF18_1_HW1_OP_EN_SHIFT, },
332 {PMIC_LDO_VRF18_1_OP_EN, PMIC_RG_LDO_VRF18_1_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF18_1_HW2_OP_EN_SHIFT, },
333 {PMIC_LDO_VRF18_1_OP_EN_SET, PMIC_RG_LDO_VRF18_1_OP_EN_SET_MASK, PMIC_RG_LDO_VRF18_1_OP_EN_SET_SHIFT, },
334 {PMIC_LDO_VRF18_1_OP_EN_CLR, PMIC_RG_LDO_VRF18_1_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF18_1_OP_EN_CLR_SHIFT, },
335 {PMIC_LDO_VRF18_1_OP_CFG, PMIC_RG_LDO_VRF18_1_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF18_1_HW0_OP_CFG_SHIFT, },
336 {PMIC_LDO_VRF18_1_OP_CFG, PMIC_RG_LDO_VRF18_1_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF18_1_HW1_OP_CFG_SHIFT, },
337 {PMIC_LDO_VRF18_1_OP_CFG, PMIC_RG_LDO_VRF18_1_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF18_1_HW2_OP_CFG_SHIFT, },
338 {PMIC_LDO_VRF18_1_OP_CFG, PMIC_RG_LDO_VRF18_1_ON_OP_MASK, PMIC_RG_LDO_VRF18_1_ON_OP_SHIFT, },
339 {PMIC_LDO_VRF18_1_OP_CFG, PMIC_RG_LDO_VRF18_1_LP_OP_MASK, PMIC_RG_LDO_VRF18_1_LP_OP_SHIFT, },
340 {PMIC_LDO_VRF18_1_OP_CFG_SET, PMIC_RG_LDO_VRF18_1_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF18_1_OP_CFG_SET_SHIFT, },
341 {PMIC_LDO_VRF18_1_OP_CFG_CLR, PMIC_RG_LDO_VRF18_1_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF18_1_OP_CFG_CLR_SHIFT, },
342 {PMIC_LDO_VRF18_1_CON1, PMIC_DA_QI_VRF18_1_MODE_MASK, PMIC_DA_QI_VRF18_1_MODE_SHIFT, },
343 {PMIC_LDO_VRF18_1_CON1, PMIC_DA_QI_VRF18_1_EN_MASK, PMIC_DA_QI_VRF18_1_EN_SHIFT, },
344 {PMIC_LDO_VRF18_1_CON2, PMIC_RG_LDO_VRF18_1_OCFB_EN_MASK, PMIC_RG_LDO_VRF18_1_OCFB_EN_SHIFT, },
345 {PMIC_LDO_VRF18_1_CON2, PMIC_DA_QI_VRF18_1_OCFB_EN_MASK, PMIC_DA_QI_VRF18_1_OCFB_EN_SHIFT, },
346 {PMIC_LDO_VRF18_2_CON0, PMIC_RG_LDO_VRF18_2_EN_MASK, PMIC_RG_LDO_VRF18_2_EN_SHIFT, },
347 {PMIC_LDO_VRF18_2_CON0, PMIC_RG_LDO_VRF18_2_LP_MASK, PMIC_RG_LDO_VRF18_2_LP_SHIFT, },
348 {PMIC_LDO_VRF18_2_OP_EN, PMIC_RG_LDO_VRF18_2_SW_OP_EN_MASK, PMIC_RG_LDO_VRF18_2_SW_OP_EN_SHIFT, },
349 {PMIC_LDO_VRF18_2_OP_EN, PMIC_RG_LDO_VRF18_2_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF18_2_HW0_OP_EN_SHIFT, },
350 {PMIC_LDO_VRF18_2_OP_EN, PMIC_RG_LDO_VRF18_2_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF18_2_HW1_OP_EN_SHIFT, },
351 {PMIC_LDO_VRF18_2_OP_EN, PMIC_RG_LDO_VRF18_2_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF18_2_HW2_OP_EN_SHIFT, },
352 {PMIC_LDO_VRF18_2_OP_EN_SET, PMIC_RG_LDO_VRF18_2_OP_EN_SET_MASK, PMIC_RG_LDO_VRF18_2_OP_EN_SET_SHIFT, },
353 {PMIC_LDO_VRF18_2_OP_EN_CLR, PMIC_RG_LDO_VRF18_2_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF18_2_OP_EN_CLR_SHIFT, },
354 {PMIC_LDO_VRF18_2_OP_CFG, PMIC_RG_LDO_VRF18_2_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF18_2_HW0_OP_CFG_SHIFT, },
355 {PMIC_LDO_VRF18_2_OP_CFG, PMIC_RG_LDO_VRF18_2_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF18_2_HW1_OP_CFG_SHIFT, },
356 {PMIC_LDO_VRF18_2_OP_CFG, PMIC_RG_LDO_VRF18_2_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF18_2_HW2_OP_CFG_SHIFT, },
357 {PMIC_LDO_VRF18_2_OP_CFG, PMIC_RG_LDO_VRF18_2_ON_OP_MASK, PMIC_RG_LDO_VRF18_2_ON_OP_SHIFT, },
358 {PMIC_LDO_VRF18_2_OP_CFG, PMIC_RG_LDO_VRF18_2_LP_OP_MASK, PMIC_RG_LDO_VRF18_2_LP_OP_SHIFT, },
359 {PMIC_LDO_VRF18_2_OP_CFG_SET, PMIC_RG_LDO_VRF18_2_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF18_2_OP_CFG_SET_SHIFT, },
360 {PMIC_LDO_VRF18_2_OP_CFG_CLR, PMIC_RG_LDO_VRF18_2_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF18_2_OP_CFG_CLR_SHIFT, },
361 {PMIC_LDO_VRF18_2_CON1, PMIC_DA_QI_VRF18_2_MODE_MASK, PMIC_DA_QI_VRF18_2_MODE_SHIFT, },
362 {PMIC_LDO_VRF18_2_CON1, PMIC_DA_QI_VRF18_2_EN_MASK, PMIC_DA_QI_VRF18_2_EN_SHIFT, },
363 {PMIC_LDO_VRF18_2_CON2, PMIC_RG_LDO_VRF18_2_OCFB_EN_MASK, PMIC_RG_LDO_VRF18_2_OCFB_EN_SHIFT, },
364 {PMIC_LDO_VRF18_2_CON2, PMIC_DA_QI_VRF18_2_OCFB_EN_MASK, PMIC_DA_QI_VRF18_2_OCFB_EN_SHIFT, },
365 {PMIC_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_EN_MASK, PMIC_RG_LDO_VRF12_EN_SHIFT, },
366 {PMIC_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_LP_MASK, PMIC_RG_LDO_VRF12_LP_SHIFT, },
367 {PMIC_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_SW_OP_EN_MASK, PMIC_RG_LDO_VRF12_SW_OP_EN_SHIFT, },
368 {PMIC_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW0_OP_EN_SHIFT, },
369 {PMIC_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW1_OP_EN_SHIFT, },
370 {PMIC_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW2_OP_EN_SHIFT, },
371 {PMIC_LDO_VRF12_OP_EN_SET, PMIC_RG_LDO_VRF12_OP_EN_SET_MASK, PMIC_RG_LDO_VRF12_OP_EN_SET_SHIFT, },
372 {PMIC_LDO_VRF12_OP_EN_CLR, PMIC_RG_LDO_VRF12_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF12_OP_EN_CLR_SHIFT, },
373 {PMIC_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW0_OP_CFG_SHIFT, },
374 {PMIC_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW1_OP_CFG_SHIFT, },
375 {PMIC_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW2_OP_CFG_SHIFT, },
376 {PMIC_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_ON_OP_MASK, PMIC_RG_LDO_VRF12_ON_OP_SHIFT, },
377 {PMIC_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_LP_OP_MASK, PMIC_RG_LDO_VRF12_LP_OP_SHIFT, },
378 {PMIC_LDO_VRF12_OP_CFG_SET, PMIC_RG_LDO_VRF12_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF12_OP_CFG_SET_SHIFT, },
379 {PMIC_LDO_VRF12_OP_CFG_CLR, PMIC_RG_LDO_VRF12_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF12_OP_CFG_CLR_SHIFT, },
380 {PMIC_LDO_VRF12_CON1, PMIC_DA_QI_VRF12_MODE_MASK, PMIC_DA_QI_VRF12_MODE_SHIFT, },
381 {PMIC_LDO_VRF12_CON1, PMIC_DA_QI_VRF12_EN_MASK, PMIC_DA_QI_VRF12_EN_SHIFT, },
382 {PMIC_LDO_VRF12_CON2, PMIC_RG_LDO_VRF12_OCFB_EN_MASK, PMIC_RG_LDO_VRF12_OCFB_EN_SHIFT, },
383 {PMIC_LDO_VRF12_CON2, PMIC_DA_QI_VRF12_OCFB_EN_MASK, PMIC_DA_QI_VRF12_OCFB_EN_SHIFT, },
384 {PMIC_LDO_VSRAM_MD_CON0, PMIC_RG_LDO_VSRAM_MD_EN_MASK, PMIC_RG_LDO_VSRAM_MD_EN_SHIFT, },
385 {PMIC_LDO_VSRAM_MD_CON0, PMIC_RG_LDO_VSRAM_MD_LP_MASK, PMIC_RG_LDO_VSRAM_MD_LP_SHIFT, },
386 {PMIC_LDO_VSRAM_MD_CON1, PMIC_RG_LDO_VSRAM_MD_VOSEL_MASK, PMIC_RG_LDO_VSRAM_MD_VOSEL_SHIFT, },
387 {PMIC_LDO_VSRAM_MD_CON2, PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP_SHIFT, },
388 {PMIC_LDO_VSRAM_MD_OP_EN, PMIC_RG_LDO_VSRAM_MD_SW_OP_EN_MASK, PMIC_RG_LDO_VSRAM_MD_SW_OP_EN_SHIFT, },
389 {PMIC_LDO_VSRAM_MD_OP_EN, PMIC_RG_LDO_VSRAM_MD_HW0_OP_EN_MASK, PMIC_RG_LDO_VSRAM_MD_HW0_OP_EN_SHIFT, },
390 {PMIC_LDO_VSRAM_MD_OP_EN, PMIC_RG_LDO_VSRAM_MD_HW1_OP_EN_MASK, PMIC_RG_LDO_VSRAM_MD_HW1_OP_EN_SHIFT, },
391 {PMIC_LDO_VSRAM_MD_OP_EN, PMIC_RG_LDO_VSRAM_MD_HW2_OP_EN_MASK, PMIC_RG_LDO_VSRAM_MD_HW2_OP_EN_SHIFT, },
392 {PMIC_LDO_VSRAM_MD_OP_EN_SET, PMIC_RG_LDO_VSRAM_MD_OP_EN_SET_MASK, PMIC_RG_LDO_VSRAM_MD_OP_EN_SET_SHIFT, },
393 {PMIC_LDO_VSRAM_MD_OP_EN_CLR, PMIC_RG_LDO_VSRAM_MD_OP_EN_CLR_MASK, PMIC_RG_LDO_VSRAM_MD_OP_EN_CLR_SHIFT, },
394 {PMIC_LDO_VSRAM_MD_OP_CFG, PMIC_RG_LDO_VSRAM_MD_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSRAM_MD_HW0_OP_CFG_SHIFT, },
395 {PMIC_LDO_VSRAM_MD_OP_CFG, PMIC_RG_LDO_VSRAM_MD_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSRAM_MD_HW1_OP_CFG_SHIFT, },
396 {PMIC_LDO_VSRAM_MD_OP_CFG, PMIC_RG_LDO_VSRAM_MD_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSRAM_MD_HW2_OP_CFG_SHIFT, },
397 {PMIC_LDO_VSRAM_MD_OP_CFG, PMIC_RG_LDO_VSRAM_MD_ON_OP_MASK, PMIC_RG_LDO_VSRAM_MD_ON_OP_SHIFT, },
398 {PMIC_LDO_VSRAM_MD_OP_CFG, PMIC_RG_LDO_VSRAM_MD_LP_OP_MASK, PMIC_RG_LDO_VSRAM_MD_LP_OP_SHIFT, },
399 {PMIC_LDO_VSRAM_MD_OP_CFG_SET, PMIC_RG_LDO_VSRAM_MD_OP_CFG_SET_MASK, PMIC_RG_LDO_VSRAM_MD_OP_CFG_SET_SHIFT, },
400 {PMIC_LDO_VSRAM_MD_OP_CFG_CLR, PMIC_RG_LDO_VSRAM_MD_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSRAM_MD_OP_CFG_CLR_SHIFT, },
401 {PMIC_LDO_VSRAM_MD_CON3, PMIC_DA_QI_VSRAM_MD_MODE_MASK, PMIC_DA_QI_VSRAM_MD_MODE_SHIFT, },
402 {PMIC_LDO_VSRAM_MD_DBG0, PMIC_DA_QI_VSRAM_MD_VOSEL_GRAY_MASK, PMIC_DA_QI_VSRAM_MD_VOSEL_GRAY_SHIFT, },
403 {PMIC_LDO_VSRAM_MD_DBG0, PMIC_DA_QI_VSRAM_MD_VOSEL_MASK, PMIC_DA_QI_VSRAM_MD_VOSEL_SHIFT, },
404 {PMIC_LDO_VSRAM_MD_DBG1, PMIC_DA_QI_VSRAM_MD_EN_MASK, PMIC_DA_QI_VSRAM_MD_EN_SHIFT, },
405 {PMIC_LDO_VSRAM_MD_DBG1, PMIC_DA_QI_VSRAM_MD_STB_MASK, PMIC_DA_QI_VSRAM_MD_STB_SHIFT, },
406 {PMIC_LDO_VSRAM_MD_DBG1, PMIC_DA_NI_VSRAM_MD_VSLEEP_SEL_MASK, PMIC_DA_NI_VSRAM_MD_VSLEEP_SEL_SHIFT, },
407 {PMIC_ALDO_ANA_CON4, PMIC_RG_VXO22_VOSEL_MASK, PMIC_RG_VXO22_VOSEL_SHIFT, },
408 {PMIC_DCXO_CW00, PMIC_XO_EXTBUF1_MODE_MASK, PMIC_XO_EXTBUF1_MODE_SHIFT, },
409 {PMIC_DCXO_CW00, PMIC_XO_EXTBUF1_EN_M_MASK, PMIC_XO_EXTBUF1_EN_M_SHIFT, },
410 {PMIC_DCXO_CW00, PMIC_XO_EXTBUF2_MODE_MASK, PMIC_XO_EXTBUF2_MODE_SHIFT, },
411 {PMIC_DCXO_CW00, PMIC_XO_EXTBUF2_EN_M_MASK, PMIC_XO_EXTBUF2_EN_M_SHIFT, },
412 {PMIC_DCXO_CW00, PMIC_XO_EXTBUF3_MODE_MASK, PMIC_XO_EXTBUF3_MODE_SHIFT, },
413 {PMIC_DCXO_CW00, PMIC_XO_EXTBUF3_EN_M_MASK, PMIC_XO_EXTBUF3_EN_M_SHIFT, },
414 {PMIC_DCXO_CW00, PMIC_XO_EXTBUF4_MODE_MASK, PMIC_XO_EXTBUF4_MODE_SHIFT, },
415 {PMIC_DCXO_CW00, PMIC_XO_EXTBUF4_EN_M_MASK, PMIC_XO_EXTBUF4_EN_M_SHIFT, },
416 {PMIC_DCXO_CW00, PMIC_XO_BB_LPM_EN_MASK, PMIC_XO_BB_LPM_EN_SHIFT, },
417 {PMIC_DCXO_CW00, PMIC_XO_ENBB_MAN_MASK, PMIC_XO_ENBB_MAN_SHIFT, },
418 {PMIC_DCXO_CW00, PMIC_XO_ENBB_EN_M_MASK, PMIC_XO_ENBB_EN_M_SHIFT, },
419 {PMIC_DCXO_CW00, PMIC_XO_CLKSEL_MAN_MASK, PMIC_XO_CLKSEL_MAN_SHIFT, },
420 {PMIC_DCXO_CW00_SET, PMIC_DCXO_CW00_SET_MASK, PMIC_DCXO_CW00_SET_SHIFT, },
421 {PMIC_DCXO_CW00_CLR, PMIC_DCXO_CW00_CLR_MASK, PMIC_DCXO_CW00_CLR_SHIFT, },
422 {PMIC_DCXO_CW02, PMIC_XO_EN32K_MAN_MASK, PMIC_XO_EN32K_MAN_SHIFT, },
423 {PMIC_DCXO_CW02, PMIC_XO_EN32K_M_MASK, PMIC_XO_EN32K_M_SHIFT, },
424 {PMIC_DCXO_CW02, PMIC_XO_XMODE_MAN_MASK, PMIC_XO_XMODE_MAN_SHIFT, },
425 {PMIC_DCXO_CW02, PMIC_XO_XMODE_M_MASK, PMIC_XO_XMODE_M_SHIFT, },
426 {PMIC_DCXO_CW02, PMIC_XO_STRUP_MODE_MASK, PMIC_XO_STRUP_MODE_SHIFT, },
427 {PMIC_DCXO_CW02, PMIC_XO_AAC_FPM_TIME_MASK, PMIC_XO_AAC_FPM_TIME_SHIFT, },
428 {PMIC_DCXO_CW02, PMIC_XO_AAC_MODE_LPM_MASK, PMIC_XO_AAC_MODE_LPM_SHIFT, },
429 {PMIC_DCXO_CW02, PMIC_XO_AAC_MODE_FPM_MASK, PMIC_XO_AAC_MODE_FPM_SHIFT, },
430 {PMIC_DCXO_CW02, PMIC_XO_EN26M_OFFSQ_EN_MASK, PMIC_XO_EN26M_OFFSQ_EN_SHIFT, },
431 {PMIC_DCXO_CW02, PMIC_XO_LDOCAL_EN_MASK, PMIC_XO_LDOCAL_EN_SHIFT, },
432 {PMIC_DCXO_CW02, PMIC_XO_CBANK_SYNC_DYN_MASK, PMIC_XO_CBANK_SYNC_DYN_SHIFT, },
433 {PMIC_DCXO_CW02, PMIC_XO_26MLP_MAN_EN_MASK, PMIC_XO_26MLP_MAN_EN_SHIFT, },
434 {PMIC_DCXO_CW02, PMIC_XO_BUFLDOK_EN_MASK, PMIC_XO_BUFLDOK_EN_SHIFT, },
435 {PMIC_DCXO_CW04, PMIC_XO_CDAC_FPM_MASK, PMIC_XO_CDAC_FPM_SHIFT, },
436 {PMIC_DCXO_CW04, PMIC_XO_CDAC_LPM_MASK, PMIC_XO_CDAC_LPM_SHIFT, },
437 {PMIC_DCXO_CW05, PMIC_XO_32KDIV_NFRAC_FPM_MASK, PMIC_XO_32KDIV_NFRAC_FPM_SHIFT, },
438 {PMIC_DCXO_CW05, PMIC_XO_COFST_FPM_MASK, PMIC_XO_COFST_FPM_SHIFT, },
439 {PMIC_DCXO_CW06, PMIC_XO_32KDIV_NFRAC_LPM_MASK, PMIC_XO_32KDIV_NFRAC_LPM_SHIFT, },
440 {PMIC_DCXO_CW06, PMIC_XO_COFST_LPM_MASK, PMIC_XO_COFST_LPM_SHIFT, },
441 {PMIC_DCXO_CW07, PMIC_XO_CORE_MAN_MASK, PMIC_XO_CORE_MAN_SHIFT, },
442 {PMIC_DCXO_CW07, PMIC_XO_CORE_EN_M_MASK, PMIC_XO_CORE_EN_M_SHIFT, },
443 {PMIC_DCXO_CW07, PMIC_XO_CORE_TURBO_EN_M_MASK, PMIC_XO_CORE_TURBO_EN_M_SHIFT, },
444 {PMIC_DCXO_CW07, PMIC_XO_CORE_AAC_EN_M_MASK, PMIC_XO_CORE_AAC_EN_M_SHIFT, },
445 {PMIC_DCXO_CW07, PMIC_XO_STARTUP_EN_M_MASK, PMIC_XO_STARTUP_EN_M_SHIFT, },
446 {PMIC_DCXO_CW07, PMIC_XO_CORE_VBFPM_EN_M_MASK, PMIC_XO_CORE_VBFPM_EN_M_SHIFT, },
447 {PMIC_DCXO_CW07, PMIC_XO_CORE_VBLPM_EN_M_MASK, PMIC_XO_CORE_VBLPM_EN_M_SHIFT, },
448 {PMIC_DCXO_CW07, PMIC_XO_LPMBIAS_EN_M_MASK, PMIC_XO_LPMBIAS_EN_M_SHIFT, },
449 {PMIC_DCXO_CW07, PMIC_XO_VTCGEN_EN_M_MASK, PMIC_XO_VTCGEN_EN_M_SHIFT, },
450 {PMIC_DCXO_CW07, PMIC_XO_IAAC_COMP_EN_M_MASK, PMIC_XO_IAAC_COMP_EN_M_SHIFT, },
451 {PMIC_DCXO_CW07, PMIC_XO_IFPM_COMP_EN_M_MASK, PMIC_XO_IFPM_COMP_EN_M_SHIFT, },
452 {PMIC_DCXO_CW07, PMIC_XO_ILPM_COMP_EN_M_MASK, PMIC_XO_ILPM_COMP_EN_M_SHIFT, },
453 {PMIC_DCXO_CW07, PMIC_XO_CORE_BYPCAS_FPM_MASK, PMIC_XO_CORE_BYPCAS_FPM_SHIFT, },
454 {PMIC_DCXO_CW07, PMIC_XO_CORE_GMX2_FPM_MASK, PMIC_XO_CORE_GMX2_FPM_SHIFT, },
455 {PMIC_DCXO_CW07, PMIC_XO_CORE_IDAC_FPM_MASK, PMIC_XO_CORE_IDAC_FPM_SHIFT, },
456 {PMIC_DCXO_CW09, PMIC_XO_CORE_BYPCAS_LPM_MASK, PMIC_XO_CORE_BYPCAS_LPM_SHIFT, },
457 {PMIC_DCXO_CW09, PMIC_XO_CORE_GMX2_LPM_MASK, PMIC_XO_CORE_GMX2_LPM_SHIFT, },
458 {PMIC_DCXO_CW09, PMIC_XO_CORE_IDAC_LPM_MASK, PMIC_XO_CORE_IDAC_LPM_SHIFT, },
459 {PMIC_DCXO_CW09, PMIC_XO_AAC_COMP_HV_LPM_MASK, PMIC_XO_AAC_COMP_HV_LPM_SHIFT, },
460 {PMIC_DCXO_CW09, PMIC_XO_AAC_VSEL_LPM_MASK, PMIC_XO_AAC_VSEL_LPM_SHIFT, },
461 {PMIC_DCXO_CW09, PMIC_XO_AAC_HV_LPM_MASK, PMIC_XO_AAC_HV_LPM_SHIFT, },
462 {PMIC_DCXO_CW09, PMIC_XO_AAC_IBIAS_LPM_MASK, PMIC_XO_AAC_IBIAS_LPM_SHIFT, },
463 {PMIC_DCXO_CW09, PMIC_XO_AAC_VOFST_LPM_MASK, PMIC_XO_AAC_VOFST_LPM_SHIFT, },
464 {PMIC_DCXO_CW09, PMIC_XO_AAC_FPM_SWEN_MASK, PMIC_XO_AAC_FPM_SWEN_SHIFT, },
465 {PMIC_DCXO_CW09, PMIC_XO_SWRST_MASK, PMIC_XO_SWRST_SHIFT, },
466 {PMIC_DCXO_CW18, PMIC_XO_STATIC_AUXOUT_SEL_MASK, PMIC_XO_STATIC_AUXOUT_SEL_SHIFT, },
467 {PMIC_DCXO_CW18, PMIC_XO_AUXOUT_SEL_MASK, PMIC_XO_AUXOUT_SEL_SHIFT, },
468 {PMIC_DCXO_CW19, PMIC_XO_STATIC_AUXOUT_MASK, PMIC_XO_STATIC_AUXOUT_SHIFT, },
469 {PMIC_AUXADC_ADC17, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
470 {PMIC_AUXADC_ADC17, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
471 {PMIC_AUXADC_RQST1_SET, PMIC_AUXADC_RQST1_SET_MASK, PMIC_AUXADC_RQST1_SET_SHIFT, },
472 {PMIC_AUXADC_RQST1_CLR, PMIC_AUXADC_RQST1_CLR_MASK, PMIC_AUXADC_RQST1_CLR_SHIFT, },
473};
474#if defined(DCL_PMIC_MODULE_CONTROL)
475DCL_HANDLE current_dcl_handle = 0;
476#endif
477
478//#define DCL_PMIC_PERMISSION_CONTROL
479#if defined(DCL_PMIC_PERMISSION_CONTROL)
480PMU_CTRL_MISC_SET_REGISTER_VALUE illegal_misc_set_register_value = {0};
481#endif
482
483//////////////////////////////////////////////////
484// WRITE APIs //
485//////////////////////////////////////////////////
486#if defined(DCL_PMIC_PERMISSION_CONTROL)
487DCL_BOOL dcl_pmic_check_permission(kal_uint16 offset)
488{
489 DCL_BOOL ret = DCL_FALSE;
490 kal_uint8 c = ((offset>>8) & 0xFF);
491
492 switch(c)
493 {
494 case 0x82:
495 {
496 //CLK : TOP_CLKSQ_SET (0x8226),TOP_CKPDN_CON0_CLR (0x8204),TOP_CLKSQ(0x8224)
497 if(offset == 0x8226 || offset == 0x8204 || offset == 0x8224)
498 ret=DCL_TRUE;
499 }
500 break;
501
502 case 0x90:
503 {
504 //LDO_DIG: 0x901A,0x901C, 0x9006, 0x9008
505 if(offset == 0x901A || offset == 0x901C || offset == 0x9006 || offset == 0x9008)
506 ret=DCL_TRUE;
507 }
508 break;
509
510 case 0x98:
511 {
512 //Audio Analog : 0x9800~0x9852
513 if(offset >= 0x9800 && offset <= 0x9852)
514 ret=DCL_TRUE;
515 }
516 break;
517
518 case 0x9A:
519 {
520 //Audio DRE : 0x9A00 ~0x9A0A
521 if(offset >= 0x9A00 && offset <= 0x9A0A)
522 ret=DCL_TRUE;
523 }
524 break;
525
526 case 0xE0:
527 case 0xE1:
528 {
529 //Audio digital : 0xE000 ~0xE138
530 if(offset >= 0xE000 && offset <= 0xE138)
531 ret=DCL_TRUE;
532 }
533 break;
534
535 default:
536 ret=DCL_FALSE;
537 break;
538 }
539 return ret;
540}
541#endif
542// Write Whole Bytes
543void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
544{
545 DCL_UINT32 idx, type;
546
547 kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
548
549 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
550 idx = pmic_access_duration_index[type];
551
552
553#if defined(DCL_PMIC_ACCESS_TIME_LOG)
554 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
555#endif
556 if(addr < PMIC_MAX_REG_NUM)
557 {
558 pmic_reg[addr] = val;
559 }
560
561 DrvPWRAP_WACS1(PMIC_WRAP_WRITE, addr, val, 0x00);
562
563#if defined(DCL_PMIC_ACCESS_TIME_LOG)
564 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
565 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
566 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
567#endif
568 kal_give_spinlock(dcl_pmic_access_spinlock);
569}
570
571// Write Whole Bytes
572void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val)
573{
574 DCL_UINT32 idx, type;
575
576 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
577 type = PMIC_LOG_TYPE_HRT_DOMAIN;
578 else
579 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
580
581 idx = pmic_access_duration_index[type];
582
583#if defined(DCL_PMIC_ACCESS_TIME_LOG)
584 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
585#endif
586
587
588 if(addr < PMIC_MAX_REG_NUM)
589 {
590 pmic_reg[addr] = val;
591 }
592
593 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
594 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
595 else
596 DrvPWRAP_WACS1(PMIC_WRAP_WRITE, addr, val, 0x00);
597
598#if defined(DCL_PMIC_ACCESS_TIME_LOG)
599 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
600 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
601 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
602#endif
603
604}
605
606// Write register field
607void dcl_pmic_field_write(PMIC6355_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
608{
609 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
610 DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
611 DCL_UINT32 idx = pmic_access_duration_index[type];
612
613 kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
614#if defined(DCL_PMIC_ACCESS_TIME_LOG)
615 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
616#endif
617
618 pmic_reg_log.command_flag = flag;
619 pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
620
621 pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
622 pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
623
624 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
625 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
626 else
627 DrvPWRAP_WACS1(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
628
629 pmic_reg_log.write_value = sel;
630 pmic_reg_log.address_offset = pTable[flag].offset;
631 pmic_reg_log.reg_mask = pTable[flag].mask;
632 pmic_reg_log.reg_shift = pTable[flag].shift;
633 pmic_reg_log.reg_addr = pTable[flag].offset;
634 pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
635
636#if defined(DCL_PMIC_ACCESS_TIME_LOG)
637 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
638 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
639#endif
640
641 kal_give_spinlock(dcl_pmic_access_spinlock);
642}
643
644// Write register field
645void dcl_pmic_field_write_nolock(PMIC6355_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
646{
647 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
648 DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
649 DCL_UINT32 idx = pmic_access_duration_index[type];
650
651#if defined(DCL_PMIC_ACCESS_TIME_LOG)
652 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
653#endif
654
655 pmic_reg_log.command_flag = flag;
656 pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
657
658 pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
659 pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
660
661 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
662 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
663 else
664 DrvPWRAP_WACS1(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
665
666 pmic_reg_log.write_value = sel;
667 pmic_reg_log.address_offset = pTable[flag].offset;
668 pmic_reg_log.reg_mask = pTable[flag].mask;
669 pmic_reg_log.reg_shift = pTable[flag].shift;
670 pmic_reg_log.reg_addr = pTable[flag].offset;
671 pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
672
673#if defined(DCL_PMIC_ACCESS_TIME_LOG)
674 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
675 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
676#endif
677
678}
679//////////////////////////////////////////////////
680// READ APIs //
681//////////////////////////////////////////////////
682
683// Read Whole Bytes
684DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr)
685{
686 DCL_UINT16 reg_temp;
687 DCL_UINT32 idx, type;
688
689 kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
690
691 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
692 idx = pmic_access_duration_index[type];
693
694#if defined(DCL_PMIC_ACCESS_TIME_LOG)
695 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
696#endif
697
698 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
699 DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
700 else
701 DrvPWRAP_WACS1(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
702
703 if(addr < PMIC_MAX_REG_NUM)
704 {
705 pmic_reg[addr] = reg_temp;
706 }
707
708#if defined(DCL_PMIC_ACCESS_TIME_LOG)
709 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
710 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
711#endif
712
713 kal_give_spinlock(dcl_pmic_access_spinlock);
714
715 return reg_temp;
716}
717
718// Read Whole Bytes
719DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr)
720{
721 DCL_UINT16 reg_temp;
722 DCL_UINT32 idx, type;
723
724 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
725 type = PMIC_LOG_TYPE_HRT_DOMAIN;
726 else
727 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
728
729 idx = pmic_access_duration_index[type];
730
731#if defined(DCL_PMIC_ACCESS_TIME_LOG)
732 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
733#endif
734
735 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
736 DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
737 else
738 DrvPWRAP_WACS1(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
739
740 if(addr < PMIC_MAX_REG_NUM)
741 {
742 pmic_reg[addr] = reg_temp;
743 }
744
745#if defined(DCL_PMIC_ACCESS_TIME_LOG)
746 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
747 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
748#endif
749
750 return reg_temp;
751}
752
753// Read register field
754DCL_UINT16 dcl_pmic_field_read(PMIC6355_FLAGS_LIST_ENUM flag)
755{
756 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
757 DCL_UINT16 reg_return = 0;
758 DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
759 DCL_UINT32 idx = pmic_access_duration_index[type];
760
761 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
762 type = PMIC_LOG_TYPE_HRT_DOMAIN;
763 else
764 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
765
766 idx = pmic_access_duration_index[type];
767
768
769#if defined(DCL_PMIC_ACCESS_TIME_LOG)
770 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
771#endif
772
773 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
774 DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
775 else
776 DrvPWRAP_WACS1(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
777
778 reg_return = ((pmic_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
779
780#if defined(DCL_PMIC_ACCESS_TIME_LOG)
781 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
782 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
783 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
784#endif
785
786 return reg_return;
787}
788
789// Exported for EM used
790void pmic_EM_reg_write(kal_uint16 reg, kal_uint16 val){
791 dcl_pmic_byte_write_nolock(reg, val);
792// dcl_pmic_byte_write(reg, val);
793}
794
795kal_uint16 pmic_EM_reg_read(kal_uint16 reg){
796 return dcl_pmic_byte_return_nolock(reg);
797}
798
799const DCL_UINT32 vpa_vosel[] =
800{
801 PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
802 PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
803 PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
804 PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
805 PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
806 PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
807 PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
808 PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
809 PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
810 PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
811 PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
812 PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
813 PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
814 PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
815 PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
816 PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
817};
818
819const DCL_UINT32 vsim1_vosel[] =
820{
821 PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_01_700000_V,
822 PMU_VOLT_01_800000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
823 PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V,
824 PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
825};
826
827const DCL_UINT32 vxo22_vosel[] =
828{
829 PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
830 PMU_VOLT_02_200000_V, PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
831};
832
833const DCL_UINT32 vmodem_vosel[] =
834{
835 PMU_VOLT_00_400000_V, PMU_VOLT_00_450000_V, PMU_VOLT_00_500000_V, PMU_VOLT_00_525000_V,
836 PMU_VOLT_00_550000_V, PMU_VOLT_00_568000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V,
837};
838
839const DCL_UINT32 vmd1_vosel[] =
840{
841 PMU_VOLT_00_400000_V, PMU_VOLT_INVALID, PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V,
842};
843
844const DCL_UINT32 vsram_vmd_vosel[] =
845{
846 PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V, PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
847 PMU_VOLT_INVALID, PMU_VOLT_INVALID,
848};
849
850PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
851{
852 {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
853 {ENC(LDO_BUCK_SET_VOLTAGE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
854 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
855 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
856 {ENC(LDO_BUCK_SET_VOLTAGE, VXO22), vxo22_vosel, NULL, GETARRNUM(vxo22_vosel) },
857 {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VMODEM), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
858 {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_MD), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
859};
860
861
862extern PMU_CONTROL_HANDLER pmu_control_handler;
863
864DCL_UINT16 pmu_parameter_size = 0;
865
866DCL_STATUS PMIC_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
867{
868 DCL_UINT16 regVal;
869 DCL_INT32 return_val = STATUS_FAIL;
870#if defined(DCL_PMIC_MODULE_CONTROL)
871 current_dcl_handle = handle;
872#endif
873 switch(cmd)
874 {
875 case LDO_BUCK_SET_EN: //Enable control in SW mode
876 {
877 PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
878
879 switch(pLdoBuckCtrl->mod)
880 {
881 case VMODEM:
882 {
883 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_EN, pLdoBuckCtrl->enable);
884 return_val = STATUS_OK;
885 }
886 break;
887
888 case VPA_SW:
889 {
890 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_EN, pLdoBuckCtrl->enable);
891 return_val = STATUS_OK;
892 }
893 break;
894
895 case VMIPI:
896 {
897 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_EN, pLdoBuckCtrl->enable);
898 return_val = STATUS_OK;
899 }
900 break;
901
902 case VTCXO24:
903 {
904 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VTCXO24_EN, pLdoBuckCtrl->enable);
905 return_val = STATUS_OK;
906 }
907 break;
908
909 case VSIM1:
910 {
911 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_EN, pLdoBuckCtrl->enable);
912 return_val = STATUS_OK;
913 }
914 break;
915
916 case VSIM2:
917 {
918 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_EN, pLdoBuckCtrl->enable);
919 return_val = STATUS_OK;
920 }
921 break;
922
923 case VFE28:
924 {
925 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_EN, pLdoBuckCtrl->enable);
926 return_val = STATUS_OK;
927 }
928 break;
929
930 case VRF18_1:
931 {
932 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_1_EN, pLdoBuckCtrl->enable);
933 return_val = STATUS_OK;
934 }
935 break;
936
937 case VRF18_2:
938 {
939 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_2_EN, pLdoBuckCtrl->enable);
940 return_val = STATUS_OK;
941 }
942 break;
943
944 case VRF12:
945 {
946 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_EN, pLdoBuckCtrl->enable);
947 return_val = STATUS_OK;
948 }
949 break;
950
951 case VSRAM_MD:
952 {
953 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_EN, pLdoBuckCtrl->enable);
954 return_val = STATUS_OK;
955 }
956 break;
957
958 case VS1:
959 {
960 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_EN, pLdoBuckCtrl->enable);
961 return_val = STATUS_OK;
962 }
963 break;
964
965 case VS2:
966 {
967 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_EN, pLdoBuckCtrl->enable);
968 return_val = STATUS_OK;
969 }
970 break;
971
972 default:
973 return_val = STATUS_UNSUPPORTED;
974 break;
975 }
976 }
977 break;
978
979 case LDO_BUCK_SET_LP_MODE_SET:
980 {
981 PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
982
983 switch(pLdoBuckCtrl->mod)
984 {
985 case VMODEM:
986 { // 1'b0:Normal mode, 1'b1:Low power mode
987 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_LP, pLdoBuckCtrl->enable);
988 return_val = STATUS_OK;
989 }
990 break;
991
992 case VSIM1:
993 { // 1'b0:Normal mode, 1'b1:Low power mode
994 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_LP, pLdoBuckCtrl->enable);
995 return_val = STATUS_OK;
996 }
997 break;
998
999 case VSIM2:
1000 { // 1'b0:Normal mode, 1'b1:Low power mode
1001 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_LP, pLdoBuckCtrl->enable);
1002 return_val = STATUS_OK;
1003 }
1004 break;
1005
1006 case VMIPI:
1007 { // 1'b0:Normal mode, 1'b1:Low power mode
1008 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_LP, pLdoBuckCtrl->enable);
1009 return_val = STATUS_OK;
1010 }
1011 break;
1012
1013 case VTCXO24:
1014 { // 1'b0:Normal mode, 1'b1:Low power mode
1015 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VTCXO24_LP, pLdoBuckCtrl->enable);
1016 return_val = STATUS_OK;
1017 }
1018 break;
1019
1020 case VFE28:
1021 { // 1'b0:Normal mode, 1'b1:Low power mode
1022 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_LP, pLdoBuckCtrl->enable);
1023 return_val = STATUS_OK;
1024 }
1025 break;
1026
1027 case VRF18_1:
1028 { // 1'b0:Normal mode, 1'b1:Low power mode
1029 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_1_LP, pLdoBuckCtrl->enable);
1030 return_val = STATUS_OK;
1031 }
1032 break;
1033
1034 case VRF18_2:
1035 { // 1'b0:Normal mode, 1'b1:Low power mode
1036 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_2_LP, pLdoBuckCtrl->enable);
1037 return_val = STATUS_OK;
1038 }
1039 break;
1040
1041 case VRF12:
1042 { // 1'b0:Normal mode, 1'b1:Low power mode
1043 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_LP, pLdoBuckCtrl->enable);
1044 return_val = STATUS_OK;
1045 }
1046 break;
1047
1048 case VSRAM_MD:
1049 { // 1'b0:Normal mode, 1'b1:Low power mode
1050 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_LP, pLdoBuckCtrl->enable);
1051 return_val = STATUS_OK;
1052 }
1053 break;
1054
1055 default:
1056 return_val = STATUS_UNSUPPORTED;
1057 break;
1058 }
1059 }
1060 break;
1061
1062 case LDO_BUCK_SET_OCFB_EN:
1063 {
1064 PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
1065
1066 switch(pLdoBuckCtrl->mod)
1067 {
1068 case VSIM1:
1069 {
1070 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
1071 return_val = STATUS_OK;
1072 }
1073 break;
1074
1075 case VSIM2:
1076 {
1077 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
1078 return_val = STATUS_OK;
1079 }
1080 break;
1081
1082 default:
1083 return_val = STATUS_UNSUPPORTED;
1084 break;
1085 }
1086 }
1087 break;
1088
1089 case LDO_BUCK_GET_VOSEL:
1090 {
1091 PMU_CTRL_LDO_BUCK_GET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVosel);
1092
1093 switch(pLdoBuckCtrl->mod)
1094 {
1095 case VMODEM:
1096 {
1097 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL);
1098 return_val = STATUS_OK;
1099 }
1100 break;
1101
1102 case VSRAM_MD:
1103 {
1104 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL);
1105 return_val = STATUS_OK;
1106 }
1107 break;
1108
1109 case VS1:
1110 {
1111 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL);
1112 return_val = STATUS_OK;
1113 }
1114 break;
1115
1116 case VS2:
1117 {
1118 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VS2_VOTER_VOSEL);
1119 return_val = STATUS_OK;
1120 }
1121 break;
1122
1123 default:
1124 return_val = STATUS_UNSUPPORTED;
1125 break;
1126 }
1127 }
1128 break;
1129
1130 case LDO_BUCK_SET_VOSEL:
1131 {
1132 PMU_CTRL_LDO_BUCK_SET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVosel);
1133
1134 switch(pLdoBuckCtrl->mod)
1135 {
1136 case VMODEM:
1137 {
1138 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL, pLdoBuckCtrl->code);
1139 return_val = STATUS_OK;
1140 }
1141 break;
1142
1143 case VSRAM_MD:
1144 {
1145 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL, pLdoBuckCtrl->code);
1146 return_val = STATUS_OK;
1147 }
1148 break;
1149
1150 case VS1:
1151 {
1152 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL, pLdoBuckCtrl->code);
1153 return_val = STATUS_OK;
1154 }
1155 break;
1156
1157 case VS2:
1158 {
1159 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_VOSEL, pLdoBuckCtrl->code);
1160 return_val = STATUS_OK;
1161 }
1162 break;
1163
1164 default:
1165 return_val = STATUS_UNSUPPORTED;
1166 break;
1167 }
1168 }
1169 break;
1170
1171 case LDO_BUCK_GET_VOSEL_SLEEP:
1172 {
1173 PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselSleep);
1174
1175 switch(pLdoBuckCtrl->mod)
1176 {
1177 case VMODEM:
1178 {
1179 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP);
1180 return_val = STATUS_OK;
1181 }
1182 break;
1183
1184 case VSRAM_MD:
1185 {
1186 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL_SLEEP);
1187 return_val = STATUS_OK;
1188 }
1189 break;
1190
1191 default:
1192 return_val = STATUS_UNSUPPORTED;
1193 break;
1194 }
1195 }
1196 break;
1197
1198 case LDO_BUCK_SET_VOSEL_SLEEP:
1199 {
1200 PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselSleep);
1201
1202 switch(pLdoBuckCtrl->mod)
1203 {
1204 case VMODEM:
1205 {
1206 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP, pLdoBuckCtrl->code);
1207 return_val = STATUS_OK;
1208 }
1209 break;
1210
1211 case VSRAM_MD:
1212 {
1213 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL_SLEEP, pLdoBuckCtrl->code);
1214 return_val = STATUS_OK;
1215 }
1216 break;
1217
1218 default:
1219 return_val = STATUS_UNSUPPORTED;
1220 break;
1221 }
1222 }
1223 break;
1224
1225 case LDO_BUCK_SET_MODESET:
1226 {
1227 PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
1228
1229 switch(pLdoBuckCtrl->mod)
1230 {
1231 case VPA_SW:
1232 {
1233 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_VPA_MODESET, pLdoBuckCtrl->mode);
1234 return_val = STATUS_OK;
1235 }
1236 break;
1237
1238 default:
1239 return_val = STATUS_UNSUPPORTED;
1240 break;
1241 }
1242 }
1243 break;
1244
1245 case LDO_BUCK_SET_OP_EN:
1246 {
1247 PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
1248
1249 kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
1250 (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
1251
1252 switch(pLdoBuckCtrl->mod)
1253 {
1254 case VMODEM:
1255 {
1256 pmic_EM_reg_write(PMIC_BUCK_VMODEM_OP_EN_SET, mode);
1257 return_val = STATUS_OK;
1258 }
1259 break;
1260
1261 case VSIM1:
1262 {
1263 pmic_EM_reg_write(PMIC_LDO_VSIM1_OP_EN_SET, mode);
1264 return_val = STATUS_OK;
1265 }
1266 break;
1267
1268 case VSIM2:
1269 {
1270 pmic_EM_reg_write(PMIC_LDO_VSIM2_OP_EN_SET, mode);
1271 return_val = STATUS_OK;
1272 }
1273 break;
1274
1275 case VMIPI:
1276 {
1277 pmic_EM_reg_write(PMIC_LDO_VMIPI_OP_EN_SET, mode);
1278 return_val = STATUS_OK;
1279 }
1280 break;
1281
1282 case VTCXO24:
1283 {
1284 pmic_EM_reg_write(PMIC_LDO_VTCXO24_OP_EN_SET, mode);
1285 return_val = STATUS_OK;
1286 }
1287 break;
1288
1289 case VFE28:
1290 {
1291 pmic_EM_reg_write(PMIC_LDO_VFE28_OP_EN_SET, mode);
1292 return_val = STATUS_OK;
1293 }
1294 break;
1295
1296 case VRF18_1:
1297 {
1298 pmic_EM_reg_write(PMIC_LDO_VRF18_1_OP_EN_SET, mode);
1299 return_val = STATUS_OK;
1300 }
1301 break;
1302
1303 case VRF18_2:
1304 {
1305 pmic_EM_reg_write(PMIC_LDO_VRF18_2_OP_EN_SET, mode);
1306 return_val = STATUS_OK;
1307 }
1308 break;
1309
1310 case VRF12:
1311 {
1312 pmic_EM_reg_write(PMIC_LDO_VRF12_OP_EN_SET, mode);
1313 return_val = STATUS_OK;
1314 }
1315 break;
1316
1317 case VSRAM_MD:
1318 {
1319 pmic_EM_reg_write(PMIC_LDO_VSRAM_MD_OP_EN, mode);
1320 return_val = STATUS_OK;
1321 }
1322 break;
1323
1324 default:
1325 return_val = STATUS_UNSUPPORTED;
1326 break;
1327 }
1328 }
1329 break;
1330
1331 case LDO_BUCK_CLR_OP_EN:
1332 {
1333 PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
1334
1335 kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
1336 (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
1337
1338 switch(pLdoBuckCtrl->mod)
1339 {
1340 case VMODEM:
1341 {
1342 pmic_EM_reg_write(PMIC_BUCK_VMODEM_OP_EN_CLR, mode);
1343 return_val = STATUS_OK;
1344 }
1345 break;
1346
1347 case VSIM1:
1348 {
1349 pmic_EM_reg_write(PMIC_LDO_VSIM1_OP_EN_CLR, mode);
1350 return_val = STATUS_OK;
1351 }
1352 break;
1353
1354 case VSIM2:
1355 {
1356 pmic_EM_reg_write(PMIC_LDO_VSIM2_OP_EN_CLR, mode);
1357 return_val = STATUS_OK;
1358 }
1359 break;
1360
1361 case VMIPI:
1362 {
1363 pmic_EM_reg_write(PMIC_LDO_VMIPI_OP_EN_CLR, mode);
1364 return_val = STATUS_OK;
1365 }
1366 break;
1367
1368 case VTCXO24:
1369 {
1370 pmic_EM_reg_write(PMIC_LDO_VTCXO24_OP_EN_CLR, mode);
1371 return_val = STATUS_OK;
1372 }
1373 break;
1374
1375 case VFE28:
1376 {
1377 pmic_EM_reg_write(PMIC_LDO_VFE28_OP_EN_CLR, mode);
1378 return_val = STATUS_OK;
1379 }
1380 break;
1381
1382 case VRF18_1:
1383 {
1384 pmic_EM_reg_write(PMIC_LDO_VRF18_1_OP_EN_CLR, mode);
1385 return_val = STATUS_OK;
1386 }
1387 break;
1388
1389 case VRF18_2:
1390 {
1391 pmic_EM_reg_write(PMIC_LDO_VRF18_2_OP_EN_CLR, mode);
1392 return_val = STATUS_OK;
1393 }
1394 break;
1395
1396 case VRF12:
1397 {
1398 pmic_EM_reg_write(PMIC_LDO_VRF12_OP_EN_CLR, mode);
1399 return_val = STATUS_OK;
1400 }
1401 break;
1402
1403 case VSRAM_MD:
1404 {
1405 pmic_EM_reg_write(PMIC_LDO_VSRAM_MD_OP_EN, mode);
1406 return_val = STATUS_OK;
1407 }
1408 break;
1409
1410 default:
1411 return_val = STATUS_UNSUPPORTED;
1412 break;
1413 }
1414 }
1415 break;
1416
1417 case LDO_BUCK_SET_HW_OP_CFG:
1418 {
1419 PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckSetHwOp);
1420
1421 kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
1422 (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
1423 (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
1424
1425 switch(pLdoBuckCtrl->mod)
1426 {
1427 case VMODEM:
1428 {
1429 pmic_EM_reg_write(PMIC_BUCK_VMODEM_OP_CFG_SET, value);
1430 return_val = STATUS_OK;
1431 }
1432 break;
1433
1434 case VSIM1:
1435 {
1436 pmic_EM_reg_write(PMIC_LDO_VSIM1_OP_CFG_SET, value);
1437 return_val = STATUS_OK;
1438 }
1439 break;
1440
1441 case VSIM2:
1442 {
1443 pmic_EM_reg_write(PMIC_LDO_VSIM2_OP_CFG_SET, value);
1444 return_val = STATUS_OK;
1445 }
1446 break;
1447
1448 case VMIPI:
1449 {
1450 pmic_EM_reg_write(PMIC_LDO_VMIPI_OP_CFG_SET, value);
1451 return_val = STATUS_OK;
1452 }
1453 break;
1454
1455 case VTCXO24:
1456 {
1457 pmic_EM_reg_write(PMIC_LDO_VTCXO24_OP_CFG_SET, value);
1458 return_val = STATUS_OK;
1459 }
1460 break;
1461
1462 case VFE28:
1463 {
1464 pmic_EM_reg_write(PMIC_LDO_VFE28_OP_CFG_SET, value);
1465 return_val = STATUS_OK;
1466 }
1467 break;
1468
1469 case VRF18_1:
1470 {
1471 pmic_EM_reg_write(PMIC_LDO_VRF18_1_OP_CFG_SET, value);
1472 return_val = STATUS_OK;
1473 }
1474 break;
1475
1476 case VRF18_2:
1477 {
1478 pmic_EM_reg_write(PMIC_LDO_VRF18_2_OP_CFG_SET, value);
1479 return_val = STATUS_OK;
1480 }
1481 break;
1482
1483 case VRF12:
1484 {
1485 pmic_EM_reg_write(PMIC_LDO_VRF12_OP_CFG_SET, value);
1486 return_val = STATUS_OK;
1487 }
1488 break;
1489
1490 case VSRAM_MD:
1491 {
1492 pmic_EM_reg_write(PMIC_LDO_VSRAM_MD_OP_CFG_SET, value);
1493 return_val = STATUS_OK;
1494 }
1495 break;
1496
1497 default:
1498 return_val = STATUS_UNSUPPORTED;
1499 break;
1500 }
1501 }
1502 break;
1503
1504 case LDO_BUCK_CLR_HW_OP_CFG:
1505 {
1506 PMU_CTRL_LDO_BUCK_CLR_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckClrHwOp);
1507
1508 kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
1509 (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
1510 (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
1511
1512 switch(pLdoBuckCtrl->mod)
1513 {
1514 case VMODEM:
1515 {
1516 pmic_EM_reg_write(PMIC_BUCK_VMODEM_OP_CFG_CLR, value);
1517 return_val = STATUS_OK;
1518 }
1519 break;
1520
1521 case VSIM1:
1522 {
1523 pmic_EM_reg_write(PMIC_LDO_VSIM1_OP_CFG_CLR, value);
1524 return_val = STATUS_OK;
1525 }
1526 break;
1527
1528 case VSIM2:
1529 {
1530 pmic_EM_reg_write(PMIC_LDO_VSIM2_OP_CFG_CLR, value);
1531 return_val = STATUS_OK;
1532 }
1533 break;
1534
1535 case VMIPI:
1536 {
1537 pmic_EM_reg_write(PMIC_LDO_VMIPI_OP_CFG_CLR, value);
1538 return_val = STATUS_OK;
1539 }
1540 break;
1541
1542 case VTCXO24:
1543 {
1544 pmic_EM_reg_write(PMIC_LDO_VTCXO24_OP_CFG_CLR, value);
1545 return_val = STATUS_OK;
1546 }
1547 break;
1548
1549 case VFE28:
1550 {
1551 pmic_EM_reg_write(PMIC_LDO_VFE28_OP_CFG_CLR, value);
1552 return_val = STATUS_OK;
1553 }
1554 break;
1555
1556 case VRF18_1:
1557 {
1558 pmic_EM_reg_write(PMIC_LDO_VRF18_1_OP_CFG_CLR, value);
1559 return_val = STATUS_OK;
1560 }
1561 break;
1562
1563 case VRF18_2:
1564 {
1565 pmic_EM_reg_write(PMIC_LDO_VRF18_2_OP_CFG_CLR, value);
1566 return_val = STATUS_OK;
1567 }
1568 break;
1569
1570 case VRF12:
1571 {
1572 pmic_EM_reg_write(PMIC_LDO_VRF12_OP_CFG_CLR, value);
1573 return_val = STATUS_OK;
1574 }
1575 break;
1576
1577 case VSRAM_MD:
1578 {
1579 pmic_EM_reg_write(PMIC_LDO_VSRAM_MD_OP_CFG_CLR, value);
1580 return_val = STATUS_OK;
1581 }
1582 break;
1583
1584 default:
1585 return_val = STATUS_UNSUPPORTED;
1586 break;
1587 }
1588 }
1589 break;
1590
1591 case LDO_BUCK_SET_GO_ON_OP:
1592 {
1593 PMU_CTRL_LDO_BUCK_SET_GO_ON_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoOnOp);
1594
1595 switch(pLdoBuckCtrl->mod)
1596 {
1597 case VMODEM:
1598 {
1599 if(pLdoBuckCtrl->mode == Prefer_OFF)
1600 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1601 else
1602 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1603 return_val = STATUS_OK;
1604 }
1605 break;
1606
1607 case VSIM1:
1608 {
1609 if(pLdoBuckCtrl->mode == Prefer_OFF)
1610 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1611 else
1612 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1613 return_val = STATUS_OK;
1614 }
1615 break;
1616
1617 case VSIM2:
1618 {
1619 if(pLdoBuckCtrl->mode == Prefer_OFF)
1620 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1621 else
1622 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1623 return_val = STATUS_OK;
1624 }
1625 break;
1626
1627 case VMIPI:
1628 {
1629 if(pLdoBuckCtrl->mode == Prefer_OFF)
1630 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1631 else
1632 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1633 return_val = STATUS_OK;
1634 }
1635 break;
1636
1637 case VTCXO24:
1638 {
1639 if(pLdoBuckCtrl->mode == Prefer_OFF)
1640 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VTCXO24_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1641 else
1642 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VTCXO24_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1643 return_val = STATUS_OK;
1644 }
1645 break;
1646
1647 case VFE28:
1648 {
1649 if(pLdoBuckCtrl->mode == Prefer_OFF)
1650 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1651 else
1652 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1653 return_val = STATUS_OK;
1654 }
1655 break;
1656
1657 case VRF18_1:
1658 {
1659 if(pLdoBuckCtrl->mode == Prefer_OFF)
1660 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_1_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1661 else
1662 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_1_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1663 return_val = STATUS_OK;
1664 }
1665 break;
1666
1667 case VRF18_2:
1668 {
1669 if(pLdoBuckCtrl->mode == Prefer_OFF)
1670 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_2_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1671 else
1672 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_2_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1673 return_val = STATUS_OK;
1674 }
1675 break;
1676
1677 case VRF12:
1678 {
1679 if(pLdoBuckCtrl->mode == Prefer_OFF)
1680 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1681 else
1682 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1683 return_val = STATUS_OK;
1684 }
1685 break;
1686
1687 case VSRAM_MD:
1688 {
1689 if(pLdoBuckCtrl->mode == Prefer_OFF)
1690 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1691 else
1692 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1693 return_val = STATUS_OK;
1694 }
1695 break;
1696
1697 default:
1698 return_val = STATUS_UNSUPPORTED;
1699 break;
1700 }
1701 }
1702 break;
1703
1704 case LDO_BUCK_SET_GO_LP_OP:
1705 {
1706 PMU_CTRL_LDO_BUCK_SET_GO_LP_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoLpOp);
1707
1708 switch(pLdoBuckCtrl->mod)
1709 {
1710 case VMODEM:
1711 {
1712 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1713 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1714 else
1715 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1716 return_val = STATUS_OK;
1717 }
1718 break;
1719
1720 case VSIM1:
1721 {
1722 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1723 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1724 else
1725 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1726 return_val = STATUS_OK;
1727 }
1728 break;
1729
1730 case VSIM2:
1731 {
1732 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1733 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1734 else
1735 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1736 return_val = STATUS_OK;
1737 }
1738 break;
1739
1740 case VMIPI:
1741 {
1742 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1743 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1744 else
1745 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1746 return_val = STATUS_OK;
1747 }
1748 break;
1749
1750 case VTCXO24:
1751 {
1752 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1753 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VTCXO24_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1754 else
1755 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VTCXO24_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1756 return_val = STATUS_OK;
1757 }
1758 break;
1759
1760 case VFE28:
1761 {
1762 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1763 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1764 else
1765 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1766 return_val = STATUS_OK;
1767 }
1768 break;
1769
1770 case VRF18_1:
1771 {
1772 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1773 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_1_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1774 else
1775 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_1_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1776 return_val = STATUS_OK;
1777 }
1778 break;
1779
1780 case VRF18_2:
1781 {
1782 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1783 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_2_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1784 else
1785 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_2_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1786 return_val = STATUS_OK;
1787 }
1788 break;
1789
1790 case VRF12:
1791 {
1792 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1793 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1794 else
1795 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1796 return_val = STATUS_OK;
1797 }
1798 break;
1799
1800 case VSRAM_MD:
1801 {
1802 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1803 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_OP_CFG_SET,1 << GO_LP_OP_SHIFT);
1804 else
1805 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1806 return_val = STATUS_OK;
1807 }
1808 break;
1809
1810 default:
1811 return_val = STATUS_UNSUPPORTED;
1812 break;
1813 }
1814 }
1815 break;
1816
1817
1818 case LDO_BUCK_SET_VOLTAGE:
1819 {
1820 PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
1821 regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
1822
1823 switch(pLdoBuckCtrl->mod)
1824 {
1825 case VSIM1:
1826 {
1827 dcl_pmic_field_write(PMIC_ENUM_RG_VSIM1_VOSEL, regVal);
1828 return_val = STATUS_OK;
1829 }
1830 break;
1831
1832 case VSIM2:
1833 {
1834 dcl_pmic_field_write(PMIC_ENUM_RG_VSIM2_VOSEL, regVal);
1835 return_val = STATUS_OK;
1836 }
1837 break;
1838
1839 case VPA_SW:
1840 {
1841 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_VOSEL, regVal);
1842 return_val = STATUS_OK;
1843 }
1844 break;
1845
1846 case VXO22:
1847 {
1848 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_VXO22_VOSEL, regVal);
1849 return_val = STATUS_OK;
1850 }
1851 break;
1852
1853 default:
1854 return_val = STATUS_UNSUPPORTED;
1855 break;
1856 }
1857 }
1858 break;
1859
1860
1861 case LDO_BUCK_GET_VOLTAGE:
1862 {
1863 PMU_CTRL_LDO_BUCK_GET_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckGetVolt);
1864
1865 switch(pLdoBuckCtrl->mod)
1866 {
1867 case VMODEM:
1868 {
1869 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VMODEM_VOSEL);
1870 return_val = STATUS_OK;
1871 }
1872 break;
1873
1874 case VSRAM_MD:
1875 {
1876 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_QI_VSRAM_MD_VOSEL);
1877 return_val = STATUS_OK;
1878 }
1879 break;
1880
1881 default:
1882 return_val = STATUS_UNSUPPORTED;
1883 break;
1884 }
1885 }
1886 break;
1887
1888 case LDO_BUCK_SET_SLEEP_VOLTAGE:
1889 {
1890 PMU_CTRL_LDO_BUCK_SET_SLEEP_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckSetSleepVoltage);
1891 regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->sleepVoltage);
1892
1893 switch(pLdoBuckCtrl->mod)
1894 {
1895 case VMODEM:
1896 {
1897 dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_SLEEP_VOLTAGE, regVal);
1898 return_val = STATUS_OK;
1899 }
1900 break;
1901
1902 case VSRAM_MD:
1903 {
1904 dcl_pmic_field_write(PMIC_ENUM_RG_VSRAM_MD_SLEEP_VOLTAGE, regVal);
1905 return_val = STATUS_OK;
1906 }
1907 break;
1908
1909 default:
1910 return_val = STATUS_UNSUPPORTED;
1911 break;
1912 }
1913 }
1914 break;
1915
1916 /*
1917 case VPA_SET_EN:
1918 {
1919 PMU_CTRL_VPA_SET_EN *pVpaSetEn = &(data->rPMUVpaSetEn);
1920 dcl_pmic6332_field_write(MT6332_VPA_EN, pVpaSetEn->enable);
1921 return_val = STATUS_OK;
1922 }
1923 break;
1924 */
1925
1926 case VPA_GET_VOLTAGE_LIST:
1927 {
1928 PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
1929 pVpaCtrl->pVoltageList = vpa_vosel;
1930 pVpaCtrl->number = GETARRNUM(vpa_vosel);
1931 return_val = STATUS_OK;
1932 }
1933 break;
1934
1935 case ADC_SET_RQST:
1936 {
1937 PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
1938 if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
1939 {
1940 ASSERT(0);
1941 }
1942 // Enable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
1943 pmic_EM_reg_write(PMIC_TOP_CLKSQ_SET, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
1944 pmic_EM_reg_write(PMIC_AUXADC_RQST1_CLR, (pAdcCtrl->enable << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
1945 pmic_EM_reg_write(PMIC_AUXADC_RQST1_SET, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
1946 AUXADC_Status = AUXADC_READ_REQUEST;
1947 return_val = STATUS_OK;
1948 }
1949 break;
1950
1951
1952 case ADC_GET_RDY_MD:
1953 {
1954 PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
1955 pAdcCtrl->status = (DCL_BOOL)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_RDY_CH7_BY_MD);
1956 if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
1957 {
1958 ASSERT(0);
1959 }
1960
1961 if(pAdcCtrl->status == DCL_TRUE)
1962 {
1963 AUXADC_Status = AUXADC_READ_READY;
1964 }
1965 else
1966 {
1967 AUXADC_Status = AUXADC_READ_BUSY;
1968 }
1969
1970 return_val = STATUS_OK;
1971 }
1972 break;
1973
1974 case ADC_GET_OUT_MD:
1975 {
1976 PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
1977 if(AUXADC_Status != AUXADC_READ_READY)
1978 {
1979 ASSERT(0);
1980 }
1981 pAdcCtrl->data = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_OUT_CH7_BY_MD);
1982 AUXADC_Status = AUXADC_READ_DATA;
1983 pmic_EM_reg_write(PMIC_AUXADC_RQST1_CLR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
1984 // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
1985 pmic_EM_reg_write(PMIC_TOP_CLKSQ_CLR, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
1986
1987 return_val = STATUS_OK;
1988 }
1989 break;
1990
1991 case TOP_SET_SRCLKEN_IN_EN:
1992 {
1993 PMU_CTRL_TOP_SET_SRCLKEN_IN_EN *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInEn);
1994
1995 switch(pTopSrclkenCtrl->mod)
1996 {
1997 case PMIC_SRCLKEN_IN0:
1998 {
1999 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_EN, pTopSrclkenCtrl->mode);
2000 return_val = STATUS_OK;
2001 }
2002 break;
2003
2004 case PMIC_SRCLKEN_IN1:
2005 {
2006 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_EN, pTopSrclkenCtrl->mode);
2007 return_val = STATUS_OK;
2008 }
2009 break;
2010
2011 default:
2012 return_val = STATUS_UNSUPPORTED;
2013 break;
2014 }
2015 }
2016 break;
2017
2018 case TOP_SET_SRCLKEN_IN_MODE:
2019 {
2020 PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInMode);
2021
2022 switch(pTopSrclkenCtrl->mod)
2023 {
2024 case PMIC_SRCLKEN_IN0:
2025 {
2026 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_HW_MODE, pTopSrclkenCtrl->mode);
2027 return_val = STATUS_OK;
2028 }
2029 break;
2030
2031 case PMIC_SRCLKEN_IN1:
2032 {
2033 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_HW_MODE, pTopSrclkenCtrl->mode);
2034 return_val = STATUS_OK;
2035 }
2036 break;
2037
2038 default:
2039 return_val = STATUS_UNSUPPORTED;
2040 break;
2041 }
2042 }
2043 break;
2044
2045 case DCXO_SET_REGISTER_VALUE:
2046 {
2047 PMU_CTRL_DCXO_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUDcxoSetRegisterValue);
2048
2049 pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
2050 return_val = STATUS_OK;
2051
2052#if 0
2053/* under construction !*/
2054/* under construction !*/
2055/* under construction !*/
2056/* under construction !*/
2057/* under construction !*/
2058/* under construction !*/
2059/* under construction !*/
2060/* under construction !*/
2061/* under construction !*/
2062#endif
2063 }
2064 break;
2065
2066 case DCXO_GET_REGISTER_VALUE:
2067 {
2068 PMU_CTRL_DCXO_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUDcxoGetRegisterValue);
2069 pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
2070 return_val = STATUS_OK;
2071 }
2072 break;
2073
2074 case MISC_SET_REGISTER_VALUE:
2075 {
2076 PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
2077#if defined(DCL_PMIC_PERMISSION_CONTROL)
2078 if(dcl_pmic_check_permission(pChrCtrl->offset)== DCL_TRUE)
2079#endif
2080 {
2081 pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
2082 return_val = STATUS_OK;
2083 }
2084#if defined(DCL_PMIC_PERMISSION_CONTROL)
2085 else
2086 {
2087 illegal_misc_set_register_value.offset = pChrCtrl->offset;
2088 illegal_misc_set_register_value.value = pChrCtrl->value;
2089 ASSERT(0);
2090 }
2091#endif
2092 }
2093 break;
2094
2095 case MISC_GET_REGISTER_VALUE:
2096 {
2097 PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
2098 pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
2099 return_val = STATUS_OK;
2100 }
2101 break;
2102
2103 default:
2104 return_val = STATUS_UNSUPPORTED;
2105 break;
2106 }
2107#if defined(DCL_PMIC_MODULE_CONTROL)
2108 current_dcl_handle = 0;
2109#endif
2110 return return_val;
2111
2112}
2113
2114extern void dcl_pmic_modem_only_init(void);
2115extern void PMIC_Read_All(void);
2116#if defined(PMIC_UNIT_TEST)
2117extern void PMIC_Read_All(void);
2118extern void PMIC_Unit_Test(void);
2119#endif
2120DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
2121{
2122 return dcl_pmic_byte_return(pmic_addr);
2123}
2124
2125void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
2126{
2127 dcl_pmic_byte_write(pmic_addr, value);
2128}
2129
2130void dcl_pmic_init(void){
2131 extern void pmic_wrap_dump_init(void);
2132 pmu_control_handler = PMIC_control_handler;
2133 pmu_parameter_size = GETARRNUM(pmu_parameter_table);
2134
2135 pmic_wrap_dump_init();
2136
2137 dcl_pmic_access_spinlock = kal_create_spinlock("pmic access");
2138 dcl_pmic_control_spinlock = kal_create_spinlock("pmic control");
2139
2140#if !defined(__SMART_PHONE_MODEM__)
2141 DrvPWRAP_Init();
2142#endif
2143 pmic_hw_version = dcl_pmic_byte_return(PMIC_HWCID);
2144 if (pmic_hw_version == 0x0)
2145 ASSERT(0);
2146
2147 PMIC_Read_All();
2148
2149#if !defined(__SMART_PHONE_MODEM__)
2150
2151/*
2152 if(DrvPWRAP_CheckCIPHER() == 1)
2153 dcl_pmic6355_modem_only_init();
2154 else
2155*/
2156 dcl_pmic_modem_only_init();
2157
2158#endif
2159
2160#if defined(PMIC_UNIT_TEST)
2161 PMIC_Read_All();
2162 PMIC_Unit_Test();
2163 PMIC_Read_All();
2164#endif
2165 pmic_init_done = DCL_TRUE;
2166
2167}
2168
2169void PMIC_Read_All(void)
2170{
2171 volatile kal_uint32 i,j;
2172 j=0;
2173 for (i = 0; i < PMIC_MAX_REG_NUM; i += 2){
2174 pmic_reg[i] = dcl_pmic_byte_return(i);
2175 while(j!=0x200){j++;}
2176 j=0;
2177 }
2178}
2179#if defined(PMIC_UNIT_TEST)
2180void PMIC_Unit_Test(void)
2181{
2182 {
2183 DCL_HANDLE handle;
2184 PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
2185 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2186 val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
2187 val.mod = VMIPI;
2188 DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
2189 DclPMU_Close(handle);
2190 }
2191
2192 {
2193 DCL_HANDLE handle;
2194 PMU_CTRL_LDO_BUCK_SET_EN val;
2195 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2196 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2197 val.mod = VMIPI;
2198 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2199 DclPMU_Close(handle);
2200 }
2201
2202 {
2203 DCL_HANDLE handle;
2204 PMU_CTRL_LDO_BUCK_SET_EN val;
2205 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2206 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2207 val.mod = VPA_SW;
2208 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2209 DclPMU_Close(handle);
2210 }
2211
2212 {
2213 DCL_HANDLE handle;
2214 PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
2215 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2216 val.mod=VPA_SW;
2217 val.voltage = PMU_VOLT_01_800000_V;
2218 /* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
2219 PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
2220 PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
2221 PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
2222 PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
2223 PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
2224 PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
2225 PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
2226 PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
2227 PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
2228 PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
2229 PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
2230 PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
2231 PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
2232 PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
2233 PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
2234 DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
2235 DclPMU_Close(handle);
2236 }
2237
2238 {
2239 DCL_HANDLE handle;
2240 PMU_CTRL_LDO_BUCK_SET_MODESET val;
2241 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2242 val.mod = VPA_SW;
2243 val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
2244 DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
2245 DclPMU_Close(handle);
2246 }
2247 {
2248 DCL_HANDLE handle;
2249 PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
2250 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2251 val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
2252 val.mod = VRF1;
2253 DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
2254 DclPMU_Close(handle);
2255 }
2256
2257 {
2258 DCL_HANDLE handle;
2259 PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
2260 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2261 val.sel = SRCLKEN_IN1_SEL;
2262 /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
2263 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
2264 val.mod = VRF1;
2265 DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
2266 DclPMU_Close(handle);
2267 }
2268
2269 {
2270 DCL_HANDLE handle;
2271 PMU_CTRL_LDO_BUCK_SET_MODESET val;
2272 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2273 val.mod = VRF1;
2274 val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
2275 DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
2276 DclPMU_Close(handle);
2277 }
2278
2279 {
2280 DCL_HANDLE handle;
2281 PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
2282 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2283 val.regval = 0x7; // (0x0~0xF)
2284 DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
2285 DclPMU_Close(handle);
2286 }
2287
2288 {
2289 DCL_HANDLE handle;
2290 PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
2291 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2292 val.regval = 0x7; // (0x0~0xF)
2293 DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
2294 DclPMU_Close(handle);
2295 }
2296
2297 {
2298 DCL_HANDLE handle;
2299 PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
2300 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2301 // val.regval will be your request value ( no need do any shift)
2302 DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
2303 DclPMU_Close(handle);
2304 }
2305
2306 {
2307 DCL_HANDLE handle;
2308 PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
2309 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2310 val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
2311 val.mod = VRF2;
2312 DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
2313 DclPMU_Close(handle);
2314 }
2315
2316 {
2317 DCL_HANDLE handle;
2318 PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
2319 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2320 val.sel = SRCLKEN_IN1_SEL;
2321 /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
2322 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
2323 val.mod = VRF2;
2324 DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
2325 DclPMU_Close(handle);
2326 }
2327
2328 {
2329 DCL_HANDLE handle;
2330 PMU_CTRL_LDO_BUCK_SET_EN val;
2331 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2332 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2333 val.mod = VRF2;
2334 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2335 DclPMU_Close(handle);
2336 }
2337
2338 {
2339 DCL_HANDLE handle;
2340 PMU_CTRL_LDO_BUCK_SET_MODESET val;
2341 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2342 val.mod = VRF1;
2343 val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
2344 DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
2345 DclPMU_Close(handle);
2346 }
2347
2348 {
2349 DCL_HANDLE handle;
2350 PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
2351 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2352 val.sel = SRCLKEN_IN1_SEL;
2353 /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
2354 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
2355 val.mod = VMIPI;
2356 DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
2357 DclPMU_Close(handle);
2358 }
2359
2360 {
2361 DCL_HANDLE handle;
2362 PMU_CTRL_LDO_BUCK_SET_EN val;
2363 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2364 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2365 val.mod = VSIM1;
2366 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2367 DclPMU_Close(handle);
2368 }
2369
2370 {
2371 DCL_HANDLE handle;
2372 PMU_CTRL_LDO_BUCK_SET_EN val;
2373 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2374 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2375 val.mod = VSIM2;
2376 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2377 DclPMU_Close(handle);
2378 }
2379
2380 {
2381 DCL_HANDLE handle;
2382 PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
2383 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2384 val.mod=VSIM1;
2385 val.voltage = PMU_VOLT_01_800000_V;
2386 /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
2387 DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
2388 DclPMU_Close(handle);
2389 }
2390
2391 {
2392 DCL_HANDLE handle;
2393 PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
2394 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2395 val.mod=VSIM2;
2396 val.voltage = PMU_VOLT_01_800000_V;
2397 /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
2398 DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
2399 DclPMU_Close(handle);
2400 }
2401}
2402#endif // End of #if defined(PMIC_UNIT_TEST)
2403
2404#endif // End of #if defined(PMIC_6355_REG_API)
2405