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192.168.1.100 / T800_MD / b0f5b85a5b9d69cbfa1dd990d559a4a9c7d8f2a6 / . / mcu / driver / devdrv / pmic / src / dcl_pmic6359.c
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2018
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
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18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * dcl_pmic6359.c
41 *
42 * Project:
43 * --------
44 * MOLY Software
45 *
46 * Description:
47 * ------------
48 * This file is for PMIC 6359
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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195 *------------------------------------------------------------------------------
196 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
197 *============================================================================
198 ****************************************************************************/
199
200#if defined(FPGA_CTP)
201#include <common.h>
202#endif
203
204#include "reg_base.h"
205#include "drv_comm.h"
206#include "init.h"
207#include "dcl.h"
208#include "dcl_pmu_sw.h"
209#include "pmic_wrap.h"
210#include "kal_public_api.h"
211#include "us_timer.h"
212#include "event_info_utility.h" // for MODEM_WARNING_MESSAGE
213
214#if defined(PMIC_6359_REG_API)
215
216// Start PMIC_UNIT_TEST
217//#define PMIC_UNIT_TEST
218// ARM Section RW/RO/ZI Use Internal SRAM
219#define PMIC_INTERNAL_SRAM
220
221#if !defined(__FUE__)
222#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
223#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
224#else /*defined(__FUE__)*/
225#define SAVEANDSETIRQMASK() 0
226#define RESTOREIRQMASK(mask) {}
227#endif /*defined(__FUE__)*/
228
229#define PMIC_MAX_REG_NUM 0x3a00 // 0x0000~0x3a00
230
231//////////////////////////////////////////////////
232// Exported APIs //
233//////////////////////////////////////////////////
234
235extern DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr);
236extern DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr);
237extern void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val);
238extern void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val);
239extern DCL_BOOL dcl_pmic_init_done_query(void);
240typedef enum
241{
242 AUXADC_READ_INIT = 0,
243 AUXADC_READ_REQUEST = 1,
244 AUXADC_READ_READY = 2,
245 AUXADC_READ_BUSY = 3,
246 AUXADC_READ_DATA = 4
247}AUXADC_FSM;
248
249typedef struct
250{
251 kal_uint32 command_flag;
252 kal_uint32 reg_before_write;
253 kal_uint32 write_value;
254 kal_uint32 address_offset;
255 kal_uint32 reg_mask;
256 kal_uint32 reg_shift;
257 kal_uint32 reg_addr;
258 kal_uint32 reg_data;
259}PMIC_REG_LOG;
260
261/* All buck/ldo use the same sw/hw OP_EN control, so use vcore as reference
262 * bit shift
263 */
264typedef enum
265{
266 RG_BUCK_LDO_HW0_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW0_OP_EN_SHIFT,
267 RG_BUCK_LDO_HW1_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW1_OP_EN_SHIFT,
268 RG_BUCK_LDO_HW2_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW2_OP_EN_SHIFT,
269 RG_BUCK_LDO_HW3_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW3_OP_EN_SHIFT,
270 RG_BUCK_LDO_HW4_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW4_OP_EN_SHIFT,
271 RG_BUCK_LDO_HW5_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW5_OP_EN_SHIFT,
272 RG_BUCK_LDO_HW6_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW6_OP_EN_SHIFT,
273 RG_BUCK_LDO_HW7_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW7_OP_EN_SHIFT,
274 RG_BUCK_LDO_HW8_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW8_OP_EN_SHIFT,
275 RG_BUCK_LDO_HW9_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW9_OP_EN_SHIFT,
276 RG_BUCK_LDO_HW10_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW10_OP_EN_SHIFT,
277 RG_BUCK_LDO_HW11_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW11_OP_EN_SHIFT,
278 RG_BUCK_LDO_HW12_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW12_OP_EN_SHIFT,
279 RG_BUCK_LDO_HW13_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW13_OP_EN_SHIFT,
280 RG_BUCK_LDO_HW14_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_HW14_OP_EN_SHIFT,
281 RG_BUCK_LDO_SW_OP_EN_SHIFT = PMIC_RG_BUCK_VCORE_SW_OP_EN_SHIFT,
282}PMIC_BUCK_LDO_OP_EN_SHIFT_ENUM;
283
284typedef enum
285{
286 RG_BUCK_LDO_HW0_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW0_OP_CFG_SHIFT,
287 RG_BUCK_LDO_HW1_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW1_OP_CFG_SHIFT,
288 RG_BUCK_LDO_HW2_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW2_OP_CFG_SHIFT,
289 RG_BUCK_LDO_HW3_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW3_OP_CFG_SHIFT,
290 RG_BUCK_LDO_HW4_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW4_OP_CFG_SHIFT,
291 RG_BUCK_LDO_HW5_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW5_OP_CFG_SHIFT,
292 RG_BUCK_LDO_HW6_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW6_OP_CFG_SHIFT,
293 RG_BUCK_LDO_HW7_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW7_OP_CFG_SHIFT,
294 RG_BUCK_LDO_HW8_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW8_OP_CFG_SHIFT,
295 RG_BUCK_LDO_HW9_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW9_OP_CFG_SHIFT,
296 RG_BUCK_LDO_HW10_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW10_OP_CFG_SHIFT,
297 RG_BUCK_LDO_HW11_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW11_OP_CFG_SHIFT,
298 RG_BUCK_LDO_HW12_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW12_OP_CFG_SHIFT,
299 RG_BUCK_LDO_HW13_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW13_OP_CFG_SHIFT,
300 RG_BUCK_LDO_HW14_OP_CFG_SHIFT = PMIC_RG_BUCK_VCORE_HW14_OP_CFG_SHIFT,
301}PMIC_BUCK_LDO_OP_CFG_SHIFT_ENUM;
302
303AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
304PMIC_REG_LOG pmic_reg_log;
305
306#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
307__attribute__ ((zero_init))
308#endif /* __MTK_TARGET__ */
309
310kal_uint8 pmic_hw_version;
311kal_uint8 pmic_sw_version;
312kal_uint16 pmic_reg[PMIC_MAX_REG_NUM];
313DCL_BOOL pmic_init_done = DCL_FALSE;
314
315kal_spinlockid dcl_pmic_access_spinlock;
316extern kal_spinlockid dcl_pmic_control_spinlock;
317
318const PMIC_FLAG_TABLE_ENTRY pmic_flags_table[] =
319{
320 {MT6359_HWCID, PMIC_HWCID_MASK, PMIC_HWCID_SHIFT, },
321 {MT6359_SWCID, PMIC_SWCID_MASK, PMIC_SWCID_SHIFT, },
322 {MT6359_TOP_CON, PMIC_RG_SRCLKEN_IN0_EN_MASK, PMIC_RG_SRCLKEN_IN0_EN_SHIFT, },
323 {MT6359_TOP_CON, PMIC_RG_SRCLKEN_IN1_EN_MASK, PMIC_RG_SRCLKEN_IN1_EN_SHIFT, },
324 {MT6359_TOP_CON, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT, },
325 {MT6359_TOP_CON, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT, },
326 {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_SHIFT, },
327 {MT6359_BUCK_TOP_ELR2, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_SHIFT, },
328 {MT6359_BUCK_VCORE_CON1, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_SHIFT, },
329 {MT6359_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_MASK, PMIC_DA_VCORE_VOSEL_SHIFT, },
330 {MT6359_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_GRAY_MASK, PMIC_DA_VCORE_VOSEL_GRAY_SHIFT, },
331 {MT6359_BUCK_VCORE_ELR0, PMIC_RG_BUCK_VCORE_VOSEL_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SHIFT, },
332 {MT6359_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_EN_MASK, PMIC_RG_BUCK_VMODEM_EN_SHIFT, },
333 {MT6359_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_LP_MASK, PMIC_RG_BUCK_VMODEM_LP_SHIFT, },
334 {MT6359_BUCK_VMODEM_CON1, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
335 {MT6359_BUCK_VMODEM_ELR0, PMIC_RG_BUCK_VMODEM_VOSEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT, },
336 {MT6359_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT, },
337 {MT6359_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT, },
338 {MT6359_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT, },
339 {MT6359_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT, },
340 {MT6359_BUCK_VMODEM_OP_EN_SET, PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT, },
341 {MT6359_BUCK_VMODEM_OP_EN_CLR, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT, },
342 {MT6359_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT, },
343 {MT6359_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT, },
344 {MT6359_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT, },
345 {MT6359_BUCK_VMODEM_OP_CFG_SET, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT, },
346 {MT6359_BUCK_VMODEM_OP_CFG_CLR, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT, },
347 {MT6359_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_MASK, PMIC_DA_VMODEM_VOSEL_SHIFT, },
348 {MT6359_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_GRAY_MASK, PMIC_DA_VMODEM_VOSEL_GRAY_SHIFT, },
349 {MT6359_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_EN_MASK, PMIC_DA_VMODEM_EN_SHIFT, },
350 {MT6359_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_STB_MASK, PMIC_DA_VMODEM_STB_SHIFT, },
351 {MT6359_BUCK_VS1_VOTER, PMIC_RG_BUCK_VS1_VOTER_EN_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SHIFT, },
352 {MT6359_BUCK_VS1_VOTER_SET, PMIC_RG_BUCK_VS1_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SET_SHIFT, },
353 {MT6359_BUCK_VS1_VOTER_CLR, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_SHIFT, },
354 {MT6359_BUCK_VS1_VOTER_CFG, PMIC_RG_BUCK_VS1_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS1_VOTER_VOSEL_SHIFT, },
355 {MT6359_BUCK_VS2_CON1, PMIC_RG_BUCK_VS2_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VS2_VOSEL_SLEEP_SHIFT, },
356 {MT6359_BUCK_VS2_VOTER, PMIC_RG_BUCK_VS2_VOTER_EN_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SHIFT, },
357 {MT6359_BUCK_VS2_VOTER_SET, PMIC_RG_BUCK_VS2_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SET_SHIFT, },
358 {MT6359_BUCK_VS2_VOTER_CLR, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_SHIFT, },
359 {MT6359_BUCK_VS2_VOTER_CFG, PMIC_RG_BUCK_VS2_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOTER_VOSEL_SHIFT, },
360 {MT6359_BUCK_VS2_ELR0, PMIC_RG_BUCK_VS2_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOSEL_SHIFT, },
361 {MT6359_BUCK_VPA_CON0, PMIC_RG_BUCK_VPA_EN_MASK, PMIC_RG_BUCK_VPA_EN_SHIFT, },
362 {MT6359_BUCK_VPA_CON1, PMIC_RG_BUCK_VPA_VOSEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_SHIFT, },
363 {MT6359_VMODEM_ANA_CON3, PMIC_RG_VMODEM_FCCM_MASK, PMIC_RG_VMODEM_FCCM_SHIFT, },
364 {MT6359_VS2_ANA_CON2, PMIC_RG_VS2_FPWM_MASK, PMIC_RG_VS2_FPWM_SHIFT, },
365 {MT6359_VPA_ANA_CON0, PMIC_RG_VPA_MODESET_MASK, PMIC_RG_VPA_MODESET_SHIFT, },
366 {MT6359_LDO_VSRAM_OTHERS_ELR, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_MASK, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT, },
367 {MT6359_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_EN_MASK, PMIC_RG_LDO_VSIM1_EN_SHIFT, },
368 {MT6359_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_LP_MASK, PMIC_RG_LDO_VSIM1_LP_SHIFT, },
369 {MT6359_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM1_SW_OP_EN_SHIFT, },
370 {MT6359_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_EN_SHIFT, },
371 {MT6359_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_EN_SHIFT, },
372 {MT6359_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_EN_SHIFT, },
373 {MT6359_LDO_VSIM1_OP_EN_SET, PMIC_RG_LDO_VSIM1_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM1_OP_EN_SET_SHIFT, },
374 {MT6359_LDO_VSIM1_OP_EN_CLR, PMIC_RG_LDO_VSIM1_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_EN_CLR_SHIFT, },
375 {MT6359_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_SHIFT, },
376 {MT6359_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_SHIFT, },
377 {MT6359_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_SHIFT, },
378 {MT6359_LDO_VSIM1_OP_CFG_SET, PMIC_RG_LDO_VSIM1_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_SET_SHIFT, },
379 {MT6359_LDO_VSIM1_OP_CFG_CLR, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_SHIFT, },
380 {MT6359_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_OCFB_EN_MASK, PMIC_RG_LDO_VSIM1_OCFB_EN_SHIFT, },
381 {MT6359_LDO_VSIM1_MON, PMIC_DA_VSIM1_OCFB_EN_MASK, PMIC_DA_VSIM1_OCFB_EN_SHIFT, },
382 {MT6359_VSIM1_ANA_CON0, PMIC_RG_VSIM1_VOSEL_MASK, PMIC_RG_VSIM1_VOSEL_SHIFT, },
383 {MT6359_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_EN_MASK, PMIC_RG_LDO_VSIM2_EN_SHIFT, },
384 {MT6359_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_LP_MASK, PMIC_RG_LDO_VSIM2_LP_SHIFT, },
385 {MT6359_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM2_SW_OP_EN_SHIFT, },
386 {MT6359_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_EN_SHIFT, },
387 {MT6359_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_EN_SHIFT, },
388 {MT6359_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_EN_SHIFT, },
389 {MT6359_LDO_VSIM2_OP_EN_SET, PMIC_RG_LDO_VSIM2_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM2_OP_EN_SET_SHIFT, },
390 {MT6359_LDO_VSIM2_OP_EN_CLR, PMIC_RG_LDO_VSIM2_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_EN_CLR_SHIFT, },
391 {MT6359_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_SHIFT, },
392 {MT6359_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_SHIFT, },
393 {MT6359_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_SHIFT, },
394 {MT6359_LDO_VSIM2_OP_CFG_SET, PMIC_RG_LDO_VSIM2_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_SET_SHIFT, },
395 {MT6359_LDO_VSIM2_OP_CFG_CLR, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_SHIFT, },
396 {MT6359_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_OCFB_EN_MASK, PMIC_RG_LDO_VSIM2_OCFB_EN_SHIFT, },
397 {MT6359_LDO_VSIM2_MON, PMIC_DA_VSIM2_OCFB_EN_MASK, PMIC_DA_VSIM2_OCFB_EN_SHIFT, },
398 {MT6359_VSIM2_ANA_CON0, PMIC_RG_VSIM2_VOSEL_MASK, PMIC_RG_VSIM2_VOSEL_SHIFT, },
399 {MT6359_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_EN_MASK, PMIC_RG_LDO_VFE28_EN_SHIFT, },
400 {MT6359_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_LP_MASK, PMIC_RG_LDO_VFE28_LP_SHIFT, },
401 {MT6359_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_SW_OP_EN_MASK, PMIC_RG_LDO_VFE28_SW_OP_EN_SHIFT, },
402 {MT6359_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW0_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW0_OP_EN_SHIFT, },
403 {MT6359_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW1_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW1_OP_EN_SHIFT, },
404 {MT6359_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW2_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW2_OP_EN_SHIFT, },
405 {MT6359_LDO_VFE28_OP_EN_SET, PMIC_RG_LDO_VFE28_OP_EN_SET_MASK, PMIC_RG_LDO_VFE28_OP_EN_SET_SHIFT, },
406 {MT6359_LDO_VFE28_OP_EN_CLR, PMIC_RG_LDO_VFE28_OP_EN_CLR_MASK, PMIC_RG_LDO_VFE28_OP_EN_CLR_SHIFT, },
407 {MT6359_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW0_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW0_OP_CFG_SHIFT, },
408 {MT6359_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW1_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW1_OP_CFG_SHIFT, },
409 {MT6359_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW2_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW2_OP_CFG_SHIFT, },
410 {MT6359_LDO_VFE28_OP_CFG_SET, PMIC_RG_LDO_VFE28_OP_CFG_SET_MASK, PMIC_RG_LDO_VFE28_OP_CFG_SET_SHIFT, },
411 {MT6359_LDO_VFE28_OP_CFG_CLR, PMIC_RG_LDO_VFE28_OP_CFG_CLR_MASK, PMIC_RG_LDO_VFE28_OP_CFG_CLR_SHIFT, },
412 {MT6359_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_OCFB_EN_MASK, PMIC_RG_LDO_VFE28_OCFB_EN_SHIFT, },
413 {MT6359_LDO_VFE28_MON, PMIC_DA_VFE28_OCFB_EN_MASK, PMIC_DA_VFE28_OCFB_EN_SHIFT, },
414 {MT6359_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_EN_MASK, PMIC_RG_LDO_VRF18_EN_SHIFT, },
415 {MT6359_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_LP_MASK, PMIC_RG_LDO_VRF18_LP_SHIFT, },
416 {MT6359_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_SW_OP_EN_MASK, PMIC_RG_LDO_VRF18_SW_OP_EN_SHIFT, },
417 {MT6359_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW0_OP_EN_SHIFT, },
418 {MT6359_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW1_OP_EN_SHIFT, },
419 {MT6359_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW2_OP_EN_SHIFT, },
420 {MT6359_LDO_VRF18_OP_EN_SET, PMIC_RG_LDO_VRF18_OP_EN_SET_MASK, PMIC_RG_LDO_VRF18_OP_EN_SET_SHIFT, },
421 {MT6359_LDO_VRF18_OP_EN_CLR, PMIC_RG_LDO_VRF18_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF18_OP_EN_CLR_SHIFT, },
422 {MT6359_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW0_OP_CFG_SHIFT, },
423 {MT6359_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW1_OP_CFG_SHIFT, },
424 {MT6359_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW2_OP_CFG_SHIFT, },
425 {MT6359_LDO_VRF18_OP_CFG_SET, PMIC_RG_LDO_VRF18_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF18_OP_CFG_SET_SHIFT, },
426 {MT6359_LDO_VRF18_OP_CFG_CLR, PMIC_RG_LDO_VRF18_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF18_OP_CFG_CLR_SHIFT, },
427 {MT6359_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_OCFB_EN_MASK, PMIC_RG_LDO_VRF18_OCFB_EN_SHIFT, },
428 {MT6359_LDO_VRF18_MON, PMIC_DA_VRF18_OCFB_EN_MASK, PMIC_DA_VRF18_OCFB_EN_SHIFT, },
429 {MT6359_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_EN_MASK, PMIC_RG_LDO_VRF12_EN_SHIFT, },
430 {MT6359_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_LP_MASK, PMIC_RG_LDO_VRF12_LP_SHIFT, },
431 {MT6359_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_SW_OP_EN_MASK, PMIC_RG_LDO_VRF12_SW_OP_EN_SHIFT, },
432 {MT6359_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW0_OP_EN_SHIFT, },
433 {MT6359_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW1_OP_EN_SHIFT, },
434 {MT6359_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW2_OP_EN_SHIFT, },
435 {MT6359_LDO_VRF12_OP_EN_SET, PMIC_RG_LDO_VRF12_OP_EN_SET_MASK, PMIC_RG_LDO_VRF12_OP_EN_SET_SHIFT, },
436 {MT6359_LDO_VRF12_OP_EN_CLR, PMIC_RG_LDO_VRF12_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF12_OP_EN_CLR_SHIFT, },
437 {MT6359_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW0_OP_CFG_SHIFT, },
438 {MT6359_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW1_OP_CFG_SHIFT, },
439 {MT6359_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW2_OP_CFG_SHIFT, },
440 {MT6359_LDO_VRF12_OP_CFG_SET, PMIC_RG_LDO_VRF12_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF12_OP_CFG_SET_SHIFT, },
441 {MT6359_LDO_VRF12_OP_CFG_CLR, PMIC_RG_LDO_VRF12_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF12_OP_CFG_CLR_SHIFT, },
442 {MT6359_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_OCFB_EN_MASK, PMIC_RG_LDO_VRF12_OCFB_EN_SHIFT, },
443 {MT6359_LDO_VRF12_MON, PMIC_DA_VRF12_OCFB_EN_MASK, PMIC_DA_VRF12_OCFB_EN_SHIFT, },
444 {MT6359_VXO22_ANA_CON0, PMIC_RG_VXO22_VOSEL_MASK, PMIC_RG_VXO22_VOSEL_SHIFT, },
445 {MT6359_DCXO_CW00, PMIC_XO_EXTBUF1_MODE_MASK, PMIC_XO_EXTBUF1_MODE_SHIFT, },
446 {MT6359_DCXO_CW00, PMIC_XO_EXTBUF1_EN_M_MASK, PMIC_XO_EXTBUF1_EN_M_SHIFT, },
447 {MT6359_DCXO_CW00, PMIC_XO_EXTBUF2_MODE_MASK, PMIC_XO_EXTBUF2_MODE_SHIFT, },
448 {MT6359_DCXO_CW00, PMIC_XO_EXTBUF2_EN_M_MASK, PMIC_XO_EXTBUF2_EN_M_SHIFT, },
449 {MT6359_DCXO_CW00, PMIC_XO_EXTBUF3_MODE_MASK, PMIC_XO_EXTBUF3_MODE_SHIFT, },
450 {MT6359_DCXO_CW00, PMIC_XO_EXTBUF3_EN_M_MASK, PMIC_XO_EXTBUF3_EN_M_SHIFT, },
451 {MT6359_DCXO_CW00, PMIC_XO_EXTBUF4_MODE_MASK, PMIC_XO_EXTBUF4_MODE_SHIFT, },
452 {MT6359_DCXO_CW00, PMIC_XO_EXTBUF4_EN_M_MASK, PMIC_XO_EXTBUF4_EN_M_SHIFT, },
453 {MT6359_DCXO_CW00, PMIC_XO_ENBB_MAN_MASK, PMIC_XO_ENBB_MAN_SHIFT, },
454 {MT6359_DCXO_CW00, PMIC_XO_ENBB_EN_M_MASK, PMIC_XO_ENBB_EN_M_SHIFT, },
455 {MT6359_DCXO_CW00, PMIC_XO_CLKSEL_MAN_MASK, PMIC_XO_CLKSEL_MAN_SHIFT, },
456 {MT6359_DCXO_CW00_SET, PMIC_DCXO_CW00_SET_MASK, PMIC_DCXO_CW00_SET_SHIFT, },
457 {MT6359_DCXO_CW00_CLR, PMIC_DCXO_CW00_CLR_MASK, PMIC_DCXO_CW00_CLR_SHIFT, },
458 {MT6359_DCXO_CW02, PMIC_XO_EN32K_MAN_MASK, PMIC_XO_EN32K_MAN_SHIFT, },
459 {MT6359_DCXO_CW02, PMIC_XO_EN32K_M_MASK, PMIC_XO_EN32K_M_SHIFT, },
460 {MT6359_DCXO_CW02, PMIC_RG_XO_CBANK_POL_MASK, PMIC_RG_XO_CBANK_POL_SHIFT, },
461 {MT6359_DCXO_CW02, PMIC_XO_XMODE_M_MASK, PMIC_XO_XMODE_M_SHIFT, },
462 {MT6359_DCXO_CW02, PMIC_XO_STRUP_MODE_MASK, PMIC_XO_STRUP_MODE_SHIFT, },
463 {MT6359_DCXO_CW02, PMIC_RG_XO_PCTAT_CCOMP_MASK, PMIC_RG_XO_PCTAT_CCOMP_SHIFT, },
464 {MT6359_DCXO_CW02, PMIC_RG_XO_VTEST_SEL_MUX_MASK, PMIC_RG_XO_VTEST_SEL_MUX_SHIFT, },
465 {MT6359_DCXO_CW02, PMIC_XO_SWRST_MASK, PMIC_XO_SWRST_SHIFT, },
466 {MT6359_DCXO_CW02, PMIC_XO_CBANK_SYNC_DYN_MASK, PMIC_XO_CBANK_SYNC_DYN_SHIFT, },
467 {MT6359_DCXO_CW02, PMIC_XO_PCTAT_EN_MAN_MASK, PMIC_XO_PCTAT_EN_MAN_SHIFT, },
468 {MT6359_DCXO_CW02, PMIC_XO_PCTAT_EN_M_MASK, PMIC_XO_PCTAT_EN_M_SHIFT, },
469 {MT6359_DCXO_CW04, PMIC_XO_CDAC_FPM_MASK, PMIC_XO_CDAC_FPM_SHIFT, },
470 {MT6359_DCXO_CW04, PMIC_XO_CDAC_LPM_MASK, PMIC_XO_CDAC_LPM_SHIFT, },
471 {MT6359_DCXO_CW05, PMIC_XO_32KDIV_NFRAC_FPM_MASK, PMIC_XO_32KDIV_NFRAC_FPM_SHIFT, },
472 {MT6359_DCXO_CW05, PMIC_XO_COFST_FPM_MASK, PMIC_XO_COFST_FPM_SHIFT, },
473 {MT6359_DCXO_CW06, PMIC_XO_32KDIV_NFRAC_LPM_MASK, PMIC_XO_32KDIV_NFRAC_LPM_SHIFT, },
474 {MT6359_DCXO_CW06, PMIC_XO_COFST_LPM_MASK, PMIC_XO_COFST_LPM_SHIFT, },
475 {MT6359_DCXO_CW07, PMIC_XO_CORE_MAN_MASK, PMIC_XO_CORE_MAN_SHIFT, },
476 {MT6359_DCXO_CW07, PMIC_XO_CORE_EN_M_MASK, PMIC_XO_CORE_EN_M_SHIFT, },
477 {MT6359_DCXO_CW07, PMIC_XO_CORE_TURBO_EN_SYNC_M_MASK, PMIC_XO_CORE_TURBO_EN_SYNC_M_SHIFT, },
478 {MT6359_DCXO_CW07, PMIC_RG_XO_PCTAT_IS_EN_MASK, PMIC_RG_XO_PCTAT_IS_EN_SHIFT, },
479 {MT6359_DCXO_CW07, PMIC_XO_STARTUP_EN_M_MASK, PMIC_XO_STARTUP_EN_M_SHIFT, },
480 {MT6359_DCXO_CW07, PMIC_RG_XO_CMP_GSEL_MASK, PMIC_RG_XO_CMP_GSEL_SHIFT, },
481 {MT6359_DCXO_CW07, PMIC_XO_CORE_VBSEL_SYNC_M_MASK, PMIC_XO_CORE_VBSEL_SYNC_M_SHIFT, },
482 {MT6359_DCXO_CW07, PMIC_XO_CORE_FPMBIAS_EN_M_MASK, PMIC_XO_CORE_FPMBIAS_EN_M_SHIFT, },
483 {MT6359_DCXO_CW07, PMIC_XO_CORE_LPMCF_SYNC_FPM_MASK, PMIC_XO_CORE_LPMCF_SYNC_FPM_SHIFT, },
484 {MT6359_DCXO_CW07, PMIC_XO_CORE_LPMCF_SYNC_LPM_MASK, PMIC_XO_CORE_LPMCF_SYNC_LPM_SHIFT, },
485 {MT6359_DCXO_CW07, PMIC_RG_XO_CORE_LPM_ISEL_MAN_MASK, PMIC_RG_XO_CORE_LPM_ISEL_MAN_SHIFT, },
486 {MT6359_DCXO_CW07, PMIC_RG_XO_CORE_LPM_IDAC_MASK, PMIC_RG_XO_CORE_LPM_IDAC_SHIFT, },
487 {MT6359_DCXO_CW09, PMIC_XO_32KDIV_SWRST_MASK, PMIC_XO_32KDIV_SWRST_SHIFT, },
488 {MT6359_DCXO_CW09, PMIC_XO_32KDIV_RATIO_MAN_MASK, PMIC_XO_32KDIV_RATIO_MAN_SHIFT, },
489 {MT6359_DCXO_CW09, PMIC_XO_32KDIV_TEST_EN_MASK, PMIC_XO_32KDIV_TEST_EN_SHIFT, },
490 {MT6359_DCXO_CW09, PMIC_XO_CTL_SYNC_BUF_MAN_MASK, PMIC_XO_CTL_SYNC_BUF_MAN_SHIFT, },
491 {MT6359_DCXO_CW09, PMIC_XO_CTL_SYNC_BUF_EN_M_MASK, PMIC_XO_CTL_SYNC_BUF_EN_M_SHIFT, },
492 {MT6359_DCXO_CW09, PMIC_RG_XO_HV_PBUF_VSET_MASK, PMIC_RG_XO_HV_PBUF_VSET_SHIFT, },
493 {MT6359_DCXO_CW09, PMIC_XO_EXTBUF6_MODE_MASK, PMIC_XO_EXTBUF6_MODE_SHIFT, },
494 {MT6359_DCXO_CW09, PMIC_XO_EXTBUF6_EN_M_MASK, PMIC_XO_EXTBUF6_EN_M_SHIFT, },
495 {MT6359_DCXO_CW09, PMIC_XO_EXTBUF7_MODE_MASK, PMIC_XO_EXTBUF7_MODE_SHIFT, },
496 {MT6359_DCXO_CW09, PMIC_XO_EXTBUF7_EN_M_MASK, PMIC_XO_EXTBUF7_EN_M_SHIFT, },
497 {MT6359_DCXO_CW16, PMIC_XO_STATIC_AUXOUT_SEL_MASK, PMIC_XO_STATIC_AUXOUT_SEL_SHIFT, },
498 {MT6359_DCXO_CW16, PMIC_XO_AUXOUT_SEL_MASK, PMIC_XO_AUXOUT_SEL_SHIFT, },
499 {MT6359_DCXO_CW17, PMIC_XO_STATIC_AUXOUT_MASK, PMIC_XO_STATIC_AUXOUT_SHIFT, },
500 {MT6359_AUXADC_ADC16, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
501 {MT6359_AUXADC_ADC16, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
502 {MT6359_AUXADC_RQST1, PMIC_AUXADC_RQST_CH7_BY_MD_MASK, PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT, },
503 {MT6359_VRF18_ANA_CON0, PMIC_RG_VRF18_VOCAL_MASK, PMIC_RG_VRF18_VOCAL_SHIFT, },
504 {MT6359_VRF12_ANA_CON0, PMIC_RG_VRF12_VOCAL_MASK, PMIC_RG_VRF12_VOCAL_SHIFT, },
505 {MT6359_VRF18_ELR_0, PMIC_RG_VRF18_VOTRIM_MASK, PMIC_RG_VRF18_VOTRIM_SHIFT, },
506 {MT6359_VRF18_ELR_2, PMIC_RG_VRF12_VOTRIM_MASK, PMIC_RG_VRF12_VOTRIM_SHIFT, },
507 {MT6359_BUCK_TOP_OC_CON0, PMIC_RG_BUCK_VPA_OC_SDN_STATUS_MASK, PMIC_RG_BUCK_VPA_OC_SDN_STATUS_SHIFT, },
508 {MT6359_BUCK_TOP_ELR0, PMIC_RG_BUCK_VPA_OC_SDN_EN_MASK, PMIC_RG_BUCK_VPA_OC_SDN_EN_SHIFT, },
509 {MT6359_LDO_VSRAM_MD_ELR, PMIC_RG_LDO_VSRAM_MD_VOSEL_MASK, PMIC_RG_LDO_VSRAM_MD_VOSEL_SHIFT, },
510 {MT6359_LDO_VSRAM_MD_VOSEL0, PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP_SHIFT, },
511 {MT6359_LDO_VSRAM_MD_VOSEL1, PMIC_DA_VSRAM_MD_VOSEL_MASK, PMIC_DA_VSRAM_MD_VOSEL_SHIFT, },
512 {MT6359_LDO_VSRAM_OTHERS_VOSEL0, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_SHIFT, },
513 {MT6359_LDO_VSRAM_OTHERS_VOSEL1, PMIC_DA_VSRAM_OTHERS_VOSEL_MASK, PMIC_DA_VSRAM_OTHERS_VOSEL_SHIFT, },
514 {MT6359_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_OP_MODE_MASK, PMIC_RG_LDO_VRF18_OP_MODE_SHIFT, },
515 {MT6359_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_OP_MODE_MASK, PMIC_RG_LDO_VRF12_OP_MODE_SHIFT, },
516 {MT6359_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_OP_MODE_MASK, PMIC_RG_LDO_VFE28_OP_MODE_SHIFT, },
517 {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
518 {MT6359_BUCK_VGPU11_CON0, PMIC_RG_BUCK_VGPU11_EN_MASK, PMIC_RG_BUCK_VGPU11_EN_SHIFT, },
519 {MT6359_BUCK_VGPU11_CON0, PMIC_RG_BUCK_VGPU11_LP_MASK, PMIC_RG_BUCK_VGPU11_LP_SHIFT, },
520 {MT6359_BUCK_VGPU11_CON1, PMIC_RG_BUCK_VGPU11_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_SLEEP_SHIFT, },
521 {MT6359_BUCK_VGPU11_ELR0, PMIC_RG_BUCK_VGPU11_VOSEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_SHIFT, },
522 {MT6359_BUCK_VGPU11_OP_EN, PMIC_RG_BUCK_VGPU11_SW_OP_EN_MASK, PMIC_RG_BUCK_VGPU11_SW_OP_EN_SHIFT, },
523 {MT6359_BUCK_VGPU11_OP_EN, PMIC_RG_BUCK_VGPU11_HW0_OP_EN_MASK, PMIC_RG_BUCK_VGPU11_HW0_OP_EN_SHIFT, },
524 {MT6359_BUCK_VGPU11_OP_EN, PMIC_RG_BUCK_VGPU11_HW1_OP_EN_MASK, PMIC_RG_BUCK_VGPU11_HW1_OP_EN_SHIFT, },
525 {MT6359_BUCK_VGPU11_OP_EN, PMIC_RG_BUCK_VGPU11_HW2_OP_EN_MASK, PMIC_RG_BUCK_VGPU11_HW2_OP_EN_SHIFT, },
526 {MT6359_BUCK_VGPU11_OP_EN_SET, PMIC_RG_BUCK_VGPU11_OP_EN_SET_MASK, PMIC_RG_BUCK_VGPU11_OP_EN_SET_SHIFT, },
527 {MT6359_BUCK_VGPU11_OP_EN_CLR, PMIC_RG_BUCK_VGPU11_OP_EN_CLR_MASK, PMIC_RG_BUCK_VGPU11_OP_EN_CLR_SHIFT, },
528 {MT6359_BUCK_VGPU11_OP_CFG, PMIC_RG_BUCK_VGPU11_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VGPU11_HW0_OP_CFG_SHIFT, },
529 {MT6359_BUCK_VGPU11_OP_CFG, PMIC_RG_BUCK_VGPU11_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VGPU11_HW1_OP_CFG_SHIFT, },
530 {MT6359_BUCK_VGPU11_OP_CFG, PMIC_RG_BUCK_VGPU11_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VGPU11_HW2_OP_CFG_SHIFT, },
531 {MT6359_BUCK_VGPU11_OP_CFG_SET, PMIC_RG_BUCK_VGPU11_OP_CFG_SET_MASK, PMIC_RG_BUCK_VGPU11_OP_CFG_SET_SHIFT, },
532 {MT6359_BUCK_VGPU11_OP_CFG_CLR, PMIC_RG_BUCK_VGPU11_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VGPU11_OP_CFG_CLR_SHIFT, },
533 {MT6359_BUCK_VGPU11_DBG0, PMIC_DA_VGPU11_VOSEL_MASK, PMIC_DA_VGPU11_VOSEL_SHIFT, },
534 {MT6359_BUCK_VGPU11_DBG0, PMIC_DA_VGPU11_VOSEL_GRAY_MASK, PMIC_DA_VGPU11_VOSEL_GRAY_SHIFT, },
535 {MT6359_BUCK_VGPU11_DBG1, PMIC_DA_VGPU11_EN_MASK, PMIC_DA_VGPU11_EN_SHIFT, },
536 {MT6359_BUCK_VGPU11_DBG1, PMIC_DA_VGPU11_STB_MASK, PMIC_DA_VGPU11_STB_SHIFT, },
537 {MT6359_VGPUVCORE_ANA_CON2, PMIC_RG_VGPU11_FCCM_MASK, PMIC_RG_VGPU11_FCCM_SHIFT, },
538 {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VGPU12_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
539 {MT6359_BUCK_VGPU12_CON0, PMIC_RG_BUCK_VGPU12_EN_MASK, PMIC_RG_BUCK_VGPU12_EN_SHIFT, },
540 {MT6359_BUCK_VGPU12_CON0, PMIC_RG_BUCK_VGPU12_LP_MASK, PMIC_RG_BUCK_VGPU12_LP_SHIFT, },
541 {MT6359_BUCK_VGPU12_CON1, PMIC_RG_BUCK_VGPU12_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VGPU12_VOSEL_SLEEP_SHIFT, },
542 {MT6359_BUCK_VGPU12_ELR0, PMIC_RG_BUCK_VGPU12_VOSEL_MASK, PMIC_RG_BUCK_VGPU12_VOSEL_SHIFT, },
543 {MT6359_BUCK_VGPU12_OP_EN, PMIC_RG_BUCK_VGPU12_SW_OP_EN_MASK, PMIC_RG_BUCK_VGPU12_SW_OP_EN_SHIFT, },
544 {MT6359_BUCK_VGPU12_OP_EN, PMIC_RG_BUCK_VGPU12_HW0_OP_EN_MASK, PMIC_RG_BUCK_VGPU12_HW0_OP_EN_SHIFT, },
545 {MT6359_BUCK_VGPU12_OP_EN, PMIC_RG_BUCK_VGPU12_HW1_OP_EN_MASK, PMIC_RG_BUCK_VGPU12_HW1_OP_EN_SHIFT, },
546 {MT6359_BUCK_VGPU12_OP_EN, PMIC_RG_BUCK_VGPU12_HW2_OP_EN_MASK, PMIC_RG_BUCK_VGPU12_HW2_OP_EN_SHIFT, },
547 {MT6359_BUCK_VGPU12_OP_EN_SET, PMIC_RG_BUCK_VGPU12_OP_EN_SET_MASK, PMIC_RG_BUCK_VGPU12_OP_EN_SET_SHIFT, },
548 {MT6359_BUCK_VGPU12_OP_EN_CLR, PMIC_RG_BUCK_VGPU12_OP_EN_CLR_MASK, PMIC_RG_BUCK_VGPU12_OP_EN_CLR_SHIFT, },
549 {MT6359_BUCK_VGPU12_OP_CFG, PMIC_RG_BUCK_VGPU12_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VGPU12_HW0_OP_CFG_SHIFT, },
550 {MT6359_BUCK_VGPU12_OP_CFG, PMIC_RG_BUCK_VGPU12_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VGPU12_HW1_OP_CFG_SHIFT, },
551 {MT6359_BUCK_VGPU12_OP_CFG, PMIC_RG_BUCK_VGPU12_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VGPU12_HW2_OP_CFG_SHIFT, },
552 {MT6359_BUCK_VGPU12_OP_CFG_SET, PMIC_RG_BUCK_VGPU12_OP_CFG_SET_MASK, PMIC_RG_BUCK_VGPU12_OP_CFG_SET_SHIFT, },
553 {MT6359_BUCK_VGPU12_OP_CFG_CLR, PMIC_RG_BUCK_VGPU12_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VGPU12_OP_CFG_CLR_SHIFT, },
554 {MT6359_BUCK_VGPU12_DBG0, PMIC_DA_VGPU12_VOSEL_MASK, PMIC_DA_VGPU12_VOSEL_SHIFT, },
555 {MT6359_BUCK_VGPU12_DBG0, PMIC_DA_VGPU12_VOSEL_GRAY_MASK, PMIC_DA_VGPU12_VOSEL_GRAY_SHIFT, },
556 {MT6359_BUCK_VGPU12_DBG1, PMIC_DA_VGPU12_EN_MASK, PMIC_DA_VGPU12_EN_SHIFT, },
557 {MT6359_BUCK_VGPU12_DBG1, PMIC_DA_VGPU12_STB_MASK, PMIC_DA_VGPU12_STB_SHIFT, },
558 {MT6359_VGPUVCORE_ANA_CON8, PMIC_RG_VGPU12_FCCM_MASK, PMIC_RG_VGPU12_FCCM_SHIFT, },
559 {MT6359_LDO_VSRAM_PROC1_ELR, PMIC_RG_LDO_VSRAM_PROC1_VOSEL_MASK, PMIC_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT, },
560 {MT6359_LDO_VSRAM_PROC1_VOSEL0, PMIC_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP_SHIFT, },
561 {MT6359_LDO_VSRAM_PROC1_VOSEL1, PMIC_DA_VSRAM_PROC1_VOSEL_MASK, PMIC_DA_VSRAM_PROC1_VOSEL_SHIFT, },
562 {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPROC1_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
563 {MT6359_BUCK_VPROC1_CON0, PMIC_RG_BUCK_VPROC1_EN_MASK, PMIC_RG_BUCK_VPROC1_EN_SHIFT, },
564 {MT6359_BUCK_VPROC1_CON0, PMIC_RG_BUCK_VPROC1_LP_MASK, PMIC_RG_BUCK_VPROC1_LP_SHIFT, },
565 {MT6359_BUCK_VPROC1_CON1, PMIC_RG_BUCK_VPROC1_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VPROC1_VOSEL_SLEEP_SHIFT, },
566 {MT6359_BUCK_VPROC1_ELR0, PMIC_RG_BUCK_VPROC1_VOSEL_MASK, PMIC_RG_BUCK_VPROC1_VOSEL_SHIFT, },
567 {MT6359_BUCK_VPROC1_OP_EN, PMIC_RG_BUCK_VPROC1_SW_OP_EN_MASK, PMIC_RG_BUCK_VPROC1_SW_OP_EN_SHIFT, },
568 {MT6359_BUCK_VPROC1_OP_EN, PMIC_RG_BUCK_VPROC1_HW0_OP_EN_MASK, PMIC_RG_BUCK_VPROC1_HW0_OP_EN_SHIFT, },
569 {MT6359_BUCK_VPROC1_OP_EN, PMIC_RG_BUCK_VPROC1_HW1_OP_EN_MASK, PMIC_RG_BUCK_VPROC1_HW1_OP_EN_SHIFT, },
570 {MT6359_BUCK_VPROC1_OP_EN, PMIC_RG_BUCK_VPROC1_HW2_OP_EN_MASK, PMIC_RG_BUCK_VPROC1_HW2_OP_EN_SHIFT, },
571 {MT6359_BUCK_VPROC1_OP_EN_SET, PMIC_RG_BUCK_VPROC1_OP_EN_SET_MASK, PMIC_RG_BUCK_VPROC1_OP_EN_SET_SHIFT, },
572 {MT6359_BUCK_VPROC1_OP_EN_CLR, PMIC_RG_BUCK_VPROC1_OP_EN_CLR_MASK, PMIC_RG_BUCK_VPROC1_OP_EN_CLR_SHIFT, },
573 {MT6359_BUCK_VPROC1_OP_CFG, PMIC_RG_BUCK_VPROC1_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VPROC1_HW0_OP_CFG_SHIFT, },
574 {MT6359_BUCK_VPROC1_OP_CFG, PMIC_RG_BUCK_VPROC1_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VPROC1_HW1_OP_CFG_SHIFT, },
575 {MT6359_BUCK_VPROC1_OP_CFG, PMIC_RG_BUCK_VPROC1_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VPROC1_HW2_OP_CFG_SHIFT, },
576 {MT6359_BUCK_VPROC1_OP_CFG_SET, PMIC_RG_BUCK_VPROC1_OP_CFG_SET_MASK, PMIC_RG_BUCK_VPROC1_OP_CFG_SET_SHIFT, },
577 {MT6359_BUCK_VPROC1_OP_CFG_CLR, PMIC_RG_BUCK_VPROC1_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VPROC1_OP_CFG_CLR_SHIFT, },
578 {MT6359_BUCK_VPROC1_DBG0, PMIC_DA_VPROC1_VOSEL_MASK, PMIC_DA_VPROC1_VOSEL_SHIFT, },
579 {MT6359_BUCK_VPROC1_DBG0, PMIC_DA_VPROC1_VOSEL_GRAY_MASK, PMIC_DA_VPROC1_VOSEL_GRAY_SHIFT, },
580 {MT6359_BUCK_VPROC1_DBG1, PMIC_DA_VPROC1_EN_MASK, PMIC_DA_VPROC1_EN_SHIFT, },
581 {MT6359_BUCK_VPROC1_DBG1, PMIC_DA_VPROC1_STB_MASK, PMIC_DA_VPROC1_STB_SHIFT, },
582 {MT6359_VPROC1_ANA_CON3, PMIC_RG_VPROC1_FCCM_MASK, PMIC_RG_VPROC1_FCCM_SHIFT, },
583 {MT6359_LDO_VSRAM_PROC2_ELR, PMIC_RG_LDO_VSRAM_PROC2_VOSEL_MASK, PMIC_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT, },
584 {MT6359_LDO_VSRAM_PROC2_VOSEL0, PMIC_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP_MASK, PMIC_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP_SHIFT, },
585 {MT6359_LDO_VSRAM_PROC2_VOSEL1, PMIC_DA_VSRAM_PROC2_VOSEL_MASK, PMIC_DA_VSRAM_PROC2_VOSEL_SHIFT, },
586 {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPROC2_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
587 {MT6359_BUCK_VPROC2_CON0, PMIC_RG_BUCK_VPROC2_EN_MASK, PMIC_RG_BUCK_VPROC2_EN_SHIFT, },
588 {MT6359_BUCK_VPROC2_CON0, PMIC_RG_BUCK_VPROC2_LP_MASK, PMIC_RG_BUCK_VPROC2_LP_SHIFT, },
589 {MT6359_BUCK_VPROC2_CON1, PMIC_RG_BUCK_VPROC2_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VPROC2_VOSEL_SLEEP_SHIFT, },
590 {MT6359_BUCK_VPROC2_ELR0, PMIC_RG_BUCK_VPROC2_VOSEL_MASK, PMIC_RG_BUCK_VPROC2_VOSEL_SHIFT, },
591 {MT6359_BUCK_VPROC2_OP_EN, PMIC_RG_BUCK_VPROC2_SW_OP_EN_MASK, PMIC_RG_BUCK_VPROC2_SW_OP_EN_SHIFT, },
592 {MT6359_BUCK_VPROC2_OP_EN, PMIC_RG_BUCK_VPROC2_HW0_OP_EN_MASK, PMIC_RG_BUCK_VPROC2_HW0_OP_EN_SHIFT, },
593 {MT6359_BUCK_VPROC2_OP_EN, PMIC_RG_BUCK_VPROC2_HW1_OP_EN_MASK, PMIC_RG_BUCK_VPROC2_HW1_OP_EN_SHIFT, },
594 {MT6359_BUCK_VPROC2_OP_EN, PMIC_RG_BUCK_VPROC2_HW2_OP_EN_MASK, PMIC_RG_BUCK_VPROC2_HW2_OP_EN_SHIFT, },
595 {MT6359_BUCK_VPROC2_OP_EN_SET, PMIC_RG_BUCK_VPROC2_OP_EN_SET_MASK, PMIC_RG_BUCK_VPROC2_OP_EN_SET_SHIFT, },
596 {MT6359_BUCK_VPROC2_OP_EN_CLR, PMIC_RG_BUCK_VPROC2_OP_EN_CLR_MASK, PMIC_RG_BUCK_VPROC2_OP_EN_CLR_SHIFT, },
597 {MT6359_BUCK_VPROC2_OP_CFG, PMIC_RG_BUCK_VPROC2_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VPROC2_HW0_OP_CFG_SHIFT, },
598 {MT6359_BUCK_VPROC2_OP_CFG, PMIC_RG_BUCK_VPROC2_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VPROC2_HW1_OP_CFG_SHIFT, },
599 {MT6359_BUCK_VPROC2_OP_CFG, PMIC_RG_BUCK_VPROC2_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VPROC2_HW2_OP_CFG_SHIFT, },
600 {MT6359_BUCK_VPROC2_OP_CFG_SET, PMIC_RG_BUCK_VPROC2_OP_CFG_SET_MASK, PMIC_RG_BUCK_VPROC2_OP_CFG_SET_SHIFT, },
601 {MT6359_BUCK_VPROC2_OP_CFG_CLR, PMIC_RG_BUCK_VPROC2_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VPROC2_OP_CFG_CLR_SHIFT, },
602 {MT6359_BUCK_VPROC2_DBG0, PMIC_DA_VPROC2_VOSEL_MASK, PMIC_DA_VPROC2_VOSEL_SHIFT, },
603 {MT6359_BUCK_VPROC2_DBG0, PMIC_DA_VPROC2_VOSEL_GRAY_MASK, PMIC_DA_VPROC2_VOSEL_GRAY_SHIFT, },
604 {MT6359_BUCK_VPROC2_DBG1, PMIC_DA_VPROC2_EN_MASK, PMIC_DA_VPROC2_EN_SHIFT, },
605 {MT6359_BUCK_VPROC2_DBG1, PMIC_DA_VPROC2_STB_MASK, PMIC_DA_VPROC2_STB_SHIFT, },
606 {MT6359_VPROC2_ANA_CON3, PMIC_RG_VPROC2_FCCM_MASK, PMIC_RG_VPROC2_FCCM_SHIFT, },
607 {MT6359_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPU_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VGPU11_VOSEL_LIMIT_SEL_SHIFT, },
608 {MT6359_BUCK_VPU_CON0, PMIC_RG_BUCK_VPU_EN_MASK, PMIC_RG_BUCK_VPU_EN_SHIFT, },
609 {MT6359_BUCK_VPU_CON0, PMIC_RG_BUCK_VPU_LP_MASK, PMIC_RG_BUCK_VPU_LP_SHIFT, },
610 {MT6359_BUCK_VPU_CON1, PMIC_RG_BUCK_VPU_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VPU_VOSEL_SLEEP_SHIFT, },
611 {MT6359_BUCK_VPU_ELR0, PMIC_RG_BUCK_VPU_VOSEL_MASK, PMIC_RG_BUCK_VPU_VOSEL_SHIFT, },
612 {MT6359_BUCK_VPU_OP_EN, PMIC_RG_BUCK_VPU_SW_OP_EN_MASK, PMIC_RG_BUCK_VPU_SW_OP_EN_SHIFT, },
613 {MT6359_BUCK_VPU_OP_EN, PMIC_RG_BUCK_VPU_HW0_OP_EN_MASK, PMIC_RG_BUCK_VPU_HW0_OP_EN_SHIFT, },
614 {MT6359_BUCK_VPU_OP_EN, PMIC_RG_BUCK_VPU_HW1_OP_EN_MASK, PMIC_RG_BUCK_VPU_HW1_OP_EN_SHIFT, },
615 {MT6359_BUCK_VPU_OP_EN, PMIC_RG_BUCK_VPU_HW2_OP_EN_MASK, PMIC_RG_BUCK_VPU_HW2_OP_EN_SHIFT, },
616 {MT6359_BUCK_VPU_OP_EN_SET, PMIC_RG_BUCK_VPU_OP_EN_SET_MASK, PMIC_RG_BUCK_VPU_OP_EN_SET_SHIFT, },
617 {MT6359_BUCK_VPU_OP_EN_CLR, PMIC_RG_BUCK_VPU_OP_EN_CLR_MASK, PMIC_RG_BUCK_VPU_OP_EN_CLR_SHIFT, },
618 {MT6359_BUCK_VPU_OP_CFG, PMIC_RG_BUCK_VPU_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VPU_HW0_OP_CFG_SHIFT, },
619 {MT6359_BUCK_VPU_OP_CFG, PMIC_RG_BUCK_VPU_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VPU_HW1_OP_CFG_SHIFT, },
620 {MT6359_BUCK_VPU_OP_CFG, PMIC_RG_BUCK_VPU_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VPU_HW2_OP_CFG_SHIFT, },
621 {MT6359_BUCK_VPU_OP_CFG_SET, PMIC_RG_BUCK_VPU_OP_CFG_SET_MASK, PMIC_RG_BUCK_VPU_OP_CFG_SET_SHIFT, },
622 {MT6359_BUCK_VPU_OP_CFG_CLR, PMIC_RG_BUCK_VPU_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VPU_OP_CFG_CLR_SHIFT, },
623 {MT6359_BUCK_VPU_DBG0, PMIC_DA_VPU_VOSEL_MASK, PMIC_DA_VPU_VOSEL_SHIFT, },
624 {MT6359_BUCK_VPU_DBG0, PMIC_DA_VPU_VOSEL_GRAY_MASK, PMIC_DA_VPU_VOSEL_GRAY_SHIFT, },
625 {MT6359_BUCK_VPU_DBG1, PMIC_DA_VPU_EN_MASK, PMIC_DA_VPU_EN_SHIFT, },
626 {MT6359_BUCK_VPU_DBG1, PMIC_DA_VPU_STB_MASK, PMIC_DA_VPU_STB_SHIFT, },
627 {MT6359_VPU_ANA_CON3, PMIC_RG_VPU_FCCM_MASK, PMIC_RG_VPU_FCCM_SHIFT, },
628 {MT6359_BUCK_VPU_OP_MODE, PMIC_RG_BUCK_VPROC2_HW0_OP_MODE_MASK, PMIC_RG_BUCK_VPROC2_HW0_OP_MODE_SHIFT, },
629 {MT6359_BUCK_VPU_OP_MODE, PMIC_RG_BUCK_VPROC2_HW1_OP_MODE_MASK, PMIC_RG_BUCK_VPROC2_HW1_OP_MODE_SHIFT, },
630 {MT6359_BUCK_VPU_OP_MODE, PMIC_RG_BUCK_VPROC2_HW2_OP_MODE_MASK, PMIC_RG_BUCK_VPROC2_HW2_OP_MODE_SHIFT, },
631 {MT6359_BUCK_VPU_OP_MODE_SET, PMIC_RG_BUCK_VPU_OP_MODE_SET_MASK, PMIC_RG_BUCK_VPU_OP_MODE_SET_SHIFT, },
632 {MT6359_BUCK_VPU_OP_MODE_CLR, PMIC_RG_BUCK_VPU_OP_MODE_CLR_MASK, PMIC_RG_BUCK_VPU_OP_MODE_CLR_SHIFT, },
633};
634#if defined(DCL_PMIC_MODULE_CONTROL)
635DCL_HANDLE current_dcl_handle = 0;
636#endif
637
638//#define DCL_PMIC_PERMISSION_CONTROL
639#if defined(DCL_PMIC_PERMISSION_CONTROL)
640PMU_CTRL_MISC_SET_REGISTER_VALUE illegal_misc_set_register_value = {0};
641#endif
642
643//////////////////////////////////////////////////
644// WRITE APIs //
645//////////////////////////////////////////////////
646#if defined(DCL_PMIC_PERMISSION_CONTROL)
647DCL_BOOL dcl_pmic_check_permission(kal_uint16 offset)
648{
649 DCL_BOOL ret = DCL_FALSE;
650 kal_uint8 c = ((offset>>8) & 0xFF);
651
652 switch(c)
653 {
654 case 0x82:
655 {
656 //CLK : TOP_CLKSQ_SET (0x8226),TOP_CKPDN_CON0_CLR (0x8204),TOP_CLKSQ(0x8224)
657 if(offset == 0x8226 || offset == 0x8204 || offset == 0x8224)
658 ret=DCL_TRUE;
659 }
660 break;
661
662 case 0x90:
663 {
664 //LDO_DIG: 0x901A,0x901C, 0x9006, 0x9008
665 if(offset == 0x901A || offset == 0x901C || offset == 0x9006 || offset == 0x9008)
666 ret=DCL_TRUE;
667 }
668 break;
669
670 case 0x98:
671 {
672 //Audio Analog : 0x9800~0x9852
673 if(offset >= 0x9800 && offset <= 0x9852)
674 ret=DCL_TRUE;
675 }
676 break;
677
678 case 0x9A:
679 {
680 //Audio DRE : 0x9A00 ~0x9A0A
681 if(offset >= 0x9A00 && offset <= 0x9A0A)
682 ret=DCL_TRUE;
683 }
684 break;
685
686 case 0xE0:
687 case 0xE1:
688 {
689 //Audio digital : 0xE000 ~0xE138
690 if(offset >= 0xE000 && offset <= 0xE138)
691 ret=DCL_TRUE;
692 }
693 break;
694
695 default:
696 ret=DCL_FALSE;
697 break;
698 }
699 return ret;
700}
701#endif
702// Write Whole Bytes
703void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
704{
705 DCL_UINT32 idx, type;
706
707 kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
708
709 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
710 idx = pmic_access_duration_index[type];
711
712
713#if defined(DCL_PMIC_ACCESS_TIME_LOG)
714 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
715#endif
716 if(addr < PMIC_MAX_REG_NUM)
717 {
718 pmic_reg[addr] = val;
719 }
720
721 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
722
723#if defined(DCL_PMIC_ACCESS_TIME_LOG)
724 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
725 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
726 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
727#endif
728 kal_give_spinlock(dcl_pmic_access_spinlock);
729}
730
731// Write Whole Bytes
732void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val)
733{
734 DCL_UINT32 idx, type;
735
736 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
737 type = PMIC_LOG_TYPE_HRT_DOMAIN;
738 else
739 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
740
741 idx = pmic_access_duration_index[type];
742
743#if defined(DCL_PMIC_ACCESS_TIME_LOG)
744 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
745#endif
746
747
748 if(addr < PMIC_MAX_REG_NUM)
749 {
750 pmic_reg[addr] = val;
751 }
752
753// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
754 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
755// else
756// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
757
758#if defined(DCL_PMIC_ACCESS_TIME_LOG)
759 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
760 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
761 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
762#endif
763
764}
765
766// Write register field
767void dcl_pmic_field_write(PMIC6359_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
768{
769 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
770 DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
771 DCL_UINT32 idx = pmic_access_duration_index[type];
772
773 kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
774#if defined(DCL_PMIC_ACCESS_TIME_LOG)
775 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
776#endif
777
778 pmic_reg_log.command_flag = flag;
779 pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
780
781 pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
782 pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
783
784// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
785 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
786// else
787// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
788
789 pmic_reg_log.write_value = sel;
790 pmic_reg_log.address_offset = pTable[flag].offset;
791 pmic_reg_log.reg_mask = pTable[flag].mask;
792 pmic_reg_log.reg_shift = pTable[flag].shift;
793 pmic_reg_log.reg_addr = pTable[flag].offset;
794 pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
795
796#if defined(DCL_PMIC_ACCESS_TIME_LOG)
797 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
798 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
799#endif
800
801 kal_give_spinlock(dcl_pmic_access_spinlock);
802}
803
804// Write register field
805void dcl_pmic_field_write_nolock(PMIC6359_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
806{
807 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
808 DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
809 DCL_UINT32 idx = pmic_access_duration_index[type];
810
811#if defined(DCL_PMIC_ACCESS_TIME_LOG)
812 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
813#endif
814
815 pmic_reg_log.command_flag = flag;
816 pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
817
818 pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
819 pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
820
821// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
822 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
823// else
824// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
825
826 pmic_reg_log.write_value = sel;
827 pmic_reg_log.address_offset = pTable[flag].offset;
828 pmic_reg_log.reg_mask = pTable[flag].mask;
829 pmic_reg_log.reg_shift = pTable[flag].shift;
830 pmic_reg_log.reg_addr = pTable[flag].offset;
831 pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
832
833#if defined(DCL_PMIC_ACCESS_TIME_LOG)
834 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
835 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
836#endif
837
838}
839//////////////////////////////////////////////////
840// READ APIs //
841//////////////////////////////////////////////////
842
843// Read Whole Bytes
844DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr)
845{
846 DCL_UINT16 reg_temp;
847 DCL_UINT32 idx, type;
848
849 kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
850
851 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
852 idx = pmic_access_duration_index[type];
853
854#if defined(DCL_PMIC_ACCESS_TIME_LOG)
855 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
856#endif
857
858// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
859 DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
860// else
861// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
862
863 if(addr < PMIC_MAX_REG_NUM)
864 {
865 pmic_reg[addr] = reg_temp;
866 }
867
868#if defined(DCL_PMIC_ACCESS_TIME_LOG)
869 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
870 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
871#endif
872
873 kal_give_spinlock(dcl_pmic_access_spinlock);
874
875 return reg_temp;
876}
877
878// Read Whole Bytes
879DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr)
880{
881 DCL_UINT16 reg_temp;
882 DCL_UINT32 idx, type;
883
884 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
885 type = PMIC_LOG_TYPE_HRT_DOMAIN;
886 else
887 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
888
889 idx = pmic_access_duration_index[type];
890
891#if defined(DCL_PMIC_ACCESS_TIME_LOG)
892 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
893#endif
894
895// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
896 DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
897// else
898// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
899
900 if(addr < PMIC_MAX_REG_NUM)
901 {
902 pmic_reg[addr] = reg_temp;
903 }
904
905#if defined(DCL_PMIC_ACCESS_TIME_LOG)
906 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
907 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
908#endif
909
910 return reg_temp;
911}
912
913// Read register field
914DCL_UINT16 dcl_pmic_field_read(PMIC6359_FLAGS_LIST_ENUM flag)
915{
916 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
917 DCL_UINT16 reg_return = 0;
918 DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
919 DCL_UINT32 idx = pmic_access_duration_index[type];
920
921 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
922 type = PMIC_LOG_TYPE_HRT_DOMAIN;
923 else
924 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
925
926 idx = pmic_access_duration_index[type];
927
928
929#if defined(DCL_PMIC_ACCESS_TIME_LOG)
930 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
931#endif
932
933// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
934 DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
935// else
936// DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
937
938 reg_return = ((pmic_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
939
940#if defined(DCL_PMIC_ACCESS_TIME_LOG)
941 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
942 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
943 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
944#endif
945
946 return reg_return;
947}
948
949// Exported for EM used
950void pmic_EM_reg_write(kal_uint16 reg, kal_uint16 val){
951 dcl_pmic_byte_write_nolock(reg, val);
952// dcl_pmic_byte_write(reg, val);
953}
954
955kal_uint16 pmic_EM_reg_read(kal_uint16 reg){
956 return dcl_pmic_byte_return_nolock(reg);
957}
958
959const DCL_UINT32 vpa_vosel[] =
960{
961 PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
962 PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
963 PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
964 PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
965 PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
966 PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
967 PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
968 PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
969 PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
970 PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
971 PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
972 PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
973 PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
974 PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
975 PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
976 PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
977};
978
979const DCL_UINT32 vsim1_vosel[] =
980{
981 PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_01_700000_V,
982 PMU_VOLT_01_800000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
983 PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V,
984 PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
985};
986
987const DCL_UINT32 vxo22_vosel[] =
988{
989 PMU_VOLT_01_800000_V, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
990 PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
991};
992
993const DCL_UINT32 vmodem_vosel[] =
994{
995 PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_750000_V,
996 PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
997};
998
999#if 0
1000/* under construction !*/
1001/* under construction !*/
1002/* under construction !*/
1003/* under construction !*/
1004#endif
1005
1006const DCL_UINT32 vsram_vmd_vosel[] =
1007{
1008 PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V, PMU_VOLT_00_750000_V,
1009 PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
1010};
1011
1012PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
1013{
1014 {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
1015 {ENC(LDO_BUCK_SET_VOLTAGE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
1016 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
1017 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
1018 {ENC(LDO_BUCK_SET_VOLTAGE, VXO22), vxo22_vosel, NULL, GETARRNUM(vxo22_vosel) },
1019 {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VMODEM), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
1020 {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_MD), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
1021 {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VGPU11), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
1022 {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VGPU12), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
1023 {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_PROC1), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
1024 {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_PROC2), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
1025};
1026
1027
1028extern PMU_CONTROL_HANDLER pmu_control_handler;
1029
1030DCL_UINT16 pmu_parameter_size = 0;
1031
1032DCL_STATUS PMIC_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
1033{
1034 DCL_UINT16 regVal;
1035 DCL_INT32 return_val = STATUS_FAIL;
1036#if defined(DCL_PMIC_MODULE_CONTROL)
1037 current_dcl_handle = handle;
1038#endif
1039 switch(cmd)
1040 {
1041 case LDO_BUCK_SET_EN: //Enable control in SW mode
1042 {
1043 PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
1044
1045 switch(pLdoBuckCtrl->mod)
1046 {
1047 case VMODEM:
1048 {
1049 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_EN, pLdoBuckCtrl->enable);
1050 return_val = STATUS_OK;
1051 }
1052 break;
1053
1054 case VPA_SW:
1055 {
1056 /* Enable BUCK_VPA_CK_SW_MODE before Enable VPA */
1057 if (pLdoBuckCtrl->enable == 0x1)
1058 dcl_pmic_byte_write_nolock(MT6359_BUCK_VPA_DBG1, 0x3000);
1059
1060 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_EN, pLdoBuckCtrl->enable);
1061
1062 /* Disable BUCK_VPA_CK_SW_MODE after Disable VPA */
1063 if (pLdoBuckCtrl->enable == 0x0)
1064 dcl_pmic_byte_write_nolock(MT6359_BUCK_VPA_DBG1, 0x0);
1065
1066 return_val = STATUS_OK;
1067 }
1068 break;
1069
1070 case VSIM1:
1071 {
1072 /* Clear INT_STATUS_VSIM1_OC before Enable VSIM1 */
1073 if (pLdoBuckCtrl->enable == 0x1)
1074 dcl_pmic_byte_write_nolock(MT6359_LDO_TOP_INT_STATUS1, 0x10);
1075
1076 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_EN, pLdoBuckCtrl->enable);
1077 return_val = STATUS_OK;
1078 }
1079 break;
1080
1081 case VSIM2:
1082 {
1083 /* Clear INT_STATUS_VSIM2_OC before Enable VSIM2 */
1084 if (pLdoBuckCtrl->enable == 0x1)
1085 dcl_pmic_byte_write_nolock(MT6359_LDO_TOP_INT_STATUS1, 0x20);
1086
1087 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_EN, pLdoBuckCtrl->enable);
1088 return_val = STATUS_OK;
1089 }
1090 break;
1091
1092 case VFE28:
1093 {
1094 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_EN, pLdoBuckCtrl->enable);
1095 return_val = STATUS_OK;
1096 }
1097 break;
1098
1099 case VRF18:
1100 {
1101 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_LDO_VRF18_EN, pLdoBuckCtrl->enable);
1102 return_val = STATUS_OK;
1103 }
1104 break;
1105
1106 case VRF12:
1107 {
1108 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_LDO_VRF12_EN, pLdoBuckCtrl->enable);
1109 return_val = STATUS_OK;
1110 }
1111 break;
1112
1113 case VS1:
1114 {
1115 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_EN, pLdoBuckCtrl->enable);
1116 return_val = STATUS_OK;
1117 }
1118 break;
1119
1120 case VS2:
1121 {
1122 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_EN, pLdoBuckCtrl->enable);
1123 return_val = STATUS_OK;
1124 }
1125 break;
1126
1127 case VGPU11:
1128 {
1129 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU11_EN, pLdoBuckCtrl->enable);
1130 return_val = STATUS_OK;
1131 }
1132 break;
1133
1134 case VGPU12:
1135 {
1136 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU12_EN, pLdoBuckCtrl->enable);
1137 return_val = STATUS_OK;
1138 }
1139 break;
1140
1141 case VPROC1:
1142 {
1143 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC1_EN, pLdoBuckCtrl->enable);
1144 return_val = STATUS_OK;
1145 }
1146 break;
1147
1148 case VPROC2:
1149 {
1150 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC2_EN, pLdoBuckCtrl->enable);
1151 return_val = STATUS_OK;
1152 }
1153 break;
1154
1155 case VPU:
1156 {
1157 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPU_EN, pLdoBuckCtrl->enable);
1158 return_val = STATUS_OK;
1159 }
1160 break;
1161
1162 default:
1163 return_val = STATUS_UNSUPPORTED;
1164 break;
1165 }
1166 }
1167 break;
1168
1169 case LDO_BUCK_SET_LP_MODE_SET:
1170 {
1171 PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
1172
1173 switch(pLdoBuckCtrl->mod)
1174 {
1175 case VMODEM:
1176 { // 1'b0:Normal mode, 1'b1:Low power mode
1177 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_LP, pLdoBuckCtrl->enable);
1178 return_val = STATUS_OK;
1179 }
1180 break;
1181
1182 case VSIM1:
1183 { // 1'b0:Normal mode, 1'b1:Low power mode
1184 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_LP, pLdoBuckCtrl->enable);
1185 return_val = STATUS_OK;
1186 }
1187 break;
1188
1189 case VSIM2:
1190 { // 1'b0:Normal mode, 1'b1:Low power mode
1191 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_LP, pLdoBuckCtrl->enable);
1192 return_val = STATUS_OK;
1193 }
1194 break;
1195
1196 case VFE28:
1197 { // 1'b0:Normal mode, 1'b1:Low power mode
1198 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_LP, pLdoBuckCtrl->enable);
1199 return_val = STATUS_OK;
1200 }
1201 break;
1202
1203 case VRF18:
1204 { // 1'b0:Normal mode, 1'b1:Low power mode
1205 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_LP, pLdoBuckCtrl->enable);
1206 return_val = STATUS_OK;
1207 }
1208 break;
1209
1210 case VRF12:
1211 { // 1'b0:Normal mode, 1'b1:Low power mode
1212 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_LP, pLdoBuckCtrl->enable);
1213 return_val = STATUS_OK;
1214 }
1215 break;
1216
1217 case VGPU11:
1218 { // 1'b0:Normal mode, 1'b1:Low power mode
1219 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU11_LP, pLdoBuckCtrl->enable);
1220 return_val = STATUS_OK;
1221 }
1222 break;
1223
1224 case VGPU12:
1225 { // 1'b0:Normal mode, 1'b1:Low power mode
1226 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU12_LP, pLdoBuckCtrl->enable);
1227 return_val = STATUS_OK;
1228 }
1229 break;
1230
1231 case VPROC1:
1232 { // 1'b0:Normal mode, 1'b1:Low power mode
1233 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC1_LP, pLdoBuckCtrl->enable);
1234 return_val = STATUS_OK;
1235 }
1236 break;
1237
1238 case VPROC2:
1239 { // 1'b0:Normal mode, 1'b1:Low power mode
1240 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC2_LP, pLdoBuckCtrl->enable);
1241 return_val = STATUS_OK;
1242 }
1243 break;
1244
1245 case VPU:
1246 { // 1'b0:Normal mode, 1'b1:Low power mode
1247 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPU_LP, pLdoBuckCtrl->enable);
1248 return_val = STATUS_OK;
1249 }
1250 break;
1251
1252 default:
1253 return_val = STATUS_UNSUPPORTED;
1254 break;
1255 }
1256 }
1257 break;
1258
1259 case LDO_BUCK_SET_OCFB_EN:
1260 {
1261 PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
1262
1263 switch(pLdoBuckCtrl->mod)
1264 {
1265 case VSIM1:
1266 {
1267 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
1268 return_val = STATUS_OK;
1269 }
1270 break;
1271
1272 case VSIM2:
1273 {
1274 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
1275 return_val = STATUS_OK;
1276 }
1277 break;
1278
1279 default:
1280 return_val = STATUS_UNSUPPORTED;
1281 break;
1282 }
1283 }
1284 break;
1285
1286 case LDO_BUCK_GET_VOSEL:
1287 {
1288 PMU_CTRL_LDO_BUCK_GET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVosel);
1289
1290 switch(pLdoBuckCtrl->mod)
1291 {
1292 case VCORE:
1293 {
1294 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VCORE_VOSEL);
1295 return_val = STATUS_OK;
1296 }
1297 break;
1298
1299 case VSRAM_OTHERS:
1300 {
1301 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL);
1302 return_val = STATUS_OK;
1303 }
1304 break;
1305
1306 case VMODEM:
1307 {
1308 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL);
1309 return_val = STATUS_OK;
1310 }
1311 break;
1312
1313 case VSRAM_MD:
1314 {
1315 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL);
1316 return_val = STATUS_OK;
1317 }
1318 break;
1319
1320 case VGPU11:
1321 {
1322 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VGPU11_VOSEL);
1323 return_val = STATUS_OK;
1324 }
1325 break;
1326
1327 case VGPU12:
1328 {
1329 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VGPU12_VOSEL);
1330 return_val = STATUS_OK;
1331 }
1332 break;
1333
1334 case VSRAM_PROC1:
1335 {
1336 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_PROC1_VOSEL);
1337 return_val = STATUS_OK;
1338 }
1339 break;
1340
1341 case VPROC1:
1342 {
1343 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPROC1_VOSEL);
1344 return_val = STATUS_OK;
1345 }
1346 break;
1347
1348 case VSRAM_PROC2:
1349 {
1350 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_PROC2_VOSEL);
1351 return_val = STATUS_OK;
1352 }
1353 break;
1354
1355 case VPROC2:
1356 {
1357 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPROC2_VOSEL);
1358 return_val = STATUS_OK;
1359 }
1360 break;
1361
1362 case VPU:
1363 {
1364 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPU_VOSEL);
1365 return_val = STATUS_OK;
1366 }
1367 break;
1368
1369 default:
1370 return_val = STATUS_UNSUPPORTED;
1371 break;
1372 }
1373 }
1374 break;
1375
1376 case LDO_BUCK_SET_VOSEL:
1377 {
1378 PMU_CTRL_LDO_BUCK_SET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVosel);
1379
1380 switch(pLdoBuckCtrl->mod)
1381 {
1382 case VCORE:
1383 {
1384 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VCORE_VOSEL, pLdoBuckCtrl->code);
1385 return_val = STATUS_OK;
1386 }
1387 break;
1388
1389 case VMODEM:
1390 {
1391 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL, pLdoBuckCtrl->code);
1392 return_val = STATUS_OK;
1393 }
1394 break;
1395
1396 case VSRAM_OTHERS:
1397 {
1398 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL, pLdoBuckCtrl->code);
1399 return_val = STATUS_OK;
1400 }
1401 break;
1402
1403 case VSRAM_MD:
1404 {
1405 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL, pLdoBuckCtrl->code);
1406 return_val = STATUS_OK;
1407 }
1408 break;
1409
1410 case VGPU11:
1411 {
1412 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU11_VOSEL, pLdoBuckCtrl->code);
1413 return_val = STATUS_OK;
1414 }
1415 break;
1416
1417 case VGPU12:
1418 {
1419 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU12_VOSEL, pLdoBuckCtrl->code);
1420 return_val = STATUS_OK;
1421 }
1422 break;
1423
1424 case VSRAM_PROC1:
1425 {
1426 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_PROC1_VOSEL, pLdoBuckCtrl->code);
1427 return_val = STATUS_OK;
1428 }
1429 break;
1430
1431 case VPROC1:
1432 {
1433 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC1_VOSEL, pLdoBuckCtrl->code);
1434 return_val = STATUS_OK;
1435 }
1436 break;
1437
1438 case VSRAM_PROC2:
1439 {
1440 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_PROC2_VOSEL, pLdoBuckCtrl->code);
1441 return_val = STATUS_OK;
1442 }
1443 break;
1444
1445 case VPROC2:
1446 {
1447 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC2_VOSEL, pLdoBuckCtrl->code);
1448 return_val = STATUS_OK;
1449 }
1450 break;
1451
1452 case VPU:
1453 {
1454 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPU_VOSEL, pLdoBuckCtrl->code);
1455 return_val = STATUS_OK;
1456 }
1457 break;
1458
1459 default:
1460 return_val = STATUS_UNSUPPORTED;
1461 break;
1462 }
1463 }
1464 break;
1465
1466 case LDO_BUCK_GET_VOSEL_SLEEP:
1467 {
1468 PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselSleep);
1469
1470 switch(pLdoBuckCtrl->mod)
1471 {
1472 case VCORE:
1473 {
1474 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VCORE_VOSEL_SLEEP);
1475 return_val = STATUS_OK;
1476 }
1477 break;
1478
1479 case VMODEM:
1480 {
1481 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP);
1482 return_val = STATUS_OK;
1483 }
1484 break;
1485
1486 case VSRAM_MD:
1487 {
1488 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL_SLEEP);
1489 return_val = STATUS_OK;
1490 }
1491 break;
1492
1493 case VSRAM_OTHERS:
1494 {
1495 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP);
1496 return_val = STATUS_OK;
1497 }
1498 break;
1499
1500 case VGPU11:
1501 {
1502 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VGPU11_VOSEL_SLEEP);
1503 return_val = STATUS_OK;
1504 }
1505 break;
1506
1507 case VGPU12:
1508 {
1509 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VGPU12_VOSEL_SLEEP);
1510 return_val = STATUS_OK;
1511 }
1512 break;
1513
1514 case VSRAM_PROC1:
1515 {
1516 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP);
1517 return_val = STATUS_OK;
1518 }
1519 break;
1520
1521 case VPROC1:
1522 {
1523 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPROC1_VOSEL_SLEEP);
1524 return_val = STATUS_OK;
1525 }
1526 break;
1527
1528 case VSRAM_PROC2:
1529 {
1530 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP);
1531 return_val = STATUS_OK;
1532 }
1533 break;
1534
1535 case VPROC2:
1536 {
1537 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPROC2_VOSEL_SLEEP);
1538 return_val = STATUS_OK;
1539 }
1540 break;
1541
1542 case VPU:
1543 {
1544 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPU_VOSEL_SLEEP);
1545 return_val = STATUS_OK;
1546 }
1547 break;
1548
1549 default:
1550 return_val = STATUS_UNSUPPORTED;
1551 break;
1552 }
1553 }
1554 break;
1555
1556 case LDO_BUCK_SET_VOSEL_SLEEP:
1557 {
1558 PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselSleep);
1559
1560 switch(pLdoBuckCtrl->mod)
1561 {
1562 case VMODEM:
1563 {
1564 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP, pLdoBuckCtrl->code);
1565 return_val = STATUS_OK;
1566 }
1567 break;
1568
1569 case VSRAM_MD:
1570 {
1571 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_MD_VOSEL_SLEEP, pLdoBuckCtrl->code);
1572 return_val = STATUS_OK;
1573 }
1574 break;
1575
1576 case VSRAM_OTHERS:
1577 {
1578 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP, pLdoBuckCtrl->code);
1579 return_val = STATUS_OK;
1580 }
1581 break;
1582
1583 case VGPU11:
1584 {
1585 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU11_VOSEL_SLEEP, pLdoBuckCtrl->code);
1586 return_val = STATUS_OK;
1587 }
1588 break;
1589
1590 case VGPU12:
1591 {
1592 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VGPU12_VOSEL_SLEEP, pLdoBuckCtrl->code);
1593 return_val = STATUS_OK;
1594 }
1595 break;
1596
1597 case VSRAM_PROC1:
1598 {
1599 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP, pLdoBuckCtrl->code);
1600 return_val = STATUS_OK;
1601 }
1602 break;
1603
1604 case VPROC1:
1605 {
1606 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC1_VOSEL_SLEEP, pLdoBuckCtrl->code);
1607 return_val = STATUS_OK;
1608 }
1609 break;
1610
1611 case VSRAM_PROC2:
1612 {
1613 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP, pLdoBuckCtrl->code);
1614 return_val = STATUS_OK;
1615 }
1616 break;
1617
1618 case VPROC2:
1619 {
1620 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPROC2_VOSEL_SLEEP, pLdoBuckCtrl->code);
1621 return_val = STATUS_OK;
1622 }
1623 break;
1624
1625 case VPU:
1626 {
1627 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPU_VOSEL_SLEEP, pLdoBuckCtrl->code);
1628 return_val = STATUS_OK;
1629 }
1630 break;
1631
1632 default:
1633 return_val = STATUS_UNSUPPORTED;
1634 break;
1635 }
1636 }
1637 break;
1638
1639 case LDO_BUCK_SET_MODESET:
1640 {
1641 PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
1642
1643 switch(pLdoBuckCtrl->mod)
1644 {
1645 case VPA_SW:
1646 {
1647 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_VPA_MODESET, pLdoBuckCtrl->mode);
1648 return_val = STATUS_OK;
1649 }
1650 break;
1651
1652 case VMODEM:
1653 {
1654 dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_FCCM, pLdoBuckCtrl->mode);
1655 return_val = STATUS_OK;
1656 }
1657 break;
1658
1659 case VS2:
1660 {
1661 dcl_pmic_field_write(PMIC_ENUM_RG_VS2_FPWM, pLdoBuckCtrl->mode);
1662 return_val = STATUS_OK;
1663 }
1664 break;
1665
1666 case VGPU11:
1667 {
1668 dcl_pmic_field_write(PMIC_ENUM_RG_VGPU11_FCCM, pLdoBuckCtrl->mode);
1669 return_val = STATUS_OK;
1670 }
1671 break;
1672
1673 case VGPU12:
1674 {
1675 dcl_pmic_field_write(PMIC_ENUM_RG_VGPU12_FCCM, pLdoBuckCtrl->mode);
1676 return_val = STATUS_OK;
1677 }
1678 break;
1679
1680 case VPROC1:
1681 {
1682 dcl_pmic_field_write(PMIC_ENUM_RG_VPROC1_FCCM, pLdoBuckCtrl->mode);
1683 return_val = STATUS_OK;
1684 }
1685 break;
1686
1687 case VPROC2:
1688 {
1689 dcl_pmic_field_write(PMIC_ENUM_RG_VPROC2_FCCM, pLdoBuckCtrl->mode);
1690 return_val = STATUS_OK;
1691 }
1692 break;
1693
1694 case VPU:
1695 {
1696 dcl_pmic_field_write(PMIC_ENUM_RG_VPU_FCCM, pLdoBuckCtrl->mode);
1697 return_val = STATUS_OK;
1698 }
1699 break;
1700
1701 default:
1702 return_val = STATUS_UNSUPPORTED;
1703 break;
1704 }
1705 }
1706 break;
1707
1708 case LDO_BUCK_SET_OP_EN:
1709 {
1710 PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
1711
1712 kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << RG_BUCK_LDO_SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << RG_BUCK_LDO_HW0_OP_EN_SHIFT) |
1713 (pLdoBuckCtrl->hw1_op_en << RG_BUCK_LDO_HW1_OP_EN_SHIFT) | (pLdoBuckCtrl->hw2_op_en << RG_BUCK_LDO_HW2_OP_EN_SHIFT));
1714
1715 switch(pLdoBuckCtrl->mod)
1716 {
1717 case VMODEM:
1718 {
1719 pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_SET_ADDR, mode);
1720 return_val = STATUS_OK;
1721 }
1722 break;
1723
1724 case VSIM1:
1725 {
1726 pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_SET_ADDR, mode);
1727 return_val = STATUS_OK;
1728 }
1729 break;
1730
1731 case VSIM2:
1732 {
1733 pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_SET_ADDR, mode);
1734 return_val = STATUS_OK;
1735 }
1736 break;
1737
1738 case VFE28:
1739 {
1740 pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_SET_ADDR, mode);
1741 return_val = STATUS_OK;
1742 }
1743 break;
1744
1745 case VRF18:
1746 {
1747 pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_SET_ADDR, mode);
1748 return_val = STATUS_OK;
1749 }
1750 break;
1751
1752 case VRF12:
1753 {
1754 pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_SET_ADDR, mode);
1755 return_val = STATUS_OK;
1756 }
1757 break;
1758
1759 case VGPU11:
1760 {
1761 pmic_EM_reg_write(PMIC_RG_BUCK_VGPU11_OP_EN_SET_ADDR, mode);
1762 return_val = STATUS_OK;
1763 }
1764 break;
1765
1766 case VGPU12:
1767 {
1768 pmic_EM_reg_write(PMIC_RG_BUCK_VGPU12_OP_EN_SET_ADDR, mode);
1769 return_val = STATUS_OK;
1770 }
1771 break;
1772
1773 case VPROC1:
1774 {
1775 pmic_EM_reg_write(PMIC_RG_BUCK_VPROC1_OP_EN_SET_ADDR, mode);
1776 return_val = STATUS_OK;
1777 }
1778 break;
1779
1780 case VPROC2:
1781 {
1782 pmic_EM_reg_write(PMIC_RG_BUCK_VPROC2_OP_EN_SET_ADDR, mode);
1783 return_val = STATUS_OK;
1784 }
1785 break;
1786
1787 case VPU:
1788 {
1789 pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_EN_SET_ADDR, mode);
1790 return_val = STATUS_OK;
1791 }
1792 break;
1793
1794 default:
1795 return_val = STATUS_UNSUPPORTED;
1796 break;
1797 }
1798 }
1799 break;
1800
1801 case LDO_BUCK_CLR_OP_EN:
1802 {
1803 PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
1804
1805 kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << RG_BUCK_LDO_SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << RG_BUCK_LDO_HW0_OP_EN_SHIFT) |
1806 (pLdoBuckCtrl->hw1_op_en << RG_BUCK_LDO_HW1_OP_EN_SHIFT) | (pLdoBuckCtrl->hw2_op_en << RG_BUCK_LDO_HW2_OP_EN_SHIFT));
1807
1808 switch(pLdoBuckCtrl->mod)
1809 {
1810 case VMODEM:
1811 {
1812 pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_CLR_ADDR, mode);
1813 return_val = STATUS_OK;
1814 }
1815 break;
1816
1817 case VSIM1:
1818 {
1819 pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_CLR_ADDR, mode);
1820 return_val = STATUS_OK;
1821 }
1822 break;
1823
1824 case VSIM2:
1825 {
1826 pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_CLR_ADDR, mode);
1827 return_val = STATUS_OK;
1828 }
1829 break;
1830
1831 case VFE28:
1832 {
1833 pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_CLR_ADDR, mode);
1834 return_val = STATUS_OK;
1835 }
1836 break;
1837
1838 case VRF18:
1839 {
1840 pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_CLR_ADDR, mode);
1841 return_val = STATUS_OK;
1842 }
1843 break;
1844
1845 case VRF12:
1846 {
1847 pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_CLR_ADDR, mode);
1848 return_val = STATUS_OK;
1849 }
1850 break;
1851
1852 case VGPU11:
1853 {
1854 pmic_EM_reg_write(PMIC_RG_BUCK_VGPU11_OP_EN_CLR_ADDR, mode);
1855 return_val = STATUS_OK;
1856 }
1857 break;
1858
1859 case VGPU12:
1860 {
1861 pmic_EM_reg_write(PMIC_RG_BUCK_VGPU12_OP_EN_CLR_ADDR, mode);
1862 return_val = STATUS_OK;
1863 }
1864 break;
1865
1866 case VPROC1:
1867 {
1868 pmic_EM_reg_write(PMIC_RG_BUCK_VPROC1_OP_EN_CLR_ADDR, mode);
1869 return_val = STATUS_OK;
1870 }
1871 break;
1872
1873 case VPROC2:
1874 {
1875 pmic_EM_reg_write(PMIC_RG_BUCK_VPROC2_OP_EN_CLR_ADDR, mode);
1876 return_val = STATUS_OK;
1877 }
1878 break;
1879
1880 case VPU:
1881 {
1882 pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_EN_CLR_ADDR, mode);
1883 return_val = STATUS_OK;
1884 }
1885 break;
1886
1887 default:
1888 return_val = STATUS_UNSUPPORTED;
1889 break;
1890 }
1891 }
1892 break;
1893
1894 case LDO_BUCK_SET_HW_OP_CFG:
1895 {
1896 PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckSetHwOp);
1897
1898 kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << RG_BUCK_LDO_HW0_OP_CFG_SHIFT) |
1899 (pLdoBuckCtrl->hw1_op_cfg << RG_BUCK_LDO_HW1_OP_CFG_SHIFT) |
1900 (pLdoBuckCtrl->hw2_op_cfg << RG_BUCK_LDO_HW2_OP_CFG_SHIFT));
1901
1902 switch(pLdoBuckCtrl->mod)
1903 {
1904 case VMODEM:
1905 {
1906 pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_SET_ADDR, value);
1907 return_val = STATUS_OK;
1908 }
1909 break;
1910
1911 case VSIM1:
1912 {
1913 pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_SET_ADDR, value);
1914 return_val = STATUS_OK;
1915 }
1916 break;
1917
1918 case VSIM2:
1919 {
1920 pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_SET_ADDR, value);
1921 return_val = STATUS_OK;
1922 }
1923 break;
1924
1925 case VFE28:
1926 {
1927 pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_SET_ADDR, value);
1928 return_val = STATUS_OK;
1929 }
1930 break;
1931
1932 case VRF18:
1933 {
1934 pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_SET_ADDR, value);
1935 return_val = STATUS_OK;
1936 }
1937 break;
1938
1939 case VRF12:
1940 {
1941 pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_SET_ADDR, value);
1942 return_val = STATUS_OK;
1943 }
1944 break;
1945
1946 case VGPU11:
1947 {
1948 pmic_EM_reg_write(PMIC_RG_BUCK_VGPU11_OP_CFG_SET_ADDR, value);
1949 return_val = STATUS_OK;
1950 }
1951 break;
1952
1953 case VGPU12:
1954 {
1955 pmic_EM_reg_write(PMIC_RG_BUCK_VGPU12_OP_CFG_SET_ADDR, value);
1956 return_val = STATUS_OK;
1957 }
1958 break;
1959
1960 case VPROC1:
1961 {
1962 pmic_EM_reg_write(PMIC_RG_BUCK_VPROC1_OP_CFG_SET_ADDR, value);
1963 return_val = STATUS_OK;
1964 }
1965 break;
1966
1967 case VPROC2:
1968 {
1969 pmic_EM_reg_write(PMIC_RG_BUCK_VPROC2_OP_CFG_SET_ADDR, value);
1970 return_val = STATUS_OK;
1971 }
1972 break;
1973
1974 case VPU:
1975 {
1976 pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_CFG_SET_ADDR, value);
1977 return_val = STATUS_OK;
1978 }
1979 break;
1980
1981 default:
1982 return_val = STATUS_UNSUPPORTED;
1983 break;
1984 }
1985 }
1986 break;
1987
1988 case LDO_BUCK_CLR_HW_OP_CFG:
1989 {
1990 PMU_CTRL_LDO_BUCK_CLR_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckClrHwOp);
1991
1992 kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << RG_BUCK_LDO_HW0_OP_CFG_SHIFT) |
1993 (pLdoBuckCtrl->hw1_op_cfg << RG_BUCK_LDO_HW1_OP_CFG_SHIFT) |
1994 (pLdoBuckCtrl->hw2_op_cfg << RG_BUCK_LDO_HW2_OP_CFG_SHIFT));
1995
1996 switch(pLdoBuckCtrl->mod)
1997 {
1998 case VMODEM:
1999 {
2000 pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_ADDR, value);
2001 return_val = STATUS_OK;
2002 }
2003 break;
2004
2005 case VSIM1:
2006 {
2007 pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_CLR_ADDR, value);
2008 return_val = STATUS_OK;
2009 }
2010 break;
2011
2012 case VSIM2:
2013 {
2014 pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_CLR_ADDR, value);
2015 return_val = STATUS_OK;
2016 }
2017 break;
2018
2019 case VFE28:
2020 {
2021 pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_CLR_ADDR, value);
2022 return_val = STATUS_OK;
2023 }
2024 break;
2025
2026 case VRF18:
2027 {
2028 pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_CLR_ADDR, value);
2029 return_val = STATUS_OK;
2030 }
2031 break;
2032
2033 case VRF12:
2034 {
2035 pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_CLR_ADDR, value);
2036 return_val = STATUS_OK;
2037 }
2038 break;
2039
2040 case VGPU11:
2041 {
2042 pmic_EM_reg_write(PMIC_RG_BUCK_VGPU11_OP_CFG_CLR_ADDR, value);
2043 return_val = STATUS_OK;
2044 }
2045 break;
2046
2047 case VGPU12:
2048 {
2049 pmic_EM_reg_write(PMIC_RG_BUCK_VGPU12_OP_CFG_CLR_ADDR, value);
2050 return_val = STATUS_OK;
2051 }
2052 break;
2053
2054 case VPROC1:
2055 {
2056 pmic_EM_reg_write(PMIC_RG_BUCK_VPROC1_OP_CFG_CLR_ADDR, value);
2057 return_val = STATUS_OK;
2058 }
2059 break;
2060
2061 case VPROC2:
2062 {
2063 pmic_EM_reg_write(PMIC_RG_BUCK_VPROC2_OP_CFG_CLR_ADDR, value);
2064 return_val = STATUS_OK;
2065 }
2066 break;
2067
2068 case VPU:
2069 {
2070 pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_CFG_CLR_ADDR, value);
2071 return_val = STATUS_OK;
2072 }
2073 break;
2074
2075 default:
2076 return_val = STATUS_UNSUPPORTED;
2077 break;
2078 }
2079 }
2080 break;
2081
2082 case LDO_BUCK_SET_VOLTAGE:
2083 {
2084 PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
2085 regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
2086
2087 switch(pLdoBuckCtrl->mod)
2088 {
2089 case VSIM1:
2090 {
2091 dcl_pmic_field_write(PMIC_ENUM_RG_VSIM1_VOSEL, regVal);
2092 return_val = STATUS_OK;
2093 }
2094 break;
2095
2096 case VSIM2:
2097 {
2098 dcl_pmic_field_write(PMIC_ENUM_RG_VSIM2_VOSEL, regVal);
2099 return_val = STATUS_OK;
2100 }
2101 break;
2102
2103 case VPA_SW:
2104 {
2105 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_VOSEL, regVal);
2106 return_val = STATUS_OK;
2107 }
2108 break;
2109
2110 case VXO22:
2111 {
2112 dcl_pmic_field_write(PMIC_ENUM_RG_VXO22_VOSEL, regVal);
2113 return_val = STATUS_OK;
2114 }
2115 break;
2116
2117 default:
2118 return_val = STATUS_UNSUPPORTED;
2119 break;
2120 }
2121 }
2122 break;
2123
2124
2125 case LDO_BUCK_GET_VOLTAGE:
2126 {
2127 PMU_CTRL_LDO_BUCK_GET_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckGetVolt);
2128
2129 switch(pLdoBuckCtrl->mod)
2130 {
2131 case VMODEM:
2132 {
2133 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VMODEM_VOSEL);
2134 return_val = STATUS_OK;
2135 }
2136 break;
2137
2138 case VSRAM_MD:
2139 {
2140 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_MD_VOSEL);
2141 return_val = STATUS_OK;
2142 }
2143 break;
2144
2145 case VSRAM_OTHERS:
2146 {
2147 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_OTHERS_VOSEL);
2148 return_val = STATUS_OK;
2149 }
2150 break;
2151
2152 case VGPU11:
2153 {
2154 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VGPU11_VOSEL);
2155 return_val = STATUS_OK;
2156 }
2157 break;
2158
2159 case VGPU12:
2160 {
2161 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VGPU12_VOSEL);
2162 return_val = STATUS_OK;
2163 }
2164 break;
2165
2166 case VSRAM_PROC1:
2167 {
2168 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_PROC1_VOSEL);
2169 return_val = STATUS_OK;
2170 }
2171 break;
2172
2173 case VPROC1:
2174 {
2175 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VPROC1_VOSEL);
2176 return_val = STATUS_OK;
2177 }
2178 break;
2179
2180 case VSRAM_PROC2:
2181 {
2182 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VSRAM_PROC2_VOSEL);
2183 return_val = STATUS_OK;
2184 }
2185 break;
2186
2187 case VPROC2:
2188 {
2189 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VPROC2_VOSEL);
2190 return_val = STATUS_OK;
2191 }
2192 break;
2193
2194 case VPU:
2195 {
2196 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VPU_VOSEL);
2197 return_val = STATUS_OK;
2198 }
2199 break;
2200
2201 default:
2202 return_val = STATUS_UNSUPPORTED;
2203 break;
2204 }
2205 }
2206 break;
2207
2208 case VPA_GET_VOLTAGE_LIST:
2209 {
2210 PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
2211 pVpaCtrl->pVoltageList = vpa_vosel;
2212 pVpaCtrl->number = GETARRNUM(vpa_vosel);
2213 return_val = STATUS_OK;
2214 }
2215 break;
2216
2217 case ADC_SET_RQST:
2218 {
2219 //PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
2220 if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
2221 {
2222 DEBUG_ASSERT(0);
2223 MODEM_WARNING_MESSAGE(0, "ADC_SET_RQST error");
2224 }
2225 // Enable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
2226 pmic_EM_reg_write(PMIC_AUXADC_RQST_CH7_BY_MD_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
2227 AUXADC_Status = AUXADC_READ_REQUEST;
2228 return_val = STATUS_OK;
2229 }
2230 break;
2231
2232
2233 case ADC_GET_RDY_MD:
2234 {
2235 PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
2236 pAdcCtrl->status = (DCL_BOOL)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_RDY_CH7_BY_MD);
2237 if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
2238 {
2239 DEBUG_ASSERT(0);
2240 MODEM_WARNING_MESSAGE(0, "ADC_GET_RDY_MD error");
2241 }
2242
2243 if(pAdcCtrl->status == DCL_TRUE)
2244 {
2245 AUXADC_Status = AUXADC_READ_READY;
2246 }
2247 else
2248 {
2249 AUXADC_Status = AUXADC_READ_BUSY;
2250 }
2251
2252 return_val = STATUS_OK;
2253 }
2254 break;
2255
2256 case ADC_GET_OUT_MD:
2257 {
2258 PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
2259 if(AUXADC_Status != AUXADC_READ_READY)
2260 {
2261 DEBUG_ASSERT(0);
2262 MODEM_WARNING_MESSAGE(0, "ADC_GET_OUT_MD error");
2263 }
2264 pAdcCtrl->data = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_OUT_CH7_BY_MD);
2265 AUXADC_Status = AUXADC_READ_DATA;
2266 // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
2267
2268 return_val = STATUS_OK;
2269 }
2270 break;
2271
2272 case TOP_SET_SRCLKEN_IN_EN:
2273 {
2274 PMU_CTRL_TOP_SET_SRCLKEN_IN_EN *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInEn);
2275
2276 switch(pTopSrclkenCtrl->mod)
2277 {
2278 case PMIC_SRCLKEN_IN0:
2279 {
2280 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_EN, pTopSrclkenCtrl->mode);
2281 return_val = STATUS_OK;
2282 }
2283 break;
2284
2285 case PMIC_SRCLKEN_IN1:
2286 {
2287 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_EN, pTopSrclkenCtrl->mode);
2288 return_val = STATUS_OK;
2289 }
2290 break;
2291
2292 default:
2293 return_val = STATUS_UNSUPPORTED;
2294 break;
2295 }
2296 }
2297 break;
2298
2299 case TOP_SET_SRCLKEN_IN_MODE:
2300 {
2301 PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInMode);
2302
2303 switch(pTopSrclkenCtrl->mod)
2304 {
2305 case PMIC_SRCLKEN_IN0:
2306 {
2307 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_HW_MODE, pTopSrclkenCtrl->mode);
2308 return_val = STATUS_OK;
2309 }
2310 break;
2311
2312 case PMIC_SRCLKEN_IN1:
2313 {
2314 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_HW_MODE, pTopSrclkenCtrl->mode);
2315 return_val = STATUS_OK;
2316 }
2317 break;
2318
2319 default:
2320 return_val = STATUS_UNSUPPORTED;
2321 break;
2322 }
2323 }
2324 break;
2325
2326 case LDO_BUCK_SET_FPWM:
2327 {
2328 PMU_CTRL_LDO_BUCK_SET_FPWM *pLdoBuckSetFpwm = &(data->rPMULdoBuckSetFpwm);
2329
2330 switch(pLdoBuckSetFpwm->mod)
2331 {
2332 case VMODEM:
2333 {
2334 dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_FCCM, pLdoBuckSetFpwm->enable);
2335 return_val = STATUS_OK;
2336 }
2337 break;
2338
2339 case VGPU11:
2340 {
2341 dcl_pmic_field_write(PMIC_ENUM_RG_VGPU11_FCCM, pLdoBuckSetFpwm->enable);
2342 return_val = STATUS_OK;
2343 }
2344 break;
2345
2346 case VGPU12:
2347 {
2348 dcl_pmic_field_write(PMIC_ENUM_RG_VGPU12_FCCM, pLdoBuckSetFpwm->enable);
2349 return_val = STATUS_OK;
2350 }
2351 break;
2352
2353 case VPROC1:
2354 {
2355 dcl_pmic_field_write(PMIC_ENUM_RG_VPROC1_FCCM, pLdoBuckSetFpwm->enable);
2356 return_val = STATUS_OK;
2357 }
2358 break;
2359
2360 case VPROC2:
2361 {
2362 dcl_pmic_field_write(PMIC_ENUM_RG_VPROC2_FCCM, pLdoBuckSetFpwm->enable);
2363 return_val = STATUS_OK;
2364 }
2365 break;
2366
2367 case VPU:
2368 {
2369 dcl_pmic_field_write(PMIC_ENUM_RG_VPU_FCCM, pLdoBuckSetFpwm->enable);
2370 return_val = STATUS_OK;
2371 }
2372 break;
2373
2374 default:
2375 return_val = STATUS_UNSUPPORTED;
2376 break;
2377 }
2378 }
2379 break;
2380
2381 case LDO_BUCK_GET_FPWM:
2382 {
2383 PMU_CTRL_LDO_BUCK_GET_FPWM *pLdoBuckCtrl = &(data->rPMULdoBuckGetFpwm);
2384
2385 switch(pLdoBuckCtrl->mod)
2386 {
2387 case VMODEM:
2388 {
2389 pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VMODEM_FCCM);
2390 return_val = STATUS_OK;
2391 }
2392 break;
2393
2394 case VGPU11:
2395 {
2396 pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VGPU11_FCCM);
2397 return_val = STATUS_OK;
2398 }
2399 break;
2400
2401 case VGPU12:
2402 {
2403 pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VGPU12_FCCM);
2404 return_val = STATUS_OK;
2405 }
2406 break;
2407
2408 case VPROC1:
2409 {
2410 pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VPROC1_FCCM);
2411 return_val = STATUS_OK;
2412 }
2413 break;
2414
2415 case VPROC2:
2416 {
2417 pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VPROC2_FCCM);
2418 return_val = STATUS_OK;
2419 }
2420 break;
2421
2422 case VPU:
2423 {
2424 pLdoBuckCtrl->enable = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_VPU_FCCM);
2425 return_val = STATUS_OK;
2426 }
2427 break;
2428
2429 default:
2430 return_val = STATUS_UNSUPPORTED;
2431 break;
2432 }
2433 }
2434 break;
2435
2436 case DCXO_SET_REGISTER_VALUE:
2437 {
2438 PMU_CTRL_DCXO_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUDcxoSetRegisterValue);
2439
2440 pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
2441 return_val = STATUS_OK;
2442
2443#if 0
2444/* under construction !*/
2445/* under construction !*/
2446/* under construction !*/
2447/* under construction !*/
2448/* under construction !*/
2449/* under construction !*/
2450/* under construction !*/
2451/* under construction !*/
2452/* under construction !*/
2453#endif
2454 }
2455 break;
2456
2457 case DCXO_GET_REGISTER_VALUE:
2458 {
2459 PMU_CTRL_DCXO_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUDcxoGetRegisterValue);
2460 pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
2461 return_val = STATUS_OK;
2462 }
2463 break;
2464
2465 case MISC_SET_REGISTER_VALUE:
2466 {
2467 PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
2468#if defined(DCL_PMIC_PERMISSION_CONTROL)
2469 if(dcl_pmic_check_permission(pChrCtrl->offset)== DCL_TRUE)
2470#endif
2471 {
2472 pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
2473 return_val = STATUS_OK;
2474 }
2475#if defined(DCL_PMIC_PERMISSION_CONTROL)
2476 else
2477 {
2478 illegal_misc_set_register_value.offset = pChrCtrl->offset;
2479 illegal_misc_set_register_value.value = pChrCtrl->value;
2480 DEBUG_ASSERT(0);
2481 MODEM_WARNING_MESSAGE(0, "MISC_SET_REGISTER_VALUE error");
2482 }
2483#endif
2484 }
2485 break;
2486
2487 case MISC_GET_REGISTER_VALUE:
2488 {
2489 PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
2490 pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
2491 return_val = STATUS_OK;
2492 }
2493 break;
2494
2495 case LDO_BUCK_SET_VOCAL:
2496 {
2497 PMU_CTRL_LDO_BUCK_SET_VOCAL *pLdoBuckSetVocal = &(data->rPMULdoBuckSetVocal);
2498
2499 switch(pLdoBuckSetVocal->mod)
2500 {
2501 case VRF18_VOCAL:
2502 {
2503 dcl_pmic_field_write(PMIC_ENUM_RG_VRF18_VOCAL, pLdoBuckSetVocal->value);
2504 return_val = STATUS_OK;
2505 }
2506 break;
2507
2508 case VRF12_VOCAL:
2509 {
2510 dcl_pmic_field_write(PMIC_ENUM_RG_VRF12_VOCAL, pLdoBuckSetVocal->value);
2511 return_val = STATUS_OK;
2512 }
2513 break;
2514
2515 default:
2516 return_val = STATUS_UNSUPPORTED;
2517 break;
2518 }
2519 }
2520 break;
2521
2522 case LDO_BUCK_GET_VOCAL:
2523 {
2524 PMU_CTRL_LDO_BUCK_GET_VOCAL *pLdoBuckGetVocal = &(data->rPMULdoBuckGetVocal);
2525
2526 switch(pLdoBuckGetVocal->mod)
2527 {
2528 case VRF18_VOCAL:
2529 {
2530 pLdoBuckGetVocal->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF18_VOCAL);
2531 return_val = STATUS_OK;
2532 }
2533 break;
2534
2535 case VRF12_VOCAL:
2536 {
2537 pLdoBuckGetVocal->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF12_VOCAL);
2538 return_val = STATUS_OK;
2539 }
2540 break;
2541
2542 default:
2543 return_val = STATUS_UNSUPPORTED;
2544 break;
2545 }
2546 }
2547 break;
2548
2549
2550 case LDO_BUCK_SET_VOTRIM:
2551 {
2552 PMU_CTRL_LDO_BUCK_SET_VOTRIM *pLdoBuckSetVotrim = &(data->rPMULdoBuckSetVotrim);
2553
2554 switch(pLdoBuckSetVotrim->mod)
2555 {
2556 case VRF18_VOTRIM:
2557 {
2558 dcl_pmic_field_write(PMIC_ENUM_RG_VRF18_VOTRIM, pLdoBuckSetVotrim->value);
2559 return_val = STATUS_OK;
2560 }
2561 break;
2562
2563 case VRF12_VOTRIM:
2564 {
2565 dcl_pmic_field_write(PMIC_ENUM_RG_VRF12_VOTRIM, pLdoBuckSetVotrim->value);
2566 return_val = STATUS_OK;
2567 }
2568 break;
2569
2570 default:
2571 return_val = STATUS_UNSUPPORTED;
2572 break;
2573 }
2574 }
2575 break;
2576
2577 case LDO_BUCK_GET_VOTRIM:
2578 {
2579 PMU_CTRL_LDO_BUCK_GET_VOTRIM *pLdoBuckGetVotrim = &(data->rPMULdoBuckGetVotrim);
2580
2581 switch(pLdoBuckGetVotrim->mod)
2582 {
2583 case VRF18_VOTRIM:
2584 {
2585 pLdoBuckGetVotrim->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF18_VOTRIM);
2586 return_val = STATUS_OK;
2587 }
2588 break;
2589
2590 case VRF12_VOTRIM:
2591 {
2592 pLdoBuckGetVotrim->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF12_VOTRIM);
2593 return_val = STATUS_OK;
2594 }
2595 break;
2596
2597 default:
2598 return_val = STATUS_UNSUPPORTED;
2599 break;
2600 }
2601 }
2602 break;
2603
2604 case LDO_BUCK_SET_VPA_OC_SDN_STATUS:
2605 {
2606 PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_STATUS *pLdoBuckSetVpaOcSdnStatus = &(data->rPMULdoBuckSetVpaOcSdnStatus);
2607
2608 switch(pLdoBuckSetVpaOcSdnStatus->mod)
2609 {
2610 case VPA_OC_SDN_STATUS:
2611 {
2612 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_STATUS, pLdoBuckSetVpaOcSdnStatus->value);
2613 return_val = STATUS_OK;
2614 }
2615 break;
2616
2617 default:
2618 return_val = STATUS_UNSUPPORTED;
2619 break;
2620 }
2621 }
2622 break;
2623
2624 case LDO_BUCK_GET_VPA_OC_SDN_STATUS:
2625 {
2626 PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_STATUS *pLdoBuckGetVpaOcSdnStatus = &(data->rPMULdoBuckGetVpaOcSdnStatus);
2627
2628 switch(pLdoBuckGetVpaOcSdnStatus->mod)
2629 {
2630 case VPA_OC_SDN_STATUS:
2631 {
2632 pLdoBuckGetVpaOcSdnStatus->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_STATUS);
2633 return_val = STATUS_OK;
2634 }
2635 break;
2636
2637 default:
2638 return_val = STATUS_UNSUPPORTED;
2639 break;
2640 }
2641 }
2642 break;
2643
2644 case LDO_BUCK_SET_VPA_OC_SDN_EN:
2645 {
2646 PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_EN *pLdoBuckSetVpaOcSdnEn = &(data->rPMULdoBuckSetVpaOcSdnEn);
2647
2648 switch(pLdoBuckSetVpaOcSdnEn->mod)
2649 {
2650 case VPA_OC_SDN_EN:
2651 {
2652 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_EN, pLdoBuckSetVpaOcSdnEn->value);
2653 return_val = STATUS_OK;
2654 }
2655 break;
2656
2657 default:
2658 return_val = STATUS_UNSUPPORTED;
2659 break;
2660 }
2661 }
2662 break;
2663
2664 case LDO_BUCK_GET_VPA_OC_SDN_EN:
2665 {
2666 PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_EN *pLdoBuckGetVpaOcSdnEn = &(data->rPMULdoBuckGetVpaOcSdnEn);
2667
2668 switch(pLdoBuckGetVpaOcSdnEn->mod)
2669 {
2670 case VPA_OC_SDN_EN:
2671 {
2672 pLdoBuckGetVpaOcSdnEn->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_EN);
2673 return_val = STATUS_OK;
2674 }
2675 break;
2676
2677 default:
2678 return_val = STATUS_UNSUPPORTED;
2679 break;
2680 }
2681 }
2682 break;
2683
2684 case LDO_BUCK_SET_OP_MODE:
2685 {
2686 PMU_CTRL_LDO_BUCK_SET_OP_MODE *pLdoBuckSetOpMode = &(data->rPMULdoBuckSetOpMode);
2687
2688 switch(pLdoBuckSetOpMode->mod)
2689 {
2690 case VRF18:
2691 {
2692 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_MODE, pLdoBuckSetOpMode->value);
2693 return_val = STATUS_OK;
2694 }
2695 break;
2696
2697 case VRF12:
2698 {
2699 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_MODE, pLdoBuckSetOpMode->value);
2700 return_val = STATUS_OK;
2701 }
2702 break;
2703
2704 case VFE28:
2705 {
2706 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_MODE, pLdoBuckSetOpMode->value);
2707 return_val = STATUS_OK;
2708 }
2709 break;
2710
2711 default:
2712 return_val = STATUS_UNSUPPORTED;
2713 break;
2714 }
2715 }
2716 break;
2717
2718 case LDO_BUCK_SET_BUCK_HW_OP_MODE:
2719 {
2720 PMU_CTRL_LDO_BUCK_SET_BUCK_HW_OP_MODE *pLdoBuckSetBuckHwOpMode = &(data->rPMULdoBuckSetBuckHwOpMode);
2721
2722 kal_uint16 value =((pLdoBuckSetBuckHwOpMode->hw0_op_mode << PMIC_RG_BUCK_VPU_HW0_OP_MODE_SHIFT) |
2723 (pLdoBuckSetBuckHwOpMode->hw1_op_mode << PMIC_RG_BUCK_VPU_HW1_OP_MODE_SHIFT) |
2724 (pLdoBuckSetBuckHwOpMode->hw2_op_mode << PMIC_RG_BUCK_VPU_HW2_OP_MODE_SHIFT));
2725
2726 switch(pLdoBuckSetBuckHwOpMode->mod)
2727 {
2728 case VPU:
2729 {
2730 pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_MODE_SET_ADDR, value);
2731 return_val = STATUS_OK;
2732 }
2733 break;
2734
2735 default:
2736 return_val = STATUS_UNSUPPORTED;
2737 break;
2738 }
2739 }
2740 break;
2741
2742 case LDO_BUCK_CLR_BUCK_HW_OP_MODE:
2743 {
2744 PMU_CTRL_LDO_BUCK_CLR_BUCK_HW_OP_MODE *pLdoBuckClrBuckHwOpMode = &(data->rPMULdoBuckClrBuckHwOpMode);
2745
2746 kal_uint16 value =((pLdoBuckClrBuckHwOpMode->hw0_op_mode << PMIC_RG_BUCK_VPU_HW0_OP_MODE_SHIFT) |
2747 (pLdoBuckClrBuckHwOpMode->hw1_op_mode << PMIC_RG_BUCK_VPU_HW1_OP_MODE_SHIFT) |
2748 (pLdoBuckClrBuckHwOpMode->hw2_op_mode << PMIC_RG_BUCK_VPU_HW2_OP_MODE_SHIFT));
2749
2750 switch(pLdoBuckClrBuckHwOpMode->mod)
2751 {
2752 case VPU:
2753 {
2754 pmic_EM_reg_write(PMIC_RG_BUCK_VPU_OP_MODE_CLR_ADDR, value);
2755 return_val = STATUS_OK;
2756 }
2757 break;
2758
2759 default:
2760 return_val = STATUS_UNSUPPORTED;
2761 break;
2762 }
2763 }
2764 break;
2765
2766 case LDO_BUCK_SET_VOTER_VOLTAGE:
2767 {
2768 PMU_CTRL_LDO_BUCK_SET_VOTER_VOLTAGE *pLdoBuckSetVoterVoltage = &(data->rPMULdoBuckSetVoterVoltage);
2769
2770 switch(pLdoBuckSetVoterVoltage->mod)
2771 {
2772 case VS1:
2773 {
2774 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL, pLdoBuckSetVoterVoltage->value);
2775 return_val = STATUS_OK;
2776 }
2777 break;
2778
2779 case VS2:
2780 {
2781 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_VOSEL, pLdoBuckSetVoterVoltage->value);
2782 return_val = STATUS_OK;
2783 }
2784 break;
2785
2786 default:
2787 return_val = STATUS_UNSUPPORTED;
2788 break;
2789 }
2790 }
2791 break;
2792
2793 case MISC_GET_CID:
2794 {
2795 PMU_CTRL_MISC_GET_CID *pMiscGetCtrl = &(data->rPMUMiscGetCid);
2796 pMiscGetCtrl->cid_value = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_HWCID);
2797 return_val = STATUS_OK;
2798 }
2799 break;
2800
2801 default:
2802 return_val = STATUS_UNSUPPORTED;
2803 break;
2804 }
2805#if defined(DCL_PMIC_MODULE_CONTROL)
2806 current_dcl_handle = 0;
2807#endif
2808 return return_val;
2809
2810}
2811
2812extern void dcl_pmic_modem_only_init(void);
2813extern void PMIC_Read_All(void);
2814#if defined(PMIC_UNIT_TEST)
2815extern void PMIC_Read_All(void);
2816extern void PMIC_Unit_Test(void);
2817#endif
2818DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
2819{
2820 return dcl_pmic_byte_return(pmic_addr);
2821}
2822
2823void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
2824{
2825 dcl_pmic_byte_write(pmic_addr, value);
2826}
2827
2828void dcl_pmic_init(void){
2829 extern void pmic_wrap_dump_init(void);
2830 pmu_control_handler = PMIC_control_handler;
2831 pmu_parameter_size = GETARRNUM(pmu_parameter_table);
2832
2833 pmic_wrap_dump_init();
2834
2835 dcl_pmic_access_spinlock = kal_create_spinlock("pmic access");
2836 dcl_pmic_control_spinlock = kal_create_spinlock("pmic control");
2837
2838#if !defined(__SMART_PHONE_MODEM__)
2839 DrvPWRAP_Init();
2840#endif
2841 pmic_hw_version = dcl_pmic_byte_return(MT6359_HWCID);
2842 if (pmic_hw_version == 0x0) {
2843 DEBUG_ASSERT(0);
2844 MODEM_WARNING_MESSAGE(0, "Get HWCID error");
2845 }
2846
2847 PMIC_Read_All();
2848
2849#if !defined(__SMART_PHONE_MODEM__)
2850
2851/*
2852 if(DrvPWRAP_CheckCIPHER() == 1)
2853 dcl_pmic6355_modem_only_init();
2854 else
2855*/
2856 dcl_pmic_modem_only_init();
2857
2858#endif
2859
2860#if defined(PMIC_UNIT_TEST)
2861 PMIC_Read_All();
2862 PMIC_Unit_Test();
2863 PMIC_Read_All();
2864#endif
2865 pmic_init_done = DCL_TRUE;
2866
2867}
2868
2869void PMIC_Read_All(void)
2870{
2871 volatile kal_uint32 i,j;
2872 j=0;
2873 for (i = 0; i < PMIC_MAX_REG_NUM; i += 2){
2874 pmic_reg[i] = dcl_pmic_byte_return(i);
2875 while(j!=0x200){j++;}
2876 j=0;
2877 }
2878}
2879#if defined(PMIC_UNIT_TEST)
2880void PMIC_Unit_Test(void)
2881{
2882 {
2883 DCL_HANDLE handle;
2884 PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
2885 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2886 val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
2887 val.mod = VMIPI;
2888 DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
2889 DclPMU_Close(handle);
2890 }
2891
2892 {
2893 DCL_HANDLE handle;
2894 PMU_CTRL_LDO_BUCK_SET_EN val;
2895 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2896 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2897 val.mod = VMIPI;
2898 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2899 DclPMU_Close(handle);
2900 }
2901
2902 {
2903 DCL_HANDLE handle;
2904 PMU_CTRL_LDO_BUCK_SET_EN val;
2905 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2906 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2907 val.mod = VPA_SW;
2908 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2909 DclPMU_Close(handle);
2910 }
2911
2912 {
2913 DCL_HANDLE handle;
2914 PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
2915 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2916 val.mod=VPA_SW;
2917 val.voltage = PMU_VOLT_01_800000_V;
2918 /* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
2919 PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
2920 PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
2921 PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
2922 PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
2923 PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
2924 PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
2925 PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
2926 PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
2927 PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
2928 PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
2929 PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
2930 PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
2931 PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
2932 PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
2933 PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
2934 DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
2935 DclPMU_Close(handle);
2936 }
2937
2938 {
2939 DCL_HANDLE handle;
2940 PMU_CTRL_LDO_BUCK_SET_MODESET val;
2941 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2942 val.mod = VPA_SW;
2943 val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
2944 DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
2945 DclPMU_Close(handle);
2946 }
2947 {
2948 DCL_HANDLE handle;
2949 PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
2950 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2951 val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
2952 val.mod = VRF1;
2953 DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
2954 DclPMU_Close(handle);
2955 }
2956
2957 {
2958 DCL_HANDLE handle;
2959 PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
2960 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2961 val.sel = SRCLKEN_IN1_SEL;
2962 /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
2963 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
2964 val.mod = VRF1;
2965 DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
2966 DclPMU_Close(handle);
2967 }
2968
2969 {
2970 DCL_HANDLE handle;
2971 PMU_CTRL_LDO_BUCK_SET_MODESET val;
2972 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2973 val.mod = VRF1;
2974 val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
2975 DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
2976 DclPMU_Close(handle);
2977 }
2978
2979 {
2980 DCL_HANDLE handle;
2981 PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
2982 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2983 val.regval = 0x7; // (0x0~0xF)
2984 DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
2985 DclPMU_Close(handle);
2986 }
2987
2988 {
2989 DCL_HANDLE handle;
2990 PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
2991 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2992 val.regval = 0x7; // (0x0~0xF)
2993 DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
2994 DclPMU_Close(handle);
2995 }
2996
2997 {
2998 DCL_HANDLE handle;
2999 PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
3000 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
3001 // val.regval will be your request value ( no need do any shift)
3002 DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
3003 DclPMU_Close(handle);
3004 }
3005
3006 {
3007 DCL_HANDLE handle;
3008 PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
3009 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
3010 val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
3011 val.mod = VRF2;
3012 DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
3013 DclPMU_Close(handle);
3014 }
3015
3016 {
3017 DCL_HANDLE handle;
3018 PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
3019 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
3020 val.sel = SRCLKEN_IN1_SEL;
3021 /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
3022 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
3023 val.mod = VRF2;
3024 DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
3025 DclPMU_Close(handle);
3026 }
3027
3028 {
3029 DCL_HANDLE handle;
3030 PMU_CTRL_LDO_BUCK_SET_EN val;
3031 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
3032 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
3033 val.mod = VRF2;
3034 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
3035 DclPMU_Close(handle);
3036 }
3037
3038 {
3039 DCL_HANDLE handle;
3040 PMU_CTRL_LDO_BUCK_SET_MODESET val;
3041 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
3042 val.mod = VRF1;
3043 val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
3044 DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
3045 DclPMU_Close(handle);
3046 }
3047
3048 {
3049 DCL_HANDLE handle;
3050 PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
3051 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
3052 val.sel = SRCLKEN_IN1_SEL;
3053 /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
3054 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
3055 val.mod = VMIPI;
3056 DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
3057 DclPMU_Close(handle);
3058 }
3059
3060 {
3061 DCL_HANDLE handle;
3062 PMU_CTRL_LDO_BUCK_SET_EN val;
3063 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
3064 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
3065 val.mod = VSIM1;
3066 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
3067 DclPMU_Close(handle);
3068 }
3069
3070 {
3071 DCL_HANDLE handle;
3072 PMU_CTRL_LDO_BUCK_SET_EN val;
3073 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
3074 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
3075 val.mod = VSIM2;
3076 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
3077 DclPMU_Close(handle);
3078 }
3079
3080 {
3081 DCL_HANDLE handle;
3082 PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
3083 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
3084 val.mod=VSIM1;
3085 val.voltage = PMU_VOLT_01_800000_V;
3086 /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
3087 DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
3088 DclPMU_Close(handle);
3089 }
3090
3091 {
3092 DCL_HANDLE handle;
3093 PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
3094 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
3095 val.mod=VSIM2;
3096 val.voltage = PMU_VOLT_01_800000_V;
3097 /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
3098 DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
3099 DclPMU_Close(handle);
3100 }
3101}
3102#endif // End of #if defined(PMIC_UNIT_TEST)
3103
3104#endif // End of #if defined(PMIC_6359_REG_API)
3105