blob: 359cc683c31da06be96b2e760733a68e45f60b8a [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +08001/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2012
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * dcl_rstctl.c
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This Module defines DCL (Driver Common Layer) of the wdt driver.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 *
59 *
60 *------------------------------------------------------------------------------
61 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
62 *============================================================================
63 ****************************************************************************/
64#include "drv_comm.h"
65#include "rstctl_reg.h"
66#include "drv_rstctl.h"
67#include "intrCtrl.h"
68
69
70#include "dcl_wdt.h"
71#include "dcl.h"
72#include "kal_general_types.h"
73#include "kal_public_api.h"
74#include "kal_internal_api.h"
75#include "kal_ex_api.h"
76
77
78/*Begin: for share memory debug information dump*/
79#include "ex_mem_manager_public.h"
80#include "ex_public.h"
81#include "ccci_if.h"
82#include "us_timer.h"
83/*End: for share memory debug information dump*/
84
85
86#if defined(MT6290_S00)
87#include "drv_bsi.h"
88#define PMIC_6339_ANALDO_CON1_ADDR (0x21)
89/*VTCXO1_ON_CTRL : 0: SW controll by RG_VTXCO1_EN*/
90/* 1: SRCLKEN */
91#define VTCXO1_ON_CTRL_BIT (0x1)
92/*RG_VTCXO1_EN : 0: Disable */
93/* 1: Enable */
94#define RG_VTCXO1_EN_BIT (0x0)
95
96#endif
97
98// Global variable for DCL WDT API usage
99#define DCL_WDT_DEV_MAGIC_NUM (0x80000000)
100
101#define DCL_WDT_GET_DEV(handle_) ((handle_) & (~DCL_WDT_DEV_MAGIC_NUM))
102
103kal_atomic_uint32 dcl_wdt_handle_count = 0;
104
105
106// The event is presented by 32-bit variable
107kal_atomic_uint32 handle_assign[32];
108#define MAX_DCL_WDT_EVENT_NUM 1
109PFN_DCL_CALLBACK dcl_wdt_event_callback[MAX_DCL_WDT_EVENT_NUM];
110
111void dcl_wdt_hisr(){
112 // Try to call rgistered callback function
113 // Search mapping array and assign callback to specofic array entry
114 {
115 kal_uint32 i;
116 kal_uint32 event_bit;
117 // TODO: integrate the code bellow in the call back function mechanism.
118 for (i=0;i<MAX_DCL_WDT_EVENT_NUM;i++){
119 event_bit = 1 << i;
120 if ((event_bit & EVENT_WDT_TIMEOUT) != 0){
121 if (dcl_wdt_event_callback[i] != NULL){
122 dcl_wdt_event_callback[i](EVENT_WDT_TIMEOUT);
123 }
124 }
125 }
126 }
127}
128
129#if defined(MT6297)
130void dcl_wdt_ap2md_wdt_lisr()
131{
132 // Just Need to Trigger Fatal Error !!!
133 kal_fatal_error_handler(KAL_ERROR_CC_SAP_WDT_TIMEOUT_EXCP, 0);
134}
135
136void dcl_wdt_register_ap2md_wdt_isr()
137{
138 //IRQ_Register_LISR(IRQ_AP2MD_APWDT_IRQ_CODE, dcl_wdt_ap2md_wdt_lisr, "AP2MD WDT LISR");
139 //IRQSensitivity(IRQ_AP2MD_APWDT_IRQ_CODE, KAL_FALSE); // Low Level Active
140 IRQUnmask(IRQ_AP2MD_APWDT_IRQ_CODE);
141}
142#else
143#define dcl_wdt_register_ap2md_wdt_isr()
144#endif
145
146
147void dcl_wdt_lisr()
148{
149 mips_isr_mdwdt_handler();
150}
151
152
153void dcl_wdt_register_md_wdt_isr()
154{
155 //IRQ_Register_LISR(IRQ_MDWDT_CODE, dcl_wdt_lisr,"DCL WDT LISR");
156 //IRQSensitivity(IRQ_MDWDT_CODE,KAL_TRUE);
157 IRQUnmask(IRQ_MDWDT_CODE);
158}
159
160
161kal_bool dcl_wdt_lisr_register_flag = KAL_FALSE;
162void dcl_wdt_register_lisr(){
163 if (dcl_wdt_lisr_register_flag){
164 return;
165 }
166
167 dcl_wdt_register_md_wdt_isr();
168 dcl_wdt_register_ap2md_wdt_isr();
169 dcl_wdt_lisr_register_flag=KAL_TRUE;
170}
171
172/*************************************************************************
173* FUNCTION
174* DclWDT_Initialize
175*
176* DESCRIPTION
177* This function is to initialize WDT module
178*
179* PARAMETERS
180* N/A
181*
182* RETURNS
183* STATUS_OK
184*
185*************************************************************************/
186DCL_STATUS DclWDT_Initialize(void)
187{
188 kal_uint8 count = 0;
189 drv_rstctl_wdt_init();
190 for(count=0;count<32;count++)
191 kal_atomic_set(&(handle_assign[count]), 0);
192
193 kal_atomic_set(&dcl_wdt_handle_count, 0);
194
195 return STATUS_OK;
196}
197
198
199/*************************************************************************
200* FUNCTION
201* DclWDT_Open
202*
203* DESCRIPTION
204* This function is to open the WDT module and return a handle
205*
206* PARAMETERS
207* dev: only valid for DCL_WDT
208* flags: no sepcial flags is needed. Please use FLAGS_NONE
209*
210* RETURNS
211* DCL_HANDLE_INVALID: Open failed.
212* other value: a valid handle
213*
214*************************************************************************/
215DCL_HANDLE DclWDT_Open(DCL_DEV dev, DCL_FLAGS flags)
216{
217 kal_uint32 handle;
218 kal_uint8 index=0;
219
220
221 if (dev != DCL_WDT){
222 return DCL_HANDLE_INVALID; // Incorrecr device ID
223 }
224 for(index=0;index<32;index++)
225 {
226 if(kal_atomic_compare_and_swap_return(&handle_assign[index],0,1)==0)
227 break;
228 }
229 if (index==32)
230 return DCL_HANDLE_INVALID;
231 kal_atomic_inc(&dcl_wdt_handle_count);
232 handle = (DCL_WDT_DEV_MAGIC_NUM | index);
233
234 // Register DCL default lisr
235 return handle;
236}
237
238/*************************************************************************
239* FUNCTION
240* DclWDT_ReadData
241*
242* DESCRIPTION
243* This function is not supported for the WDT module now.
244*
245* PARAMETERS
246* N/A
247*
248* RETURNS
249* STATUS_UNSUPPORTED
250*
251*************************************************************************/
252DCL_STATUS DclWDT_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
253{
254 return STATUS_UNSUPPORTED;
255
256}
257
258/*************************************************************************
259* FUNCTION
260* DclWDT_WriteData
261*
262* DESCRIPTION
263* This function is not supported for the WDT module now.
264*
265* PARAMETERS
266* N/A
267*
268* RETURNS
269* STATUS_UNSUPPORTED
270*
271*************************************************************************/
272DCL_STATUS DclWDT_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options)
273{
274 return STATUS_UNSUPPORTED;
275}
276
277/*************************************************************************
278* FUNCTION
279* DclWDT_Configure
280*
281* DESCRIPTION
282* This function is not supported for the WDT module now.
283*
284* PARAMETERS
285* N/A
286*
287* RETURNS
288* STATUS_UNSUPPORTED
289*
290*************************************************************************/
291DCL_STATUS DclWDT_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure)
292{
293 return STATUS_UNSUPPORTED;
294
295}
296
297/*************************************************************************
298* FUNCTION
299* DclWDT_RegisterCallback
300*
301* DESCRIPTION
302* This function is to set callback function for the WDT module.
303*
304* PARAMETERS
305* handle: the returned handle value of DclWDT_Open
306* event: Supported events:
307* EVENT_WDT_TIMEOUT: Watch dog time out interrupt
308* callback: the callback function for registered events
309*
310* RETURNS
311* STATUS_OK: Successfully register the callback function.
312* STATUS_INVALID_DCL_HANDLE: It's a invalid handle.
313* STATUS_NOT_OPENED: The module has not been opened.
314* STATUS_INVALID_EVENT: The event parameter is invalid.
315*
316*************************************************************************/
317DCL_STATUS DclWDT_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
318{
319 //kal_uint32 i;
320 // Check magic number
321 if ((handle & DCL_WDT_DEV_MAGIC_NUM) != DCL_WDT_DEV_MAGIC_NUM){
322 DEBUG_ASSERT(0);
323 return STATUS_INVALID_DCL_HANDLE;
324 }
325
326 // Error check
327 if (kal_atomic_read(&dcl_wdt_handle_count) == 0){
328 DEBUG_ASSERT(0);
329 return STATUS_NOT_OPENED;
330 }
331 // Check if the passed-in event bitmap is supported or NOT
332 if (((kal_uint32)event & (~(EVENT_WDT_TIMEOUT))) != 0){
333 DEBUG_ASSERT(0);
334 return STATUS_INVALID_EVENT;
335 }
336
337 //i=DCL_WDT_GET_DEV(handle);
338
339 dcl_wdt_register_lisr();
340
341 return STATUS_OK;
342
343}
344
345
346/*************************************************************************
347* FUNCTION
348* DclWDT_Control
349*
350* DESCRIPTION
351* This function is to send command to control the WDT module.
352*
353* PARAMETERS
354* handle: The handle value returned from DclWDT_Open
355* cmd: a control command for WDT module
356* 1. WDT_CMD_ENABLE: to enable/disable WDT
357* 2. WDT_CMD_SET_EXT_POL: to set ploarity of external pin when WDT expired
358* 3. WDT_CMD_SET_EXT_RESET: to generate an external watchdog reset signal when WDT expired
359* 4. WDT_CMD_SET_VALUE: to set WDT count value
360* 5 WDT_CMD_RESTART: to restart counter
361* 6. WDT_CMD_DRV_RESET: to reset device
362* 7. WDT_CMD_ABN_RESET: to reset device with abnormal flag set to indicate it is a abnormal reset
363* 8. WDT_CMD_IRQ: to generate interrupt instead of reseting device
364* data: The data of the control command
365* 1. WDT_CMD_ENABLE: pointer to a WDT_CTRL_ENABLE_T structure
366* 2. WDT_CMD_SET_EXT_POL: pointer to a WDT_CTRL_SET_EXT_POL_T structure
367* 3. WDT_CMD_SET_EXT_RESET: pointer to a WDT_CTRL_SET_EXT_RESET_T structure
368* 4. WDT_CMD_SET_VALUE: pointer to a WDT_CTRL_SET_VALUE_T structure
369* 5 WDT_CMD_RESTART: A null pointer
370* 6. WDT_CMD_DRV_RESET: A null pointer
371* 7. WDT_CMD_ABN_RESET: A null pointer
372* 8. WDT_CMD_IRQ: pointer to a WDT_CTRL_IRQ_T structure
373*
374* RETURNS
375* STATUS_OK: command is executed successfully.
376* STATUS_FAIL: command is failed.
377* STATUS_INVALID_CMD: It's a invalid command.
378*
379*************************************************************************/
380DCL_STATUS DclWDT_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data)
381{
382 WDT_CTRL_GET_RSTINTERVAL_T *prst;
383 WDT_CTRL_SET_VALUE_T *prSetValue;
384 WDT_CTRL_ENABLE_T *prEnable;
385 WDT_CTRL_IRQ_T *prIRQ;
386 WDT_CTRL_DEBUG_T *prWDTDebug;
387 /*Begin: preserve debug information in share memory. */
388 volatile kal_uint32 callerAddr;
389 volatile kal_uint32 callerVPE;
390 volatile kal_uint32 usTime;
391 /*End: preserve debug information in share memory. */
392#if defined(MT6290_S00)
393 kal_uint16 val;
394#endif
395
396 if (sst_get_exception_count() == 0) {
397 // Check magic number
398 if ((handle & DCL_WDT_DEV_MAGIC_NUM) != DCL_WDT_DEV_MAGIC_NUM){
399 DEBUG_ASSERT(0);
400 return STATUS_INVALID_DCL_HANDLE;
401 }
402
403 // Error check
404 if (kal_atomic_read(&dcl_wdt_handle_count) == 0){
405 DEBUG_ASSERT(0);
406 return STATUS_NOT_OPENED;
407 }
408 }
409
410 /*Begin: preserve debug information in share memory. */
411 GET_RETURN_ADDRESS(callerAddr);
412 callerVPE = kal_get_current_vpe_id();
413 usTime = ust_get_current_time();
414 /*End: preserve debug information in share memory. */
415 switch (cmd)
416 {
417 case WDT_CMD_ENABLE:
418 prEnable = &(data->rWDTEnable);
419 /*Begin: preserve debug information in share memory. */
420 if(prEnable->fgEnable)
421 {
422 EMM_WriteDbgInfo(EMM_WDT1_EN_CALLER, (void*)&callerAddr);
423 EMM_WriteDbgInfo(EMM_WDT1_EN_TIME, (void*)&usTime);
424 EMM_WriteDbgInfo(EMM_WDT2_EN_CALLER, (void*)&callerAddr);
425 EMM_WriteDbgInfo(EMM_WDT2_EN_TIME, (void*)&usTime);
426 }
427 else
428 {
429 EMM_WriteDbgInfo(EMM_WDT1_DIS_CALLER, (void*)&callerAddr);
430 EMM_WriteDbgInfo(EMM_WDT1_DIS_TIME, (void*)&usTime);
431 EMM_WriteDbgInfo(EMM_WDT2_DIS_CALLER, (void*)&callerAddr);
432 EMM_WriteDbgInfo(EMM_WDT2_DIS_TIME, (void*)&usTime);
433 }
434 /*End: preserve debug information in share memory. */
435 drv_rstctl_wdt_enable((kal_bool)prEnable->fgEnable);
436 drv_rstctl_wdt_enable_aux((kal_bool)prEnable->fgEnable);
437 break;
438 case WDT_CMD_SET_EXT_POL:
439 //MT6290 wait for new feature release
440 break;
441 case WDT_CMD_SET_EXT_RESET:
442 //MT6290 wait for new feature release
443 break;
444 case WDT_CMD_SET_VALUE:
445 prSetValue = &(data->rWDTSetValue);
446 drv_rstctl_wdt_setInterval(prSetValue->u2Value);
447 drv_rstctl_wdt_setInterval_aux(prSetValue->u2Value);
448 break;
449 case WDT_CMD_RESTART:
450 drv_rstctl_restartWDT();
451 break;
452 case WDT_CMD_DRV_RESET:
453 /*Begin: preserve debug information in share memory. */
454 EMM_WriteDbgInfo(EMM_WDT_DRV_RST_CALLER, (void*)&callerAddr);
455 EMM_WriteDbgInfo(EMM_WDT_DRV_RST_TIME, (void*)&usTime);
456 /*End: preserve debug information in share memory. */
457 drv_rstctl_wdt_reset();
458 break;
459 case WDT_CMD_GET_RSTINTERVAL:
460 prst = &(data->rRstValue);
461 prst->rstInterval = drv_rstctl_wd_getInterval();
462 break;
463 case WDT_CMD_GET_RSTINTERVAL_AUX:
464 prst = &(data->rRstValue);
465 prst->rstInterval = drv_rstctl_wd_getInterval_aux();
466 break;
467 case WDT_CMD_ABN_RESET:
468 /*Begin: preserve debug information in share memory. */
469 EMM_WriteDbgInfo(EMM_WDT_ABN_RST_CALLER, (void*)&callerAddr);
470 EMM_WriteDbgInfo(EMM_WDT_ABN_RST_TIME, (void*)&usTime);
471 /*End: preserve debug information in share memory. */
472 drv_rstctl_wdt_abnReset();
473 break;
474 case WDT_CMD_IRQ:
475 prIRQ = &(data->rWDTIRQ);
476 drv_rstctl_wdt_enableInterrupt((kal_bool)prIRQ->fgEnable);
477 break;
478 case WDT_CMD_IRQ_AUX:
479 prIRQ = &(data->rWDTIRQ);
480 drv_rstctl_wdt_enableInterrupt_aux((kal_bool)prIRQ->fgEnable);
481 break;
482 case WDT_CMD_ENABLE_DEBUG:
483 prWDTDebug=&(data->rWDTDebug);
484 drv_rstctl_wdt_enableDebugMode(prWDTDebug->fgEnable);
485 break;
486 case WDT_CMD_CLR_CHECK:
487 prSetValue = &(data->rWDTSetValue);
488 EMM_WriteDbgInfo(EMM_VPE0_WDT_CLR_CHK_CALLER + ((prSetValue->u2Value)*3), (void*)&callerAddr);
489 EMM_WriteDbgInfo(EMM_VPE0_WDT_CLR_CHK_CALLERVPE + ((prSetValue->u2Value)*3), (void*)&callerVPE);
490 EMM_WriteDbgInfo(EMM_VPE0_WDT_CLR_CHK_TIME + ((prSetValue->u2Value)*3), (void*)&usTime);
491 drv_rstctl_clr_check_bit(prSetValue->u2Value);
492 break;
493 case WDT_CMD_SET_CHECK:
494 prSetValue = &(data->rWDTSetValue);
495 EMM_WriteDbgInfo(EMM_VPE0_WDT_SET_CHK_CALLER + ((prSetValue->u2Value)*3), (void*)&callerAddr);
496 EMM_WriteDbgInfo(EMM_VPE0_WDT_SET_CHK_CALLERVPE + ((prSetValue->u2Value)*3), (void*)&callerVPE);
497 EMM_WriteDbgInfo(EMM_VPE0_WDT_SET_CHK_TIME + ((prSetValue->u2Value)*3), (void*)&usTime);
498 drv_rstctl_set_check_bit(prSetValue->u2Value);
499 break;
500 case WDT_CMD_CLR_KICK:
501 prSetValue = &(data->rWDTSetValue);
502 drv_rstctl_clr_kick_bit(prSetValue->u2Value);
503 break;
504 case WDT_CMD_SET_KICK:
505 prSetValue = &(data->rWDTSetValue);
506 drv_rstctl_set_kick_bit(prSetValue->u2Value);
507 break;
508 default:
509 return STATUS_INVALID_CMD;
510 }
511 return STATUS_OK;
512}
513
514/*************************************************************************
515* FUNCTION
516* DclWDT_Close
517*
518* DESCRIPTION
519* This function is to close the WDT module.
520*
521* PARAMETERS
522* handle: the returned handle value of DclWDT_Open
523*
524* RETURNS
525* STATUS_OK
526*
527*************************************************************************/
528DCL_STATUS DclWDT_Close(DCL_HANDLE handle)
529{
530 kal_uint32 i;
531 // Check magic number
532 if ((handle & DCL_WDT_DEV_MAGIC_NUM) != DCL_WDT_DEV_MAGIC_NUM){
533 DEBUG_ASSERT(0);
534 return STATUS_INVALID_DCL_HANDLE;
535 }
536
537 // Error check
538 if (kal_atomic_read(&dcl_wdt_handle_count) == 0){
539 DEBUG_ASSERT(0);
540 return STATUS_NOT_OPENED;
541 }
542/*
543 // Clear all registered event callbacks for the specific handle
544 // Note: If we support multiple handles, we need to take care of the clear
545 {
546 kal_uint32 i;
547 for (i=0;i<MAX_DCL_WDT_EVENT_NUM;i++){
548 dcl_wdt_event_callback[i] = NULL;
549 }
550 }
551*/
552 i=(handle & ~DCL_WDT_DEV_MAGIC_NUM);
553
554 kal_atomic_set(&(handle_assign[i]), 0);
555 dcl_wdt_event_callback[i%MAX_DCL_WDT_EVENT_NUM] = NULL;
556
557 kal_atomic_dec(&dcl_wdt_handle_count);
558
559 return STATUS_OK;
560}
561
562