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192.168.1.100 / T800_MD / b0f5b85a5b9d69cbfa1dd990d559a4a9c7d8f2a6 / . / mcu / driver / devdrv / rstctl / src / drv_rstctl.c
blob: 3016adc3b64925bb85b984f2b103d9b368ea0023 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2012
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
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12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
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20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
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24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
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28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
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32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*******************************************************************************
37 * Filename:
38 * ---------
39 * drv_rstctl.c
40 *
41 * Project:
42 * --------
43 * TATAKA
44 *
45 * Description:
46 * ------------
47 *
48 *
49 * Author:
50 * Barry Hong
51 *
52 *
53 * ==========================================================================
54 * $Log$
55 *
56 * 09 03 2019 yuke.ren
57 * [MOLY00435227] Update MDRGU DrvTest Code
58 * update MDRGU drvtest code for RGU IT
59 *
60 * 08 26 2019 yao.xue
61 * [MOLY00434900] [VMOLY][PETRUS]sync Petrus Patch to APOLLO SQC branch:disable WDT in PETRUS ENG load
62 * sync Petrus Patch to APOLLO SQC branch:disable WDT in PETRUS ENG load
63 *
64 * 08 19 2019 yao.xue
65 * [MOLY00432830] [VMOLY.APOLLO.SQC]add the reboot timeout interval to 60s in case of SAP not reset MD within 4s.
66 * add the automatic reboot timeout interval to 60s in case of SAP not reset MD within 4s.
67 *
68 * 01 09 2019 yao.xue
69 * [MOLY00378064] Requirment ENG load Enable WDT
70 * ENG load open WDT
71 *
72 * 10 09 2018 yuke.ren
73 * [MOLY00357526] [MT6297] Rstctl driver porting
74 * .
75 *
76 * 04 10 2018 yuke.ren
77 * [MOLY00318371] Update RGU IT framework
78 * 1. Fix AP software reset MD
79 * 2. Unify reset delay unit to 512 1T 32K (15.6ms)
80 *
81 * 04 09 2018 da.li
82 * [MOLY00315163] [UMOLYE]Reset control driver porting for EIGER
83 * Fix driver warning for GCC6.
84 *
85 * 04 04 2018 yuke.ren
86 * [MOLY00318371] Update RGU IT framework
87 * Don't use low 8-bits to save rgu test accumulator
88 *
89 * 12 29 2017 da.li
90 * [MOLY00298401] [UMOLYA][TRUNK] WDT operation MACRO for MD INIT flow
91 * WDT operation MACRO for MD INIT flow.
92 *
93 * 12 29 2017 da.li
94 * [MOLY00298401] [UMOLYA][TRUNK] WDT operation MACRO for MD INIT flow
95 * WDT operation MACRO for MD INIT flow.
96 *
97 * 12 29 2017 da.li
98 * [MOLY00298401] [UMOLYA][TRUNK] WDT operation MACRO for MD INIT flow
99 * WDT operation MACRO for MD INIT flow.
100 *
101 * 12 29 2017 da.li
102 * [MOLY00298401] [UMOLYA][TRUNK] WDT operation MACRO for MD INIT flow
103 * WDT operation MACRO for MD INIT flow.
104 *
105 * 12 29 2017 da.li
106 * [MOLY00298401] [UMOLYA][TRUNK] WDT operation MACRO for MD INIT flow
107 * WDT operation MACRO for MD INIT flow.
108 *
109 * 12 29 2017 da.li
110 * [MOLY00298401] [UMOLYA][TRUNK] WDT operation MACRO for MD INIT flow
111 * WDT operation MACRO for MD INIT flow.
112 *
113 * 11 23 2017 da.li
114 * [MOLY00275013] [LR12] Enable WDT on ENG load
115 * WDT disabled on MD debug load.
116 *
117 * 10 25 2017 da.li
118 * [MOLY00281544] [PVT must resolve] [ASSERT] file:mcu/common/driver/devdrv/rstctl/src/drv_rstctl.c line:1119
119 * Update reset driver for RGU IT on FPGA.
120 *
121 * 10 19 2017 da.li
122 * [MOLY00281544] [PVT must resolve] [ASSERT] file:mcu/common/driver/devdrv/rstctl/src/drv_rstctl.c line:1119
123 * Re-send WDT IRQ to AP while AP wants to reset MD but without recieving WDT IRQ.
124 *
125 * 08 31 2017 da.li
126 * [MOLY00275013] [LR12] Enable WDT on ENG load
127 * Enable WDT1(only) on ENG load
128 *
129 * 05 23 2017 da.li
130 * [MOLY00248360] [BIANCO] Change IRQ mask API to HRT domain
131 * Build warning fix.
132 *
133 * 05 12 2017 da.li
134 * [MOLY00248360] [BIANCO] Change IRQ mask API to HRT domain
135 * change HRT API to disable interrupt.
136 *
137 * 04 06 2017 da.li
138 * [MOLY00233063] [BIANCO] rstctl driver update for RGU IT
139 * Remove warning.
140 *
141 * 03 03 2017 da.li
142 * [MOLY00233063] [BIANCO] rstctl driver update for RGU IT
143 * for BIANCO RGU IT.
144 *
145 * 02 16 2017 da.li
146 * [MOLY00211939] [Bianco] Reset control driver porting
147 * Remove redundant project macros.
148 *
149 * 11 17 2016 da.li
150 * [MOLY00211939] [Bianco] Reset control driver porting
151 * Update for RGU IT test.
152 * Add workaround to make reset environment more stable.
153 *
154 * 11 08 2016 da.li
155 * [MOLY00211939] [Bianco] Reset control driver porting
156 * Reset control driver porting from LR12
157 *
158 * 03 30 2016 owen.ho
159 * [MOLY00171832] [UMOLYA]
160 * Add compile option for GEN93 project
161 *
162 * 03 03 2016 owen.ho
163 * [MOLY00141883] [ELBRUS][FPGA]
164 * remove including file for MSBB violation
165 *
166 * 01 19 2016 owen.ho
167 * [MOLY00070771] [6291][FPGA]solve build error
168 * Update software reset enum
169 *
170 * 11 26 2015 owen.ho
171 * [MOLY00141883] [ELBRUS][FPGA] Add RGU IT framework for elbrus
172 *
173 * 10 13 2015 owen.ho
174 * [MOLY00141883] [ELBRUS][FPGA]
175 * Solve build error for irq name changed
176 *
177 * 09 25 2015 owen.ho
178 * [MOLY00141883] [ELBRUS][FPGA]
179 * Solve build error
180 *
181 * 09 25 2015 owen.ho
182 * [MOLY00141883] [ELBRUS][FPGA]
183 * Driver porting for Elbrus
184 *
185 * 08 17 2015 owen.ho
186 * [MOLY00070771] [6291][FPGA]solve build error
187 * Solve build error for build ELBRUS
188 *
189 * 07 24 2015 owen.ho
190 * [MOLY00070771] [6291][FPGA]solve build error
191 * Modify RGU IT framework for reset with delay cycle case
192 *
193 * 07 24 2015 owen.ho
194 * [MOLY00070771] [6291][FPGA]solve build error
195 * Fix IT framework for drvtest environment
196 *
197 * 07 03 2015 owen.ho
198 * [MOLY00070771] [6291][FPGA]solve build error Modify RGU drvtest & devdrv for JADE
199 *
200 * 06 11 2015 dennis.chueh
201 * [MOLY00070771] [6291][FPGA]solve build error
202 * Add compile option flag to restrict WDT enable without __PRODUCTION_RELEASE__ in abnrset api.
203 * Add BB_Register dump.
204 * Add EMMWriteDebugInfo for track caller info in share memory.
205 *
206 * 04 28 2015 dennis.chueh
207 * [MOLY00070771] [6291][FPGA]solve build error
208 * Add silent reboot in exception flow and trigger fatal error upon receving L1WDT IRQ.
209 *
210 * 04 27 2015 dennis.chueh
211 * [MOLY00070771] [6291][FPGA]solve build error
212 * Klocwork correction.
213 *
214 * 04 09 2015 owen.ho
215 * [MOLY00070771] [6291][FPGA]solve build error Update RGU IT framework
216 * .
217 *
218 * 03 30 2015 owen.ho
219 * [MOLY00070771] [6291][FPGA]solve build error:Update RGU IT framework
220 *
221 * 01 29 2015 dennis.chueh
222 * [MOLY00070771] [6291][FPGA]solve build error
223 * Correct g_ABNORMAL_RST_REG and g_ABNORMAL_RST_VAL.
224 *
225 * 01 28 2015 dennis.chueh
226 * [MOLY00070771] [6291][FPGA]solve build error
227 * Solve trunk's build error.
228 *
229 * 01 06 2015 dennis.chueh
230 * [MOLY00070771] [6291][FPGA]solve build error
231 * Chnage L1 boot slave address for L2copro's requirement that needs more memory space (256MB).
232 * Cooperate with HVT dummy load built by "make mcore_6291_drvtest_nand_booting".
233 *
234 * 12 26 2014 dennis.chueh
235 * [MOLY00070771] [6291][FPGA]solve build error
236 * Include system_coverage into ungate_l1core.
237 *
238 * 12 26 2014 dennis.chueh
239 * [MOLY00070771] [6291][FPGA]solve build error
240 * Disable WDTRR in UMOLY while in DRVTEST mode.
241 * Add system_coverage in _rst_set_system_ready_sts for different 3G/4G FPGA configuration.
242 *
243 * 12 22 2014 dennis.chueh
244 * [MOLY00070771] [6291][FPGA]solve build error
245 * Patch drv_rstctl.c for the condition that target system is not included in the system coverage.
246 *
247 * 12 16 2014 dennis.chueh
248 * [MOLY00070771] [6291][FPGA]solve build error
249 * Provide interface for USB WDT test.
250 *
251 * 12 15 2014 dennis.chueh
252 * [MOLY00070771] [6291][FPGA]solve build error
253 * Message layout adjustment.
254 *
255 * 12 15 2014 dennis.chueh
256 * [MOLY00070771] [6291][FPGA]solve build error
257 * Patch incorrect ARM7WDT WDTRR KEY setting.
258 *
259 * 12 09 2014 dennis.chueh
260 * [MOLY00070771] [6291][FPGA]solve build error
261 * Add ATEST_ENABLE to solve UMOLY build error.
262 *
263 * 12 09 2014 dennis.chueh
264 * [MOLY00070771] [6291][FPGA]solve build error
265 * Add ATEST_ENABLE to solve UMOLY build error.
266 *
267 * 12 09 2014 dennis.chueh
268 * [MOLY00070771] [6291][FPGA]solve build error
269 * RGU IT Framework
270 *
271 * 10 23 2014 vmick.lin
272 * [MOLY00062072] [MT6291][RGU] Implement
273 * Change IRQ name from MD_IRQID_MD_WDT to IRQ_MD_WDT_CODE
274 *
275 * 10 22 2014 dennis.chueh
276 * [MOLY00070771] [6291][FPGA]solve build error
277 * Modification software reset mechanis of RST_NFI and RST_NFI_AO.
278 * They need to be reset at the same time.
279 *
280 * 10 15 2014 dennis.chueh
281 * [MOLY00070771] [6291][FPGA]solve build error
282 * Add RST_SOE and RST_BUS_RECORD in drv_rstctl_sw_reset.
283 *
284 * 09 25 2014 dennis.chueh
285 * [MOLY00070771] [6291][FPGA]solve build error
286 * synchronization of definitions
287 *
288 * 08 27 2014 dennis.chueh
289 * [MOLY00070771] [6291][FPGA]solve build error.
290 * drv_rstctl.h add reset enumerators for APSYS IPs
291 * rstctl_reg.h 1.add definitions of APRGU control registers
292 * 2.add definitions of software reset for APSYS IPs
293 * drv_rstctl.c 1. enhance_RESET_ITEM_REGs to support APSYS/MDSYS IPs
294 * 2. enhacne _rst_resetIP to supoort APSYS/MDSYS IPs
295 * 3. enlarge the reset scope of drv_rstctl_sw_reset (including APSYS IPs. )
296 *
297 * 07 17 2014 dennis.chueh
298 * [MOLY00070771] [6291][FPGA]solve build error
299 * .Add drv_rstctl_sw_reset function for UMOLY IP functional test.
300 *
301 * 07 02 2014 dennis.chueh
302 * [MOLY00070771] [6291][FPGA]solve build error
303 * .
304 *
305 * 05 27 2014 vmick.lin
306 * [MOLY00062072] [TK6291][RGU] Implement
307 * .
308 * Disable Arm7/L1core bypass irq configuration while init
309 *
310 * 05 20 2014 vmick.lin
311 * [MOLY00062072] [TK6291][RGU] Implement
312 * .
313 *
314 * 05 20 2014 vmick.lin
315 * [MOLY00062072] [TK6291][RGU] Implement
316 * Because WDTIR default is 0x20000, so need to SW workaround
317 *
318 * 05 20 2014 vmick.lin
319 * [MOLY00062072] [TK6291][RGU] Implement
320 * .
321 *
322 * 04 14 2014 vmick.lin
323 * [MOLY00062072] [TK6291][RGU] Implement
324 * Resolve build error
325 *
326 * 04 10 2014 vmick.lin
327 * [MOLY00062072] [TK6291][RGU] Implement
328 * Fix build error
329 *
330 * 04 08 2014 vmick.lin
331 * [MOLY00062072] [TK6291][RGU] Implement: Fix build error temporarily
332 *
333 * 02 17 2014 vmick.lin
334 * [MOLY00056239] [6595] RGU integration test
335 * Stop call while system calling wdt reset
336 *
337 * 02 10 2014 vmick.lin
338 * [MOLY00055629] [MT6290][CPE_DONGLE_TYPE]CR4 watchdog reset in dormant mode
339 * clear wdt status while init
340 *
341 * 01 13 2014 vend_mick.lin
342 * [MOLY00051688] [MT6595 Bring-Up] Verify RGU driver
343 * Add accessing Top RGU retention data API for test
344 *
345 * 01 13 2014 vend_mick.lin
346 * [MOLY00051688] Verify RGU driver in ROME EVB
347 * Add whole system reset function to PSD1
348 *
349 * 12 27 2013 vend_mick.lin
350 * [MOLY00051688] Verify RGU driver in ROME EVB
351 * Change enum type RST_LTEL2 to original RST_L2COP
352 *
353 * 12 18 2013 vend_mick.lin
354 * [MOLY00050015] Add CLDMA sw reset in RGU driver
355 * Modify get_duration macro
356 *
357 * 12 12 2013 vend_mick.lin
358 * [MOLY00050015] Add CLDMA sw reset in RGU driver
359 * .
360 *
361 * 12 06 2013 vend_mick.lin
362 * [MOLY00049273] Add MT6595 RGU driver
363 * [MT6595] RGU code merge
364 *
365 * 10 30 2013 vend_mick.lin
366 * [MOLY00043729] Change watchdog timeout period for product release
367 * Change Watch dog timer to 4 sec and enable IRQ mode in phone type
368 *
369 * 10 04 2013 vend_mick.lin
370 * [MOLY00040268] SDIO transfer speed is very low after MOLY boot-up about 10 seconds
371 * ext_rst_b set low active as phone type request
372 *
373 * 09 25 2013 vend_mick.lin
374 * [MOLY00038948] Add infinite loop in sw watch dog reset function if irq_en not set
375 *
376 * 09 17 2013 vend_mick.lin
377 * [MOLY00038329] Ext_rst setting affects SDIO transmission speed
378 * change ext_rst polarity as high active as workaround solution
379 *
380 * 08 30 2013 vend_mick.lin
381 * [MOLY00035988] Change polarity of ext_rst signal to low active
382 * For phone type request
383 *
384 * 08 29 2013 vend_mick.lin
385 * [MOLY00035823] Delete warning message while build code of rstctrl part
386 * Delete waring message
387 *
388 * 08 15 2013 vend_mick.lin
389 * Fix CR: MOLY00033807 ; Dont reset APCLK after WDT
390 *
391 * 08 02 2013 barry.hong
392 * [MOLY00021294] [MT6290 Bring-up]6290 WDT driver update
393 * Fraom wei-de phone project request. set EXT_RST default to high active
394 *
395 * 07 17 2013 barry.hong
396 * [MOLY00021294] [MT6290 Bring-up]6290 WDT driver update
397 * .remove APCLK reset when USB call WD reset
398 *
399 * 05 30 2013 barry.hong
400 * [MOLY00013643] [MT6290 Bring-up]Modify Sleep mode driver
401 * .*: update for USB suspend IT test
402 *
403 * 05 29 2013 barry.hong
404 * [MOLY00021294] [MT6290 Bring-up]6290 WDT driver update
405 * .update 6290 WDT driver
406 *
407 * 05 09 2013 barry.hong
408 * [MOLY00021294] [MT6290 Bring-up]6290 WDT driver update
409 * .*:
410 * 1.Add drv_rstctl_wd_clrCnt API to clear WD CNT
411 * 2.Modify drv_rstctl_wd_rst_set_bitmap for U2 suspend wakeup not reset APCLK request
412 *
413 * 05 02 2013 barry.hong
414 * [MOLY00021294] [MT6290 Bring-up]6290 WDT driver update
415 * .change g_ABNORMAL_RST_VAL define to WDT_RSTINTERVAL_VALUE
416 *
417 * 03 08 2013 barry.hong
418 * [MOLY00011608] MT6290 MOLY fake API remove
419 * .remove fakeAPI
420 *
421 * 02 04 2013 barry.hong
422 * [MOLY00009902] MT7208 rename
423 * MT7208 rename to MT6290.
424 *
425 * 11 20 2012 barry.hong
426 * [MOLY00006416] Update Driver for MT6290 FPGA 20121105_MD_a4_b12_cx
427 * .merge TATAKA driver to MOLY
428 ****************************************************************************/
429
430#include "drv_features_wdt.h"
431#include "drv_comm.h"
432
433#include "rstctl_reg.h"
434#include "drv_rstctl.h"
435#include "intrCtrl.h"
436#include "us_timer.h"
437
438#include "dcl.h"
439#include "kal_general_types.h"
440#include "kal_public_api.h"
441#include "kal_hrt_api.h"
442#include "ex_public.h" /*Include this header file for register BBreg dump*/
443#include "kal_internal_api.h"
444
445#if defined(ATEST_ENABLE)
446#include "drvtest_sm.h"
447#endif
448#if !defined(DRV_RSTCTL_OFF)
449
450extern kal_uint32 *WDT_SET_KICKBIT_BASE;
451extern kal_uint32 *WDT_SET_CHECKBIT_BASE;
452extern kal_uint32 *WDT_CLR_CHECKBIT_BASE;
453//extern void MIPSGIC_LOCAL_IRQMask(LOCAL_IRQ_T irq);
454
455/*Global vaialbe for BBreg dump*/
456#if defined(__MTK_TARGET__)
457 EX_BBREG_DUMP Pcore_RGU_dump;
458 const kal_uint32 Pcore_RGU_dump_regions[] = {
459 BASE_ADDR_MDRSTCTL, 0x0360, 4,
460 };
461#endif
462
463#define UT_DELAY_LOOP(n) \
464do{ \
465 volatile register kal_uint32 _delay_loop; \
466 for(_delay_loop = 0; _delay_loop < n; _delay_loop++) { ; } \
467}while(0)
468
469#define _RESET_ITEM_REGs(reg, item_r, waitLoopCnt) do { \
470 {\
471 DRV_WriteReg32(reg, (item_r));\
472 DRV_WriteReg32(REG_MDRSTCTL_SRCMR, RSTCTL_SRCMR_KEY_SWRST);\
473 UT_DELAY_LOOP(waitLoopCnt);\
474 DRV_WriteReg32(reg, 0);\
475 DRV_WriteReg32(REG_MDRSTCTL_SRCMR, RSTCTL_SRCMR_KEY_SWRST);\
476 }\
477 } while(0)
478
479/*****************************************************************************
480 * Global/External Variable *
481 *****************************************************************************/
482
483const kal_uint32 g_WATCHDOG_RESTART_REG = REG_MDRSTCTL_WDTRR; //Externally referenced somewhere
484const kal_uint32 g_WATCHDOG_CTL_REG = REG_MDRSTCTL_WDTCR;
485#if defined (ATEST_ENABLE)
486const kal_uint32 g_WATCHDOG_RESTART_VALUE = (RSTCTL_WDTRR_WDT_RESTART); //Disable Restart function for DRVTEST.
487#else
488const kal_uint32 g_WATCHDOG_RESTART_VALUE = (RSTCTL_WDTRR_KEY | RSTCTL_WDTRR_WDT_RESTART); //Externally referenced somewhere
489#endif
490const kal_uint32 g_ABNORMAL_RST_REG = REG_MDRSTCTL_WDTIR;
491const kal_uint32 g_ABNORMAL_RST_REG_AUX = REG_MDRSTCTL_WDTIR_AUX;
492const kal_uint32 g_ABNORMAL_RST_VAL = WDT_RSTINTERVAL_VALUE;
493const kal_uint32 g_ABNORMAL_RST_VAL_AUX = WDT_RSTINTERVAL_VALUE2;
494
495void _rst_clrSwRstStatus(kal_uint32 reg, kal_uint32 statusMaskToClear)
496{
497 /* If status Mask == 0 -> clear ALL */
498 statusMaskToClear = (statusMaskToClear)?statusMaskToClear:0xffffffff;
499 DRV_WriteReg32(reg, statusMaskToClear);
500}
501
502void _rst_resetIP(kal_uint32 reg, kal_uint32 item_r, kal_uint32 waitLoopCnt)
503{
504 kal_uint32 rstStatus;
505 kal_uint32 timeout_cnt=0;
506 kal_uint32 sta_reg=0;
507
508 /* Reset IP */
509 _RESET_ITEM_REGs(reg, item_r,waitLoopCnt);
510
511 /* Check the status and clear it */
512 switch (reg)
513 {
514 case REG_MDRSTCTL_SRBER_MDSYS:
515 sta_reg = (REG_MDRSTCTL_SRSTR_MDSYS);
516 break;
517
518 //For Yts's reset CLDMA
519 case REG_APRSTCTL_SRBER_APINFRA:
520 sta_reg = (REG_APRSTCTL_SRSTR_APINFRA);
521 break;
522 case REG_APRSTCTL_SRBER_APPERI:
523 sta_reg = (REG_APRSTCTL_SRSTR_APPERI);
524 break;
525 default:
526 ASSERT(0); /*To prevent undefined status register address returned by default case.*/
527 break;
528 }
529
530 rstStatus = (DRV_Reg32(sta_reg)&item_r);
531
532
533 while((item_r != rstStatus) && timeout_cnt<10000)
534 {
535 rstStatus = DRV_Reg32(sta_reg);
536 timeout_cnt++;
537 };
538
539 ASSERT(timeout_cnt<10000);
540 ASSERT(item_r == rstStatus);
541
542 _rst_clrSwRstStatus(sta_reg, item_r);
543
544}
545
546/**
547 * @brief Procedure for software triggered reset process
548 * This procedure triggers software watchdog reset and wait for its completeness
549 * Note: It needs less than 1T(32k) (eaxtly 1T-2*bus clock period) to do reset after WDTSR changes
550 */
551static void _rst_swWdReset(void)
552{
553 DRV_WriteReg32(REG_MDRSTCTL_WDTER_MDSYS, 0xBFFFFFFF);
554 /* Always clear indication bits before reset */
555 DRV_WriteReg32(REG_MDRSTCTL_WDTSR,(RSTCTL_WDTSR_KEY)|(RSTCTL_WDTSR_STATUS_MASK << RSTCTL_WDTSR_STATUS_OFFSET));
556 /* Trigger watchdog reset immediately : We use software reset */
557 DRV_WriteReg32(REG_MDRSTCTL_SRCMR_SWDT, RSTCTL_SRCMR_KEY_SWDT);
558 DRV_Reg32(REG_MDRSTCTL_SRCMR_SWDT); /* Read the value of RSTCTL_SRCMR back to make sure the previous write operation is done */
559 while ((DRV_Reg32(REG_MDRSTCTL_WDTSR) & (RSTCTL_WDTSR_STATUS_MASK<<RSTCTL_WDTSR_STATUS_OFFSET)) == 0);
560 /*If irq_en not set, just while(1) to wait reset happen */
561 if(!(DRV_Reg32(REG_MDRSTCTL_WDTCR) & RSTCTL_WDTCR_WDT_IRQEN))
562 {
563 #if defined(ATEST_ENABLE)
564 dbg_print("[%s]Emulation of WHILE(1) for IRQEN not set.\r\n", __FUNCTION__);
565 #else
566 while(1);
567 #endif
568 }
569}
570
571static void _rst_swWdReset_aux(void)
572{
573 DRV_WriteReg32(REG_MDRSTCTL_WDTER_MDSYS, 0xBFFFFFFF);
574 /* Always clear indication bits before reset */
575 DRV_WriteReg32(REG_MDRSTCTL_WDTSR,(RSTCTL_WDTSR_KEY)|(RSTCTL_WDTSR_AUX_STATUS_MASK<<RSTCTL_WDTSR_AUX_STS_CLR_OFFSET));
576 /* Trigger watchdog reset immediately : We use software reset */
577 DRV_WriteReg32(REG_MDRSTCTL_SRCMR_SWDT, RSTCTL_AUX_SRCMR_KEY_SWDT);
578 DRV_Reg32(REG_MDRSTCTL_SRCMR_SWDT); /* Read the value of RSTCTL_SRCMR back to make sure the previous write operation is done */
579 while ((DRV_Reg32(REG_MDRSTCTL_WDTSR) & (RSTCTL_WDTSR_AUX_STATUS_MASK<<RSTCTL_WDTSR_AUX_STATUS_OFFSET)) == 0);
580 if(!(DRV_Reg32(REG_MDRSTCTL_WDTCR) & RSTCTL_WDTCR_AUX_WDT_IRQEN))
581 {
582 #if defined(ATEST_ENABLE)
583 dbg_print("[%s]Do nothing if IRQEN is not set.\r\n", __FUNCTION__);
584 #endif
585 }
586}
587
588#if !defined(DRV_WDT_SWRST)
589static void _rst_restartWDT(void)
590{
591 /* Simply reload watchdog counter */
592 DRV_WriteReg32(REG_MDRSTCTL_WDTRR, RSTCTL_WDTRR_KEY | RSTCTL_WDTRR_WDT_RESTART);
593}
594#endif
595
596void _rst_enableWdt(kal_uint32 wdtEnable, kal_uint32 wdtInterval)
597{
598 if (wdtEnable)
599 {
600 /* Set watchdog interval */
601 DRV_WriteReg32(REG_MDRSTCTL_WDTIR,
602 ((RSTCTL_WDTIR_KEY)|
603 ((wdtInterval & RSTCTL_WDTIR_INTERVAL_MASK) << RSTCTL_WDTIR_INTERVAL_OFFSET)));
604 /* Enable/disable watchdog */
605 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) |((DRV_Reg32(REG_MDRSTCTL_WDTCR))|RSTCTL_WDTCR_WDT_EN));
606 DRV_WriteReg32(REG_MDRSTCTL_WDTRR,((RSTCTL_WDTRR_KEY)|0x1));
607 }
608 else
609 {
610 /* Just simply set WDTCR for WDT disabling operation */
611 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) |((DRV_Reg32(REG_MDRSTCTL_WDTCR))&(~RSTCTL_WDTCR_WDT_EN)));
612 }
613}
614
615void _rst_enableWdt_aux(kal_uint32 wdtEnable, kal_uint32 wdtInterval)
616{
617 if (wdtEnable)
618 {
619 /* Set watchdog interval */
620 DRV_WriteReg32(REG_MDRSTCTL_WDTIR_AUX,
621 ((RSTCTL_WDTIR_AUX_KEY)|
622 ((wdtInterval & RSTCTL_WDTIR_INTERVAL_MASK) << RSTCTL_WDTIR_INTERVAL_OFFSET)));
623 /* Enable/disable watchdog */
624 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) |((DRV_Reg32(REG_MDRSTCTL_WDTCR))|RSTCTL_WDTCR_AUX_WDT_EN));
625 DRV_WriteReg32(REG_MDRSTCTL_WDTRR,((RSTCTL_WDTRR_KEY)|0x1));
626 }
627 else
628 {
629 /* Just simply set WDTCR for WDT disabling operation */
630 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) |((DRV_Reg32(REG_MDRSTCTL_WDTCR))&(~RSTCTL_WDTCR_AUX_WDT_EN)));
631 }
632}
633
634/*************************************************************************
635* FUNCTION
636* Get_WATCHDOG_BASE
637*
638* DESCRIPTION
639* This function is to get restart wd timer base address
640*
641* PARAMETERS
642* none
643*
644* RETURN VALUES
645* wd timer kick base address
646*
647*************************************************************************/
648kal_uint32 Get_WATCHDOG_BASE()
649{
650 return (REG_MDRSTCTL_KICK_BIT_SET);
651}
652
653/*************************************************************************
654* FUNCTION
655* Get_WATCHDOG_RESTART_CMD
656*
657* DESCRIPTION
658* This function is to get restart wd timer key
659*
660* PARAMETERS
661* none
662*
663* RETURN VALUES
664* wd timer kick command key
665*
666*************************************************************************/
667kal_uint32 Get_WATCHDOG_RESTART_CMD()
668{
669 kal_uint32 vpe_id;
670 vpe_id = (kal_uint32) kal_get_current_vpe_id();
671 #if defined (ATEST_ENABLE)
672 return (0x1 << vpe_id); //For drvtest, do not return WDTRR Key to prevent the test.
673 #else
674 return (((RSTCTL_MD_CHECK_AND_KICK_KEY + vpe_id) << RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET) | (0x1 << vpe_id));
675 #endif
676}
677
678void drv_rstctl_wd_disable(void)
679{
680 /* Just simply set WDTCR for WDT disabling operation */
681 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) |((DRV_Reg32(REG_MDRSTCTL_WDTCR))&(~RSTCTL_WDTCR_WDT_EN)));
682}
683
684void drv_rstctl_wd_disable_aux(void)
685{
686 /* Just simply set WDTCR for WDT2 disabling operation */
687 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) |((DRV_Reg32(REG_MDRSTCTL_WDTCR))&(~RSTCTL_WDTCR_AUX_WDT_EN)));
688}
689
690kal_bool drv_rstctl_disable_all_WDTs(void)
691{
692 drv_rstctl_wd_disable();
693 drv_rstctl_wd_disable_aux();
694 kal_uint32 timeout_count = 0;
695 while((((DRV_Reg32(REG_MDRSTCTL_WDTCR) & RSTCTL_WDTCR_AUX_WDT_EN)!=0) || ((DRV_Reg32(REG_MDRSTCTL_WDTCR) & RSTCTL_WDTCR_WDT_EN)!=0)) && (timeout_count < 10000))
696 timeout_count++;
697 if (timeout_count == 10000)
698 {
699 #if defined(ATEST_ENABLE)
700 dbg_print("ASSERT (RGU): <line: %d in function: %s>\r\n", __LINE__, __FUNCTION__); //This case should not happen.
701 #endif
702 return KAL_FALSE;
703 }
704 else
705 return KAL_TRUE;
706}
707
708/*************************************************************************
709* FUNCTION
710* drv_rstctl_wdt_enable
711*
712* DESCRIPTION
713* This function is used to on/off wd timer
714*
715* PARAMETERS
716* none
717*
718* RETURN VALUES
719* none
720*
721* NOTE
722* Need to restart wdt timer to apply this value
723*************************************************************************/
724void drv_rstctl_wdt_enable(kal_bool en)
725{
726 if (en == KAL_TRUE)
727 {
728 #if !defined(__WDT_DISABLE_BY_MD_DBG__)
729 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) |((DRV_Reg32(REG_MDRSTCTL_WDTCR))|RSTCTL_WDTCR_WDT_EN));
730 /*Reload wdt interval*/
731 DRV_WriteReg32(REG_MDRSTCTL_WDTRR, RSTCTL_WDTRR_KEY | RSTCTL_WDTRR_WDT_RESTART);
732 #endif
733 }
734 else
735 {
736 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) |((DRV_Reg32(REG_MDRSTCTL_WDTCR))&(~RSTCTL_WDTCR_WDT_EN)));
737 }
738}
739
740void drv_rstctl_wdt_enable_aux(kal_bool en)
741{
742 if (en == KAL_TRUE)
743 {
744 #if defined(MT6297) ||defined(MERCURY)//apollo ENG/USER LOAD enable WDT
745 #if !defined(__WDT_DISABLE_BY_MD_DBG__)
746 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) |((DRV_Reg32(REG_MDRSTCTL_WDTCR))|RSTCTL_WDTCR_AUX_WDT_EN));
747 /*Reload wdt interval*/
748 DRV_WriteReg32(REG_MDRSTCTL_WDTRR, RSTCTL_WDTRR_KEY | RSTCTL_WDTRR_WDT_RESTART);
749 #endif
750 #else//PETRUS ENG load not enable WDT
751 #if defined(__PRODUCTION_RELEASE__) && !defined(__WDT_DISABLE_BY_MD_DBG__)
752 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) |((DRV_Reg32(REG_MDRSTCTL_WDTCR))|RSTCTL_WDTCR_AUX_WDT_EN));
753 /*Reload wdt interval*/
754 DRV_WriteReg32(REG_MDRSTCTL_WDTRR, RSTCTL_WDTRR_KEY | RSTCTL_WDTRR_WDT_RESTART);
755 #endif
756 #endif
757 }
758 else
759 {
760 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) |((DRV_Reg32(REG_MDRSTCTL_WDTCR))&(~RSTCTL_WDTCR_AUX_WDT_EN)));
761 }
762}
763
764/*************************************************************************
765* FUNCTION
766* drv_rstctl_wdt_enableInterrupt
767*
768* DESCRIPTION
769* This function is used to on/off irq mode
770* reset or trigger interrupt while watchdog timout happening
771*
772* PARAMETERS
773* none
774*
775* RETURN VALUES
776* none
777*
778*************************************************************************/
779void drv_rstctl_wdt_enableInterrupt(kal_bool enable)
780{
781 if (enable == KAL_TRUE)
782 {
783 DRV_WriteReg32(REG_MDRSTCTL_WDTCR,(RSTCTL_WDTCR_KEY)|((DRV_Reg32(REG_MDRSTCTL_WDTCR)) | RSTCTL_WDTCR_WDT_IRQEN));
784 }
785 else
786 {
787 DRV_WriteReg32(REG_MDRSTCTL_WDTCR,(RSTCTL_WDTCR_KEY)|((DRV_Reg32(REG_MDRSTCTL_WDTCR)) & (~RSTCTL_WDTCR_WDT_IRQEN)));
788 }
789}
790
791void drv_rstctl_wdt_enableInterrupt_aux(kal_bool enable)
792{
793 if (enable == KAL_TRUE)
794 {
795 DRV_WriteReg32(REG_MDRSTCTL_WDTCR,(RSTCTL_WDTCR_KEY)|((DRV_Reg32(REG_MDRSTCTL_WDTCR)) | RSTCTL_WDTCR_AUX_WDT_IRQEN));
796 }
797 else
798 {
799 DRV_WriteReg32(REG_MDRSTCTL_WDTCR,(RSTCTL_WDTCR_KEY)|((DRV_Reg32(REG_MDRSTCTL_WDTCR)) & (~RSTCTL_WDTCR_AUX_WDT_IRQEN)));
800 }
801}
802
803/*************************************************************************
804* FUNCTION
805* drv_rstctl_wdt_setInterval
806*
807* DESCRIPTION
808* This function is used to set wd tiemr
809*
810* PARAMETERS
811* none
812*
813* RETURN VALUES
814* none
815*
816* NOTE
817* Need to restart wdt timer to apply this value
818*************************************************************************/
819void drv_rstctl_wdt_setInterval(kal_uint32 wdtInterval)
820{
821 /* Set watchdog interval */
822 DRV_WriteReg32(REG_MDRSTCTL_WDTIR,
823 ((RSTCTL_WDTIR_KEY)|
824 ((wdtInterval & RSTCTL_WDTIR_INTERVAL_MASK) << RSTCTL_WDTIR_INTERVAL_OFFSET)));
825}
826
827void drv_rstctl_wdt_setInterval_aux(kal_uint32 wdtInterval)
828{
829 /* Set watchdog interval */
830 DRV_WriteReg32(REG_MDRSTCTL_WDTIR_AUX,
831 ((RSTCTL_WDTIR_AUX_KEY)|
832 ((wdtInterval & RSTCTL_WDTIR_INTERVAL_MASK) << RSTCTL_WDTIR_INTERVAL_OFFSET)));
833}
834
835/*************************************************************************
836* FUNCTION
837* drv_rstctl_wd_getInterval
838*
839* DESCRIPTION
840* This function is used to get wd timer interval(uint:T(32k))
841*
842* PARAMETERS
843* none
844*
845* RETURN VALUES
846* none
847*************************************************************************/
848kal_uint32 drv_rstctl_wd_getInterval(void)
849{
850 return (kal_uint32)(RSTCTL_WDTIR_INTERVAL_MASK & DRV_Reg32(REG_MDRSTCTL_WDTIR));
851}
852
853kal_uint32 drv_rstctl_wd_getInterval_aux(void)
854{
855 return (kal_uint32)(RSTCTL_WDTIR_INTERVAL_MASK & DRV_Reg32(REG_MDRSTCTL_WDTIR_AUX));
856}
857
858/*************************************************************************
859* FUNCTION
860* drv_rstctl_wd_clrSta
861*
862* DESCRIPTION
863* This function is used to clear wdt status
864*
865* PARAMETERS
866* none
867*
868* RETURN VALUES
869* none
870*************************************************************************/
871void drv_rstctl_wd_clrSta(void)
872{
873 DRV_WriteReg32(REG_MDRSTCTL_WDTSR,(RSTCTL_WDTSR_KEY)|(RSTCTL_WDTSR_STATUS_MASK<<RSTCTL_WDTSR_STS_CLR_OFFSET));
874}
875
876void drv_rstctl_wd_clrSta_aux(void)
877{
878 DRV_WriteReg32(REG_MDRSTCTL_WDTSR,(RSTCTL_WDTSR_KEY)|(RSTCTL_WDTSR_AUX_STATUS_MASK<<RSTCTL_WDTSR_AUX_STS_CLR_OFFSET));
879}
880
881/*************************************************************************
882* FUNCTION
883* drv_rstctl_wd_getSta
884*
885* DESCRIPTION
886* This function is used to get wdt status
887*
888* PARAMETERS
889* none
890*
891* RETURN VALUES
892* bit[7]:MD WDT2 SWDT indicator
893* bit[6]:MD WDT2 HWDT indicator
894* bit[2]:MD OST timer timout is triggered
895* bit[1]:MD sw WD reset indicator
896* bit[0]:MD hw WD reset indicator
897*************************************************************************/
898kal_uint32 drv_rstctl_wd_getSta(void)
899{
900 kal_uint32 wdt_sta;
901 wdt_sta = DRV_Reg32(REG_MDRSTCTL_WDTSR);
902 return wdt_sta;
903}
904
905/*************************************************************************
906* FUNCTION
907* drv_rstctl_wd_kick
908*
909* DESCRIPTION
910* This function is used to retart wd tiemr
911*
912* PARAMETERS
913* none
914*
915* RETURN VALUES
916* none
917*************************************************************************/
918void drv_rstctl_restartWDT(void)
919{
920 #if !defined (ATEST_ENABLE)
921 /* Simply reload watchdog counter */
922 DRV_WriteReg32(REG_MDRSTCTL_WDTRR, RSTCTL_WDTRR_KEY | RSTCTL_WDTRR_WDT_RESTART);
923 #endif
924}
925
926void drv_rstctl_wd_rst_set_bitmap(kal_uint8 type)
927{
928 //if (cp15_get_cpu_id() == CPU_CORTEX_R4_ID)
929 //originally difference
930 // type == 0
931 // do not reset ssusb
932 // type == 1
933 // do not reset usb
934 // But for TK6291, all these bit are out of Pcore control.
935 // Therefore, there is no difference for these two types.
936 if ((type == 0)|| (type == 1))
937 {
938 DRV_WriteReg32(REG_MDRSTCTL_WDTER_MDSYS, 0xBFFFFFFF);
939 }
940 else
941 {
942 #if defined(ATEST_ENABLE)
943 dbg_print("[%s]Wrong type....\r\n", __FUNCTION__);
944 #endif
945 ASSERT(0);
946 }
947}
948
949/*************************************************************************
950* FUNCTION
951* drv_rstctl_wdt_init
952*
953* DESCRIPTION
954* This function is to initialize the WDT module
955*
956*
957* PARAMETERS
958* none
959*
960* RETURN VALUES
961* none
962*
963*************************************************************************/
964void drv_rstctl_wdt_init(void)
965{
966 /*TODO: Read status bit and PC monitor for debug before clear status*/
967#if !defined(ATEST_ENABLE)
968 drv_rstctl_wd_clrSta();
969#endif
970 drv_rstctl_wdt_setInterval(WDT_RSTINTERVAL_VALUE);
971#if defined(DRV_WDT_IRQ_MODE)
972 drv_rstctl_wdt_enableInterrupt(KAL_TRUE); //IRQ to MDMCU
973 /*TODO register IRQ and handle ISR*/
974 //IRQSensitivity(IRQ_MD_WDT_CODE, KAL_TRUE);
975 //IRQUnmask(IRQ_MD_WDT_CODE);
976#endif
977}
978
979void drv_rstctl_wdt_init_aux(void)
980{
981 /*TODO: Read status bit and PC monitor for debug before clear status*/
982#if !defined(ATEST_ENABLE)
983 drv_rstctl_wd_clrSta_aux();
984#endif
985 drv_rstctl_wdt_setInterval_aux(WDT_RSTINTERVAL_VALUE2);
986#if defined(DRV_WDT_IRQ_MODE)
987 drv_rstctl_wdt_enableInterrupt_aux(KAL_TRUE); //IRQ to APMCU
988#endif
989}
990
991void drv_rstctl_wd_reset(wdt_irq_e irq_en, rst_target_e wdTarget, kal_uint32 wdtInterval)
992{
993 /* Disable WD and clear indicators*/
994 drv_rstctl_wd_clrSta();
995 if (wdTarget == RST_MDALL)
996 {
997 DRV_WriteReg32(REG_MDRSTCTL_WDTER_MDSYS, 0xBFFFFFFF);
998 }
999 else
1000 {
1001 //_rst_setWdTarget(wdTarget);
1002 }
1003 /**< Step 2 : configure WDT register to start counting */
1004 drv_rstctl_wdt_enableInterrupt(irq_en);
1005 if (0 != wdtInterval)
1006 {
1007 _rst_enableWdt(1, wdtInterval); /* Maximum interval to watchdog timeout */
1008 //_rst_restartWDT(); /* Kick watchdog to prevent from timeout */ //already done in _rst_enableWdt
1009 }
1010 else
1011 {
1012 _rst_swWdReset(); /* To trigger software watchdog reset */
1013 }
1014}
1015
1016void drv_rstctl_wd_reset_aux(wdt_irq_e irq_en, rst_target_e wdTarget, kal_uint32 wdtInterval)
1017{
1018 /* Disable WD and clear indicators*/
1019 drv_rstctl_wd_clrSta_aux();
1020 if (wdTarget == RST_MDALL)
1021 {
1022 DRV_WriteReg32(REG_MDRSTCTL_WDTER_MDSYS, 0xBFFFFFFF);
1023 }
1024 else
1025 {
1026 //_rst_setWdTarget(wdTarget);
1027 }
1028 /**< Step 2 : configure WDT register to start counting */
1029 drv_rstctl_wdt_enableInterrupt_aux(irq_en);
1030 if (0 != wdtInterval)
1031 {
1032 _rst_enableWdt_aux(1, wdtInterval); /* Maximum interval to watchdog timeout */
1033 //_rst_restartWDT(); /* Kick watchdog to prevent from timeout */ //already done in _rst_enableWdt
1034 }
1035 else
1036 {
1037 _rst_swWdReset_aux(); /* To trigger software watchdog reset */
1038 }
1039}
1040
1041/*************************************************************************
1042* FUNCTION
1043* drv_rstctl_sw_reset
1044*
1045* DESCRIPTION
1046* This function is used to do SW reset
1047*
1048* PARAMETERS
1049* targetIP: sw module defined in RGU
1050*
1051* RETURN VALUES
1052* none
1053*************************************************************************/
1054kal_bool drv_rstctl_sw_reset(rst_target_e targetIP)
1055{
1056 switch (targetIP)
1057 {
1058#if defined(__MD93__) // removed from gen95 & gen97
1059 case RST_IA_LOGGER:
1060 {_rst_resetIP(REG_MDRSTCTL_SRBER_MDSYS, RSTCTL_MDSRBER_IA_LOGGER_RST, _RST_DURATION_LOOP_DEFAULT_VALUE);break;}
1061 case RST_USIM1:
1062 {_rst_resetIP(REG_MDRSTCTL_SRBER_MDSYS, RSTCTL_MDSRBER_USIM1_RST, _RST_DURATION_LOOP_DEFAULT_VALUE);break;}
1063 case RST_USIM2:
1064 {_rst_resetIP(REG_MDRSTCTL_SRBER_MDSYS, RSTCTL_MDSRBER_USIM2_RST, _RST_DURATION_LOOP_DEFAULT_VALUE);break;}
1065 case RST_L1SYS:
1066 {_rst_resetIP(REG_MDRSTCTL_SRBER_MDSYS, RSTCTL_MDSRBER_L1SYS_RST, _RST_DURATION_LOOP_DEFAULT_VALUE);break;}
1067 case RST_MML2:
1068 {_rst_resetIP(REG_MDRSTCTL_SRBER_MDSYS, RSTCTL_MDSRBER_MML2_RST, _RST_DURATION_LOOP_DEFAULT_VALUE);break;}
1069 case RST_MDTOPSM:
1070 {_rst_resetIP(REG_MDRSTCTL_SRBER_MDSYS, RSTCTL_MDSRBER_MDTOPSM_RST, _RST_DURATION_LOOP_DEFAULT_VALUE);break;}
1071 case RST_MDOST:
1072 {_rst_resetIP(REG_MDRSTCTL_SRBER_MDSYS, RSTCTL_MDSRBER_MDOST_RST, _RST_DURATION_LOOP_DEFAULT_VALUE);break;}
1073#endif
1074 case RST_MDUART0:
1075 {_rst_resetIP(REG_MDRSTCTL_SRBER_MDSYS, RSTCTL_MDSRBER_MDUART0_RST, _RST_DURATION_LOOP_DEFAULT_VALUE);break;}
1076 case RST_MDUART1:
1077 {_rst_resetIP(REG_MDRSTCTL_SRBER_MDSYS, RSTCTL_MDSRBER_MDUART1_RST, _RST_DURATION_LOOP_DEFAULT_VALUE);break;}
1078 case RST_TRACE:
1079 {_rst_resetIP(REG_MDRSTCTL_SRBER_MDSYS, RSTCTL_MDSRBER_TRACE_RST, _RST_DURATION_LOOP_DEFAULT_VALUE);break;}
1080 case RST_SOE:
1081 {_rst_resetIP(REG_MDRSTCTL_SRBER_MDSYS, RSTCTL_MDSRBER_SOE_RST, _RST_DURATION_LOOP_DEFAULT_VALUE);break;}
1082 case RST_GPT:
1083 {_rst_resetIP(REG_MDRSTCTL_SRBER_MDSYS, RSTCTL_MDSRBER_MDGPTM_RST, _RST_DURATION_LOOP_DEFAULT_VALUE);break;}
1084 default:
1085 return KAL_FALSE;
1086 break;
1087 }
1088
1089 return KAL_TRUE;
1090}
1091
1092/*************************************************************************
1093* FUNCTION
1094* drv_rstctl_wdt_reset
1095*
1096* DESCRIPTION
1097* This function is to do wdt reset
1098*
1099* PARAMETERS
1100* none
1101*
1102* RETURN VALUES
1103* none
1104*
1105*************************************************************************/
1106
1107void drv_rstctl_wdt_reset(void)
1108{
1109#if defined(DRV_WDT_RESET_PKEY_RELEASE)
1110 kal_uint16 powerkey_status;
1111
1112
1113 #ifdef PMIC_PRESENT
1114
1115 if (BMT.PWRon != CHRPWRON)
1116 {
1117 switch(Pwrkey_Position)
1118 {
1119 case low_key:
1120 powerkey_status= DRV_Reg32(KP_LOW_KEY);
1121 break;
1122 #if 0
1123/* under construction !*/
1124/* under construction !*/
1125/* under construction !*/
1126 #endif
1127 case high_key:
1128 powerkey_status= DRV_Reg32(KP_HI_KEY);
1129 break;
1130 default:
1131 ASSERT(0);
1132 break;
1133 }
1134 if(WdtPowerKey_Pressed())
1135 {
1136 TargetReset = 1;
1137 }
1138 else
1139 {
1140 /*lint -e(534)*/SaveAndSetIRQMask();
1141
1142 drv_rstctl_wdt_setInterval(1);
1143 _rst_restartWDT();
1144 drv_rstctl_wdt_enable(KAL_TRUE);
1145 while(1);
1146 }
1147 }
1148 else
1149 {
1150 /*lint -e(534)*/SaveAndSetIRQMask();
1151
1152 drv_rstctl_wdt_setInterval_aux(1);
1153 _rst_restartWDT();
1154 drv_rstctl_wdt_enable_aux(KAL_TRUE);
1155 while(1);
1156 }
1157 #else /*PMIC_PRESENT*/
1158 /*lint -e(534)*/SaveAndSetIRQMask();
1159
1160 drv_rstctl_wdt_setInterval_aux(1);
1161 _rst_restartWDT();
1162 drv_rstctl_wdt_enable_aux(KAL_TRUE);
1163 while(1);
1164 #endif /*PMIC_PRESENT*/
1165#else /*!DRV_WDT_RESET_PKEY_RELEASE*/
1166
1167 kal_uint16 index;
1168 volatile kal_uint32 trigger_time;
1169 kal_uint32 retry_count = 0;
1170
1171#if defined(DRV_RTC_REG_COMM)
1172 DCL_HANDLE rtc_handler;
1173 RTC_CTRL_CONFIG_PDN_BIT_T rtc_cmd_data8;
1174#endif /*DRV_RTC_REG_COMM*/
1175 /*lint -e(534)*/kal_hrt_SaveAndSetIRQMask();
1176
1177 for(index=0;index<1000;index++);
1178#if defined(DRV_RTC_REG_COMM)
1179 //RTC_Set_PDN_bits(rtc_pdn2 ,DRV_COMM_REG2_NORMAL_RESET);
1180 rtc_handler = DclRTC_Open(DCL_RTC,FLAGS_NONE);
1181 rtc_cmd_data8.PDNIndex = DCL_RTC_PDN2;
1182 rtc_cmd_data8.fgConfigBit = DRV_COMM_REG2_NORMAL_RESET;
1183 DclRTC_Control(rtc_handler, RTC_CMD_SET_PDN_BITS, (DCL_CTRL_DATA_T *)&rtc_cmd_data8); // New API with CMD & DATA
1184#endif /*DRV_RTC_REG_COMM*/
1185 #if !defined(DRV_WDT_SWRST)
1186 drv_rstctl_wdt_setInterval_aux(1);
1187 _rst_restartWDT();
1188 drv_rstctl_wdt_enable_aux(KAL_TRUE);
1189 while(1);
1190 #else
1191 _rst_swWdReset_aux(); /* To trigger software watchdog reset */
1192 trigger_time = ust_get_current_time();
1193 do
1194 {
1195 if ((ust_get_current_time() - trigger_time) > 4000000) {
1196 if (retry_count >= 3)
1197 ASSERT(0);
1198
1199 trigger_time = ust_get_current_time();
1200 retry_count++;
1201 _rst_swWdReset_aux();
1202 }
1203 }
1204 while(1);
1205 #endif
1206#endif /*!DRV_WDT_RESET_PKEY_RELEASE*/
1207
1208}
1209
1210/*************************************************************************
1211* FUNCTION
1212* drv_rstctl_wdt_abnReset
1213*
1214* DESCRIPTION
1215* This function is used to do abnormal reset
1216*
1217* PARAMETERS
1218* none
1219*
1220* RETURN VALUES
1221* none
1222*
1223*************************************************************************/
1224void drv_rstctl_wdt_abnReset(void)
1225{
1226 kal_uint32 trigger_time;
1227
1228 /*TODO: Need to check using sw wdt trigger instead of using hw wdt timeout*/
1229 #if !defined(ATEST_ENABLE)
1230 kal_hrt_SaveAndSetIRQMask();
1231 #endif
1232
1233 _rst_swWdReset_aux();
1234 trigger_time = ust_get_current_time();
1235 do
1236 {
1237 ASSERT((ust_get_current_time() - trigger_time) < 60000000); //Check AP reset MD exceed 4s
1238 }
1239 while(1);
1240}
1241
1242/*************************************************************************
1243* FUNCTION
1244* drv_rstctl_wdt_enableDebugMode
1245*
1246* DESCRIPTION
1247* This function is used to on/off debug mode
1248*
1249* PARAMETERS
1250* enable
1251* 0: disable
1252* 1: enable
1253*
1254* RETURN VALUES
1255* none
1256*************************************************************************/
1257
1258void drv_rstctl_wdt_enableDebugMode(kal_bool enable)
1259{
1260 if (enable==KAL_TRUE)
1261 {
1262 IRQUnmask(IRQ_MDWDT_CODE);
1263 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) | ((DRV_Reg32(REG_MDRSTCTL_WDTCR))| (RSTCTL_WDTCR_WDT_EN | RSTCTL_WDTCR_WDT_IRQEN)));
1264 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) | ((DRV_Reg32(REG_MDRSTCTL_WDTCR))| (RSTCTL_WDTCR_AUX_WDT_EN | RSTCTL_WDTCR_AUX_WDT_IRQEN)));
1265 }
1266 else
1267 {
1268 IRQMask(IRQ_MDWDT_CODE);
1269 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) | ((DRV_Reg32(REG_MDRSTCTL_WDTCR)) & ~(RSTCTL_WDTCR_WDT_EN | RSTCTL_WDTCR_WDT_IRQEN)));
1270 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, (RSTCTL_WDTCR_KEY) | ((DRV_Reg32(REG_MDRSTCTL_WDTCR)) & ~(RSTCTL_WDTCR_AUX_WDT_EN | RSTCTL_WDTCR_AUX_WDT_IRQEN)));
1271 }
1272}
1273
1274void drv_rstctl_set_check_bit(vpeid_e vpe)
1275{
1276 DRV_WriteReg32(REG_MDRSTCTL_CHECK_BIT_SET, ((RSTCTL_MD_CHECK_AND_KICK_KEY + vpe) << RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET) | (0x1 << vpe));
1277}
1278
1279void drv_rstctl_clr_check_bit(vpeid_e vpe)
1280{
1281 DRV_WriteReg32(REG_MDRSTCTL_CHECK_BIT_CLR, ((RSTCTL_MD_CHECK_AND_KICK_KEY + vpe) << RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET) | (0x1 << vpe));
1282}
1283
1284void drv_rstctl_set_kick_bit(vpeid_e vpe)
1285{
1286 DRV_WriteReg32(REG_MDRSTCTL_KICK_BIT_SET, ((RSTCTL_MD_CHECK_AND_KICK_KEY + vpe) << RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET) | (0x1 << vpe));
1287}
1288
1289void drv_rstctl_clr_kick_bit(vpeid_e vpe)
1290{
1291 DRV_WriteReg32(REG_MDRSTCTL_KICK_BIT_CLR, ((RSTCTL_MD_CHECK_AND_KICK_KEY + vpe) << RSTCTL_MD_CHECK_AND_KICK_KEY_OFFSET) | (0x1 << vpe));
1292}
1293
1294kal_uint32 drv_rstctl_get_check_sts(void)
1295{
1296 return DRV_Reg32(REG_MDRSTCTL_CHECK_BIT_STS);
1297}
1298
1299kal_uint32 drv_rstctl_get_kick_sts(void)
1300{
1301 return DRV_Reg32(REG_MDRSTCTL_KICK_BIT_STS);
1302}
1303
1304/*************************************************************************
1305* FUNCTION
1306* WDT_init
1307*
1308* DESCRIPTION
1309* This function is to initialize the WDT module
1310*
1311* PARAMETERS
1312* none
1313*
1314* RETURN VALUES
1315* none
1316*
1317*************************************************************************/
1318void WDT_init(void)
1319{
1320 static DCL_HANDLE wdt_handle;
1321 WDT_SET_KICKBIT_BASE = (kal_uint32*)REG_MDRSTCTL_KICK_BIT_SET;
1322 WDT_SET_CHECKBIT_BASE = (kal_uint32*)REG_MDRSTCTL_CHECK_BIT_SET;
1323 WDT_CLR_CHECKBIT_BASE = (kal_uint32*)REG_MDRSTCTL_CHECK_BIT_CLR;
1324 drv_rstctl_wdt_init();
1325 drv_rstctl_wdt_init_aux();
1326 //set check bit for all vpes
1327 vpeid_e vpe_id;
1328 for(vpe_id=0 ; vpe_id<VPE_NUM; vpe_id++)
1329 drv_rstctl_set_check_bit(vpe_id);
1330 drv_rstctl_restartWDT();
1331
1332 wdt_handle = DclWDT_Open(DCL_WDT, 0);
1333 if(STATUS_OK !=DclWDT_RegisterCallback(wdt_handle,EVENT_WDT_TIMEOUT, NULL))
1334 {
1335 ASSERT(0);
1336 }
1337 if (STATUS_OK != DclWDT_Close(wdt_handle))
1338 {
1339 ASSERT(0);
1340 }
1341 #if defined(__MTK_TARGET__)
1342 /*Begin : Register BB_Reg DUMP*/
1343 Pcore_RGU_dump.regions = (kal_uint32*)Pcore_RGU_dump_regions;
1344 Pcore_RGU_dump.num = sizeof(Pcore_RGU_dump_regions) / (sizeof(kal_uint32) * 3);
1345 Pcore_RGU_dump.bbreg_dump_callback = NULL;
1346 EX_REGISTER_BBREG_DUMP(&Pcore_RGU_dump);
1347 /*End : Register BB_Reg DUMP*/
1348 #endif
1349}
1350
1351/*************************************************************************
1352* FUNCTION
1353* Is_WDT_Init
1354*
1355* DESCRIPTION
1356* Check WD timer is set to system default value already or not
1357*
1358* PARAMETERS
1359* none
1360*
1361* RETURN VALUES
1362* TRUE: already set
1363* FALSE: not yet
1364*
1365*************************************************************************/
1366kal_bool Is_WDT_Init()// for ex_item.c
1367{
1368 //**Actually, this function is used to check if abnormal reset happened in reset mode
1369 //WDT_interval is at WDT reset field in Elbrus, so we ckeck WDTSR
1370
1371 if((DRV_Reg32(REG_MDRSTCTL_WDTSR) != 0) || (drv_rstctl_wd_getInterval() == WDT_RSTINTERVAL_VALUE))
1372 return KAL_TRUE;
1373 else
1374 return KAL_FALSE;
1375}
1376
1377void wdt_enable(kal_bool en)
1378{
1379 drv_rstctl_wdt_enable(en);
1380 drv_rstctl_wdt_enable_aux(en);
1381}
1382
1383void mips_isr_mdwdt_handler(void)
1384{
1385 kal_uint32 check_sts = drv_rstctl_get_check_sts();
1386 kal_uint32 kick_sts = drv_rstctl_get_kick_sts();
1387 kal_uint32 error_code2 = (check_sts ^ kick_sts) & check_sts;
1388 #if defined(ATEST_ENABLE)
1389 dbg_print("[%s] handling mdwdt irq\r\n", __FUNCTION__);
1390 dbg_print("[%s] Issuing fatale error(KAL_ERROR_L1CORE_HW_WDT_TIMEOUT_EXCP, code2=%x). \r\n", __FUNCTION__, error_code2);
1391 #endif
1392 kal_fatal_error_handler(KAL_ERROR_L1CORE_HW_WDT_TIMEOUT_EXCP, error_code2);
1393}
1394
1395void invalidate_WDTBASE(void)
1396{
1397 WDT_SET_KICKBIT_BASE = (kal_uint32*)REG_MDRSTCTL_WDT_DUMMY;
1398}
1399
1400#if defined(ATEST_ENABLE)
1401
1402
1403#define RGU_RESET_UT_RESULT_OFFSET (31) //UT result is used to determine if next iteration should proceed.
1404#define RGU_RESET_UT_RESULT_MASK (0x80000000)
1405#define RGU_RESET_SCOPE_OFFSET (29)
1406#define RGU_RESET_SCOPE_MASK (0x60000000)
1407#define RGU_FRMWRK_PARAMETER_OFFSET (27) //Parameter let the counter-part know what the triger source is.
1408#define RGU_FRMWRK_PARAMETER_MASK (0x18000000)
1409#define RGU_SCOPE_TO_CLEAR_STATE_OFFSET (25)
1410#define RGU_SCOPE_TO_CLEAR_STATE_MASK (0x06000000) //For IPs that could not software reset during testing, reset the system to clear corresponding state.
1411#define RGU_API_CALL_ACCUMULATOR_OFFSET (8)
1412#define RGU_API_CALL_ACCUMULATOR_MASK (0x01ffff00)
1413
1414
1415#define RSTCTL_APWDTCR_WDT_IRQEN (1 << 3)
1416#define RSTCTL_APWDTCR_WDT_SPD_UP (1 << 15)
1417#define RSTCTL_APWDTCR_KEY (0x55 << 24)
1418#define RSTCTL_APWDTRR_KEY ((0x7208 << 16)| 1)
1419#define RSTCTL_APWDTCR_WDT_EN (1 << 0)
1420#define RSTCTL_APWDTIR_KEY (0x67 << 24)
1421#define RSTCTL_APWDTIR_INTERVAL_MASK (0x3Fffff)
1422#define RSTCTL_APWDTSR_STATUS_MASK 0x07
1423#define RSTCTL_APWDTSR_STS_CLR_MASK 0X07 // CLR_AP_OSTT_STS(bit5), CLR_AP_SWDT_STS(bit4), CLR_AP_HWDT_STS(bit3)
1424#define RSTCTL_APWDTSR_STS_CLR_OFFSET 3
1425#define RSTCTL_APWDTSR_CNT_CLR_MASK 0x03 // CLR_AP_SW_WDT_CNT (bit7), CLR_AP_HW_WDT_CNT (bit6)
1426#define RSTCTL_APWDTSR_CNT_CLR_OFFSET 6
1427#define RSTCTL_APWDTSR_SW_WDT_CNT_MASK 0XFF
1428#define RSTCTL_APWDTSR_SW_WDT_CNT_OFFSET 16
1429#define RSTCTL_APWDTSR_HW_WDT_CNT_MASK 0XFF
1430#define RSTCTL_APWDTSR_HW_WDT_CNT_OFFSET 8
1431#define RSTCTL_APWDTSR_KEY (0x76 << 24)
1432#define RSTCTL_APWDTSR_HWDT_STS (1 << 0)
1433#define RSTCTL_APWDTSR_SWDT_STS (1 << 1)
1434#define RSTCTL_APWDTSR_OSTT_STS (1 << 2)
1435#define RSTCTL_APWDTSR_MD1_STATUS_MASK (0x01) /* MD1_WDT_STS(bit0): WDT_IRQ fired && ! AP_AUTO_RST */
1436#define RSTCTL_APWDTSR_MD1_STATUS_OFFSET (0)
1437#define RSTCTL_APWDTSR_MD1_KEY (0x7663 << 16)
1438#define RSTCTL_APWDTSR_MD1_STS_CLR_MASK (0X01) /* CLR_MD1_WDT_STS(bit1) */
1439#define RSTCTL_APWDTSR_MD1_STS_CLR_OFFSET (1)
1440#define RSTCTL_APMDWDTCFG_MD1_KEY (0X2555 << 16)
1441#define RSTCTL_APMDWDTCFG_MD1_WDT_LV_EN_MD1 (1 << 0)
1442
1443typedef enum
1444{
1445 SOFTWARE_RESET = 0, //Software reset target IP
1446 WHOLE_SYSTEM_RESET, //Trigger source: APRGU
1447 AP_SOFTWARE_RESET_MD, //Trigger source: MDRGU
1448 RGU_RESET_SCOPE_END //The last used to distinguish the end of framewor.
1449}RGU_reset_scope_e;
1450
1451extern kal_bool UART_CheckTxAllSentOut(UART_PORT port);
1452
1453kal_uint32 wdt_lisr_vpe_flag = 0;
1454
1455void _rst_wdt_lisr(){
1456
1457 kal_uint32 count = 0;
1458
1459 if(kal_get_current_vpe_id()%2)
1460 kal_hrt_SaveAndSetIRQMask();
1461 else
1462 SaveAndSetIRQMask();
1463
1464 if (kal_get_current_vpe_id() == 0) {
1465 /* Wait other VPEs */
1466 //while(kal_atomic_read(&wdt_lisr_vpe_flag) < 3);
1467
1468 /* Trigger SWDT to AP */
1469 DRV_WriteReg32(REG_MDRSTCTL_SRCMR_SWDT,RSTCTL_AUX_SRCMR_KEY_SWDT);
1470
1471 do {
1472 count++;
1473 if (count%50000 == 0)
1474 /* Trigger SWDT to AP again */
1475 DRV_WriteReg32(REG_MDRSTCTL_SRCMR_SWDT,RSTCTL_AUX_SRCMR_KEY_SWDT);
1476 } while(1);
1477 } else {
1478 kal_atomic_inc(&wdt_lisr_vpe_flag);
1479 while(1);
1480 }
1481}
1482
1483void _rst_register_lisr(){
1484
1485 IRQ_Register_LISR(IRQ_MDWDT_CODE, _rst_wdt_lisr, "DCL WDT LISR");
1486 IRQSensitivity(IRQ_MDWDT_CODE,KAL_TRUE);
1487 IRQUnmask(IRQ_MDWDT_CODE);
1488}
1489
1490#if !defined(RSTCTL_FPGA_PLAT)
1491
1492#if !defined(BASE_MADDR_TOP_RGU)
1493#define BASE_MADDR_TOP_RGU (0xC0007000)
1494#endif
1495#define REG_TOPRGU_MODE (BASE_MADDR_TOP_RGU+0x0)
1496#define REG_TOPRGU_SWRST (BASE_MADDR_TOP_RGU+0x14)
1497#define REG_TOPRGU_RETAIN (BASE_MADDR_TOP_RGU+0x20)
1498#define REG_TOPRGU_DUMMY (BASE_MADDR_TOP_RGU + 0x20)
1499#define REG_TOPRGU_LENGTH (BASE_MADDR_TOP_RGU + 0x04)
1500#define REG_TOPRGU_RESTART (BASE_MADDR_TOP_RGU+0x08)
1501
1502#if 1
1503void _rst_set_system_ready_sts(kal_uint32 system, kal_uint32 system_coverage)
1504{
1505 kal_uint32 current_val;
1506 if ((system & system_coverage)== 0)
1507 {
1508 dbg_print("%s: system out of system coverage\n\r", __FUNCTION__);
1509 ASSERT(0);
1510 }
1511 //Add switch case to prevent race condition
1512 switch (system)
1513 {
1514 case APSYS: //is the first one to enable ready status.
1515 //no need to wait.
1516 dbg_print("Setting MDRGU WDT DUMMY ....\r\n");
1517 break;
1518 case MD1SYS: //is the second one to enable ready status.
1519 dbg_print("Wait for (APSYS) APRGU WDT DUMMY write ready...\r\n");
1520 while((DRV_Reg32(REG_MDRSTCTL_WDT_DUMMY) & (APSYS))!= (APSYS & system_coverage));
1521 break;
1522 }
1523 current_val = DRV_Reg32(REG_MDRSTCTL_WDT_DUMMY) | system;
1524 DRV_WriteReg32(REG_MDRSTCTL_WDT_DUMMY, current_val);
1525 dbg_print("After writing ready status, REG_APRSTCTL_WDT_DUMMY = 0x%x\r\n", DRV_Reg32(REG_APRSTCTL_WDT_DUMMY));
1526}
1527
1528void _rst_clr_system_ready_sts(kal_uint32 system)
1529{
1530 kal_uint32 current_val;
1531 if ((system & (APSYS | MD1SYS))== 0)
1532 {
1533 dbg_print("%s: system out of coverage\n\r", __FUNCTION__);
1534 ASSERT(0);
1535 }
1536 current_val = DRV_Reg32(REG_MDRSTCTL_WDT_DUMMY) & ~(system);
1537 DRV_WriteReg32(REG_MDRSTCTL_WDT_DUMMY, current_val);
1538}
1539
1540kal_uint32 _rst_get_system_ready_sts(void)
1541{
1542 return (DRV_Reg32(REG_MDRSTCTL_WDT_DUMMY));
1543}
1544
1545#endif
1546kal_uint32 _rst_get_this_reset_scope(void)
1547{
1548 kal_uint32 this_reset_scope;
1549 this_reset_scope = (DRV_Reg32(REG_TOPRGU_RETAIN) & RGU_RESET_SCOPE_MASK) >> RGU_RESET_SCOPE_OFFSET;
1550 return this_reset_scope;
1551}
1552
1553void _rst_set_next_reset_scope(kal_uint32 next_reset_scope)
1554{
1555 kal_uint32 dummy_content;
1556 dummy_content = (DRV_Reg32(REG_TOPRGU_RETAIN) & (~RGU_RESET_SCOPE_MASK)) | (next_reset_scope << RGU_RESET_SCOPE_OFFSET);
1557 DRV_WriteReg32(REG_TOPRGU_RETAIN, dummy_content);
1558}
1559
1560
1561void _rst_set_rgu_frmwrk_parameter(kal_uint32 content)
1562{
1563 kal_uint32 current_val;
1564 current_val = DRV_Reg32(REG_TOPRGU_RETAIN) & (~RGU_FRMWRK_PARAMETER_MASK);
1565 if (((content << RGU_FRMWRK_PARAMETER_OFFSET) & (~RGU_FRMWRK_PARAMETER_MASK)) > 0) //exceed the parameter range.
1566 ASSERT(0);
1567 else
1568 {
1569 current_val |= ((content << RGU_FRMWRK_PARAMETER_OFFSET) & RGU_FRMWRK_PARAMETER_MASK);
1570 DRV_WriteReg32(REG_TOPRGU_RETAIN, current_val);
1571 }
1572}
1573
1574kal_uint32 _rst_get_rgu_frmwrk_parameter(void)
1575{
1576 return (DRV_Reg32(REG_TOPRGU_RETAIN) & RGU_FRMWRK_PARAMETER_MASK) >> RGU_FRMWRK_PARAMETER_OFFSET;
1577}
1578
1579void _rst_set_rgu_ut_result(kal_uint32 ut_result) //ut_result = UT_REPORT_PASS (0) or UT_REPORT_FAIL(-1).
1580{
1581 kal_uint32 current_val;
1582 current_val = DRV_Reg32(REG_TOPRGU_RETAIN) & (~RGU_RESET_UT_RESULT_MASK);
1583 current_val |= (ut_result & RGU_RESET_UT_RESULT_MASK >> RGU_RESET_UT_RESULT_OFFSET)<<RGU_RESET_UT_RESULT_OFFSET;
1584 DRV_WriteReg32(REG_TOPRGU_RETAIN, current_val);
1585}
1586
1587kal_uint32 _rst_get_rgu_ut_result(void)
1588{
1589 kal_uint32 current_val;
1590 current_val = (DRV_Reg32(REG_TOPRGU_RETAIN) & RGU_RESET_UT_RESULT_MASK) >> RGU_RESET_UT_RESULT_OFFSET;
1591 if (UT_REPORT_PASS == current_val)
1592 return UT_REPORT_PASS;
1593 else
1594 return UT_REPORT_FAIL;
1595}
1596
1597void _rst_set_rgu_scope_to_clear_state(kal_uint32 clear_scope)
1598{
1599 kal_uint32 current_val;
1600 current_val = DRV_Reg32(REG_TOPRGU_RETAIN) & (~RGU_SCOPE_TO_CLEAR_STATE_MASK) ;
1601 current_val |= (clear_scope & (RGU_SCOPE_TO_CLEAR_STATE_MASK >> RGU_SCOPE_TO_CLEAR_STATE_OFFSET)) << RGU_SCOPE_TO_CLEAR_STATE_OFFSET;
1602 DRV_WriteReg32(REG_TOPRGU_RETAIN, current_val);
1603}
1604
1605kal_uint32 _rst_get_rgu_scope_to_clear_state(void)
1606{
1607 return ((DRV_Reg32(REG_TOPRGU_RETAIN) & RGU_SCOPE_TO_CLEAR_STATE_MASK) >> RGU_SCOPE_TO_CLEAR_STATE_OFFSET);
1608}
1609
1610
1611
1612void _rst_inc_rgu_api_call_accumulator(void)
1613{
1614 kal_uint32 current_val;
1615 current_val = (DRV_Reg32(REG_TOPRGU_RETAIN) & (~RGU_API_CALL_ACCUMULATOR_MASK));
1616 current_val |= (((DRV_Reg32(REG_TOPRGU_RETAIN) & RGU_API_CALL_ACCUMULATOR_MASK) + (1<<RGU_API_CALL_ACCUMULATOR_OFFSET))&RGU_API_CALL_ACCUMULATOR_MASK);
1617 DRV_WriteReg32(REG_TOPRGU_RETAIN, current_val);
1618}
1619
1620kal_uint32 _rst_get_rgu_api_call_accumulator(void)
1621{
1622 return ((DRV_Reg32(REG_TOPRGU_RETAIN) & RGU_API_CALL_ACCUMULATOR_MASK)>>RGU_API_CALL_ACCUMULATOR_OFFSET);
1623}
1624
1625kal_bool _rst_is_system_within_converage(subsystem_e target_system, subsystem_e system_converage)
1626{
1627 if ((target_system & system_converage) == target_system)
1628 return KAL_TRUE;
1629 else
1630 return KAL_FALSE;
1631}
1632
1633subsystem_e _rst_return_dominate_system(subsystem_e target_system)
1634{
1635 if (APSYS == (target_system & APSYS))
1636 return APSYS;
1637 if (MD1SYS == (target_system & MD1SYS))
1638 return MD1SYS;
1639 ASSERT(0);
1640 return 0;
1641}
1642
1643
1644kal_bool _rst_setup_whole_system_reset_trigger_path(void)
1645{
1646 kal_bool ret_status = KAL_TRUE;
1647 //actually, for whole system reset, it does not need to setup the trigger path.
1648 //Set APRGU in reset mode. --> APRGU IRQ disable.
1649 DRV_WriteReg32(REG_TOPRGU_MODE,0x22000005);
1650 _rst_set_rgu_frmwrk_parameter(WHOLE_SYSTEM_RESET);
1651 //make MDRSTCTL_DUMMY dirty
1652 DRV_WriteReg32(REG_MDRSTCTL_DUMMY,0x22222222);
1653 return ret_status;
1654}
1655
1656kal_bool _rst_trigger_whole_system_reset(kal_uint32 delay_cycles)
1657{
1658 kal_bool ret_status = KAL_TRUE;
1659 _rst_setup_whole_system_reset_trigger_path(); //Set APRGU in reset mode.
1660
1661 //for this case, we need to trigger reset in APRGU.
1662 if (0 < delay_cycles)
1663 {
1664 //set toprgu timeout interval
1665 DRV_WriteReg32(REG_TOPRGU_LENGTH,0x8|(delay_cycles << 5)); //one delay cycle equals to 15.6ms
1666 DRV_WriteReg32(REG_TOPRGU_RESTART,0x1971);
1667 }
1668 else //trigger software WDT
1669 {
1670 //swwdt will not work if not restart
1671 DRV_WriteReg32(REG_TOPRGU_RESTART,0x1971);
1672 UT_DELAY_LOOP(_RST_DURATION_LOOP_DEFAULT_VALUE);
1673 //trigger TOPRGU SWDT reset
1674 DRV_WriteReg32(REG_TOPRGU_SWRST,0x00001209);
1675 }
1676 return ret_status;
1677}
1678
1679kal_bool _rst_is_whole_system_reset_triggered()
1680{
1681 if ((WHOLE_SYSTEM_RESET == _rst_get_rgu_frmwrk_parameter()) && (0 == DRV_Reg32(REG_MDRSTCTL_DUMMY)))
1682 {
1683 dbg_print("Whole system reset is triggered\r\n");
1684 return KAL_TRUE;
1685 }
1686 else
1687 return KAL_FALSE;
1688}
1689
1690kal_bool _rst_clear_whole_system_reset_status(void)
1691{
1692 DRV_WriteReg32(REG_TOPRGU_MODE,0x22000000);
1693 _rst_set_rgu_frmwrk_parameter(0);
1694 return KAL_FALSE;
1695}
1696
1697kal_bool md_rst_trigger_flag = KAL_FALSE;
1698
1699kal_bool _rst_setup_ap_software_reset_trigger_path(void)
1700{
1701 kal_bool ret_status = KAL_TRUE;
1702 kal_uint32 current_val;
1703
1704 md_rst_trigger_flag = KAL_TRUE;
1705 _rst_set_rgu_frmwrk_parameter(AP_SOFTWARE_RESET_MD);
1706 //Set the path from MDRGU to APRGU. (MDRGU IRQ enable)
1707 current_val = DRV_Reg32(REG_MDRSTCTL_WDTCR);
1708 current_val &= ~(RSTCTL_WDTCR_WDT_SPD_UP);
1709 current_val |= (RSTCTL_WDTCR_AUX_WDT_IRQEN);
1710 DRV_WriteReg32(REG_MDRSTCTL_WDTCR,RSTCTL_WDTCR_KEY | current_val); //1. disable speedup. 2. Enable IRQ_EN to AP
1711
1712 DRV_WriteReg32(REG_MDRSTCTL_WDTER_MDSYS, 0xBFFFFFFF);
1713 return ret_status;
1714}
1715
1716kal_bool _rst_trigger_ap_software_reset(kal_uint32 delay_cycles)
1717{
1718 kal_bool ret_status = KAL_TRUE;
1719 kal_uint32 current_val;
1720 _rst_setup_ap_software_reset_trigger_path(); //Set up the path to allow trigger CA7 ISR. (MDRGU: enable IRQ, APRGU: enable level )
1721
1722 if (0 < delay_cycles)
1723 {
1724#if 0
1725/* under construction !*/
1726/* under construction !*/
1727/* under construction !*/
1728/* under construction !*/
1729/* under construction !*/
1730/* under construction !*/
1731/* under construction !*/
1732/* under construction !*/
1733 #else
1734 DRV_WriteReg32(REG_MDRSTCTL_WDTIR_AUX, RSTCTL_WDTIR_AUX_KEY | ((delay_cycles<<9) & RSTCTL_WDTIR_INTERVAL_MASK));
1735 current_val = DRV_Reg32(REG_MDRSTCTL_WDTCR);
1736 current_val |= RSTCTL_WDTCR_AUX_WDT_EN;
1737 DRV_WriteReg32(REG_MDRSTCTL_WDTCR,RSTCTL_WDTCR_KEY | current_val);
1738 DRV_WriteReg32(REG_MDRSTCTL_WDTRR, RSTCTL_WDTRR_KEY|RSTCTL_WDTRR_WDT_RESTART); //we only needs to wait for MDRGU WDT to down count the delay cycles.
1739 #endif
1740 }
1741 else
1742 {
1743#if 0
1744/* under construction !*/
1745/* under construction !*/
1746/* under construction !*/
1747/* under construction !*/
1748/* under construction !*/
1749/* under construction !*/
1750/* under construction !*/
1751/* under construction !*/
1752#else
1753 DRV_WriteReg32(REG_MDRSTCTL_SRCMR_SWDT,RSTCTL_AUX_SRCMR_KEY_SWDT);
1754#endif
1755 }
1756
1757 return ret_status;
1758}
1759
1760
1761kal_bool _rst_is_ap_software_reset_triggered()
1762{
1763 //CHECK WDTSR (MD1_WDT_STS)
1764 if ((AP_SOFTWARE_RESET_MD == _rst_get_rgu_frmwrk_parameter() && (!md_rst_trigger_flag)))//&&(DRV_Reg32(REG_MDRSTCTL_WDTSR) != 0))
1765 {
1766 dbg_print("AP software reset MD triggered by MDRGU \r\n");
1767 return KAL_TRUE;
1768 }
1769 else
1770 return KAL_FALSE;
1771}
1772
1773kal_bool _rst_clear_ap_software_reset_status(void)
1774{
1775 kal_uint32 current_val;
1776 //Note: remember to disable WDT make sure system under control.
1777 current_val = DRV_Reg32(REG_MDRSTCTL_WDTCR);
1778 current_val &= ~RSTCTL_WDTCR_AUX_WDT_EN;
1779 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, RSTCTL_WDTCR_KEY | current_val);
1780 //clear status
1781 DRV_WriteReg32(REG_MDRSTCTL_WDTSR,(RSTCTL_WDTSR_KEY)|(RSTCTL_WDTSR_STATUS_MASK<<RSTCTL_WDTSR_STS_CLR_OFFSET));
1782 DRV_WriteReg32(REG_MDRSTCTL_WDTSR,(RSTCTL_WDTSR_KEY)|(RSTCTL_WDTSR_AUX_STATUS_MASK<<RSTCTL_WDTSR_AUX_STS_CLR_OFFSET));
1783 //Clear the parameter as well.
1784 _rst_set_rgu_frmwrk_parameter(0);
1785 return KAL_TRUE;
1786}
1787
1788UT_REPORT_STATUS _rst_check_ip_reset(ut_testcase_struct *testcase_ptr, kal_uint32 test_items) //Only check if reset correctly.
1789{
1790 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
1791 if (0 < test_items) //test_items must equals 1 at least. (test case is mandatorily located at 1st entry. )
1792 {
1793 dbg_print("\nCheck IP initial value: %s\n\r", (testcase_ptr)[0].description);
1794 ut_ret_status = (testcase_ptr)[0]._main_fn(testcase_ptr[0].flags, testcase_ptr[0].para); // check initial after reset
1795 }
1796 else
1797 {
1798 dbg_print("ASSERT (RGU): <line: %d in function: %s>\r\n", __LINE__, __FUNCTION__); //This case should not happen.
1799 ut_ret_status = UT_REPORT_FAIL;
1800 }
1801 if (UT_REPORT_PASS == ut_ret_status)
1802 dbg_print("\n\n IP initial value check: PASS \n\r");
1803 else
1804 dbg_print("\n\n IP initial value check: FAIL \n\r");
1805 return ut_ret_status;
1806}
1807
1808UT_REPORT_STATUS _rst_run_ip_ut(ut_testcase_struct *testcase_ptr, kal_uint32 test_items)
1809{
1810 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
1811 kal_uint32 func_idx;
1812 if (1 < test_items)
1813 {
1814 for(func_idx = 1; func_idx < test_items; func_idx ++)
1815 {
1816 dbg_print("\nIP unit test: %s\n\r", (testcase_ptr)[func_idx].description);
1817 ut_ret_status = (testcase_ptr)[func_idx]._main_fn(testcase_ptr[func_idx].flags, testcase_ptr[func_idx].para); // Other UTs exclude initial value check.
1818 if (UT_REPORT_FAIL == ut_ret_status)
1819 return ut_ret_status;
1820 }
1821 }
1822 else //1. no test case. 2. check IP's initial value only (no other UTs)
1823 {
1824 dbg_print("ASSERT (RGU): <line: %d in function: %s>\r\n", __LINE__, __FUNCTION__); //This case should not happen.
1825 ut_ret_status = UT_REPORT_FAIL;
1826 }
1827 if (UT_REPORT_PASS == ut_ret_status)
1828 dbg_print("\n\n IP unit test: PASS \n\r");
1829 else
1830 dbg_print("\n\n IP unit test: FAIL \n\r");
1831 return ut_ret_status;
1832}
1833
1834void _rst_prepare_for_next_rgu_it_call(subsystem_e system_coverage, UT_REPORT_STATUS ut_ret_status)
1835{
1836 _rst_set_rgu_scope_to_clear_state(RGU_RESET_SCOPE_END); //For the next iteration, it is necessary to offer a clear dependent state. To distinguish framework or new iteration reset, we burry RGU_RESET_SCOPE_END.
1837 _rst_set_next_reset_scope(SOFTWARE_RESET); //Upon all the reset scopes are tested, set the reset scope condition back to SOFTWARE_RESET.
1838 _rst_inc_rgu_api_call_accumulator(); //Increase RGU_API_CALL accumulator to prevent executing allready tested RGU_API.
1839 _rst_set_rgu_ut_result(ut_ret_status); //Store the ut_ret_status. If the status is UT_REPORT_FAIL, all the reset RGU_APIs will be ignored.
1840 UT_DELAY_LOOP(_RST_DURATION_LOOP_DEFAULT_VALUE); //Wait for effective register write.
1841 if (APSYS == (system_coverage & APSYS))
1842 {
1843 dbg_print("Trigger AP reset MD for next framework interation....\n\r");
1844 _rst_trigger_ap_software_reset(0); //At the end of this API call, trigger whole systemr reset to make system ready for next API call.
1845 while(1);
1846
1847 }
1848 else //Without AP, system coverage only includes MD1SYS, L1SYS, and/or ARM7SYS.
1849 {
1850 dbg_print("Without AP to boot up Pcore, you need to reload code through CMM again. \n\r");
1851 while(1);
1852 }
1853}
1854
1855UT_REPORT_STATUS _rst_examine_ip_through_software_reset(rst_target_e targetIP, ut_testcase_struct *testcase_ptr, kal_uint32 test_items)
1856{
1857 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
1858
1859 dbg_print("\n\n\nINFO (RGU) Software reset stage: \r\n");
1860 if (RST_NULL == targetIP) {
1861 dbg_print("IGNORED (RGU) UT check[software reset] @ %s \r\n\n\n", __FUNCTION__);
1862 dbg_print("****************************************\r\n");
1863 dbg_print("^^ Software reset stage test :: IGNORED::&&\r\n");
1864 dbg_print("****************************************\r\n");
1865 return UT_REPORT_PASS; //Some IPs (like MEMSYS) do not tolerate software reset.
1866 }
1867 ut_ret_status = _rst_check_ip_reset(testcase_ptr, test_items); //Only check if power on reset correctly.
1868 if (UT_REPORT_FAIL == ut_ret_status)
1869 return ut_ret_status;
1870 ut_ret_status = _rst_run_ip_ut(testcase_ptr, test_items);
1871 if (UT_REPORT_FAIL == ut_ret_status)
1872 return ut_ret_status;
1873
1874 dbg_print("PASS (RGU) UT check after bootup @ %s \r\n", __FUNCTION__);
1875 //The softwre reset function
1876 dbg_print("INFO (RGU) Software reset IP @ %s \r\n", __FUNCTION__);
1877 if (KAL_FALSE == drv_rstctl_sw_reset(targetIP)) {
1878 dbg_print("Target IP do NOT support SW reset function\r\n");
1879 goto end;
1880 }
1881 ut_ret_status = _rst_check_ip_reset(testcase_ptr, test_items); //Only check if reset correctly.
1882 if (UT_REPORT_FAIL == ut_ret_status)
1883 return ut_ret_status;
1884 ut_ret_status = _rst_run_ip_ut(testcase_ptr, test_items);
1885
1886end:
1887 if (UT_REPORT_FAIL == ut_ret_status)
1888 {
1889 dbg_print("FAIL (RGU) UT check[software reset] @ %s \r\n\n\n", __FUNCTION__);
1890 dbg_print("****************************************\r\n");
1891 dbg_print("^^ Software reset stage test ::FAIL::&&\r\n");
1892 dbg_print("****************************************\r\n");
1893 }
1894 else
1895 {
1896 dbg_print("PASS (RGU) UT check[software reset] @ %s \r\n", __FUNCTION__);
1897 dbg_print("****************************************\r\n");
1898 dbg_print("^^ Software reset stage test ::PASS::&&\r\n");
1899 dbg_print("****************************************\r\n");
1900 }
1901 return ut_ret_status;
1902}
1903
1904UT_REPORT_STATUS _rst_examine_ip_through_whole_system_reset(subsystem_e system_converage,ut_testcase_struct *testcase_ptr, kal_uint32 test_items, kal_uint32 delay_cycles)
1905{
1906 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
1907 dbg_print("\n\n\nINFO (RGU) Whole system reset stage: \r\n");
1908 if (KAL_TRUE ==_rst_is_system_within_converage(APSYS, system_converage))
1909 {
1910 //(1) --> UT --> (2) --> (3) --> reboot --> UT -->(4)
1911 //1 (1)
1912 if ((0 < delay_cycles)&&(!_rst_is_whole_system_reset_triggered()))
1913 {
1914 dbg_print("INFO (RGU) whole system reseting with delay cycles:%d... @ %s \r\n", delay_cycles, __FUNCTION__);
1915 while(!UART_CheckTxAllSentOut(uart_port1)){}
1916 _rst_trigger_whole_system_reset(delay_cycles);
1917 }
1918 ut_ret_status = _rst_check_ip_reset(testcase_ptr, test_items); //Only check if reset correctly.
1919 if (UT_REPORT_FAIL == ut_ret_status)
1920 return ut_ret_status;
1921 ut_ret_status = _rst_run_ip_ut(testcase_ptr, test_items);
1922 if (UT_REPORT_FAIL == ut_ret_status)
1923 return ut_ret_status;
1924 dbg_print("PASS (RGU) UT check after bootup @ %s \r\n", __FUNCTION__);
1925
1926 if ((0 < delay_cycles)&&(!_rst_is_whole_system_reset_triggered())) //reset should be triggered before UT finished
1927 {
1928 dbg_print("Delay cycle exceeds the UT runtime @ %s \r\n", __FUNCTION__);
1929 while(1);
1930 }
1931 //1 (2)
1932 if ((0 == delay_cycles)&&(!_rst_is_whole_system_reset_triggered()))
1933 {
1934 dbg_print("INFO (RGU) whole system reseting ... @ %s \r\n", __FUNCTION__);
1935 while(!UART_CheckTxAllSentOut(uart_port1)){}
1936 _rst_trigger_whole_system_reset(0); //whole system reset.
1937 while(1);
1938 }
1939 else
1940 dbg_print("INFO (RGU) whole system reset has been triggered @ %s \r\n", __FUNCTION__);
1941 //1 (3)
1942 //while(!_rst_is_whole_system_reset_triggered());
1943 //1 (4)
1944 _rst_clear_whole_system_reset_status();
1945 }
1946 else //Igrnore whole system reset.
1947 {
1948 dbg_print("INFO(RGU) APSYS is 'not' included in system converage. Whole system reset test is ignored. \r\n");
1949 return UT_REPORT_PASS;
1950 }
1951 if (UT_REPORT_FAIL == ut_ret_status)
1952 {
1953 dbg_print("********************************************\r\n");
1954 dbg_print("^^ Whole system reset stage test ::FAIL::&&\r\n");
1955 dbg_print("********************************************\r\n");
1956 }
1957 else
1958 {
1959 dbg_print("********************************************\r\n");
1960 dbg_print("^^ Whole system reset stage test ::PASS::&&\r\n");
1961 dbg_print("********************************************\r\n");
1962 }
1963 return ut_ret_status;
1964
1965}
1966
1967kal_bool g_ip_sup_sw_rst = KAL_TRUE;
1968
1969UT_REPORT_STATUS _rst_examine_ip_through_ap_software_reset(subsystem_e system_converage, ut_testcase_struct *testcase_ptr, kal_uint32 test_items, kal_uint32 delay_cycles, kal_bool is_core_rebooted)
1970{
1971 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
1972 dbg_print("\n\n\nINFO (RGU) AP software reset stage: \r\n");
1973 //AP software reset MD requires cooperation between APSYS and MD1SYS.
1974 if (KAL_TRUE ==_rst_is_system_within_converage(MD1SYS | APSYS, system_converage))
1975 {
1976 //(1) --> UT --> (2) --> (3) --> reboot --> (4) [is_core_rebooted == KAL_TRUE]
1977 //(1) --> UT --> (2) --> (3) --> (4) --> (5) UT [is_core_rebooted == KAL_FALSE] --> Check this IP is effected by resetting other subsystem.
1978
1979 //1 (1)
1980 if ((0 < delay_cycles)&&(!_rst_is_ap_software_reset_triggered()))
1981 {
1982 dbg_print("INFO (RGU) ap software reseting with delay cycles:%d... @ %s \r\n", delay_cycles, __FUNCTION__);
1983 while(!UART_CheckTxAllSentOut(uart_port1)){}
1984 _rst_trigger_ap_software_reset(delay_cycles);
1985 }
1986
1987 if (_rst_is_ap_software_reset_triggered() || g_ip_sup_sw_rst)
1988 ut_ret_status = _rst_check_ip_reset(testcase_ptr, test_items); //Only check if reset correctly.
1989 if (UT_REPORT_FAIL == ut_ret_status) return ut_ret_status;
1990
1991 ut_ret_status = _rst_run_ip_ut(testcase_ptr, test_items);
1992 if (UT_REPORT_FAIL == ut_ret_status) return ut_ret_status;
1993
1994 dbg_print("PASS (RGU) UT check after bootup @ %s \r\n", __FUNCTION__);
1995 if ((0 < delay_cycles)&&(!_rst_is_ap_software_reset_triggered())) //reset should be triggered before UT finished
1996 {
1997 dbg_print("Delay cycle exceeds the UT runtime @ %s \r\n", __FUNCTION__);
1998 //_rst_clear_ap_software_reset_status();
1999 while(1);
2000 }
2001 //1 (2)
2002 if ((0 == delay_cycles)&&(!_rst_is_ap_software_reset_triggered()))
2003 {
2004 dbg_print("INFO (RGU) ap software reseting ... @ %s \r\n", __FUNCTION__);
2005 while(!UART_CheckTxAllSentOut(uart_port1)){}
2006 _rst_trigger_ap_software_reset(0); //only md1sys got reboot. AP is not effected, therefore APSYS IP UT is necessary.
2007 while(1);
2008 }
2009 else
2010 dbg_print("INFO (RGU) ap software reset has been triggered @ %s \r\n", __FUNCTION__);
2011
2012 //dbg_print(".%s----%d\r\n", __FUNCTION__, i);
2013 //1 (4)
2014 _rst_clear_ap_software_reset_status();
2015
2016 if (KAL_FALSE == is_core_rebooted)
2017 {
2018 //1 (5)
2019 ut_ret_status = _rst_run_ip_ut(testcase_ptr, test_items);
2020 }
2021 }
2022 else
2023 {
2024 dbg_print("INFO(RGU) APSYS or MD1SYS is 'not' included in system converage. AP software reset test is ignored. \r\n");
2025 return UT_REPORT_PASS;
2026 }
2027 if (UT_REPORT_FAIL == ut_ret_status)
2028 {
2029 dbg_print("********************************************\r\n");
2030 dbg_print("^^ AP software reset stage test ::FAIL::&&\r\n");
2031 dbg_print("********************************************\r\n");
2032 }
2033 else
2034 {
2035 dbg_print("********************************************\r\n");
2036 dbg_print("^^ AP software reset stage test ::PASS::&&\r\n");
2037 dbg_print("********************************************\r\n");
2038 }
2039 return ut_ret_status;
2040}
2041
2042UT_REPORT_STATUS _rst_md1sys_dominate_reset_scope(kal_bool control_load, rst_target_e targetIP,subsystem_e system_coverage, ut_testcase_struct *testcase_ptr, kal_uint32 test_items, kal_uint32 delay_cycles)
2043{
2044 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
2045 kal_uint32 reset_scope_idx;
2046
2047 dbg_print("Dominate RGU scope (%s) @ MIPS\r\n", __FUNCTION__);
2048 if (AP_SOFTWARE_RESET_MD == _rst_get_rgu_scope_to_clear_state())
2049 {
2050 _rst_clear_ap_software_reset_status();
2051 _rst_set_rgu_scope_to_clear_state(0);
2052 }
2053 reset_scope_idx = _rst_get_this_reset_scope();
2054 while (reset_scope_idx < RGU_RESET_SCOPE_END)
2055 {
2056 dbg_print("INFO (RGU) Waiting for all cores in the system coverage ready...\n\r");
2057 //TODO: wait system all ready
2058 dbg_print("INFO (RGU) All cores in the system coverage are ready. \r\n");
2059 switch (reset_scope_idx)
2060 {
2061 case SOFTWARE_RESET:
2062 ut_ret_status = _rst_examine_ip_through_software_reset(targetIP, testcase_ptr, test_items);
2063 break;
2064 case WHOLE_SYSTEM_RESET:
2065 ut_ret_status = _rst_examine_ip_through_whole_system_reset(system_coverage, testcase_ptr, test_items, delay_cycles);
2066 ut_ret_status = UT_REPORT_PASS;
2067 break;
2068 case AP_SOFTWARE_RESET_MD:
2069 ut_ret_status = _rst_examine_ip_through_ap_software_reset(system_coverage, testcase_ptr, test_items, delay_cycles, KAL_TRUE);
2070 break;
2071 default:
2072 dbg_print("ASSERT (Dennis): <line: %d in function: %s>\r\n", __LINE__, __FUNCTION__);
2073 ut_ret_status = UT_REPORT_FAIL;
2074 }
2075 if (UT_REPORT_PASS == ut_ret_status)
2076 {
2077 _rst_set_next_reset_scope(reset_scope_idx + 1);
2078 reset_scope_idx = _rst_get_this_reset_scope();
2079
2080 //To prevent some uncareful UT design that forgets to restore initial valu, this framework software reset the target IP before new scope test. .
2081 dbg_print("INFO (RGU) Restore IP's original value @ %s \r\n", __FUNCTION__);
2082 if (RST_NULL != targetIP)
2083 g_ip_sup_sw_rst = drv_rstctl_sw_reset(targetIP);
2084 else //Since the IP could not be reset, we need to clear the state for the next reset scope.
2085 {
2086 //Add AP software reset md here to create a clear state for the next reset scope.
2087 //Add the system state clear flag for distinguishment from reset for UT test.
2088 dbg_print("For RST_NULL, we use AP reset MD to restore IP's original value. \n\r");
2089 while(!UART_CheckTxAllSentOut(uart_port1)){}
2090 _rst_set_rgu_scope_to_clear_state(AP_SOFTWARE_RESET_MD);
2091 _rst_trigger_ap_software_reset(0);
2092 while(1);
2093 }
2094 }
2095 else
2096 {
2097 dbg_print("ASSERT (RGU): IP UT check fail. <line: %d in function: %s>\r\n", __LINE__, __FUNCTION__);
2098 return ut_ret_status;
2099 }
2100 }
2101
2102 return ut_ret_status;
2103}
2104
2105kal_uint32 g_RGU_IT_API_CALL_ACCUMULATOR = 0;
2106
2107UT_REPORT_STATUS drv_UT_within_RGU_framework(rst_target_e targetIP, subsystem_e target_system, subsystem_e system_coverage,
2108 ut_testcase_struct *testcase_ptr, kal_uint32 test_items, kal_uint32 delay_cycles)
2109{
2110 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
2111
2112 _rst_register_lisr();
2113
2114 if(drv_rstctl_disable_all_WDTs() == KAL_FALSE)
2115 {
2116 dbg_print("ASSERT (RGU): Disable WDT FAIL <line: %d in function: %s>\r\n", __LINE__, __FUNCTION__); //This case should not happen.
2117 return UT_REPORT_FAIL;
2118 }
2119 g_RGU_IT_API_CALL_ACCUMULATOR ++; //Global variable used to count the number of iterations that APIs are called.
2120 if (_rst_get_rgu_ut_result() != UT_REPORT_PASS) //The UT result of the previous iteration. If UT fails in earlier iteration, this iteration is ignored.
2121 { //Note: For the 1st iteration, the default value is 0. And UT_REPORT_PASS is 0 as well.
2122 dbg_print("Checking (api_call_acc,api_passed_acc) = (%d, %d): %d\r\n", g_RGU_IT_API_CALL_ACCUMULATOR,_rst_get_rgu_api_call_accumulator(), _rst_get_rgu_ut_result());
2123 if (g_RGU_IT_API_CALL_ACCUMULATOR == _rst_get_rgu_api_call_accumulator())
2124 dbg_print("INFO (RGU) RGU_IT UT fail! @ drv_UT_within_RGU_framework (%d)\r\n", g_RGU_IT_API_CALL_ACCUMULATOR);
2125 return UT_REPORT_FAIL; //If some UT fails one of early RGU_IT_API call, the reset RGU_IT_APIs are ignored.
2126 }
2127 dbg_print("INFO ACCUMU1:%d ; ACCUMU2:%d \r\n", g_RGU_IT_API_CALL_ACCUMULATOR, _rst_get_rgu_api_call_accumulator());
2128 if (g_RGU_IT_API_CALL_ACCUMULATOR <= _rst_get_rgu_api_call_accumulator())
2129 return UT_REPORT_PASS;
2130 dbg_print("\r\n\n\n\nINFO (RGU) API call accumulator: %d; Delay cycles: %d\n\n\r", g_RGU_IT_API_CALL_ACCUMULATOR, delay_cycles);
2131
2132 if (KAL_FALSE == _rst_is_system_within_converage(target_system, system_coverage))
2133 {
2134 dbg_print("ASSERT (RGU): Target system is not included in the system coverage <line: %d in function: %s>\r\n", __LINE__, __FUNCTION__);
2135 return UT_REPORT_FAIL;
2136 }
2137
2138 if (RGU_RESET_SCOPE_END == _rst_get_rgu_scope_to_clear_state()) //If the last whole system reset is triggered for a new iternation, the status must be cleared.
2139 {
2140 _rst_clear_ap_software_reset_status(); //Clear the whole system reset status.
2141 _rst_set_rgu_scope_to_clear_state(0); //Clear the ditinguishable flag that was marked as RGU_RESET_SCOPE_END.
2142 }
2143
2144 dbg_print("%s @ MIPS-iterAptiv\n\r", __FUNCTION__);
2145
2146 ut_ret_status = _rst_md1sys_dominate_reset_scope(KAL_TRUE, targetIP, system_coverage, testcase_ptr, test_items, delay_cycles); //Dominate the reset scope and tests the UTs.
2147 _rst_prepare_for_next_rgu_it_call(system_coverage, ut_ret_status); //reset the system to for the next API (drv_UT_within_RGU_framework) call.
2148
2149 return ut_ret_status;
2150}
2151
2152
2153#else /* !defined(RSTCTL_FPGA_PLAT) */
2154
2155void _rst_set_system_ready_sts(kal_uint32 system, kal_uint32 system_coverage)
2156{
2157 kal_uint32 current_val;
2158 if ((system & system_coverage)== 0)
2159 {
2160 dbg_print("%s: system out of system coverage\n\r", __FUNCTION__);
2161 ASSERT(0);
2162 }
2163 //Add switch case to prevent race condition
2164 switch (system)
2165 {
2166 case APSYS: //is the first one to enable ready status.
2167 //no need to wait.
2168 dbg_print("Setting MDRGU WDT DUMMY ....\r\n");
2169 break;
2170 case MD1SYS: //is the second one to enable ready status.
2171 dbg_print("Wait for (APSYS) APRGU WDT DUMMY write ready...\r\n");
2172 while((DRV_Reg32(REG_APRSTCTL_WDT_DUMMY) & (APSYS))!= (APSYS & system_coverage));
2173 break;
2174 }
2175 current_val = DRV_Reg32(REG_APRSTCTL_WDT_DUMMY) | system;
2176 DRV_WriteReg32(REG_APRSTCTL_WDT_DUMMY, current_val);
2177 dbg_print("After writing ready status, REG_APRSTCTL_WDT_DUMMY = 0x%x\r\n", DRV_Reg32(REG_APRSTCTL_WDT_DUMMY));
2178}
2179
2180void _rst_clr_system_ready_sts(kal_uint32 system)
2181{
2182 kal_uint32 current_val;
2183 if ((system & (APSYS | MD1SYS))== 0)
2184 {
2185 dbg_print("%s: system out of coverage\n\r", __FUNCTION__);
2186 ASSERT(0);
2187 }
2188 current_val = DRV_Reg32(REG_APRSTCTL_WDT_DUMMY) & ~(system);
2189 DRV_WriteReg32(REG_APRSTCTL_WDT_DUMMY, current_val);
2190}
2191
2192kal_uint32 _rst_get_system_ready_sts(void)
2193{
2194 return (DRV_Reg32(REG_APRSTCTL_WDT_DUMMY));
2195}
2196
2197kal_uint32 _rst_get_this_reset_scope(void)
2198{
2199 kal_uint32 this_reset_scope;
2200 this_reset_scope = (DRV_Reg32(REG_APRSTCTL_DUMMY) & RGU_RESET_SCOPE_MASK) >> RGU_RESET_SCOPE_OFFSET;
2201 return this_reset_scope;
2202}
2203
2204void _rst_set_next_reset_scope(kal_uint32 next_reset_scope)
2205{
2206 kal_uint32 dummy_content;
2207 dummy_content = (DRV_Reg32(REG_APRSTCTL_DUMMY) & (~RGU_RESET_SCOPE_MASK)) | (next_reset_scope << RGU_RESET_SCOPE_OFFSET);
2208 DRV_WriteReg32(REG_APRSTCTL_DUMMY, dummy_content);
2209}
2210
2211
2212void _rst_set_rgu_frmwrk_parameter(kal_uint32 content)
2213{
2214 kal_uint32 current_val;
2215 current_val = DRV_Reg32(REG_APRSTCTL_DUMMY) & (~RGU_FRMWRK_PARAMETER_MASK);
2216 if ((content & (~RGU_FRMWRK_PARAMETER_MASK)) > 0) //exceed the parameter range.
2217 ASSERT(0);
2218 else
2219 {
2220 current_val |= ((content << RGU_FRMWRK_PARAMETER_OFFSET) & RGU_FRMWRK_PARAMETER_MASK);
2221 DRV_WriteReg32(REG_APRSTCTL_DUMMY, current_val);
2222 }
2223}
2224
2225kal_uint32 _rst_get_rgu_frmwrk_parameter(void)
2226{
2227 return (DRV_Reg32(REG_APRSTCTL_DUMMY) & RGU_FRMWRK_PARAMETER_MASK) >> RGU_FRMWRK_PARAMETER_OFFSET;
2228}
2229
2230void _rst_set_rgu_ut_result(kal_uint32 ut_result) //ut_result = UT_REPORT_PASS (0) or UT_REPORT_FAIL(-1).
2231{
2232 kal_uint32 current_val;
2233 current_val = DRV_Reg32(REG_APRSTCTL_DUMMY) & (~RGU_RESET_UT_RESULT_MASK);
2234 current_val |= (ut_result & RGU_RESET_UT_RESULT_MASK >> RGU_RESET_UT_RESULT_OFFSET)<<RGU_RESET_UT_RESULT_OFFSET;
2235 DRV_WriteReg32(REG_APRSTCTL_DUMMY, current_val);
2236}
2237
2238kal_uint32 _rst_get_rgu_ut_result(void)
2239{
2240 kal_uint32 current_val;
2241 current_val = (DRV_Reg32(REG_APRSTCTL_DUMMY) & RGU_RESET_UT_RESULT_MASK) >> RGU_RESET_UT_RESULT_OFFSET;
2242 if (UT_REPORT_PASS == current_val)
2243 return UT_REPORT_PASS;
2244 else
2245 return UT_REPORT_FAIL;
2246}
2247
2248void _rst_set_rgu_scope_to_clear_state(kal_uint32 clear_scope)
2249{
2250 kal_uint32 current_val;
2251 current_val = DRV_Reg32(REG_APRSTCTL_DUMMY) & (~RGU_SCOPE_TO_CLEAR_STATE_MASK) ;
2252 current_val |= (clear_scope & (RGU_SCOPE_TO_CLEAR_STATE_MASK >> RGU_SCOPE_TO_CLEAR_STATE_OFFSET)) << RGU_SCOPE_TO_CLEAR_STATE_OFFSET;
2253 DRV_WriteReg32(REG_APRSTCTL_DUMMY, current_val);
2254}
2255
2256kal_uint32 _rst_get_rgu_scope_to_clear_state(void)
2257{
2258 return ((DRV_Reg32(REG_APRSTCTL_DUMMY) & RGU_SCOPE_TO_CLEAR_STATE_MASK) >> RGU_SCOPE_TO_CLEAR_STATE_OFFSET);
2259}
2260
2261
2262void _rst_inc_rgu_api_call_accumulator(void)
2263{
2264 kal_uint32 current_val;
2265 current_val = (DRV_Reg32(REG_APRSTCTL_DUMMY) & (~RGU_API_CALL_ACCUMULATOR_MASK));
2266 current_val |= (((DRV_Reg32(REG_APRSTCTL_DUMMY) & RGU_API_CALL_ACCUMULATOR_MASK) + (1<<RGU_API_CALL_ACCUMULATOR_OFFSET))&RGU_API_CALL_ACCUMULATOR_MASK);
2267 DRV_WriteReg32(REG_APRSTCTL_DUMMY, current_val);
2268}
2269
2270kal_uint32 _rst_get_rgu_api_call_accumulator(void)
2271{
2272 return ((DRV_Reg32(REG_APRSTCTL_DUMMY) & RGU_API_CALL_ACCUMULATOR_MASK)>>RGU_API_CALL_ACCUMULATOR_OFFSET);
2273}
2274
2275
2276kal_bool _rst_is_system_within_converage(subsystem_e target_system, subsystem_e system_converage)
2277{
2278 if ((target_system & system_converage) == target_system)
2279 return KAL_TRUE;
2280 else
2281 return KAL_FALSE;
2282}
2283
2284subsystem_e _rst_return_dominate_system(subsystem_e target_system)
2285{
2286 if (APSYS == (target_system & APSYS))
2287 return APSYS;
2288 if (MD1SYS == (target_system & MD1SYS))
2289 return MD1SYS;
2290 ASSERT(0);
2291 return 0;
2292}
2293
2294
2295kal_bool _rst_setup_whole_system_reset_trigger_path(void)
2296{
2297 kal_bool ret_status = KAL_TRUE;
2298 kal_uint32 current_val;
2299 //actually, for whole system reset, it does not need to setup the trigger path.
2300 //Set APRGU in reset mode. --> APRGU IRQ disable.
2301 current_val = DRV_Reg32(REG_APRSTCTL_WDTCR) & ~(RSTCTL_APWDTCR_WDT_IRQEN);
2302 current_val &= ~(RSTCTL_APWDTCR_WDT_SPD_UP);
2303 DRV_WriteReg32(REG_APRSTCTL_WDTCR,RSTCTL_APWDTCR_KEY | current_val);
2304 return ret_status;
2305}
2306
2307kal_bool _rst_trigger_whole_system_reset(kal_uint32 delay_cycles)
2308{
2309 kal_bool ret_status = KAL_TRUE;
2310 _rst_setup_whole_system_reset_trigger_path(); //Set APRGU in reset mode.
2311
2312 //for this case, we need to trigger reset in APRGU.
2313 if (0 < delay_cycles)
2314 {
2315 kal_uint32 current_val;
2316 DRV_WriteReg32(REG_APRSTCTL_WDTIR, RSTCTL_APWDTIR_KEY | (delay_cycles & RSTCTL_APWDTIR_INTERVAL_MASK));
2317 current_val = DRV_Reg32(REG_APRSTCTL_WDTCR);
2318 current_val |= RSTCTL_APWDTCR_WDT_EN;
2319 DRV_WriteReg32(REG_APRSTCTL_WDTCR,RSTCTL_APWDTCR_KEY | current_val);
2320 DRV_WriteReg32(REG_APRSTCTL_WDTRR, RSTCTL_APWDTRR_KEY);
2321 }
2322 else //trigger software WDT
2323 DRV_WriteReg32(REG_APRSTCTL_SRCMR_SWDT,RSTCTL_SRCMR_KEY_SWDT);
2324 return ret_status;
2325}
2326
2327kal_bool _rst_is_whole_system_reset_triggered()
2328{
2329 kal_uint32 current_val;
2330 //Check WDTSR.
2331 current_val = DRV_Reg32(REG_APRSTCTL_WDTSR);
2332 switch(current_val & RSTCTL_APWDTSR_STATUS_MASK)
2333 {
2334 case RSTCTL_APWDTSR_HWDT_STS:
2335 dbg_print("Hardware WDT (%d times)\r\n", (current_val>>RSTCTL_APWDTSR_HW_WDT_CNT_OFFSET) & RSTCTL_APWDTSR_HW_WDT_CNT_MASK);
2336 return KAL_TRUE;
2337 case RSTCTL_APWDTSR_SWDT_STS:
2338 dbg_print("Software WDT (%d times)\r\n", (current_val>>RSTCTL_APWDTSR_SW_WDT_CNT_OFFSET) & RSTCTL_APWDTSR_SW_WDT_CNT_MASK);
2339 return KAL_TRUE;
2340 case 0:
2341 dbg_print("INFO (RGU) Whole system reset is not triggered\r\n");
2342 return KAL_FALSE;
2343 default:
2344 dbg_print("Assert(RGU): Unexpected status case 0X%08X <%d line in %s>\r\n",(current_val & RSTCTL_APWDTSR_STATUS_MASK), __LINE__, __FUNCTION__ );
2345 return KAL_FALSE;
2346 }
2347}
2348
2349kal_bool _rst_clear_whole_system_reset_status(void)
2350{
2351 kal_uint32 current_val;
2352 //Note: remember to disable WDT make sure system under control.
2353 //Disable the trigger path
2354
2355 current_val = DRV_Reg32(REG_APRSTCTL_WDTCR);
2356 current_val &= ~RSTCTL_APWDTCR_WDT_EN;
2357 DRV_WriteReg32(REG_APRSTCTL_WDTCR, RSTCTL_APWDTCR_KEY | current_val);
2358 //Clear the status caused by APRGU reset.
2359 //Status register: WDTSR (swdt counter, hwdt counter, status)
2360 DRV_WriteReg32(REG_APRSTCTL_WDTSR, RSTCTL_APWDTSR_KEY
2361 | RSTCTL_APWDTSR_CNT_CLR_MASK << RSTCTL_APWDTSR_CNT_CLR_OFFSET
2362 | RSTCTL_APWDTSR_STS_CLR_MASK << RSTCTL_APWDTSR_STS_CLR_OFFSET);
2363 return KAL_FALSE;
2364}
2365
2366kal_bool _rst_setup_ap_software_reset_trigger_path(void)
2367{
2368 kal_bool ret_status = KAL_TRUE;
2369 kal_uint32 current_val;
2370 //Set the path from MDRGU to APRGU. (MDRGU IRQ enable)
2371 current_val = DRV_Reg32(REG_MDRSTCTL_WDTCR);
2372 current_val &= ~(RSTCTL_WDTCR_WDT_SPD_UP);
2373 current_val |= (RSTCTL_WDTCR_AUX_WDT_IRQEN);
2374 DRV_WriteReg32(REG_MDRSTCTL_WDTCR,RSTCTL_WDTCR_KEY | current_val); //1. disable speedup. 2. Enable IRQ_EN to AP
2375 //Set up the path to trigger CA7 ISR.
2376 DRV_WriteReg32(REG_APRSTCTL_MDWDTCFG_MD1,RSTCTL_APMDWDTCFG_MD1_KEY | RSTCTL_APMDWDTCFG_MD1_WDT_LV_EN_MD1);
2377
2378 DRV_WriteReg32(REG_MDRSTCTL_WDTER_MDSYS, 0xBFFFFFFF);
2379
2380 return ret_status;
2381}
2382
2383kal_bool _rst_trigger_ap_software_reset(kal_uint32 delay_cycles)
2384{
2385 kal_bool ret_status = KAL_TRUE;
2386 kal_uint32 current_val;
2387 _rst_setup_ap_software_reset_trigger_path(); //Set up the path to allow trigger CA7 ISR. (MDRGU: enable IRQ, APRGU: enable level )
2388 if (0 < delay_cycles)
2389 {
2390 #if 0
2391/* under construction !*/
2392/* under construction !*/
2393/* under construction !*/
2394/* under construction !*/
2395/* under construction !*/
2396/* under construction !*/
2397/* under construction !*/
2398/* under construction !*/
2399 #endif
2400
2401 DRV_WriteReg32(REG_MDRSTCTL_WDTIR_AUX, RSTCTL_WDTIR_AUX_KEY | (delay_cycles & RSTCTL_WDTIR_INTERVAL_MASK));
2402 current_val = DRV_Reg32(REG_MDRSTCTL_WDTCR);
2403 current_val |= RSTCTL_WDTCR_AUX_WDT_EN;
2404 DRV_WriteReg32(REG_MDRSTCTL_WDTCR,RSTCTL_WDTCR_KEY | current_val);
2405 DRV_WriteReg32(REG_MDRSTCTL_WDTRR, RSTCTL_WDTRR_KEY|RSTCTL_WDTRR_WDT_RESTART);
2406 }
2407 else
2408 {
2409 /* Also trigger WDT1, the time interval should be 1 */
2410 DRV_WriteReg32(REG_MDRSTCTL_WDTIR, RSTCTL_WDTIR_KEY | (1 & RSTCTL_WDTIR_INTERVAL_MASK));
2411
2412 current_val = DRV_Reg32(REG_MDRSTCTL_WDTCR);
2413 current_val |= RSTCTL_WDTCR_WDT_EN;
2414 DRV_WriteReg32(REG_MDRSTCTL_WDTCR,RSTCTL_WDTCR_KEY | current_val);
2415
2416 DRV_WriteReg32(REG_MDRSTCTL_WDTRR, RSTCTL_WDTRR_KEY|RSTCTL_WDTRR_WDT_RESTART); //we only needs to wait for MDRGU WDT to down count the delay cycles.
2417 }
2418 return ret_status;
2419}
2420
2421
2422kal_bool _rst_is_ap_software_reset_triggered()
2423{
2424 //CHECK WDTSR (MD1_WDT_STS)
2425 kal_uint32 current_val;
2426 current_val = (DRV_Reg32(REG_APRSTCTL_WDTSR_MD1)>>RSTCTL_APWDTSR_MD1_STATUS_OFFSET)& RSTCTL_APWDTSR_MD1_STATUS_MASK;
2427 if ((current_val > 0)&& (AP_SOFTWARE_RESET_MD == _rst_get_rgu_frmwrk_parameter()))
2428 {
2429 dbg_print("AP software reset MD triggered by MDRGU \r\n");
2430 return KAL_TRUE;
2431 }
2432 else
2433 return KAL_FALSE;
2434}
2435
2436kal_bool _rst_clear_ap_software_reset_status(void)
2437{
2438 kal_uint32 current_val;
2439 //Note: remember to disable WDT make sure system under control.
2440 current_val = DRV_Reg32(REG_MDRSTCTL_WDTCR);
2441 current_val &= ~RSTCTL_WDTCR_AUX_WDT_EN;
2442 DRV_WriteReg32(REG_MDRSTCTL_WDTCR, RSTCTL_WDTCR_KEY | current_val);
2443 //Disable the trigger path
2444 current_val = DRV_Reg32(REG_APRSTCTL_MDWDTCFG_MD1) & ~RSTCTL_APMDWDTCFG_MD1_WDT_LV_EN_MD1;
2445 DRV_WriteReg32(REG_APRSTCTL_MDWDTCFG_MD1, RSTCTL_APMDWDTCFG_MD1_KEY | current_val);
2446 //Clear the status caused by MDRGU IRQ
2447 DRV_WriteReg32(REG_APRSTCTL_WDTSR_MD1, RSTCTL_APWDTSR_MD1_KEY | RSTCTL_APWDTSR_MD1_STS_CLR_MASK << RSTCTL_APWDTSR_MD1_STS_CLR_OFFSET);
2448 //Clear the parameter as well.
2449 _rst_set_rgu_frmwrk_parameter(0);
2450 return KAL_TRUE;
2451}
2452
2453UT_REPORT_STATUS _rst_check_ip_reset(ut_testcase_struct *testcase_ptr, kal_uint32 test_items) //Only check if reset correctly.
2454{
2455 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
2456 if (0 < test_items) //test_items must equals 1 at least. (test case is mandatorily located at 1st entry. )
2457 {
2458 dbg_print("\nCheck IP initial value: %s\n\r", (testcase_ptr)[0].description);
2459 ut_ret_status = (testcase_ptr)[0]._main_fn(testcase_ptr[0].flags, testcase_ptr[0].para); // check initial after reset
2460 }
2461 else
2462 {
2463 dbg_print("ASSERT (RGU): <line: %d in function: %s>\r\n", __LINE__, __FUNCTION__); //This case should not happen.
2464 ut_ret_status = UT_REPORT_FAIL;
2465 }
2466 if (UT_REPORT_PASS == ut_ret_status)
2467 dbg_print("\n\n IP initial value check: PASS \n\r");
2468 else
2469 dbg_print("\n\n IP initial value check: FAIL \n\r");
2470 return ut_ret_status;
2471}
2472
2473UT_REPORT_STATUS _rst_run_ip_ut(ut_testcase_struct *testcase_ptr, kal_uint32 test_items)
2474{
2475 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
2476 kal_uint32 func_idx;
2477 if (1 < test_items)
2478 {
2479 for(func_idx = 1; func_idx < test_items; func_idx ++)
2480 {
2481 dbg_print("\nIP unit test: %s\n\r", (testcase_ptr)[func_idx].description);
2482 ut_ret_status = (testcase_ptr)[func_idx]._main_fn(testcase_ptr[func_idx].flags, testcase_ptr[func_idx].para); // Other UTs exclude initial value check.
2483 if (UT_REPORT_FAIL == ut_ret_status)
2484 return ut_ret_status;
2485 }
2486 }
2487 else //1. no test case. 2. check IP's initial value only (no other UTs)
2488 {
2489 dbg_print("ASSERT (RGU): <line: %d in function: %s>\r\n", __LINE__, __FUNCTION__); //This case should not happen.
2490 ut_ret_status = UT_REPORT_FAIL;
2491 }
2492 if (UT_REPORT_PASS == ut_ret_status)
2493 dbg_print("\n\n IP unit test: PASS \n\r");
2494 else
2495 dbg_print("\n\n IP unit test: FAIL \n\r");
2496 return ut_ret_status;
2497}
2498
2499void _rst_prepare_for_next_rgu_it_call(subsystem_e system_coverage, UT_REPORT_STATUS ut_ret_status)
2500{
2501 _rst_inc_rgu_api_call_accumulator(); //Increase RGU_API_CALL accumulator to prevent executing allready tested RGU_API.
2502 _rst_set_rgu_ut_result(ut_ret_status); //Store the ut_ret_status. If the status is UT_REPORT_FAIL, all the reset RGU_APIs will be ignored.
2503 UT_DELAY_LOOP(_RST_DURATION_LOOP_DEFAULT_VALUE); //Wait for effective register write.
2504 if (APSYS == (system_coverage & APSYS))
2505 {
2506 dbg_print("Trigger AP reset MD for next framework interation....\n\r");
2507 dbg_print("Reseting MDSYS through AP reset MD....\n\r\n\r\n\r");
2508 _rst_clr_system_ready_sts(MD1SYS);
2509 _rst_set_rgu_scope_to_clear_state(AP_SOFTWARE_RESET_MD);
2510 _rst_trigger_ap_software_reset(0); //At the end of this API call, trigger whole systemr reset to make system ready for next API call.
2511 while(1);
2512
2513 }
2514 else //Without AP, system coverage only includes MD1SYS, L1SYS, and/or ARM7SYS.
2515 {
2516 dbg_print("Without AP to boot up Pcore, you need to reload code through CMM again. \n\r");
2517 while(1);
2518 }
2519}
2520
2521UT_REPORT_STATUS _rst_examine_ip_through_software_reset(rst_target_e targetIP, ut_testcase_struct *testcase_ptr, kal_uint32 test_items)
2522{
2523 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
2524 if (RST_NULL == targetIP) return UT_REPORT_PASS; //Some IPs (like MEMSYS) do not tolerate software reset.
2525 dbg_print("\n\n\nINFO (RGU) Software reset stage: \r\n");
2526 ut_ret_status = _rst_check_ip_reset(testcase_ptr, test_items); //Only check if power on reset correctly.
2527 if (UT_REPORT_FAIL == ut_ret_status)
2528 return ut_ret_status;
2529 ut_ret_status = _rst_run_ip_ut(testcase_ptr, test_items);
2530 if (UT_REPORT_FAIL == ut_ret_status)
2531 return ut_ret_status;
2532
2533 dbg_print("PASS (RGU) UT check after bootup @ %s \r\n", __FUNCTION__);
2534 //The softwre reset function
2535 dbg_print("INFO (RGU) Software reset IP @ %s \r\n", __FUNCTION__);
2536 if (KAL_FALSE == drv_rstctl_sw_reset(targetIP)) {
2537 dbg_print("Target IP do NOT support SW reset function\r\n");
2538 goto end;
2539 }
2540 ut_ret_status = _rst_check_ip_reset(testcase_ptr, test_items); //Only check if reset correctly.
2541 if (UT_REPORT_FAIL == ut_ret_status)
2542 return ut_ret_status;
2543 ut_ret_status = _rst_run_ip_ut(testcase_ptr, test_items);
2544
2545end:
2546 if (UT_REPORT_FAIL == ut_ret_status)
2547 {
2548 dbg_print("FAIL (RGU) UT check[software reset] @ %s \r\n\n\n", __FUNCTION__);
2549 dbg_print("****************************************\r\n");
2550 dbg_print("^^ Software reset stage test ::FAIL::&&\r\n");
2551 dbg_print("****************************************\r\n");
2552 }
2553 else
2554 {
2555 dbg_print("PASS (RGU) UT check[software reset] @ %s \r\n", __FUNCTION__);
2556 dbg_print("****************************************\r\n");
2557 dbg_print("^^ Software reset stage test ::PASS::&&\r\n");
2558 dbg_print("****************************************\r\n");
2559 }
2560 return ut_ret_status;
2561}
2562
2563UT_REPORT_STATUS _rst_examine_ip_through_whole_system_reset(subsystem_e system_converage,ut_testcase_struct *testcase_ptr, kal_uint32 test_items, kal_uint32 delay_cycles)
2564{
2565 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
2566 dbg_print("\n\n\nINFO (RGU) Whole system reset stage: \r\n");
2567 if (KAL_TRUE ==_rst_is_system_within_converage(APSYS, system_converage))
2568 {
2569 //(1) --> UT --> (2) --> (3) --> reboot --> UT -->(4)
2570 //1 (1)
2571 if ((0 < delay_cycles)&&(!_rst_is_whole_system_reset_triggered()))
2572 {
2573 _rst_clr_system_ready_sts(APSYS | MD1SYS);
2574 _rst_trigger_whole_system_reset(delay_cycles);
2575 }
2576 ut_ret_status = _rst_check_ip_reset(testcase_ptr, test_items); //Only check if reset correctly.
2577 if (UT_REPORT_FAIL == ut_ret_status)
2578 return ut_ret_status;
2579 ut_ret_status = _rst_run_ip_ut(testcase_ptr, test_items);
2580 if (UT_REPORT_FAIL == ut_ret_status)
2581 return ut_ret_status;
2582 dbg_print("PASS (RGU) UT check after bootup @ %s \r\n", __FUNCTION__);
2583
2584 if ((0 < delay_cycles)&&(!_rst_is_whole_system_reset_triggered())) //reset should be triggered before UT finished
2585 {
2586 dbg_print("Delay cycle exceeds the UT runtime @ %s \r\n", __FUNCTION__);
2587 _rst_clear_whole_system_reset_status();
2588 ASSERT(0);
2589 }
2590 //1 (2)
2591 if ((0 == delay_cycles)&&(!_rst_is_whole_system_reset_triggered()))
2592 {
2593 dbg_print("INFO (RGU) whole system reseting ... @ %s \r\n", __FUNCTION__);
2594 _rst_clr_system_ready_sts(APSYS | MD1SYS);
2595 _rst_trigger_whole_system_reset(0); //whole system reset.
2596 while(1);
2597 }
2598 else
2599 dbg_print("INFO (RGU) whole system reset has been triggered @ %s \r\n", __FUNCTION__);
2600 //1 (3)
2601 //while(!_rst_is_whole_system_reset_triggered());
2602 //1 (4)
2603 _rst_clear_whole_system_reset_status();
2604 }
2605 else //Igrnore whole system reset.
2606 {
2607 dbg_print("INFO(RGU) APSYS is 'not' included in system converage. Whole system reset test is ignored. \r\n");
2608 return UT_REPORT_PASS;
2609 }
2610 if (UT_REPORT_FAIL == ut_ret_status)
2611 {
2612 dbg_print("********************************************\r\n");
2613 dbg_print("^^ Whole system reset stage test ::FAIL::&&\r\n");
2614 dbg_print("********************************************\r\n");
2615 }
2616 else
2617 {
2618 dbg_print("********************************************\r\n");
2619 dbg_print("^^ Whole system reset stage test ::PASS::&&\r\n");
2620 dbg_print("********************************************\r\n");
2621 }
2622 return ut_ret_status;
2623
2624}
2625
2626kal_bool g_ip_sup_sw_rst = KAL_FALSE;
2627
2628UT_REPORT_STATUS _rst_examine_ip_through_ap_software_reset(subsystem_e system_converage, ut_testcase_struct *testcase_ptr, kal_uint32 test_items, kal_uint32 delay_cycles, kal_bool is_core_rebooted)
2629{
2630 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
2631 dbg_print("\n\n\nINFO (RGU) AP software reset stage: \r\n");
2632 //AP software reset MD requires cooperation between APSYS and MD1SYS.
2633 if (KAL_TRUE ==_rst_is_system_within_converage(MD1SYS | APSYS, system_converage))
2634 {
2635 //(1) --> UT --> (2) --> (3) --> reboot --> (4) [is_core_rebooted == KAL_TRUE]
2636 //(1) --> UT --> (2) --> (3) --> (4) --> (5) UT [is_core_rebooted == KAL_FALSE] --> Check this IP is effected by resetting other subsystem.
2637
2638 //1 (1)
2639 if ((0 < delay_cycles)&&(!_rst_is_ap_software_reset_triggered()))
2640 {
2641 dbg_print("INFO (RGU) ap software reseting with delay cycles:%d... @ %s \r\n", delay_cycles, __FUNCTION__);
2642 _rst_clr_system_ready_sts(MD1SYS);
2643 _rst_trigger_ap_software_reset(delay_cycles);
2644 }
2645
2646 if (_rst_is_ap_software_reset_triggered() || g_ip_sup_sw_rst)
2647 ut_ret_status = _rst_check_ip_reset(testcase_ptr, test_items); //Only check if reset correctly.
2648
2649 if (UT_REPORT_FAIL == ut_ret_status)
2650 return ut_ret_status;
2651 ut_ret_status = _rst_run_ip_ut(testcase_ptr, test_items);
2652 if (UT_REPORT_FAIL == ut_ret_status)
2653 return ut_ret_status;
2654 dbg_print("PASS (RGU) UT check after bootup @ %s \r\n", __FUNCTION__);
2655 if ((0 < delay_cycles)&&(!_rst_is_ap_software_reset_triggered())) //reset should be triggered before UT finished
2656 {
2657 dbg_print("Delay cycle exceeds the UT runtime @ %s \r\n", __FUNCTION__);
2658 //_rst_clear_ap_software_reset_status();
2659 //ASSERT(0);
2660 while(1);
2661 }
2662 //1 (2)
2663 if ((0 == delay_cycles)&&(!_rst_is_ap_software_reset_triggered()))
2664 {
2665 dbg_print("INFO (RGU) ap software reseting ... @ %s \r\n", __FUNCTION__);
2666 _rst_clr_system_ready_sts(MD1SYS);
2667 _rst_trigger_ap_software_reset(0); //only md1sys got reboot. AP is not effected, therefore APSYS IP UT is necessary.
2668 while(1);
2669 }
2670 else
2671 dbg_print("INFO (RGU) ap software reset has been triggered @ %s \r\n", __FUNCTION__);
2672
2673 //1 (4)
2674 _rst_clear_ap_software_reset_status();
2675
2676 if (KAL_FALSE == is_core_rebooted)
2677 {
2678 //1 (5)
2679 ut_ret_status = _rst_run_ip_ut(testcase_ptr, test_items);
2680 }
2681 }
2682 else
2683 {
2684 dbg_print("INFO(RGU) APSYS or MD1SYS is 'not' included in system converage. AP software reset test is ignored. \r\n");
2685 return UT_REPORT_PASS;
2686 }
2687 if (UT_REPORT_FAIL == ut_ret_status)
2688 {
2689 dbg_print("********************************************\r\n");
2690 dbg_print("^^ AP software reset stage test ::FAIL::&&\r\n");
2691 dbg_print("********************************************\r\n");
2692 }
2693 else
2694 {
2695 dbg_print("********************************************\r\n");
2696 dbg_print("^^ AP software reset stage test ::PASS::&&\r\n");
2697 dbg_print("********************************************\r\n");
2698 }
2699 return ut_ret_status;
2700}
2701
2702UT_REPORT_STATUS _rst_md1sys_dominate_reset_scope(kal_bool control_load, rst_target_e targetIP,subsystem_e system_coverage, ut_testcase_struct *testcase_ptr, kal_uint32 test_items, kal_uint32 delay_cycles)
2703{
2704 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
2705 kal_uint32 reset_scope_idx;
2706
2707 _rst_set_system_ready_sts(MD1SYS, system_coverage); //Notify the reset cores that MD1SYS is ready.
2708 if (0== test_items)
2709 {
2710 dbg_print("Waiting for wall cores are ready....\r\n");
2711 while(system_coverage != (_rst_get_system_ready_sts()& system_coverage));
2712 dbg_print("INFO (RGU) All cores in the system coverage are ready. \r\n");
2713 dbg_print("Dummy load to react RGU req (%s) @ MIPS\r\n", __FUNCTION__);
2714 while(1); //Just act as a dummy-load
2715 }
2716 else //Control load or support load
2717 {
2718 if (KAL_TRUE != control_load) //Support load
2719 {
2720 dbg_print("Waiting for wall cores are ready....\r\n");
2721 while(system_coverage != (_rst_get_system_ready_sts()& system_coverage));
2722 dbg_print("INFO (RGU) All cores in the system coverage are ready. \r\n");
2723 dbg_print("Support load to call the UT (%s) @ MIPS\n\r", __FUNCTION__);
2724 while(UT_REPORT_PASS == ut_ret_status) // As long as the ut_ret_status is UT_REPORT_PASS, the support load could run the program infinitely.
2725 {
2726 ut_ret_status = _rst_check_ip_reset(testcase_ptr, test_items); //Only check if power on reset correctly.
2727 if (UT_REPORT_PASS == ut_ret_status )
2728 {
2729 dbg_print("PASS (RGU) [Support load] Initial check pass @%s\r\n", __FUNCTION__);
2730 ut_ret_status = _rst_run_ip_ut(testcase_ptr, test_items);
2731 if (UT_REPORT_PASS == ut_ret_status )
2732 dbg_print("PASS (RGU) [Support load] UT check pass @%s\r\n", __FUNCTION__);
2733 else
2734 dbg_print("FAIL (RGU) [Support load] UT check fail @%s\r\n", __FUNCTION__);
2735 }
2736 else
2737 dbg_print("FAIL (RGU) [Support load] Initial check fail @%s\r\n", __FUNCTION__);
2738 while(system_coverage != (_rst_get_system_ready_sts()& system_coverage));
2739 }
2740 while(1); //If one of the UT's ut_ret_statuses is UT_REPORT_FAIL, the support load will break the above cycle to act as a dummy load.
2741 }
2742 else //Control load
2743 {
2744 dbg_print("Dominate RGU scope (%s) @ MIPS\r\n", __FUNCTION__);
2745 if (AP_SOFTWARE_RESET_MD == _rst_get_rgu_scope_to_clear_state())
2746 {
2747 _rst_clear_ap_software_reset_status();
2748 _rst_set_rgu_scope_to_clear_state(0);
2749 }
2750 reset_scope_idx = _rst_get_this_reset_scope();
2751 while (reset_scope_idx < RGU_RESET_SCOPE_END)
2752 {
2753 dbg_print("INFO (RGU) Waiting for all cores in the system coverage ready...\n\r");
2754 //TODO: wait system all ready
2755 dbg_print("INFO (RGU) All cores in the system coverage are ready. \r\n");
2756 switch (reset_scope_idx)
2757 {
2758 case SOFTWARE_RESET:
2759 ut_ret_status = _rst_examine_ip_through_software_reset(targetIP, testcase_ptr, test_items);
2760 break;
2761 case WHOLE_SYSTEM_RESET:
2762 //ut_ret_status = _rst_examine_ip_through_whole_system_reset(system_coverage, testcase_ptr, test_items, delay_cycles);
2763 ut_ret_status = UT_REPORT_PASS;
2764 break;
2765 case AP_SOFTWARE_RESET_MD:
2766 ut_ret_status = _rst_examine_ip_through_ap_software_reset(system_coverage, testcase_ptr, test_items, delay_cycles, KAL_TRUE);
2767 break;
2768 default:
2769 dbg_print("ASSERT (Dennis): <line: %d in function: %s>\r\n", __LINE__, __FUNCTION__);
2770 ut_ret_status = UT_REPORT_FAIL;
2771 }
2772 if (UT_REPORT_PASS == ut_ret_status)
2773 {
2774 _rst_set_next_reset_scope(reset_scope_idx + 1);
2775 reset_scope_idx = _rst_get_this_reset_scope();
2776
2777 //To prevent some uncareful UT design that forgets to restore initial valu, this framework software reset the target IP before new scope test. .
2778 dbg_print("INFO (RGU) Restore IP's original value @ %s \r\n", __FUNCTION__);
2779 if (RST_NULL != targetIP)
2780 g_ip_sup_sw_rst = drv_rstctl_sw_reset(targetIP);
2781 else //Since the IP could not be reset, we need to clear the state for the next reset scope.
2782 {
2783 //Add AP software reset md here to create a clear state for the next reset scope.
2784 //Add the system state clear flag for distinguishment from reset for UT test.
2785 _rst_set_rgu_scope_to_clear_state(AP_SOFTWARE_RESET_MD);
2786 _rst_clr_system_ready_sts(MD1SYS);
2787 _rst_trigger_ap_software_reset(0);
2788 dbg_print("For RST_NULL, we use AP reset MD to restore IP's original value. \n\r");
2789 while(1);
2790 }
2791 }
2792 else
2793 {
2794 dbg_print("ASSERT (RGU): IP UT check fail. <line: %d in function: %s>\r\n", __LINE__, __FUNCTION__);
2795 return ut_ret_status;
2796 }
2797 }
2798 } //end ocntrol load
2799 } //end item!=0
2800 if (RGU_RESET_SCOPE_END == reset_scope_idx) //Considering multiple call of this API, we need to reset the scope idx as well..
2801 _rst_set_next_reset_scope(SOFTWARE_RESET); //Upon all the reset scopes are tested, set the reset scope condition back to SOFTWARE_RESET.
2802
2803 return ut_ret_status;
2804}
2805
2806kal_uint32 g_RGU_IT_API_CALL_ACCUMULATOR = 0;
2807
2808UT_REPORT_STATUS drv_UT_within_RGU_framework(rst_target_e targetIP, subsystem_e target_system, subsystem_e system_coverage,
2809 ut_testcase_struct *testcase_ptr, kal_uint32 test_items, kal_uint32 delay_cycles)
2810{
2811 UT_REPORT_STATUS ut_ret_status = UT_REPORT_PASS;
2812
2813 _rst_register_lisr();
2814
2815 if(drv_rstctl_disable_all_WDTs() == KAL_FALSE)
2816 {
2817 dbg_print("ASSERT (RGU): Disable WDT FAIL <line: %d in function: %s>\r\n", __LINE__, __FUNCTION__); //This case should not happen.
2818 return UT_REPORT_FAIL;
2819 }
2820 g_RGU_IT_API_CALL_ACCUMULATOR ++; //Global variable used to count the number of iterations that APIs are called.
2821 if (_rst_get_rgu_ut_result() != UT_REPORT_PASS) //The UT result of the previous iteration. If UT fails in earlier iteration, this iteration is ignored.
2822 { //Note: For the 1st iteration, the default value is 0. And UT_REPORT_PASS is 0 as well.
2823 dbg_print("Checking (api_call_acc,api_passed_acc) = (%d, %d): %d\r\n", g_RGU_IT_API_CALL_ACCUMULATOR,_rst_get_rgu_api_call_accumulator(), _rst_get_rgu_ut_result());
2824 if (g_RGU_IT_API_CALL_ACCUMULATOR == _rst_get_rgu_api_call_accumulator())
2825 dbg_print("INFO (RGU) RGU_IT UT fail! @ drv_UT_within_RGU_framework (%d)\r\n", g_RGU_IT_API_CALL_ACCUMULATOR);
2826 return UT_REPORT_FAIL; //If some UT fails one of early RGU_IT_API call, the reset RGU_IT_APIs are ignored.
2827 }
2828 dbg_print("INFO ACCUMU1:%d ; ACCUMU2:%d \r\n", g_RGU_IT_API_CALL_ACCUMULATOR, _rst_get_rgu_api_call_accumulator());
2829 if (g_RGU_IT_API_CALL_ACCUMULATOR <= _rst_get_rgu_api_call_accumulator())
2830 return UT_REPORT_PASS;
2831 dbg_print("\r\n\nINFO (RGU) API call accumulator: %d; Delay cycles: %d\n\n\r", g_RGU_IT_API_CALL_ACCUMULATOR, delay_cycles);
2832
2833 if (KAL_FALSE == _rst_is_system_within_converage(target_system, system_coverage))
2834 {
2835 dbg_print("ASSERT (RGU): Target system is not included in the system coverage <line: %d in function: %s>\r\n", __LINE__, __FUNCTION__);
2836 return UT_REPORT_FAIL;
2837 }
2838
2839 if (RGU_RESET_SCOPE_END == _rst_get_rgu_scope_to_clear_state()) //If the last whole system reset is triggered for a new iternation, the status must be cleared.
2840 {
2841 _rst_clear_ap_software_reset_status(); //Clear the whole system reset status.
2842 _rst_set_rgu_scope_to_clear_state(0); //Clear the ditinguishable flag that was marked as RGU_RESET_SCOPE_END.
2843 }
2844
2845 dbg_print("%s @ MIPS-iterAptiv\n\r", __FUNCTION__);
2846
2847 if (MD1SYS == (target_system & MD1SYS))
2848 {
2849 dbg_print("target system = MD1SYS\n\r");
2850 if (MD1SYS == _rst_return_dominate_system(target_system))
2851 {
2852 ut_ret_status = _rst_md1sys_dominate_reset_scope(KAL_TRUE, targetIP, system_coverage, testcase_ptr, test_items, delay_cycles); //Dominate the reset scope and tests the UTs.
2853 _rst_set_rgu_scope_to_clear_state(RGU_RESET_SCOPE_END); //For the next iteration, it is necessary to offer a clear dependent state. To distinguish framework or new iteration reset, we burry RGU_RESET_SCOPE_END.
2854 _rst_prepare_for_next_rgu_it_call(system_coverage, ut_ret_status); //reset the system to for the next API (drv_UT_within_RGU_framework) call.
2855 }
2856 else
2857 _rst_md1sys_dominate_reset_scope(KAL_FALSE, targetIP, system_coverage, testcase_ptr, test_items, delay_cycles); //Call the UTs but controlled by other subsystem.
2858 }
2859 else
2860 {
2861 _rst_md1sys_dominate_reset_scope(KAL_FALSE, 0, system_coverage, NULL, 0, 0); //act as md1_dummy load.
2862 }
2863 return ut_ret_status;
2864}
2865
2866#endif /*!defined(RSTCTL_FPGA_PLAT)*/
2867#endif /*defined(ATEST_ENABLE)*/
2868
2869#else /*!defined(DRV_RSTCTL_OFF)*/
2870
2871#endif /*!defined(DRV_RSTCTL_OFF)*/