Gitiles
Code Review Sign In
192.168.1.100 / T800_MD / b0f5b85a5b9d69cbfa1dd990d559a4a9c7d8f2a6 / . / mcu / driver / devdrv / usim / src / usim_smt.c
blob: 7ebc59f19be9ffdeeaf2d447ebeb02a98909b8e3 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1#include "kal_public_api.h"
2#include "drv_comm.h"
3#include "reg_base.h"
4
5#include "sim_hw_mtk.h"
6#include "sim_drv_HW_def_MTK.h"
7#include "sim_al.h"
8#include "sim_drv_SW_struct.h"
9#include "sim_drv_SW_API.h"
10
11#include "sim_drv_SW_function.h"
12
13#include "drv_rstctl.h"
14#include "drvpdn.h"
15#include "drv_gdma.h"
16#include "us_timer.h"
17
18
19#define USIM_ATRSTA_OFF 0x0001
20
21#define USIM_3_3V KAL_TRUE
22#ifdef USIM_3_3V
23 #define USIM_VOL_CFG 0x1
24#else
25 #define USIM_VOL_CFG 0x0
26#endif
27
28#define USIM_SMT_NO_ERROR 0x0
29#define USIM_SMT_NO_TS 0x1
30#define USIM_SMT_NO_TOUT 0x2
31#define USIM_SMT_NO_T0END 0x3
32#define USIM_SMT_NO_ATRSTA_OFF 0x4
33#define USIM_SMT_SW_ERROR 0x5
34#define USIM_SMT_COUNT_ERROR 0x6
35#define USIM_SMT_HDMA_ERROR 0x7
36#define USIM_SMT_IFCLR_ERROR 0x8
37#define USIM_SMT_PPS_ERROR 0x9
38#define USIM_SMT_MT6306_ERROR 0xA
39#define USIM_SMT_INVALID_TS 0xB
40#define USIM_SMT_TOO_MANY_ATR 0xC
41#define USIM_SMT_ATR_TIMEOUT 0xD
42#define USIM_SMT_UNEXPT_DATA 0xE
43#define USIM_SMT_INTERFACE_ERROR 0xF
44
45// macro
46#define USIM_SMT_UPDATE_USIM_IF_FLAG(_if) do { \
47 if((_if) == 0) \
48 { \
49 usim_base = SIM_base; \
50 } else if((_if) == 1) \
51 { \
52 usim_base = SIM2_base; \
53 } else SIM_DEBUG_ASSERT(0); \
54 } while(0)
55
56#define USIM_SMT_BASIC_SETTING(_if) do { \
57 if((_if) == 0) \
58 { \
59 PDN_CLR(PDN_USIM1); \
60 HDMA_PDN_CLR(0); \
61 } else if((_if) == 1) \
62 { \
63 PDN_CLR(PDN_USIM2); \
64 HDMA_PDN_CLR(1); \
65 } else SIM_DEBUG_ASSERT(0); \
66 usim_iftest_sw_reset_usim((_if)); \
67 } while(0)
68
69#ifdef __FPGA__
70#define USIM_SMT_DEACTIVATION(_if) do { \
71 DRV_Reg32(usim_base + SIM_CTRL_MTK) = (DRV_Reg32(usim_base + SIM_CTRL_MTK) & (~SIM_CTRL_SIMON)); \
72 } while(0)
73#else
74#define USIM_SMT_DEACTIVATION(_if) do { \
75 DRV_WriteReg32((usim_base + SIM_IRQEN_MTK), SIM_IRQEN_ALLOFF); \
76 DRV_WriteReg32((usim_base + SIM_CTRL_MTK), DRV_Reg32(usim_base + SIM_CTRL_MTK) | SIM_CTRL_IFCLR); \
77 DRV_Reg32(usim_base + SIM_CTRL_MTK) = (DRV_Reg32(usim_base + SIM_CTRL_MTK) & (~SIM_CTRL_SIMON)); \
78 while(!(DRV_Reg32(usim_base + SIM_ATRSTA_MTK) & 0x0001)); \
79 DRV_ICC_PMU_switch((_if), KAL_FALSE); \
80 } while(0)
81#endif
82
83extern kal_uint32 sim_uncachedTxBuffer0[], sim_uncachedRxBuffer0[], sim_uncachedTxBuffer1[], sim_uncachedRxBuffer1[];
84
85int usim_iftest_for_smt(kal_uint32 hwInterfaceNo);
86void usim_iftest_sw_reset_usim(kal_uint32 hwInterfaceNo);
87
88extern kal_char sim_shared_dbgstr[];
89#if !defined(ATEST_DRV_ENABLE)
90extern void slt_dbg_print(char *fmt, ...);
91#else
92#define slt_dbg_print(...) dbg_print( __VA_ARGS__)
93#endif
94
95#ifdef SIM_DRV_SWITCH_MT6306
96#include "sim_mt6306.h"
97extern void MT6306_Writer_GPIO(kal_uint8 device_addr, kal_uint8 data_addr, kal_uint8 data_value);
98extern void MT6306_HW_I2C_writer(kal_uint8 addr, kal_uint8 data_addr, kal_uint8 data_value);
99extern kal_uint32 MT6306_geti2cInterface(kal_uint32 MT6306Interface);
100extern kal_uint8 MT6306_Reader_AL(kal_uint8 chipno, kal_uint16 addr);
101extern kal_bool MT6306_ShowReg(int chip);
102extern DCL_HANDLE clkHandle, datHandle;;
103
104static int MT6306_validateREG(kal_uint8 chipno, kal_uint8 reg, kal_uint8 writeVal)
105{
106 kal_uint8 readvalue = MT6306_Reader_AL(chipno, reg);
107 kal_uint32 log_size = 0;
108
109 if (readvalue != writeVal)
110 {
111 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]MT6306 Error: chip:%d, reg:%x, Write:%x, Read:%x\n\r", chipno, reg, writeVal, readvalue);
112 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
113
114 return USIM_SMT_MT6306_ERROR;
115 }
116
117 return USIM_SMT_NO_ERROR;
118}
119
120int MT6306_blockRST(kal_uint8 chipno, kal_uint8 port, kal_uint8 level)
121{
122 kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_RST);
123
124 value |= (1 << port);
125 value &= ~(4 << port);
126 if (level) value |= (4 << port);
127 if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
128 MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_RST + (chipno * 4), value);
129 else
130 MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_RST + (chipno * 4), value);
131
132 return MT6306_validateREG(chipno, SIM_MT6306_REG_RST, value);
133}
134
135int MT6306_blockCLK(kal_uint8 chipno, kal_uint8 port)
136{
137 kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_CLK);
138
139 value &= ~(1 << port);
140 value &= ~(4 << port);
141 if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
142 MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_CLK + (chipno * 4), value);
143 else
144 MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_CLK + (chipno * 4), value);
145
146 return MT6306_validateREG(chipno, SIM_MT6306_REG_CLK, value);
147}
148
149int MT6306_blockDAT(kal_uint8 chipno, kal_uint8 port)
150{
151 kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_DAT);
152
153 value &= ~(1 << port);
154 value &= ~(4 << port);
155 if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
156 MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_DAT + (chipno * 4), value);
157 else
158 MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_DAT + (chipno * 4), value);
159
160 return MT6306_validateREG(chipno, SIM_MT6306_REG_DAT, value);
161}
162
163int MT6306_passRST(kal_uint8 chipno, kal_uint8 port)
164{
165 kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_RST);
166
167 value &= ~(1 << port);
168 if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
169 MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_RST + (chipno * 4), value);
170 else
171 MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_RST + (chipno * 4), value);
172
173 return MT6306_validateREG(chipno, SIM_MT6306_REG_RST, value);
174}
175
176int MT6306_passCLK(kal_uint8 chipno, kal_uint8 port)
177{
178 kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_CLK);
179
180 value |= (1 << port);
181 value &= ~(4 << port);
182
183 if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
184 MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_CLK + (chipno * 4), value);
185 else
186 MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_CLK + (chipno * 4), value);
187
188 return MT6306_validateREG(chipno, SIM_MT6306_REG_CLK, value);
189}
190
191int MT6306_passDAT(kal_uint8 chipno, kal_uint8 port)
192{
193 kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_DAT);
194
195 value |= (1 << port);
196 value &= ~(4 << port);
197 if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
198 MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_DAT + (chipno * 4), value);
199 else
200 MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_DAT + (chipno * 4), value);
201
202 return MT6306_validateREG(chipno, SIM_MT6306_REG_DAT, value);
203}
204
205int MT6306_setVCC(kal_uint8 chipno, kal_uint8 port, kal_uint32 onoff, kal_uint32 level)
206{
207 kal_uint8 value = MT6306_Reader_AL(chipno, SIM_MT6306_REG_VCC);
208
209 if (onoff == 0) value &= ~(4 << port);
210 else value |= (4 << port);
211
212 if (level == 0) value &= ~(1 << port);
213 else value |= (1 << port);
214
215 if (MT6306_geti2cInterface(0) == MT6306_I2C_USE_HW_I2C)
216 MT6306_HW_I2C_writer(0x64, SIM_MT6306_REG_VCC + (chipno * 4), value);
217 else
218 MT6306_Writer_GPIO(0x64, SIM_MT6306_REG_VCC + (chipno * 4), value);
219
220 return MT6306_validateREG(chipno, SIM_MT6306_REG_VCC, value);
221}
222
223int MT6306_passALLSignal(kal_uint8 chipno, kal_uint8 port)
224{
225 int result = USIM_SMT_NO_ERROR;
226
227 result |= MT6306_passRST(chipno, port);
228 result |= MT6306_passCLK(chipno, port);
229 result |= MT6306_passDAT(chipno, port);
230
231 return result;
232}
233
234int MT6306_blockALLSignal(kal_uint8 chipno, kal_uint8 port)
235{
236 int result = USIM_SMT_NO_ERROR;
237
238 result |= MT6306_blockRST(chipno, port, 0);
239 result |= MT6306_blockCLK(chipno, port);
240 result |= MT6306_blockDAT(chipno, port);
241
242 return result;
243}
244#endif // #ifdef SIM_DRV_SWITCH_MT6306
245
246#ifdef __FPGA__
247#else
248// extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
249#endif
250
251static int usim_iftest_sim_activation_conv(kal_uint32 hwInterfaceNo, kal_uint32 class_b_or_c, usim_dir_enum conv)
252{
253 kal_uint32 usim_base = 0;
254 kal_uint16 reg_val = 0;
255
256 // 0. Update USIM interface flag
257 USIM_SMT_BASIC_SETTING(hwInterfaceNo);
258 USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
259
260 // 1. get ATR STR
261#ifdef __FPGA__
262#else
263 // 1.0 Deactivate SIM
264 DRV_ICC_PMU_switch(hwInterfaceNo, KAL_FALSE);
265 ust_us_busyloop(50000);
266#endif
267#if defined(DRV_SIM_6292_SERIES)|| defined(DRV_SIM_6293_SERIES)
268 DRV_Reg32(usim_base + SIM_BRR_MTK) = (372 << 2);
269#elif defined(SIM_DRV_3_71MHZ_SCLK)
270 DRV_Reg32(usim_base + SIM_BRR_MTK) = (DRV_Reg32(usim_base + SIM_BRR_MTK) & 0x0800) | (372 << 2);
271#else
272 DRV_Reg32(usim_base + SIM_BRR_MTK) = (DRV_Reg32(usim_base + SIM_BRR_MTK) & 0x3) | (372 << 2);
273#endif
274 DRV_Reg32(usim_base + SIM_TOUT_MTK) = (10000 >> 4) + 1;
275 DRV_Reg32(usim_base + SIM_CONF_MTK) = DRV_Reg32(usim_base + SIM_CONF_MTK) & ~(SIM_CONF_TOUTEN);
276 DRV_Reg32(usim_base + SIM_CTRL_MTK) = DRV_Reg32(usim_base + SIM_CTRL_MTK) & ~(SIM_CTRL_SIMON);
277
278 // 1.1 Set RXTIDE of SIM_TIDE to 0 and TXTIDE to 1
279 DRV_Reg32(usim_base + SIM_TIDE_MTK) = (DRV_Reg32(usim_base + SIM_TIDE_MTK) & (~SIM_TIDE_RXMASK) & (~SIM_TIDE_TXMASK)) | 0x0100;
280
281 // 1.2 Clear Interrupt
282 DRV_Reg32(usim_base + SIM_STS_MTK) = DRV_Reg32(usim_base + SIM_STS_MTK);
283
284 // 1.3 If TOUT = 1, T0EN/T1EN = 0
285 reg_val = (DRV_Reg32(usim_base + SIM_CONF_MTK) & ~(SIM_CONF_T0EN | SIM_CONF_T1EN | SIM_CONF_TOUTEN | USIM_VOL_CFG)) | (SIM_CONF_TOUTEN | USIM_VOL_CFG);
286 if (conv == USIM_DIRECT)
287 {
288 reg_val &= ~(SIM_CONF_CONV);
289 }
290 else
291 {
292 reg_val |= SIM_CONF_CONV;
293 }
294 DRV_Reg32(usim_base + SIM_CONF_MTK) = reg_val;
295#ifdef __FPGA__
296#else
297 DRV_ICC_PMU_setVolt(hwInterfaceNo, class_b_or_c);
298 DRV_ICC_PMU_switch(hwInterfaceNo, KAL_TRUE);
299#endif
300 // 1.4 Set SIMON, Activate SIM
301 DRV_Reg32(usim_base + SIM_CTRL_MTK) = (DRV_Reg32(usim_base + SIM_CTRL_MTK) & (~SIM_CTRL_SIMON)) | SIM_CTRL_SIMON;
302
303 return 0;
304}
305
306int usim_iftest_sim_activation(kal_uint32 hwInterfaceNo, kal_uint32 class_b_or_c)
307{
308 return usim_iftest_sim_activation_conv(hwInterfaceNo, class_b_or_c, USIM_DIRECT);
309}
310
311int usim_iftest_sim_activation_inverse(kal_uint32 hwInterfaceNo, kal_uint32 class_b_or_c)
312{
313 return usim_iftest_sim_activation_conv(hwInterfaceNo, class_b_or_c, USIM_INVERSE);
314}
315
316int usim_iftest_tout_test(kal_uint32 hwInterfaceNo) {
317 kal_uint32 usim_base = 0;
318 kal_uint32 orig_brr = 0;
319 kal_uint32 ret_val = USIM_SMT_NO_ERROR;
320 kal_uint32 etu_setting = 0, tout_setting = 0, int_sts = 0;
321
322 // 0. Update USIM interface flag
323 USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
324
325 // 1. Disable Interrupt & Clear Interrupt Status
326 DRV_Reg32(usim_base + SIM_IRQEN_MTK) = 0;
327 DRV_Reg32(usim_base + SIM_STS_MTK) = 0xFFFFFFFF;
328
329 // 2. Save BRR, will restore before case complete
330 orig_brr = DRV_Reg32(usim_base + SIM_BRR_MTK);
331
332 for (etu_setting = 16; etu_setting <= 32 && ret_val == USIM_SMT_NO_ERROR; etu_setting *= 2) {
333 // Set 1ETU = etu_setting CLK
334 DRV_Reg32(usim_base + SIM_BRR_MTK) = (orig_brr & (~(0x1FF<<2))) | (16<<2);
335
336 for (tout_setting = 5; tout_setting < 10; tout_setting += 2) {
337 // 3. Set TOUT to (tout_setting+1)*16ETU
338 DRV_Reg32(usim_base + SIM_CONF_MTK) = DRV_Reg32(usim_base + SIM_CONF_MTK) & (~SIM_CONF_TOUTEN);
339 DRV_Reg32(usim_base + SIM_TOUT_MTK) = tout_setting; // means (tout_setting+1)*16 ETU
340 DRV_Reg32(usim_base + SIM_CONF_MTK) = DRV_Reg32(usim_base + SIM_CONF_MTK) | (SIM_CONF_TOUTEN);
341
342 // 4. Wait TOUT Interrupt Status
343 kal_uint32 start_time = ust_get_current_time();
344 kal_uint32 duration;
345 while ((duration = ust_us_duration(start_time, ust_get_current_time())) < 10*1000) {
346 // TOUT should happen after ([6,8,10])*16*([16,32])=1536~5120 SIM CLKs@3.25MHz < 1.58ms
347 if ((int_sts = DRV_Reg32(usim_base + SIM_STS_MTK)) & SIM_STS_TOUT) {
348 break;
349 }
350 }
351
352 DRV_Reg32(usim_base + SIM_STS_MTK) = int_sts;
353 if ((int_sts & SIM_STS_TOUT) == 0) {
354 ret_val = USIM_SMT_NO_TOUT;
355 slt_dbg_print("[SIM_SMT]: TOUT not happen when etu=%d tout=%d\r\n", etu_setting, tout_setting);
356 break;
357 }
358
359 // Check duration ???
360 }
361 }
362
363 // 5. Disable TOUT & Clear Interrupt Status & Restore BRR
364 DRV_Reg32(usim_base + SIM_CONF_MTK) = DRV_Reg32(usim_base + SIM_CONF_MTK) & (~SIM_CONF_TOUTEN);
365 DRV_Reg32(usim_base + SIM_STS_MTK) = 0xFFFFFFFF;
366 DRV_Reg32(usim_base + SIM_BRR_MTK) = orig_brr;
367
368 return ret_val;
369}
370
371void pmic_dump(void)
372{
373/*
374 int i, j = 0;
375 kal_uint32 val = 0;
376
377 for (i = 0; i < 0xff0; i += 2)
378 {
379 if (j % 5) slt_dbg_print("[PMIC_DVT] ");
380#ifdef __FPGA__
381#else
382 val = DRV_Read_PMIC_Data(i);
383#endif
384
385 if (val != 0x5aa5) slt_dbg_print("[0x%x]= 0x%x ", i, val);
386
387 j++;
388
389 if ((j % 5) == 0) slt_dbg_print("\n\r");
390 }
391*/
392 return;
393}
394
395void sim_dump_reg_debug(kal_uint32 usim_base)
396{
397 slt_dbg_print("SIM Reg Dump: \n\r");
398 slt_dbg_print("%x, %x, %x, %x, %x\n\r", usim_base, DRV_Reg32(usim_base + SIM_VERSION_MTK),
399 DRV_Reg32(usim_base + SIM_CTRL_MTK), DRV_Reg32(usim_base + SIM_CONF_MTK), DRV_Reg32(usim_base + SIM_CONFSTA_MTK));
400
401 slt_dbg_print("%x, %x, %x, %x, %x\n\r", DRV_Reg32(usim_base + SIM_BRR_MTK), DRV_Reg32(usim_base + SIM_IRQEN_MTK),
402 DRV_Reg32(usim_base + SIM_STS_MTK), DRV_Reg32(usim_base + SIM_RETRY_MTK), DRV_Reg32(usim_base + SIM_TIDE_MTK));
403
404 slt_dbg_print("%x, %x, %x, %x, %x\n\r", 0, DRV_Reg32(usim_base + SIM_COUNT_MTK),
405 DRV_Reg32(usim_base + SIM_ATIME_MTK), DRV_Reg32(usim_base + SIM_DTIME_MTK), DRV_Reg32(usim_base + SIM_TOUT_MTK));
406
407 slt_dbg_print("%x, %x, %x, %x, %x\n\r", DRV_Reg32(usim_base + SIM_GTIME_MTK), DRV_Reg32(usim_base + SIM_ETIME_MTK),
408 DRV_Reg32(usim_base + SIM_EXT_TIME_MTK), DRV_Reg32(usim_base + SIM_CGTIME_MTK), DRV_Reg32(usim_base + SIM_COMDCTRL_MTK));
409
410 slt_dbg_print("%x, %x, %x, %x, %x\n\r", DRV_Reg32(usim_base + SIM_COMDLEN_MTK), DRV_Reg32(usim_base + SIM_LEFTLEN_MTK),
411 DRV_Reg32(usim_base + SIM_SW1_MTK), DRV_Reg32(usim_base + SIM_SW2_MTK), DRV_Reg32(usim_base + SIM_ATRSTA_MTK));
412
413 return;
414}
415
416int usim_iftest_get_atr(kal_uint32 hwInterfaceNo, kal_uint8 atr_bytes[])
417{
418 kal_uint32 usim_base = 0, log_size = 0;
419 kal_uint8 *atr_ptr = atr_bytes + 1;
420 kal_uint8 TS, TDi, hist_cnt, next_cnt;
421 kal_uint32 start_time = 0;
422 kal_bool T0_Recved = KAL_FALSE, Hist_Recved = KAL_FALSE;
423 int ret_val = USIM_SMT_NO_ERROR;
424
425start:
426
427 USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
428 start_time = ust_get_current_time();
429
430 // Wait first bytes of ATR
431 while (DRV_Reg32(usim_base + SIM_COUNT_MTK) == 0) {
432 if (DRV_Reg32(usim_base + SIM_STS_MTK) & SIM_STS_NATR) {
433 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: NO TS, %x, %d\n\r", usim_base, hwInterfaceNo);
434 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
435 ret_val = USIM_SMT_NO_TS;
436 goto end;
437 }
438 }
439
440 // Check if TS is valid
441 TS = DRV_Reg32(usim_base + SIM_DATA_MTK);
442 if (TS != 0x3B && TS != 0x3F) {
443 if (TS == 0x03) {
444 // Inverse Convention 0x3F will be decoded as 0x03 in Direct Convention
445 usim_iftest_sim_activation_inverse(hwInterfaceNo, CLASS_B_30V);
446 goto start;
447 } else {
448 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: Invalid TS, %x, %d, %x\n\r", usim_base, hwInterfaceNo, TS);
449 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
450 ret_val = USIM_SMT_INVALID_TS;
451 goto end;
452 }
453 }
454
455
456 // Got Valid TS
457 *atr_ptr++ = TS;
458
459 // Receive other ATR bytes
460 next_cnt = 1; // To read T0
461 for (;;) {
462 while (next_cnt > 0) {
463 if (DRV_Reg32(usim_base + SIM_COUNT_MTK) > 0) {
464 *atr_ptr++ = DRV_Reg32(usim_base + SIM_DATA_MTK);
465 next_cnt --;
466
467 if (atr_ptr - atr_bytes - 1 > 32) {
468 ret_val = USIM_SMT_TOO_MANY_ATR;
469 DRV_ICC_print_str("[SIM_SMT]: Received ATR data > 32 bytes");
470 goto end;
471 }
472 }
473
474 if ((DRV_Reg32(usim_base + SIM_STS_MTK) & SIM_STS_TOUT) != 0
475 || ust_us_duration(start_time, ust_get_current_time()) > 2*1000*1000L ) {
476 // Actually TOUT should happen if it's functinality is OK
477 ret_val = USIM_SMT_ATR_TIMEOUT;
478 DRV_ICC_print_str("[SIM_SMT]: Timeout when receiving ATR data");
479 goto end;
480 }
481 }
482
483 if (Hist_Recved == KAL_TRUE) {
484 // All ATR bytes have been received, excluding the optional byte of TCK
485 kal_uint32 tck_poll_start = ust_get_current_time();
486 while(ust_us_duration(tck_poll_start, ust_get_current_time()) < 10*1000) {
487 // TCK will come in 12 ETU, 1.4ms@3.25MHz SIM CLK, if not coming TCK is not exist
488 if (DRV_Reg32(usim_base + SIM_COUNT_MTK) > 0) {
489 *atr_ptr++ = DRV_Reg32(usim_base + SIM_DATA_MTK); // TCK
490 break;
491 }
492 }
493
494 // SIO should be idle now, Check TOUT function
495 if (usim_iftest_tout_test(hwInterfaceNo) != USIM_SMT_NO_ERROR) {
496 ret_val = USIM_SMT_NO_TOUT;
497 goto end;
498 }
499
500 // Check if more data in FIFO, it's error if there are more data
501 if (DRV_Reg32(usim_base + SIM_COUNT_MTK) > 0) {
502 ret_val = USIM_SMT_UNEXPT_DATA;
503 DRV_ICC_print_str("[SIM_SMT]: ATR received, but have unexpected data in FIFO");
504 goto end;
505 }
506
507 // Now, every thing should be good
508 atr_bytes[0] = atr_ptr - atr_bytes - 1;
509 goto end;
510 }
511
512 TDi = atr_ptr[-1]; // T0, TD1, TD2, ...
513
514 if (T0_Recved == KAL_FALSE) {
515 T0_Recved = KAL_TRUE;
516 hist_cnt = TDi&0x0F;
517 }
518
519 next_cnt = 0; // actually, it have already been 0
520 USIM_CAL_TD_COUNT(TDi, next_cnt);
521
522 if (TDi & TDMask) {
523 next_cnt ++;
524 } else {
525 next_cnt += hist_cnt;
526 Hist_Recved = KAL_TRUE;
527 }
528 }
529
530end:
531 if (ret_val != USIM_SMT_NO_ERROR) {
532 DRV_Reg32(usim_base + SIM_CONF_MTK) = DRV_Reg32(usim_base + SIM_CONF_MTK) & ~(SIM_CONF_TOUTEN);
533 DRV_Reg32(usim_base + SIM_STS_MTK) = DRV_Reg32(usim_base + SIM_STS_MTK);
534
535 sim_dump_reg_debug(usim_base);
536 pmic_dump();
537
538 USIM_SMT_DEACTIVATION(hwInterfaceNo);
539 }
540 return ret_val;
541}
542
543int usim_iftest_send_pps(kal_uint32 hwInterfaceNo, kal_uint8 atr_bytes[], kal_uint8 pps_buf[], kal_bool *need_pps)
544{
545 kal_uint32 usim_base = 0, j = 0, log_size = 0;
546 kal_uint32 cksum = 0xFF;
547
548 USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
549
550 if (atr_bytes[2] & 0x80) // TD1
551 {
552 j = 0;
553 if (atr_bytes[2] & 0x10) j++;
554 if (atr_bytes[2] & 0x20) j++;
555 if (atr_bytes[2] & 0x40) j++;
556 if (atr_bytes[2] & 0x80) j++;
557 if (atr_bytes[2 + j] & 0x10) // TA2
558 {
559 // TA1 && negotiable TA2
560 if ((atr_bytes[2] & 0x10) && (atr_bytes[2 + j + 1] & 0x80) == 0x0) *need_pps = KAL_TRUE;
561 }
562 else
563 {
564 // TA1 && TD1
565 if ((atr_bytes[2] & 0x10)) *need_pps = KAL_TRUE;
566 }
567 }
568 else if (atr_bytes[2] & 0x10) // TA1 && no TD1
569 {
570 *need_pps = KAL_TRUE;
571 }
572
573 *need_pps = atr_bytes[3] != 0x01 && atr_bytes[3] != 0x11 && (atr_bytes[2] & 0x10) && *need_pps;
574
575 if (*need_pps)
576 {
577 // Set TOUT = 1
578 DRV_Reg32(usim_base + SIM_CONF_MTK) = (DRV_Reg32(usim_base + SIM_CONF_MTK) & ~(SIM_CONF_TOUTEN | USIM_VOL_CFG)) | (SIM_CONF_TOUTEN | USIM_VOL_CFG);
579 // Clear
580 DRV_Reg32(usim_base + SIM_COMDCTRL_MTK) = DRV_Reg32(usim_base + SIM_COMDCTRL_MTK) | SIM_CTRL_IFCLR;
581 j = 0;
582 while (DRV_Reg32(usim_base + SIM_CONFSTA_MTK) & SIM_CONFSTA_IFCLR_ON)
583 {
584 if (j > 0xFFFFFF)
585 {
586 USIM_SMT_DEACTIVATION(hwInterfaceNo);
587 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: IFCLR ERROR\n\r");
588 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
589 return USIM_SMT_IFCLR_ERROR;
590 }
591 j++;
592 }
593
594 // Set RXTIDE of SIM_TIDE to 0 and TXTIDE to 1
595 DRV_Reg32(usim_base + SIM_TIDE_MTK) = (DRV_Reg32(usim_base + SIM_TIDE_MTK) & (~SIM_TIDE_RXMASK) & (~SIM_TIDE_TXMASK)) | 0x0100;
596
597 j = 0;
598 // Send PPSS
599 DRV_Reg32(usim_base + SIM_DATA_MTK) = 0xFF;
600 pps_buf[j++] = 0xFF;
601 // Send PPS0
602 DRV_Reg32(usim_base + SIM_DATA_MTK) = 0x10;
603 cksum ^= 0x10;
604 pps_buf[j++] = 0x10;
605 // Send PPS1
606 // Propose new Fi, Di
607 DRV_Reg32(usim_base + SIM_DATA_MTK) = atr_bytes[3];
608 cksum ^= atr_bytes[3];
609 pps_buf[j++] = atr_bytes[3];
610
611 // Send PCK
612 DRV_Reg32(usim_base + SIM_DATA_MTK) = cksum;
613 pps_buf[j++] = cksum;
614
615 // Wait Until TX FIFO Empty
616 j = 0;
617 while (DRV_Reg32(usim_base + SIM_COUNT_MTK) != 0)
618 {
619 if (j > 0xFFFFFF)
620 {
621 USIM_SMT_DEACTIVATION(hwInterfaceNo);
622 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: COUNT ERROR\n\r");
623 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
624 return USIM_SMT_COUNT_ERROR;
625 }
626 j++;
627
628 }
629 }
630
631 return 0; // temp
632}
633
634int usim_iftest_get_pps(kal_uint32 hwInterfaceNo, kal_uint8 atr_bytes[], kal_uint8 pps_buf[], kal_bool need_pps)
635{
636 kal_uint32 usim_base = 0, i = 0, j = 0;
637 kal_uint32 data = 0, fifo_cnt = 0, log_size = 0;
638
639 if (need_pps == KAL_FALSE) return 0;
640
641 USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
642
643 // PPS Exchange RX
644 while (1)
645 {
646 fifo_cnt = DRV_Reg32(usim_base + SIM_COUNT_MTK);
647
648 // FIFO Non-Empty
649 if (fifo_cnt != 0x0)
650 {
651 for (i = 0; i < fifo_cnt; i++)
652 {
653 data = DRV_Reg32(usim_base + SIM_DATA_MTK);
654 if (pps_buf[j++] != data)
655 {
656 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: not consistent:%x %x\n\r", data, pps_buf[j - 1]);
657 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
658 USIM_SMT_DEACTIVATION(hwInterfaceNo);
659 return USIM_SMT_PPS_ERROR;
660 }
661 }
662 }
663
664 // TOUT status = 1
665 if ((DRV_Reg32(usim_base + SIM_STS_MTK) & SIM_STS_TOUT) || (j >= 4))
666 {
667 if (data == 0)
668 {
669 if (DRV_Reg32(usim_base + SIM_COUNT_MTK) == 0x0)
670 {
671 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: USIM does not reply on time\n\r");
672 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
673 USIM_SMT_DEACTIVATION(hwInterfaceNo);
674 return USIM_SMT_PPS_ERROR;
675 }
676 }
677
678 // Clear Interrupt
679 DRV_Reg32(usim_base + SIM_STS_MTK) = DRV_Reg32(usim_base + SIM_STS_MTK);
680 // Clear IP's Internal TOUT enable bit
681 DRV_Reg32(usim_base + SIM_CONF_MTK) = (DRV_Reg32(usim_base + SIM_CONF_MTK) & ~(SIM_CONF_TOUTEN | USIM_VOL_CFG)) | (USIM_VOL_CFG);
682 break;
683 }
684 }
685
686 if (atr_bytes[3] == ATR_TA1_64) DRV_Reg32(usim_base + SIM_BRR_MTK) = (DRV_Reg32(usim_base + SIM_BRR_MTK) & 0x3) | ((512 / 8) << 2);
687 else if (atr_bytes[3] == ATR_TA1_32) DRV_Reg32(usim_base + SIM_BRR_MTK) = (DRV_Reg32(usim_base + SIM_BRR_MTK) & 0x3) | ((512 / 16) << 2);
688 else if (atr_bytes[3] == ATR_TA1_16) DRV_Reg32(usim_base + SIM_BRR_MTK) = (DRV_Reg32(usim_base + SIM_BRR_MTK) & 0x3) | ((512 / 32) << 2);
689 else if (atr_bytes[3] == ATR_TA1_8) DRV_Reg32(usim_base + SIM_BRR_MTK) = (DRV_Reg32(usim_base + SIM_BRR_MTK) & 0x3) | ((512 / 64) << 2);
690 else SIM_DEBUG_ASSERT(0);
691
692 return 0;
693}
694
695
696
697int usim_iftest_send_sim_command(kal_uint32 hwInterfaceNo, kal_uint8 tx_buf[], kal_uint32 tx_len, kal_uint32 rx_len)
698{
699 kal_uint32 usim_base = 0, i = 0, j = 0, log_size = 0;
700
701 USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
702
703 // clear
704 DRV_Reg32(usim_base + SIM_CTRL_MTK) = DRV_Reg32(usim_base + SIM_CTRL_MTK) | SIM_CTRL_IFCLR;
705 j = 0;
706 while (DRV_Reg32(usim_base + SIM_CONFSTA_MTK) & SIM_CONFSTA_IFCLR_ON)
707 {
708 if (j > 0xFFFFFF)
709 {
710 USIM_SMT_DEACTIVATION(hwInterfaceNo);
711 log_size = kal_sprintf(sim_shared_dbgstr, " [SIM_SMT]: IFCLR ERROR\n\r");
712 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
713 return USIM_SMT_IFCLR_ERROR ;
714 }
715 j++;
716 }
717 // 2.0 Select File of ICCID
718 // 2.0 set file id
719
720 // 2.1 Set RXTIDE of SIM_TIDE to 0 and TXTIDE to 1 (Note: TXTIDE cannot be 0 for DMA)
721 DRV_Reg32(usim_base + SIM_TIDE_MTK) = (DRV_Reg32(usim_base + SIM_TIDE_MTK) & (~SIM_TIDE_RXMASK) & (~SIM_TIDE_TXMASK)) | 0x0100;
722
723 // 2.2 Enable T0
724 DRV_Reg32(usim_base + SIM_CONF_MTK) = DRV_Reg32(usim_base + SIM_CONF_MTK) | SIM_CONF_T0EN;
725
726 // 2.3 Directly Write File ID to USIM FIFO
727 DRV_Reg32(usim_base + SIM_DATA_MTK) = tx_buf[0];
728 DRV_Reg32(usim_base + SIM_DATA_MTK) = tx_buf[1];
729 DRV_Reg32(usim_base + SIM_DATA_MTK) = tx_buf[2];
730 DRV_Reg32(usim_base + SIM_DATA_MTK) = tx_buf[3];
731 DRV_Reg32(usim_base + SIM_DATA_MTK) = tx_buf[4];
732
733 if (tx_len > 5)
734 {
735 if (hwInterfaceNo)
736 {
737 // HDMA TX (Memory to Device), USIM's Bus Width is Fixed to 8 bits
738 for (i = 5; i < tx_len; i++)
739 DRV_Reg8(((kal_uint32) sim_uncachedTxBuffer1) + i - 5) = tx_buf[i];
740
741 MM_Sync();
742
743 DRV_Reg32(REG_HDMA_HDCTRR1) = HDCTRR_RX_SEL0(0) | HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) | HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) | HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32);
744 DRV_Reg32(REG_HDMA_HPRGA0R1) = (kal_uint32) sim_uncachedTxBuffer1;
745 DRV_Reg32(REG_HDMA_HDC0R1) = HDCR_XFER_SIZE0(tx_buf[4]) | HDCR_START0;
746 }
747 else
748 {
749 // HDMA TX (Memory to Device), USIM's Bus Width is Fixed to 8 bits
750 for (i = 5; i < tx_len; i++)
751 DRV_Reg8(((kal_uint32) sim_uncachedTxBuffer0) + i - 5) = tx_buf[i];
752
753 MM_Sync();
754
755 DRV_Reg32(REG_HDMA_HDCTRR0) = HDCTRR_RX_SEL0(0) | HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) | HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) | HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32);
756 DRV_Reg32(REG_HDMA_HPRGA0R0) = (kal_uint32) sim_uncachedTxBuffer0;
757 DRV_Reg32(REG_HDMA_HDC0R0) = HDCR_XFER_SIZE0(tx_buf[4]) | HDCR_START0;
758 }
759 }
760
761 // for Get Responseo
762 if (rx_len && tx_len <= 5)
763 {
764 if (hwInterfaceNo)
765 {
766 // HDMA RX (Memory to Device), USIM's Bus Width is Fixed to 8 bits
767 DRV_Reg32(REG_HDMA_HDCTRR1) = HDCTRR_RX_SEL0(1) | HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) | HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) | HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32);
768 DRV_Reg32(REG_HDMA_HPRGA0R1) = (kal_uint32) sim_uncachedRxBuffer1;
769 DRV_Reg32(REG_HDMA_HDC0R1) = HDCR_XFER_SIZE0(rx_len) | HDCR_START0;
770 }
771 else
772 {
773 // HDMA RX (Memory to Device), USIM's Bus Width is Fixed to 8 bits
774 DRV_Reg32(REG_HDMA_HDCTRR0) = HDCTRR_RX_SEL0(1) | HDCTRR_BST_SIZE(HDCTRR_BST_SIZE_16) | HDCTRR_DEV_BUS_WIDTH(HDCTRR_BUS_WIDTH_8) | HDCTRR_MEM_BUS_WIDTH(HDCTRR_BUS_WIDTH_32);
775 DRV_Reg32(REG_HDMA_HPRGA0R0) = (kal_uint32) sim_uncachedRxBuffer0;
776 DRV_Reg32(REG_HDMA_HDC0R0) = HDCR_XFER_SIZE0(rx_len) | HDCR_START0;
777 }
778 }
779
780 DRV_Reg32(usim_base + SIM_COMDLEN_MTK) = tx_buf[4];
781
782 if (tx_len > 5)
783 {
784 DRV_Reg32(usim_base + SIM_COMDCTRL_MTK) = SIM_INS_START | SIM_INS_INSD | tx_buf[1]; // Expect to Send
785 }
786 else if (rx_len && tx_len <= 5)
787 {
788 DRV_Reg32(usim_base + SIM_COMDCTRL_MTK) = SIM_INS_START | tx_buf[1]; // Expect to Send
789 }
790
791 MO_Sync();
792
793 return 0;
794}
795
796int usim_iftest_get_sim_response(kal_uint32 hwInterfaceNo, kal_bool rx_data, kal_uint32 *sw1, kal_uint32 *sw2)
797{
798 kal_uint32 usim_base = 0, log_size = 0;
799 kal_uint32 j = 0;
800
801 USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
802
803 // Wait Until TX FIFO Empty
804 j = 0;
805 while (DRV_Reg32(usim_base + SIM_COUNT_MTK) != 0)
806 {
807 if (j > 0xFFFFFF)
808 {
809 USIM_SMT_DEACTIVATION(hwInterfaceNo);
810 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: COUNT ERROR\n\r");
811 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
812 return USIM_SMT_COUNT_ERROR;
813 }
814 j++;
815 }
816
817 // 2.4 Wait for Operation Done (Including Response)
818 j = 0;
819 while (!(DRV_Reg32(usim_base + SIM_STS_MTK) & SIM_STS_T0END))
820 {
821 if (j > 0xFFFFFF)
822 {
823 USIM_SMT_DEACTIVATION(hwInterfaceNo);
824 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT:%d]: NO T0END\n\r", __LINE__);
825 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
826 return USIM_SMT_NO_T0END;
827 }
828 j++;
829 }
830
831 if (rx_data)
832 {
833 j = 0;
834 if (hwInterfaceNo)
835 {
836 while ((DRV_Reg32(REG_HDMA_HDSR) & HDMA_STAT0_1))
837 {
838 if (j > 0xFFFFFF)
839 {
840 USIM_SMT_DEACTIVATION(hwInterfaceNo);
841 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: HDMA ERROR\n\r");
842 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
843 return USIM_SMT_HDMA_ERROR;
844 }
845 j++;
846 }
847 /*
848 kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: Get %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n\r",
849 sim_uncachedRxBuffer1[0], sim_uncachedRxBuffer1[1], sim_uncachedRxBuffer1[2], sim_uncachedRxBuffer1[3], sim_uncachedRxBuffer1[4],
850 sim_uncachedRxBuffer1[5], sim_uncachedRxBuffer1[6], sim_uncachedRxBuffer1[7], sim_uncachedRxBuffer1[8], sim_uncachedRxBuffer1[9],
851 sim_uncachedRxBuffer1[10], sim_uncachedRxBuffer1[11], sim_uncachedRxBuffer1[12], sim_uncachedRxBuffer1[13], sim_uncachedRxBuffer1[14]);
852 */
853
854 for (j=0;j<15;j++)
855 {
856 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: Get %d:%x\r\n", j, *(((kal_uint8 *) sim_uncachedRxBuffer1) + j));
857 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
858 }
859
860 }
861 else
862 {
863 while ((DRV_Reg32(REG_HDMA_HDSR) & HDMA_STAT0_0))
864 {
865 if (j > 0xFFFFFF)
866 {
867 USIM_SMT_DEACTIVATION(hwInterfaceNo);
868 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: HDMA ERROR\n\r");
869 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
870 return USIM_SMT_HDMA_ERROR;
871 }
872 j++;
873 }
874 /*
875 kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: Get %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n\r",
876 sim_uncachedRxBuffer0[0], sim_uncachedRxBuffer0[1], sim_uncachedRxBuffer0[2], sim_uncachedRxBuffer0[3], sim_uncachedRxBuffer0[4],
877 sim_uncachedRxBuffer0[5], sim_uncachedRxBuffer0[6], sim_uncachedRxBuffer0[7], sim_uncachedRxBuffer0[8], sim_uncachedRxBuffer0[9],
878 sim_uncachedRxBuffer0[10], sim_uncachedRxBuffer0[11], sim_uncachedRxBuffer0[12], sim_uncachedRxBuffer0[13], sim_uncachedRxBuffer0[14]);
879 */
880 for (j=0;j<15;j++)
881 {
882 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: Get %d:%x\r\n", j, *(((kal_uint8 *) sim_uncachedRxBuffer0) + j));
883 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
884 }
885 }
886 //DRV_ICC_print_str(sim_shared_dbgstr);
887 }
888
889 // 2.5 Clear Interrupt
890 DRV_Reg32(usim_base + SIM_STS_MTK) = DRV_Reg32(usim_base + SIM_STS_MTK);
891
892 // 2.6 Check Returned Status Bytes
893 *sw1 = DRV_Reg32(usim_base + SIM_SW1_MTK);
894 *sw2 = DRV_Reg32(usim_base + SIM_SW2_MTK);
895
896 if ((*sw1 & 0xF0) != 0x90 && *sw1 != 0x69)
897 {
898 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: SW ERROR %x %x\n\r", *sw1, *sw2);
899 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
900 return USIM_SMT_SW_ERROR;
901 }
902
903 return 0;
904}
905
906int usim_iftest_sim_deactivation(kal_uint32 hwInterfaceNo)
907{
908 kal_uint32 usim_base = 0, log_size = 0;
909 kal_uint32 j = 0;
910
911 USIM_SMT_UPDATE_USIM_IF_FLAG(hwInterfaceNo);
912
913 // 3. Deactivation
914 // 3.0 If SIM Aleady Activated, Deactivate it
915 DRV_Reg32(usim_base + SIM_CTRL_MTK) = DRV_Reg32(usim_base + SIM_CTRL_MTK) & (~SIM_CTRL_SIMON);
916 j = 0;
917 while (!(DRV_Reg32(usim_base + SIM_ATRSTA_MTK) & USIM_ATRSTA_OFF))
918 {
919 if (j > 0xFFFFFF)
920 {
921 USIM_SMT_DEACTIVATION(hwInterfaceNo);
922 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: NO ATRSTA OFF\n\r");
923 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
924 return USIM_SMT_NO_ATRSTA_OFF;
925 }
926 j++;
927 }
928#ifdef __FPGA__
929#else
930 DRV_ICC_PMU_switch(hwInterfaceNo, KAL_FALSE);
931#endif
932
933 return 0;
934}
935
936#if defined(__SIM_DRV_CO_LOAD_MT6306__) && defined(SIM_DRV_SWITCH_MT6306)
937 extern kal_bool sim_connectMT6306;
938#endif
939int usim_iftest_for_smt(kal_uint32 interfaceNo)
940{
941 kal_uint32 func_status = 0;
942 kal_uint8 atr_bytes[50] = {0}, tx_buf[25] = {0}, pps_buf[10] = {0};
943 kal_uint32 sw1 = 0, sw2 = 0;
944 kal_bool need_pps = KAL_FALSE, forced_18v = KAL_FALSE;
945 kal_uint32 class_b_or_c = CLASS_B_30V, hwInterfaceNo = interfaceNo & 0xF, log_size = 0;
946
947 if (interfaceNo & 0xF0)
948 forced_18v = KAL_TRUE;
949
950 interfaceNo = interfaceNo & 0xF;
951
952 // for 3-SIM project, check sim_connectMT6306
953 if (interfaceNo == 4)
954 {
955#if defined(SIM_DRV_SWITCH_MT6306) && defined(__SIM_DRV_CO_LOAD_MT6306__)
956 return (kal_uint32) sim_connectMT6306;
957#elif defined(SIM_DRV_SWITCH_MT6306) && !defined(__SIM_DRV_CO_LOAD_MT6306__)
958 return (kal_uint32) KAL_TRUE;
959#else
960 return (kal_uint32) KAL_FALSE;
961#endif
962 }
963
964#ifdef SIM_DRV_SWITCH_MT6306
965 // for 3-SIM project, interfaceNo != hwInterfaceNo
966 kal_uint8 port = 0, chip = 0;
967#if defined(__SIM_DRV_CO_LOAD_MT6306__)
968 if(sim_connectMT6306 == KAL_TRUE)
969 {
970#endif
971 // hwInterfaceNo will be 0, 1, 2
972 hwInterfaceNo = interfaceNo / 2;
973 port = interfaceNo % 2;
974 chip = hwInterfaceNo;
975 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]hwInterfaceNo:%d, chip:%d, port:%d", hwInterfaceNo, chip, port);
976 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
977#if defined(__SIM_DRV_CO_LOAD_MT6306__)
978 }
979#endif
980#endif
981
982 // check hwInterfaceNo
983 if (hwInterfaceNo > 1)
984 {
985 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: Invalid Interface:%d\n\r",hwInterfaceNo);
986 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
987 return USIM_SMT_INTERFACE_ERROR;
988 }
989
990 // Cards may be activated by other AT+CMD
991 usim_dcb_struct *usim_dcb;
992 usim_dcb = GET_USIM_CB(interfaceNo);
993 if (usim_dcb->present)
994 {
995 log_size = kal_sprintf(sim_shared_dbgstr, "[SIM_SMT]: driver status is correct\n\r");
996 if (log_size > 0) DRV_ICC_print_str(sim_shared_dbgstr);
997 return USIM_SMT_NO_ERROR;
998 }
999
1000 // adjust VCC (default 3V)
1001#if defined(SIM_DRV_SWITCH_MT6306) && defined(__SIM_DRV_CO_LOAD_MT6306__)
1002 if(sim_connectMT6306 == KAL_TRUE) class_b_or_c = CLASS_C_18V;
1003#elif defined(SIM_DRV_SWITCH_MT6306) && !defined(__SIM_DRV_CO_LOAD_MT6306__)
1004 class_b_or_c = CLASS_C_18V;
1005#else
1006 if (forced_18v) class_b_or_c = CLASS_C_18V;
1007#endif
1008
1009#ifdef SIM_DRV_SWITCH_MT6306
1010#if defined(__SIM_DRV_CO_LOAD_MT6306__)
1011 if(sim_connectMT6306 == KAL_TRUE)
1012 {
1013#endif
1014 //Block all chip, all port
1015 if (USIM_SMT_NO_ERROR != MT6306_blockALLSignal(0, 0))
1016 return USIM_SMT_MT6306_ERROR;
1017 if (USIM_SMT_NO_ERROR != MT6306_blockALLSignal(0, 1))
1018 return USIM_SMT_MT6306_ERROR;
1019 if (USIM_SMT_NO_ERROR != MT6306_blockALLSignal(1, 0))
1020 return USIM_SMT_MT6306_ERROR;
1021 if (USIM_SMT_NO_ERROR != MT6306_blockALLSignal(1, 1))
1022 return USIM_SMT_MT6306_ERROR;
1023 if (USIM_SMT_NO_ERROR != MT6306_setVCC(chip, 0, 0, 0))//turn off port 0
1024 return USIM_SMT_MT6306_ERROR;
1025 if (USIM_SMT_NO_ERROR != MT6306_setVCC(chip, 1, 0, 0))//turn off port 1
1026 return USIM_SMT_MT6306_ERROR;
1027
1028 // adjsut VCC
1029 if (forced_18v == KAL_TRUE)
1030 {
1031 // CLASS_C_18V
1032 MT6306_setVCC(hwInterfaceNo, port, 1, 0);
1033 }
1034 else
1035 {
1036 // CLASS_B_30V
1037 MT6306_setVCC(hwInterfaceNo, port, 1, 1);
1038 }
1039
1040 // pass all signals of (chip, port)
1041 MT6306_passALLSignal(chip, port);
1042#if defined(__SIM_DRV_CO_LOAD_MT6306__)
1043 }
1044#endif
1045#endif
1046
1047 usim_iftest_sim_activation(hwInterfaceNo, class_b_or_c);
1048
1049 func_status = usim_iftest_get_atr(hwInterfaceNo, atr_bytes);
1050 if (func_status) return func_status;
1051
1052 func_status = usim_iftest_send_pps(hwInterfaceNo, atr_bytes, pps_buf, &need_pps);
1053 if (func_status) return func_status;
1054 func_status = usim_iftest_get_pps(hwInterfaceNo, atr_bytes, pps_buf, need_pps);
1055 if (func_status) return func_status;
1056 if (need_pps) kal_sleep_task(KAL_TICKS_50_MSEC);
1057
1058#define EF_ICCID 0x2FE2
1059 tx_buf[0] = 0xA0;
1060 tx_buf[1] = 0xA4;
1061 tx_buf[2] = 0x00;
1062 tx_buf[3] = 0x00;
1063 tx_buf[4] = 0x02;
1064 tx_buf[5] = 0x2F;
1065 tx_buf[6] = 0xE2;
1066 func_status = usim_iftest_send_sim_command(hwInterfaceNo, tx_buf, 7, 0);
1067 if (func_status) return func_status;
1068 func_status = usim_iftest_get_sim_response(hwInterfaceNo, KAL_FALSE, &sw1, &sw2);
1069 if (func_status) return func_status;
1070// --
1071 tx_buf[0] = 0xA0;
1072 tx_buf[1] = 0xC0;
1073 tx_buf[2] = 0x00;
1074 tx_buf[3] = 0x00;
1075 tx_buf[4] = sw2;
1076 func_status = usim_iftest_send_sim_command(hwInterfaceNo, tx_buf, 5, tx_buf[4]);
1077 if (func_status) return func_status;
1078 func_status = usim_iftest_get_sim_response(hwInterfaceNo, KAL_TRUE, &sw1, &sw2);
1079 if (func_status) return func_status;
1080// --
1081 tx_buf[0] = 0xA0;
1082 tx_buf[1] = 0xB0;
1083 tx_buf[2] = 0x00;
1084 tx_buf[3] = 0x00;
1085 tx_buf[4] = 10;
1086 func_status = usim_iftest_send_sim_command(hwInterfaceNo, tx_buf, 5, tx_buf[4]);
1087 if (func_status) return func_status;
1088 func_status = usim_iftest_get_sim_response(hwInterfaceNo, KAL_TRUE, &sw1, &sw2);
1089 if (func_status) return func_status;
1090
1091 func_status = usim_iftest_sim_deactivation(hwInterfaceNo);
1092
1093#ifdef SIM_DRV_SWITCH_MT6306
1094#if defined(__SIM_DRV_CO_LOAD_MT6306__)
1095 if(sim_connectMT6306 == KAL_TRUE)
1096 {
1097#endif
1098 // patch for 3-SIM USIMSMT
1099 MT6306_blockALLSignal(chip, port);
1100 MT6306_setVCC(hwInterfaceNo, port, 0, 0); //Turn off VSIM
1101#if defined(__SIM_DRV_CO_LOAD_MT6306__)
1102 }
1103#endif
1104#endif
1105
1106 if (func_status) return func_status;
1107
1108 return USIM_SMT_NO_ERROR;
1109}
1110
1111void usim_iftest_sw_reset_usim(kal_uint32 hwInterfaceNo)
1112{
1113#if defined(MT6752)
1114#endif
1115 return;
1116}
1117#if defined(__IC_SLT__)
1118typedef enum
1119{
1120 REG_GROUP_HDMA = 0,
1121 REG_GROUP_USIM,
1122 REG_GROUP_USIM2,
1123 REG_GROUP_NUM,
1124} REG_GROUP;
1125typedef struct
1126{
1127 kal_uint32 addr;
1128 kal_char attr[32];
1129 kal_char reset_val[32];
1130} usim_reg_desc_t;
1131#define BASE_HDMA BASE_ADDR_MDGDMA
1132#define REG_HDMA_HDCSR0 (BASE_HDMA + 0x0100)
1133#define HDMA_MODE_0 (1 << 9) //channel 0
1134#define HDMA_MODE_1 (1 << 25) //channel 1
1135#define REG_HDMA_HDSR (BASE_HDMA + 0x0120) // shared
1136#define HDMA_STAT0_0 (1 << 0) // buffer 0, channel 0
1137#define HDMA_STAT0_1 (1 << 1) // buffer 0, channel 1
1138#define HDMA_STAT1_0 (1 << 16) // buffer 1, channel 0
1139#define HDMA_STAT1_1 (1 << 17) // buffer 1, channel 1
1140#define REG_HDMA_HDCPR (BASE_HDMA + 0x0124) // shared
1141#define HDMA_HCURR_PTR_0 (1 << 0) // channel 0
1142#define HDMA_HCURR_PTR_1 (1 << 1) // channel 1
1143#define REG_HDMA_HDCTRR0 (BASE_HDMA + 0x0140) // channel 0
1144#define REG_HDMA_HDCTRR1 (BASE_HDMA + 0x0160) // channel 1
1145#define HDCTRR_STOP (1 << 2)
1146#define HDCTRR_MEM_BUS_WIDTH(n) ((n) << 4)
1147#define HDCTRR_DEV_BUS_WIDTH(n) ((n) << 6)
1148#define HDCTRR_BUS_WIDTH_8 0
1149#define HDCTRR_BUS_WIDTH_16 1
1150#define HDCTRR_BUS_WIDTH_32 2
1151#define HDCTRR_BST_SIZE(n) ((n) << 12)
1152#define HDCTRR_BST_SIZE_4 2
1153#define HDCTRR_BST_SIZE_8 3
1154#define HDCTRR_BST_SIZE_16 4
1155#define HDCTRR_BST_SIZE_32 5 // reserved
1156#define HDCTRR_BST_SIZE_64 6 // reserved
1157#define HDCTRR_BST_SIZE_128 7 // reserved
1158#define HDCTRR_RX_SEL0(n) ((n) << 30)
1159#define HDCTRR_RX_SEL1(n) ((n) << 31)
1160#define REG_HDMA_HDC0R0 (BASE_HDMA + 0x0144) // channel 0
1161#define REG_HDMA_HDC0R1 (BASE_HDMA + 0x0164) // channel 1
1162#define HDCR_XFER_SIZE0(n) ((n) << 16)
1163#define HDCR_START0 (1 << 0)
1164#define REG_HDMA_HDC1R0 (BASE_HDMA + 0x0148) // channel 0
1165#define REG_HDMA_HDC1R1 (BASE_HDMA + 0x0168) // channel 1
1166#define HDCR_XFER_SIZE1(n) ((n) << 16)
1167#define HDCR_START1 (1 << 0)
1168#define REG_HDMA_HPRGA0R0 (BASE_HDMA + 0x014C) // channel 0
1169#define REG_HDMA_HPRGA0R1 (BASE_HDMA + 0x016C) // channel 1
1170#define REG_HDMA_HPRGA1R0 (BASE_HDMA + 0x0150) // channel 0
1171#define REG_HDMA_HPRGA1R1 (BASE_HDMA + 0x0170) // channel 1
1172#define REG_HDMA_HCCR0 (BASE_HDMA + 0x0154) // channel 0
1173#define REG_HDMA_HCCR1 (BASE_HDMA + 0x0174) // channel 1
1174#define HDMA_HCURR_CNT0 0x0000FFFF
1175#define HDMA_HCURR_CNT1 0xFFFF0000
1176#define REG_HDMA_HDCPR0 (BASE_HDMA + 0x0158) // channel 0
1177#define REG_HDMA_HDCPR1 (BASE_HDMA + 0x0178) // channel 1
1178#define REG_GDMA_GISAR2 (BASE_HDMA + 0x608)
1179#define HDMA_DONE_0x (1<<0)
1180#define HDMA_DONE_1x (1<<1)
1181#define REG_GDMA_GIMRK4 (BASE_HDMA + 0x630)
1182
1183
1184#define UT_USIM_BASE_ADDR_USIM1 BASE_ADDR_USIM1
1185#define UT_USIM_BASE_ADDR_USIM2 BASE_ADDR_USIM2
1186
1187usim_reg_desc_t hdma_reg[] =
1188{
1189 // 8 4 0 6 2 8 4 0 8 4 0 6 2 8 4 0
1190 {REG_HDMA_HDCSR0, {"axxxxaaaxxxxxxxxaxxxxaaaxxxxxxxx"}, {"0xxxx010xxxxxxxx0xxxx010xxxxxxxx"}},
1191 {REG_HDMA_HDSR, {"xxxxxxxxxxxxxxrrxxxxxxxxxxxxxxrr"}, {"xxxxxxxxxxxxxx00xxxxxxxxxxxxxx00"}},
1192 {REG_HDMA_HDCPR, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxrr"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00"}},
1193
1194 {REG_HDMA_HDCTRR0, {"aaxxxxxxxxxxxxxxaaaaxxxxaaaaxfxx"}, {"00xxxxxxxxxxxxxx0100xxxx0010x0xx"}},
1195 {REG_HDMA_HDCTRR1, {"aaxxxxxxxxxxxxxxaaaaxxxxaaaaxfxx"}, {"00xxxxxxxxxxxxxx0100xxxx0010x0xx"}},
1196 {REG_HDMA_HDC0R0, {"aaaaaaaaaaaaaaaaxxxxxxxxxxxxxxff"}, {"0000000000000000xxxxxxxxxxxxxx00"}},
1197 {REG_HDMA_HDC0R1, {"aaaaaaaaaaaaaaaaxxxxxxxxxxxxxxff"}, {"0000000000000000xxxxxxxxxxxxxx00"}},
1198 {REG_HDMA_HDC1R0, {"aaaaaaaaaaaaaaaaxxxxxxxxxxxxxxff"}, {"0000000000000000xxxxxxxxxxxxxx00"}},
1199 {REG_HDMA_HDC1R1, {"aaaaaaaaaaaaaaaaxxxxxxxxxxxxxxff"}, {"0000000000000000xxxxxxxxxxxxxx00"}},
1200
1201 {REG_HDMA_HPRGA0R0, {"aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"}, {"00000000000000000000000000000000"}},
1202 {REG_HDMA_HPRGA0R1, {"aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"}, {"00000000000000000000000000000000"}},
1203 {REG_HDMA_HPRGA1R0, {"aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"}, {"00000000000000000000000000000000"}},
1204 {REG_HDMA_HPRGA1R1, {"aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"}, {"00000000000000000000000000000000"}},
1205 {REG_HDMA_HCCR0, {"rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr"}, {"00000000000000000000000000000000"}},
1206 {REG_HDMA_HCCR1, {"rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr"}, {"00000000000000000000000000000000"}},
1207 {REG_HDMA_HDCPR0, {"rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr"}, {"00000000000000000000000000000000"}},
1208 {REG_HDMA_HDCPR1, {"rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr"}, {"00000000000000000000000000000000"}},
1209
1210 {REG_GDMA_GISAR2, {"xxccxxccxxxxxxccxxxxxxccxxxxxxcc"}, {"xx00xx00xxxxxx00xxxxxx00xxxxxx00"}},
1211 {REG_GDMA_GIMRK4, {"xxaaxxaaxxxxxxaaxxxxxxaaxxxxxxaa"}, {"xx11xx11xxxxxx11xxxxxx11xxxxxx11"}}, //97 Change
1212
1213};
1214
1215// USIM IP
1216usim_reg_desc_t usim_reg[] =
1217{
1218 // 8 4 0 6 2 8 4 0 8 4 0 6 2 8 4 0
1219 {UT_USIM_BASE_ADDR_USIM1 + 0x0000, {"rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"}}, //REG_USIM_CODA_VERSION
1220 {UT_USIM_BASE_ADDR_USIM1 + 0x0010, {"xxxxxxxxxxxxxxxxxxxxxxxxxxpaapaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxx000000"}}, //REG_USIM_CTRL
1221 {UT_USIM_BASE_ADDR_USIM1 + 0x0014, {"xxxxxxxxxxxxxxxxxxxxaaaaaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxx000000000000"}}, //REG_USIM_CONF
1222 {UT_USIM_BASE_ADDR_USIM1 + 0x0018, {"xxxxxxxxxxxxxxxxxxxxxuxxxxxxxxxu"}, {"xxxxxxxxxxxxxxxxxxxxx0xxxxxxxxx0"}}, //REG_USIM_CONFSTA
1223 {UT_USIM_BASE_ADDR_USIM1 + 0x001C, {"xxxxxxxxxxxxxxxxxxaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxx00010111010000"}}, //REG_USIM_BRR
1224 {UT_USIM_BASE_ADDR_USIM1 + 0x0020, {"xxxxxxxxxxxxxxxxxxxxaaaaaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxx000000000000"}}, //REG_USIM_IRQEN
1225 {UT_USIM_BASE_ADDR_USIM1 + 0x0024, {"xxxxxxxxxxxxxxxxxxxxccccccccccuu"}, {"xxxxxxxxxxxxxxxxxxxx000000000000"}}, //REG_USIM_STS
1226 {UT_USIM_BASE_ADDR_USIM1 + 0x0030, {"xxxxxxxxxxxxxxxxxxxxaaaaxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxx0011xxxx0011"}}, //REG_USIM_RETRY
1227 {UT_USIM_BASE_ADDR_USIM1 + 0x0034, {"xxxxxxxxxxxxxxxxxxxxaaaaxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxx0000xxxx0000"}}, //REG_USIM_TIDE
1228 {UT_USIM_BASE_ADDR_USIM1 + 0x0040, {"xxxxxxxxxxxxxxxxxxxxxxxxffffffff"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"}}, //REG_USIM_DATA: special, FIFO type
1229 {UT_USIM_BASE_ADDR_USIM1 + 0x0044, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxx00000"}}, //REG_USIM_COUNT
1230 {UT_USIM_BASE_ADDR_USIM1 + 0x0054, {"xxxxxxxxxxxxxxxxxxxxxxxxxxaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxx001111"}}, //REG_USIM_DTIME
1231 {UT_USIM_BASE_ADDR_USIM1 + 0x0058, {"xxxxxxxxxxaaaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxx0000000000001001100000"}}, //REG_USIM_WTIME
1232 {UT_USIM_BASE_ADDR_USIM1 + 0x005C, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxx1010"}}, //REG_USIM_GTIME
1233 {UT_USIM_BASE_ADDR_USIM1 + 0x0060, {"xxxxxxxxxxxxxxxxxxxxxxxxxxaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxx001111"}}, //REG_USIM_ETIME
1234 {UT_USIM_BASE_ADDR_USIM1 + 0x0064, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxx0001"}}, //REG_USIM_EXT_TIME
1235 {UT_USIM_BASE_ADDR_USIM1 + 0x0068, {"xxxxxxxxxxxxxxxxxxxxxxxxaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000010"}}, //REG_USIM_CGTIME
1236 {UT_USIM_BASE_ADDR_USIM1 + 0x0070, {"xxxxxxxxxxxxxxxxpxxxxxxaaaaaaaaa"}, {"xxxxxxxxxxxxxxxx0xxxxxx000000000"}}, //REG_USIM_COMDCTRL
1237 {UT_USIM_BASE_ADDR_USIM1 + 0x0074, {"xxxxxxxxxxxxxxxxxxxxxxxxaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000000"}}, //REG_USIM_COMDLEN
1238 {UT_USIM_BASE_ADDR_USIM1 + 0x0078, {"xxxxxxxxxxxxxxxxxxxxxxxuuuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxx000000000"}}, //REG_USIM_LEFTLEN
1239 {UT_USIM_BASE_ADDR_USIM1 + 0x007C, {"xxxxxxxxxxxxxxxxxxxxxxxxuuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000000"}}, //REG_USIM_LATCH1
1240 {UT_USIM_BASE_ADDR_USIM1 + 0x0080, {"xxxxxxxxxxxxxxxxxxxxxxxxuuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000000"}}, //REG_USIM_LATCH2
1241 {UT_USIM_BASE_ADDR_USIM1 + 0x0090, {"xxxxxxxxxxxxxxxxxxxxxxxuuxxxxxxu"}, {"xxxxxxxxxxxxxxxxxxxxxxx00xxxxxx1"}}, //REG_USIM_ATRSTA
1242 {UT_USIM_BASE_ADDR_USIM1 + 0x0094, {"xxxxxxxxxxxxxxxxxxxxxxxxxuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxxx0000001"}}, //REG_USIM_T0PTLSTA
1243 {UT_USIM_BASE_ADDR_USIM1 + 0x0098, {"xxxxuuuuxxxuuuuuxxxuuuuuxxxuuuuu"}, {"xxxx0000xxx00000xxx00000xxx00000"}}, //REG_USIM_DBG
1244 {UT_USIM_BASE_ADDR_USIM1 + 0x009C, {"xxxxxxxxxxxxxxxxxxxxuuuuffffffff"}, {"xxxxxxxxxxxxxxxxxxxx0000xxxxxxxx"}}, //REG_USIM_DBGDATA: special, read will cause side effect
1245 {UT_USIM_BASE_ADDR_USIM1 + 0x00A0, {"xxxxxxxxxxxxxxxxxxxxxxxxffffffff"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"}}, //REG_USIM_DMADATA: special, FIFO type
1246 {UT_USIM_BASE_ADDR_USIM1 + 0x00A8, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0"}}, //REG_USIM_RPTR_LOCK_EN
1247 {UT_USIM_BASE_ADDR_USIM1 + 0x00B0, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME1
1248 {UT_USIM_BASE_ADDR_USIM1 + 0x00B4, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME2
1249 {UT_USIM_BASE_ADDR_USIM1 + 0x00B8, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME3
1250 {UT_USIM_BASE_ADDR_USIM1 + 0x00BC, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME4
1251 {UT_USIM_BASE_ADDR_USIM1 + 0x00C0, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0"}}, //REG_USIM_SIMOE_MODE
1252 {UT_USIM_BASE_ADDR_USIM1 + 0x00D0, {"uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu"}, {"00000000000000000000000000000000"}}, //REG_USIM_DEBUG1
1253 {UT_USIM_BASE_ADDR_USIM1 + 0x00D4, {"uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu"}, {"00000000000000000000000000000000"}}, //REG_USIM_DEBUG2
1254
1255};
1256
1257usim_reg_desc_t usim_reg2[] =
1258{
1259 // 8 4 0 6 2 8 4 0 8 4 0 6 2 8 4 0
1260 {UT_USIM_BASE_ADDR_USIM2 + 0x0000, {"rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"}}, //REG_USIM_CODA_VERSION
1261 {UT_USIM_BASE_ADDR_USIM2 + 0x0010, {"xxxxxxxxxxxxxxxxxxxxxxxxxxpaapaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxx000000"}}, //REG_USIM_CTRL
1262 {UT_USIM_BASE_ADDR_USIM2 + 0x0014, {"xxxxxxxxxxxxxxxxxxxxaaaaaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxx000000000000"}}, //REG_USIM_CONF
1263 {UT_USIM_BASE_ADDR_USIM2 + 0x0018, {"xxxxxxxxxxxxxxxxxxxxxuxxxxxxxxxu"}, {"xxxxxxxxxxxxxxxxxxxxx0xxxxxxxxx0"}}, //REG_USIM_CONFSTA
1264 {UT_USIM_BASE_ADDR_USIM2 + 0x001C, {"xxxxxxxxxxxxxxxxxxaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxx00010111010000"}}, //REG_USIM_BRR
1265 {UT_USIM_BASE_ADDR_USIM2 + 0x0020, {"xxxxxxxxxxxxxxxxxxxxaaaaaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxx000000000000"}}, //REG_USIM_IRQEN
1266 {UT_USIM_BASE_ADDR_USIM2 + 0x0024, {"xxxxxxxxxxxxxxxxxxxxccccccccccuu"}, {"xxxxxxxxxxxxxxxxxxxx000000000000"}}, //REG_USIM_STS
1267 {UT_USIM_BASE_ADDR_USIM2 + 0x0030, {"xxxxxxxxxxxxxxxxxxxxaaaaxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxx0011xxxx0011"}}, //REG_USIM_RETRY
1268 {UT_USIM_BASE_ADDR_USIM2 + 0x0034, {"xxxxxxxxxxxxxxxxxxxxaaaaxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxx0000xxxx0000"}}, //REG_USIM_TIDE
1269 {UT_USIM_BASE_ADDR_USIM2 + 0x0040, {"xxxxxxxxxxxxxxxxxxxxxxxxffffffff"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"}}, //REG_USIM_DATA: special, FIFO type
1270 {UT_USIM_BASE_ADDR_USIM2 + 0x0044, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxx00000"}}, //REG_USIM_COUNT
1271 {UT_USIM_BASE_ADDR_USIM2 + 0x0054, {"xxxxxxxxxxxxxxxxxxxxxxxxxxaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxx001111"}}, //REG_USIM_DTIME
1272 {UT_USIM_BASE_ADDR_USIM2 + 0x0058, {"xxxxxxxxxxaaaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxx0000000000001001100000"}}, //REG_USIM_WTIME
1273 {UT_USIM_BASE_ADDR_USIM2 + 0x005C, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxx1010"}}, //REG_USIM_GTIME
1274 {UT_USIM_BASE_ADDR_USIM2 + 0x0060, {"xxxxxxxxxxxxxxxxxxxxxxxxxxaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxx001111"}}, //REG_USIM_ETIME
1275 {UT_USIM_BASE_ADDR_USIM2 + 0x0064, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxx0001"}}, //REG_USIM_EXT_TIME
1276 {UT_USIM_BASE_ADDR_USIM2 + 0x0068, {"xxxxxxxxxxxxxxxxxxxxxxxxaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000010"}}, //REG_USIM_CGTIME
1277 {UT_USIM_BASE_ADDR_USIM2 + 0x0070, {"xxxxxxxxxxxxxxxxpxxxxxxaaaaaaaaa"}, {"xxxxxxxxxxxxxxxx0xxxxxx000000000"}}, //REG_USIM_COMDCTRL
1278 {UT_USIM_BASE_ADDR_USIM2 + 0x0074, {"xxxxxxxxxxxxxxxxxxxxxxxxaaaaaaaa"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000000"}}, //REG_USIM_COMDLEN
1279 {UT_USIM_BASE_ADDR_USIM2 + 0x0078, {"xxxxxxxxxxxxxxxxxxxxxxxuuuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxx000000000"}}, //REG_USIM_LEFTLEN
1280 {UT_USIM_BASE_ADDR_USIM2 + 0x007C, {"xxxxxxxxxxxxxxxxxxxxxxxxuuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000000"}}, //REG_USIM_LATCH1
1281 {UT_USIM_BASE_ADDR_USIM2 + 0x0080, {"xxxxxxxxxxxxxxxxxxxxxxxxuuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxx00000000"}}, //REG_USIM_LATCH2
1282 {UT_USIM_BASE_ADDR_USIM2 + 0x0090, {"xxxxxxxxxxxxxxxxxxxxxxxuuxxxxxxu"}, {"xxxxxxxxxxxxxxxxxxxxxxx00xxxxxx1"}}, //REG_USIM_ATRSTA
1283 {UT_USIM_BASE_ADDR_USIM2 + 0x0094, {"xxxxxxxxxxxxxxxxxxxxxxxxxuuuuuuu"}, {"xxxxxxxxxxxxxxxxxxxxxxxxx0000001"}}, //REG_USIM_T0PTLSTA
1284 {UT_USIM_BASE_ADDR_USIM2 + 0x0098, {"xxxxuuuuxxxuuuuuxxxuuuuuxxxuuuuu"}, {"xxxx0000xxx00000xxx00000xxx00000"}}, //REG_USIM_DBG
1285 {UT_USIM_BASE_ADDR_USIM2 + 0x009C, {"xxxxxxxxxxxxxxxxxxxxuuuuffffffff"}, {"xxxxxxxxxxxxxxxxxxxx0000xxxxxxxx"}}, //REG_USIM_DBGDATA: special, read will cause side effect
1286 {UT_USIM_BASE_ADDR_USIM2 + 0x00A0, {"xxxxxxxxxxxxxxxxxxxxxxxxffffffff"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"}}, //REG_USIM_DMADATA: special, FIFO type
1287 {UT_USIM_BASE_ADDR_USIM2 + 0x00A8, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxa"}, {"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0"}}, //REG_USIM_RPTR_LOCK_EN
1288 {UT_USIM_BASE_ADDR_USIM2 + 0x00B0, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME1
1289 {UT_USIM_BASE_ADDR_USIM2 + 0x00B4, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME2
1290 {UT_USIM_BASE_ADDR_USIM2 + 0x00B8, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME3
1291 {UT_USIM_BASE_ADDR_USIM2 + 0x00BC, {"xxxxxxxxxxxxaaaaaaaaaaaaaaaaaaaa"}, {"xxxxxxxxxxxx00000000001010111110"}}, //REG_USIM_ATIME4
1292 {UT_USIM_BASE_ADDR_USIM2 + 0x00D0, {"uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu"}, {"00000000000000000000000000000000"}}, //REG_USIM_DEBUG1
1293 {UT_USIM_BASE_ADDR_USIM2 + 0x00D4, {"uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu"}, {"00000000000000000000000000000000"}}, //REG_USIM_DEBUG2
1294
1295};
1296#define GET_FIELD(val, bit_offset, bit_len) \
1297 (((val) >> (bit_offset)) & (~(0xFFFFFFFF << (bit_len))))
1298#define SET_FIELD(val, bit_offset, bit_len, field_val) \
1299 ((val) = ((val) & ~((1 << ((bit_offset) + (bit_len))) - (1 << ((bit_offset))))) | ( ((field_val) << (bit_offset)) & ((1 << ((bit_offset) + (bit_len))) - (1 << ((bit_offset))))))
1300
1301
1302kal_bool USIM_SLT_reg_read_write_test()
1303{
1304
1305 kal_bool ut_usim_breset_status = KAL_TRUE;
1306 kal_uint32 reg_index, reg_group_index, bit_index;
1307
1308 kal_uint32 reg_addr, expected_val, i;
1309 kal_char *reset_val, *attr;
1310 kal_uint32 reg_num;
1311 kal_char bypass_items[] = { 0x40, 0x9C, 0xA0};
1312
1313 for (reg_group_index = 0; reg_group_index < REG_GROUP_NUM; reg_group_index++)
1314 {
1315 switch (reg_group_index)
1316 {
1317 case REG_GROUP_HDMA:
1318 slt_dbg_print( " ---- %s ----\r\n", "HDMA");
1319 reg_num = sizeof(hdma_reg) / sizeof(usim_reg_desc_t);
1320 break;
1321 case REG_GROUP_USIM:
1322 slt_dbg_print( " ---- %s ----\r\n", "USIM0");
1323 reg_num = sizeof(usim_reg) / sizeof(usim_reg_desc_t);
1324 break;
1325 case REG_GROUP_USIM2:
1326 slt_dbg_print( " ---- %s ----\r\n", "USIM1");
1327 reg_num = sizeof(usim_reg2) / sizeof(usim_reg_desc_t);
1328 break;
1329 default:
1330 ASSERT(0);
1331 }
1332
1333 /*
1334 * Check Default Values
1335 */
1336 for (reg_index = 0; reg_index < reg_num; reg_index++)
1337 {
1338 switch (reg_group_index)
1339 {
1340 case REG_GROUP_HDMA:
1341 reg_addr = hdma_reg[reg_index].addr;
1342 reset_val = hdma_reg[reg_index].reset_val;
1343 break;
1344 case REG_GROUP_USIM:
1345 reg_addr = usim_reg[reg_index].addr;
1346 reset_val = usim_reg[reg_index].reset_val;
1347 break;
1348 case REG_GROUP_USIM2:
1349 reg_addr = usim_reg2[reg_index].addr;
1350 reset_val = usim_reg2[reg_index].reset_val;
1351 break;
1352 default:
1353 ASSERT(0);
1354 }
1355
1356 if (reg_group_index == REG_GROUP_USIM || reg_group_index == REG_GROUP_USIM2)
1357 {
1358 for (i = 0; i < (sizeof(bypass_items) / sizeof(kal_char)); i++)
1359 if ((reg_addr & 0xFF) == bypass_items[i])
1360 break;
1361 if (i < (sizeof(bypass_items) / sizeof(kal_char)))
1362 continue;
1363 }
1364
1365 expected_val = DRV_Reg32(reg_addr);
1366 //slt_dbg_print("Check default Value, addr:%x, expected value:%x\r\n",reg_addr,expected_val);
1367
1368 for (bit_index = 0; bit_index < 32; bit_index++)
1369 {
1370 kal_uint32 expected_bit_type = reset_val[bit_index];
1371 kal_uint32 expected_bit_val = GET_FIELD(expected_val, 32 - 1 - bit_index, 1);
1372
1373 switch (expected_bit_type)
1374 {
1375 case '0':
1376 if (expected_bit_val != 0)
1377 {
1378 slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
1379 slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
1380 slt_dbg_print("Bit[%d] is not '0'\r\n", 32 - 1 - bit_index);
1381 slt_dbg_print("Reg Val: 0x%08X\r\n", expected_val);
1382
1383 ut_usim_breset_status = KAL_FALSE;
1384 }
1385 break;
1386 case '1':
1387 if (expected_bit_val != 1)
1388 {
1389 slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
1390 slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
1391 slt_dbg_print("Bit[%d] is not '1'\r\n", 32 - 1 - bit_index);
1392
1393 ut_usim_breset_status = KAL_FALSE;
1394 }
1395 break;
1396 case 'x':
1397 break;
1398 default:
1399 break;
1400 }
1401 }
1402 }
1403
1404 /*
1405 * Check Types That Cause No Side Effects
1406 */
1407 for (reg_index = 0; reg_index < reg_num; reg_index++)
1408 {
1409 switch (reg_group_index)
1410 {
1411 case REG_GROUP_HDMA:
1412 reg_addr = hdma_reg[reg_index].addr;
1413 attr = hdma_reg[reg_index].attr;
1414 break;
1415 case REG_GROUP_USIM:
1416 reg_addr = usim_reg[reg_index].addr;
1417 attr = usim_reg[reg_index].attr;
1418 break;
1419 case REG_GROUP_USIM2:
1420 reg_addr = usim_reg2[reg_index].addr;
1421 attr = usim_reg2[reg_index].attr;
1422 break;
1423 default:
1424 ASSERT(0);
1425 }
1426
1427 if (reg_group_index == REG_GROUP_USIM || reg_group_index == REG_GROUP_USIM2)
1428 {
1429 for (i = 0; i < (sizeof(bypass_items) / sizeof(kal_char)); i++)
1430 if ((reg_addr & 0xFF) == bypass_items[i])
1431 break;
1432 if (i < (sizeof(bypass_items) / sizeof(kal_char)))
1433 continue;
1434 }
1435 //slt_dbg_print("Check default Attr, addr:%x,0x98:%x_%x\r\n",reg_addr,DRV_Reg32(0xB0040098)>>16,DRV_Reg32(0xB0040098)&0xFFFF);
1436 for (bit_index = 0; bit_index < 32; bit_index++)
1437 {
1438 kal_uint32 expected_bit_attr = attr[bit_index];
1439 kal_uint32 expected_bit_val = GET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1);
1440
1441 switch (expected_bit_attr)
1442 {
1443 /*
1444 * Check if '0' & '1'' Write-able
1445 */
1446 case 'a':
1447 // Set Bit to '0' and Check
1448 DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, 0));
1449
1450 if (GET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1) != 0)
1451 {
1452 slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
1453 slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
1454 slt_dbg_print("Bit[%d] is not '0' Write-able\r\n", 32 - 1 - bit_index);
1455
1456 ut_usim_breset_status = KAL_FALSE;
1457 }
1458
1459 // Set Bit to '1' and Check
1460 DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, 1));
1461
1462 if (GET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1) != 1)
1463 {
1464 slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
1465 slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
1466 slt_dbg_print("Bit[%d] is not '1' Write-able\r\n", 32 - 1 - bit_index);
1467
1468 ut_usim_breset_status = KAL_FALSE;
1469 }
1470
1471 // Set Bit to Default Value
1472 DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, expected_bit_val));
1473 break;
1474 case 'k':
1475 case 'p':
1476 case 'c':
1477 // Set 1 and Check if Bit is 0
1478 DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, 1));
1479
1480 if (GET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1) != 0)
1481 {
1482 slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
1483 slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
1484 slt_dbg_print("Bit[%d] is Write-one-clear, but currently read to be 1\r\n", 32 - 1 - bit_index);
1485
1486 ut_usim_breset_status = KAL_FALSE;
1487 }
1488 break;
1489 case 'r':
1490 // Set Bit to Inverse of Default Value and Check if Bit Changed
1491 DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, ~expected_bit_val));
1492
1493 if (GET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1) != expected_bit_val)
1494 {
1495 slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
1496 slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
1497 slt_dbg_print("Bit[%d] is write-able, but expected to be read-only\r\n", 32 - 1 - bit_index);
1498
1499 // Set Bit to Default Value For Future Tests
1500 DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, expected_bit_val));
1501
1502 ut_usim_breset_status = KAL_FALSE;
1503 }
1504 break;
1505 /*
1506 * Bypass Don't Care Bit
1507 */
1508 case 'u': /* May Update by Design */
1509 case 'f': /* Special Type */
1510 case 'x':
1511 break;
1512 default:
1513 break;
1514 }
1515 }
1516 }
1517
1518 /*
1519 * Check Types That Cause Side Effects
1520 */
1521 for (reg_index = 0; reg_index < reg_num; reg_index++)
1522 {
1523 switch (reg_group_index)
1524 {
1525 case REG_GROUP_HDMA:
1526 reg_addr = hdma_reg[reg_index].addr;
1527 attr = hdma_reg[reg_index].attr;
1528 break;
1529 case REG_GROUP_USIM:
1530 reg_addr = usim_reg[reg_index].addr;
1531 attr = usim_reg[reg_index].attr;
1532 break;
1533 case REG_GROUP_USIM2:
1534 reg_addr = usim_reg2[reg_index].addr;
1535 attr = usim_reg2[reg_index].attr;
1536 break;
1537 default:
1538 ASSERT(0);
1539 }
1540
1541 if (reg_group_index == REG_GROUP_USIM || reg_group_index == REG_GROUP_USIM2)
1542 {
1543 for (i = 0; i < (sizeof(bypass_items) / sizeof(kal_char)); i++)
1544 if ((reg_addr & 0xFF) == bypass_items[i])
1545 break;
1546 if (i < (sizeof(bypass_items) / sizeof(kal_char)))
1547 continue;
1548 }
1549
1550 for (bit_index = 0; bit_index < 32; bit_index++)
1551 {
1552 kal_uint32 expected_bit_attr = attr[bit_index];
1553
1554 switch (expected_bit_attr)
1555 {
1556 case 's':
1557 // Set Bit to 1 and Check if Bit Changed
1558 DRV_WriteReg32(reg_addr, SET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1, 1));
1559
1560 if (GET_FIELD(DRV_Reg32(reg_addr), 32 - 1 - bit_index, 1) == 1)
1561 {
1562 slt_dbg_print("[ERR] FILE: %s, FUNC: %s, LINE: %d\r\n", __FILE__, __FUNCTION__, __LINE__);
1563 slt_dbg_print("Reg Address: 0x%08X\r\n", reg_addr);
1564 slt_dbg_print("Bit[%d] is write-able, but expected to be read-only\r\n", 32 - 1 - bit_index);
1565
1566 ut_usim_breset_status = KAL_FALSE;
1567 }
1568 break;
1569 /*
1570 * Bypass All Others
1571 */
1572 default:
1573 break;
1574 }
1575 }
1576 }
1577
1578 }
1579 //Reset Interface
1580 for (i=0;i<2;i++)
1581 {
1582 if (i==0)
1583 reg_addr = UT_USIM_BASE_ADDR_USIM1;
1584 else
1585 reg_addr = UT_USIM_BASE_ADDR_USIM2;
1586
1587 DRV_WriteReg32(reg_addr + SIM_CTRL_MTK,SIM_CTRL_SIMON|SIM_CTRL_IFCLR);
1588 while ((DRV_Reg32(reg_addr +SIM_ATRSTA_MTK) & (SIM_ATRSTA_IR | SIM_ATRSTA_AL)) == 0);
1589 while (DRV_Reg32(reg_addr+SIM_CONFSTA_MTK) & SIM_CONFSTA_IFCLR_ON);
1590 DRV_WriteReg32(reg_addr + SIM_CTRL_MTK,0x0); //SIM
1591 }
1592 return ut_usim_breset_status;
1593}
1594#endif