| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | #ifndef __UART_SW_INT_H__ |
| 2 | #define __UART_SW_INT_H__ |
| 3 | |
| 4 | /* |
| 5 | * NoteXXX: Below is the sample code to set UART |
| 6 | * UART clock is MPLL clock / 8. |
| 7 | * baud rate is 115200. |
| 8 | * Thus UART1_DLL = 0xE. |
| 9 | * You should specify UART1_DLL based on |
| 10 | * divisor(DLH+DLL) = (UART_CLOCK_RATE) |
| 11 | */ |
| 12 | |
| 13 | |
| 14 | #define UART_SETUP(_n, _divL, _divH) \ |
| 15 | do { \ |
| 16 | volatile kal_uint16 tmp; \ |
| 17 | \ |
| 18 | /* Setup 8-N-1,(UART_WLS_8 | UART_NONE_PARITY | UART_ */ \ |
| 19 | UART_WriteReg(UART##_n##_LCR,0x0003); \ |
| 20 | \ |
| 21 | /* divisor: 8 */ \ |
| 22 | UART_WriteReg(UART##_n##_HIGHSPEED,0x0001); \ |
| 23 | \ |
| 24 | /* Set BaudRate */ \ |
| 25 | tmp = UART_ReadReg(UART##_n##_LCR); \ |
| 26 | tmp |= UART_LCR_DLAB; \ |
| 27 | UART_WriteReg(UART##_n##_LCR, tmp); \ |
| 28 | \ |
| 29 | /* MCU_CLK 491520000(491.52MHz) */ \ |
| 30 | /* UART_CLK (MCU_CLK / 8) */ \ |
| 31 | \ |
| 32 | /* divisorL = ((UART_CLK / 8) / 115200) & 0xFF; */ \ |
| 33 | /* divisorH = ((UART_CLK / 8) / 115200) >> 8; */ \ |
| 34 | \ |
| 35 | /* UART_WriteReg(_DLL, divisorL); */ \ |
| 36 | UART_WriteReg(UART##_n##_DLL, (_divL)); \ |
| 37 | /* UART_WriteReg(_DLM, divisorH); */ \ |
| 38 | UART_WriteReg(UART##_n##_DLM, (_divH)); \ |
| 39 | \ |
| 40 | UART_WriteReg(UART##_n##_LCR, 0x0003); \ |
| 41 | /* Enable Fifo, and Rx Trigger level = 16bytes, flush */ \ |
| 42 | /* (UART_FCR_FIFOEN | UART_FCR_4Byte_Level | UART_FCR */ \ |
| 43 | UART_WriteReg(UART##_n##_FCR, 0x0047); \ |
| 44 | \ |
| 45 | /* DTR , RTS is on, data will be coming,Output2 is hi */ \ |
| 46 | UART_WriteReg(UART##_n##_MCR,(kal_uint16)0x0003); \ |
| 47 | \ |
| 48 | /* _IER, enable RDA, RLS, MS , disable THR inter */ \ |
| 49 | /* UART_WriteReg(UART##_n##_IER, UART_IER_RDA); */ \ |
| 50 | UART_WriteReg(UART##_n##_IER, IER_HW_NORMALINTS); \ |
| 51 | } while(0) |
| 52 | |
| 53 | #endif /* __UART_SW_INT_H__ */ |