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rjw6c1fd8f2022-11-30 14:33:01 +08001#ifndef _BTDMA_PUBLIC_H_
2#define _BTDMA_PUBLIC_H_
3
4
5typedef kal_uint32 btdma_uint32;
6typedef kal_int32 btdma_int32 ;
7typedef kal_uint8 btdma_uint8 ;
8
9typedef enum BTDMA_PRIORITY_CHAIN
10{
11 PRIORITY_0 = 0,
12 PRIORITY_1 ,
13 PRIORITY_2 ,
14 PRIORITY_3 ,
15 PRIORITY_4 ,
16 PRIORITY_5 ,
17 PRIORITY_6 ,
18 PRIORITY_7
19
20} btdma_priority_chain;
21
22typedef enum BTDMA_IP
23{
24 TTBIT = 0 ,
25 SFBIT ,
26 OTEBIT
27} btdma_ip;
28
29typedef enum BTDMA_CORE
30{
31 UNGATE_VCORE = 0 ,
32 UNGATE_MCORE0 = 2 ,
33 UNGATE_MCORE1 = 3
34} btdma_core;
35
36typedef enum BTDMA_CALLBACK
37{
38 #undef BTDMA_CALLBACK_REGISTER
39 #define BTDMA_CALLBACK_REGISTER(KEY,CALLBACK) KEY,
40 #include "btdma_callback_reg.h"
41 #undef BTDMA_CALLBACK_REGISTER
42 BTDMA_CALLBACK_NUM
43} btdma_callback_index;
44
45
46typedef struct BTDMA_DESCRIPTION
47{
48 btdma_uint32 source_address ;
49 btdma_uint32 target_address ;
50 btdma_uint32 crc32 ;
51 btdma_uint32 length :19 ;
52 btdma_uint32 reserved_1 :5 ;
53 btdma_uint32 crc_enable :1 ;
54 btdma_ip src_ip :2 ;
55 btdma_ip dest_ip :2 ;
56 btdma_uint32 reserved_2 :3 ;
57 btdma_uint32 signal_enable :14 ;
58 btdma_uint32 reserved_5 :10 ;
59 btdma_uint32 axi_qos_r_ultra :2 ;
60 btdma_uint32 axi_qos_r_flush :2 ;
61 btdma_uint32 axi_qos_w_ultra :2 ;
62 btdma_uint32 axi_qos_w_flush :2 ;
63 btdma_callback_index callback_key ;
64 btdma_uint32 caller ;
65 btdma_uint8 job_num :4 ;
66 btdma_uint32 reserved_6 :20 ;
67 btdma_uint8 own ;
68} btdma_description;
69
70#define BTDMA_NO_SIGNAL_ENABLE (0)
71#define BTDMA_MCORE0_BOOTDONE_ENABLE (1 << 0)
72#define BTDMA_MCORE1_BOOTDONE_ENABLE (1 << 1)
73#define BTDMA_VCORE0_BOOTDONE_ENABLE (1 << 2)
74#define BTDMA_MCORE0_INTERRUPT_ENABLE (1 << 3)
75#define BTDMA_MCORE1_INTERRUPT_ENABLE (1 << 4)
76#define BTDMA_L1CORE_INTERRUPT_ENABLE (1 << 5)
77
78
79#define BTDMA_MCORE0_TH0_COMPLETE_ENABLE (1 << 6)
80#define BTDMA_MCORE1_TH0_COMPLETE_ENABLE (1 << 7)
81#define BTDMA_MCORE0_TH1_COMPLETE_ENABLE (1 << 8)
82#define BTDMA_MCORE1_TH1_COMPLETE_ENABLE (1 << 9)
83#define BTDMA_MCORE0_TH2_COMPLETE_ENABLE (1 << 10)
84#define BTDMA_MCORE1_TH2_COMPLETE_ENABLE (1 << 11)
85#define BTDMA_MCORE0_TH3_COMPLETE_ENABLE (1 << 12)
86#define BTDMA_MCORE1_TH3_COMPLETE_ENABLE (1 << 13)
87
88#define BTDMA_MCORE_TH_COMPLETE_ENABLE (1 << 6)
89
90
91#define BTDMA_Trigger_User(source_addr,source_ip,target_addr,target_ip,length,BTDMA_L1CORE_INTERRUPT_ENABLE,priority,callback_key)
92
93void SS_BTDMA_Trigger(btdma_description* desc,
94 btdma_priority_chain priority,
95 btdma_callback_index callback_key);
96void BTDMA_MPU_EMI_Region_Set(btdma_uint32 start_address,btdma_uint32 end_address);
97
98void BTDMA_SW_Enable_Ungate_Signal(btdma_core core);
99void BTDMA_SW_Disable_Ungate_Signal(btdma_core core);
100void BTDMA_Init();
101void BTDMA_Polling_Priority_idle(btdma_uint32 priority);
102
103/***************************************************
104*
105*
106* Marco for assign descriptor
107*
108*
109***************************************************/
110#define DESCRIPTION_ASSIGN(SA,TA,SIZE,SE) \
111.source_address = SA , \
112.target_address = TA , \
113.crc32 = 0 , \
114.length = SIZE , \
115.signal_enable = SE , \
116.src_ip = OTEBIT , \
117.dest_ip = OTEBIT , \
118.own = 0xA5
119
120
121#define DESCRIPTION_ASSIGN_CRC(SA,SIP,TA,TIP,SIZE,SE,CRC) \
122.source_address = SA , \
123.target_address = TA , \
124.crc32 = CRC , \
125.length = SIZE , \
126.signal_enable = SE , \
127.crc_enable = 1 , \
128.src_ip = SIP , \
129.dest_ip = TIP , \
130.own = 0xA5
131
132#define DESCRIPTION_ASSIGN_NO_CRC(SA,SIP,TA,TIP,SIZE,SE) \
133.source_address = SA , \
134.target_address = TA , \
135.length = SIZE , \
136.signal_enable = SE , \
137.crc_enable = 0 , \
138.src_ip = SIP , \
139.dest_ip = TIP , \
140.own = 0xA5
141
142
143
144#define DESCRIPTION_END \
145.source_address = 0, \
146.target_address = 0, \
147.crc32 = 0, \
148.length = 0, \
149.crc_enable = 0, \
150.src_ip = TTBIT, \
151.dest_ip = TTBIT, \
152.own = 0
153
154
155#endif