rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * intrCtrl.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * Maui_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * Common type and structure definition for MediaTek GSM/GPRS software |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
| 58 | * removed! |
| 59 | * removed! |
| 60 | * removed! |
| 61 | * |
| 62 | * removed! |
| 63 | * removed! |
| 64 | * removed! |
| 65 | * |
| 66 | * |
| 67 | *------------------------------------------------------------------------------ |
| 68 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 69 | *============================================================================ |
| 70 | ****************************************************************************/ |
| 71 | |
| 72 | #ifndef _INTRCTRL_H |
| 73 | #define _INTRCTRL_H |
| 74 | |
| 75 | /******************************************************************************* |
| 76 | * Include header files |
| 77 | *******************************************************************************/ |
| 78 | #include "kal_general_types.h" |
| 79 | #include "mips_ia_utils_public.h" |
| 80 | #include "us_timer.h" |
| 81 | #include "kal_public_api.h" |
| 82 | |
| 83 | #if defined(MERCURY) |
| 84 | #include "intrCtrl_MERCURY.h" |
| 85 | #endif |
| 86 | |
| 87 | /******************************************************************************* |
| 88 | * Declarations and Definitions |
| 89 | *******************************************************************************/ |
| 90 | #define __ENABLE_SW_TRIGGER_INTERRUPT__ |
| 91 | |
| 92 | #define EDGE_SENSITIVE KAL_TRUE |
| 93 | #define LEVEL_SENSITIVE KAL_FALSE |
| 94 | |
| 95 | #define IRQ_NOT_LISR_CONTEXT (0xFFFF) |
| 96 | |
| 97 | #if defined(__CIRQ_MASK_REG_NR_1_NEW__) || defined(__CIRQ_MASK_REG_NR_2_NEW__) || defined(__CIRQ_MASK_REG_NR_3_NEW__) || defined(__CIRQ_MASK_REG_NR_4_NEW__) || defined(__CIRQ_MASK_REG_NR_5_NEW__) |
| 98 | #define __CIRQ_DESIGN_NEW__ |
| 99 | #endif |
| 100 | |
| 101 | typedef struct CIRQ_MASK_VALUE_STRUCT |
| 102 | { |
| 103 | kal_uint32 irq_mask[12]; |
| 104 | } CIRQ_MASK_VALUE_T; |
| 105 | |
| 106 | /* To enable SW Trigger Interrupt for new BB chips |
| 107 | Need to modify 3 files |
| 108 | 1. add a file intrCtrl_MTxxxx_SW_Handler.h |
| 109 | 2. add an entry on intrCtrl_SW_Handler.h |
| 110 | 3. modify IRQ_SetSWRegister & IRQ_ResetSWRegister to support BB Chips on intrCtrl.c */ |
| 111 | #if defined(__ENABLE_SW_TRIGGER_INTERRUPT__) |
| 112 | typedef enum |
| 113 | { |
| 114 | #define X_SW_HANDLE_CONST(a, b, c) a=(b), |
| 115 | #include "intrCtrl_SW_Handle.h" |
| 116 | #undef X_SW_HANDLE_CONST |
| 117 | SW_HANDLE_END |
| 118 | } SW_CODE_HANDLE; |
| 119 | |
| 120 | #define Activate_LISR(code) MDCIRQ_Activate_LISR(code) |
| 121 | #define Deactivate_LISR(code) MDCIRQ_Deactivate_LISR(code) |
| 122 | |
| 123 | extern void MDCIRQ_Activate_LISR(SW_CODE_HANDLE code); |
| 124 | extern void MDCIRQ_Deactivate_LISR(SW_CODE_HANDLE code); |
| 125 | extern void MDCIRQ_Activate_LISR_without_ITC(SW_CODE_HANDLE code); |
| 126 | extern void MDCIRQ_Deactivate_LISR_without_ITC(SW_CODE_HANDLE code); |
| 127 | extern const kal_uint16 SW_Code_Handle2Code[NUM_IRQ_SOURCES]; |
| 128 | |
| 129 | /* Use to translate the mapping between software handler to hardware interrupt code */ |
| 130 | #define SW_code_handle2code(a) (a) |
| 131 | |
| 132 | extern kal_uint32 SW_INT_Counter[NUM_IRQ_SOURCES]; |
| 133 | |
| 134 | #endif /* __ENABLE_SW_TRIGGER_INTERRUPT__ */ |
| 135 | |
| 136 | |
| 137 | #define IRQClearInt(vector) MDCIRQ_IRQClearInt(vector) |
| 138 | #define IRQMask(vector) MDCIRQ_IRQMask(vector) |
| 139 | #define IRQUnmask(vector) MDCIRQ_IRQUnmask(vector) |
| 140 | #define IRQSensitivity(vector, e) MDCIRQ_IRQSensitivity(vector, e) |
| 141 | #define IRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code) MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code) |
| 142 | |
| 143 | |
| 144 | extern kal_uint32 SaveAndSetIRQMask(void); |
| 145 | extern void RestoreIRQMask(kal_uint32); |
| 146 | extern void MDCIRQ_IRQClearInt(kal_uint16); |
| 147 | extern void MDCIRQ_IRQMask(kal_uint16); |
| 148 | extern void MDCIRQ_IRQUnmask(kal_uint16); |
| 149 | extern void MDCIRQ_IRQSensitivity(kal_uint16, kal_bool); |
| 150 | extern void initINTR(void); |
| 151 | extern kal_uint32 IRQMask_Status(kal_uint16 code); |
| 152 | extern kal_uint32 IRQ_Status(void); |
| 153 | |
| 154 | |
| 155 | #define IRQ_Register_LISR(code, lisr, description) \ |
| 156 | MDCIRQ_IRQ_Register_LISR(code, (void*)lisr, description) |
| 157 | extern void MDCIRQ_IRQ_Register_LISR(kal_uint16 code, void (*reg_lisr)(kal_uint32 vector), char* description); |
| 158 | |
| 159 | #define NRIRQ_Affinity_Change_NSA() MDCIRQ_Runtime_Change_NRIRQ_Affinity_NSA() |
| 160 | #define NRIRQ_Affinity_Change_SA() MDCIRQ_Runtime_Change_NRIRQ_Affinity_SA() |
| 161 | extern void MDCIRQ_Runtime_Change_NRIRQ_Affinity_NSA(); |
| 162 | extern void MDCIRQ_Runtime_Change_NRIRQ_Affinity_SA(); |
| 163 | |
| 164 | #define LTEIRQ_Affinity_Change_ENDC() MDCIRQ_Runtime_Change_LTEIRQ_Affinity_ENDC() |
| 165 | #define LTEIRQ_Affinity_Change_LTEONLY() MDCIRQ_Runtime_Change_LTEIRQ_Affinity_LTEONLY() |
| 166 | extern void MDCIRQ_Runtime_Change_LTEIRQ_Affinity_ENDC(); |
| 167 | extern void MDCIRQ_Runtime_Change_LTEIRQ_Affinity_LTEONLY(); |
| 168 | |
| 169 | extern void initVPEIRQ(void); |
| 170 | |
| 171 | extern kal_uint32 sst_dhl_irq_count[]; |
| 172 | extern kal_uint32 sst_dhl_irq_caller[]; |
| 173 | extern kal_uint32 DHLIrqCounter[]; |
| 174 | |
| 175 | extern kal_int32 INC_Initialize_State; |
| 176 | |
| 177 | typedef enum |
| 178 | { |
| 179 | #define IRQ_PRIORITY_CONST(a) a##_PRIORITY, |
| 180 | #include "irqPriority.h" |
| 181 | #undef IRQ_PRIORITY_CONST |
| 182 | IRQ_PRIORITY_END, |
| 183 | IRQ_HRT_PRIORITY_THRESHOLD = IRQ_SW_LISR40_CODE_PRIORITY + 1, |
| 184 | IRQ_EQUALLY_DISPATCH_PRIORITY_THRESHOLD = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE_PRIORITY, |
| 185 | } IRQ_PRIORITY; |
| 186 | |
| 187 | typedef enum { |
| 188 | MDCIRQ_To_BUS_Normal = 0x0, |
| 189 | MDCIRQ_To_BUS_PreUltra = 0x1, |
| 190 | MDCIRQ_To_BUS_Ultra =0x2, |
| 191 | } MDCIRQ_Bus_QoS_Signal; |
| 192 | |
| 193 | /*********************************** |
| 194 | NOTE: |
| 195 | 1. below API is only for L1 logging, please not use |
| 196 | 2. if you want to use, please confirm with CIRQ owner first |
| 197 | ***********************************/ |
| 198 | #define IF_DI_OR_LISR() (Ibit_Status()==0 || kal_if_lisr()) |
| 199 | |
| 200 | /*********************************** |
| 201 | NOTE: |
| 202 | 1. below API is only for L2 logging, please not use |
| 203 | 2. if you want to use, please confirm with CIRQ owner first |
| 204 | ***********************************/ |
| 205 | #define __IRQ_LOCK_WITHOUT_CHECK__ |
| 206 | #define __NESTED_DI_CHECK__ |
| 207 | |
| 208 | #if defined(__L2_LOGGING_IRQ_LOC__) |
| 209 | #if defined(__IRQ_LOCK_WITHOUT_CHECK__) && (defined(__MIPS_IA__) || defined(__MIPS_I7200__)) |
| 210 | #if defined(__NESTED_DI_CHECK__) && !defined (__ESL_MASE_GEN97__) |
| 211 | #define LOCK_CPU_INTERRUPT(oldmask, newmask) \ |
| 212 | do{\ |
| 213 | kal_uint32 vpe_num = 0;\ |
| 214 | miu_mt_dmt();\ |
| 215 | __asm__ __volatile__\ |
| 216 | (\ |
| 217 | "di %0\n\t"\ |
| 218 | "ehb\n\t"\ |
| 219 | :"=&r"(oldmask), "=&r"(newmask)\ |
| 220 | :\ |
| 221 | :"$31","memory"\ |
| 222 | );\ |
| 223 | oldmask &= 0x1;\ |
| 224 | vpe_num = miu_get_current_vpe_id();\ |
| 225 | sst_dhl_irq_count[vpe_num]++;\ |
| 226 | sst_dhl_irq_caller[vpe_num] = (kal_uint32)__builtin_return_address(0);\ |
| 227 | DHLIrqCounter[vpe_num] = ust_get_current_time();\ |
| 228 | } while(0) |
| 229 | |
| 230 | #define UNLOCK_CPU_INTERRUPT(oldmask) \ |
| 231 | do{\ |
| 232 | kal_uint32 tmp=1;\ |
| 233 | sst_dhl_irq_count[miu_get_current_vpe_id()]--;\ |
| 234 | __asm__ __volatile__\ |
| 235 | (\ |
| 236 | "bne %0, %1, END\n\t"\ |
| 237 | "ei\n\t"\ |
| 238 | "ehb\n\t"\ |
| 239 | "END:emt\n\t"\ |
| 240 | "ehb\n\t"\ |
| 241 | :\ |
| 242 | :"r"(oldmask), "r"(tmp)\ |
| 243 | :"memory"\ |
| 244 | );\ |
| 245 | } while(0) |
| 246 | #else |
| 247 | #define LOCK_CPU_INTERRUPT(oldmask, newmask) \ |
| 248 | do{\ |
| 249 | miu_mt_dmt();\ |
| 250 | __asm__ __volatile__\ |
| 251 | (\ |
| 252 | "di %0\n\t"\ |
| 253 | "ehb\n\t"\ |
| 254 | :"=&r"(oldmask), "=&r"(newmask)\ |
| 255 | :\ |
| 256 | :"$31","memory"\ |
| 257 | );\ |
| 258 | oldmask &= 0x1;\ |
| 259 | } while(0) |
| 260 | |
| 261 | #define UNLOCK_CPU_INTERRUPT(oldmask) \ |
| 262 | do{\ |
| 263 | kal_uint32 tmp=1;\ |
| 264 | __asm__ __volatile__\ |
| 265 | (\ |
| 266 | "bne %0, %1, END\n\t"\ |
| 267 | "ei\n\t"\ |
| 268 | "ehb\n\t"\ |
| 269 | "END:emt\n\t"\ |
| 270 | "ehb\n\t"\ |
| 271 | :\ |
| 272 | :"r"(oldmask), "r"(tmp)\ |
| 273 | :"memory"\ |
| 274 | );\ |
| 275 | } while(0) |
| 276 | #endif |
| 277 | |
| 278 | #else |
| 279 | |
| 280 | #define LOCK_CPU_INTERRUPT(oldmask, newmask) \ |
| 281 | do{ \ |
| 282 | oldmask = kal_hrt_SaveAndSetIRQMask(); \ |
| 283 | }while(0); |
| 284 | |
| 285 | #define UNLOCK_CPU_INTERRUPT(oldmask) \ |
| 286 | do{ \ |
| 287 | kal_hrt_RestoreIRQMask(oldmask); \ |
| 288 | }while(0); |
| 289 | |
| 290 | #endif |
| 291 | #endif |
| 292 | |
| 293 | #endif /* _INTRCTRL_H */ |
| 294 | |