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192.168.1.100 / T800_MD / b0f5b85a5b9d69cbfa1dd990d559a4a9c7d8f2a6 / . / mcu / interface / driver / devdrv / pll / pll_gen95.h
blob: 9857dcbf99c9c24218f7e7c060dfdfa810efe049 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*******************************************************************************
2 * Copyright Statement:
3 * --------------------
4 * This software is protected by Copyright and the information contained
5 * herein is confidential. The software may not be copied and the information
6 * contained herein may not be used or disclosed except with the written
7 * permission of MediaTek Inc. (C) 2012
8 *
9 * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19 * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20 * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21 *
22 * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23 * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27 *
28 * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29 * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30 * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31 * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32 * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33 *
34 ******************************************************************************/
35
36/*******************************************************************************
37 * Filename:
38 * ---------
39 * pll_gen95.h
40 *
41 * Project:
42 * --------
43 * UMOLYA
44 *
45 * Description:
46 * ------------
47 * PLL Related Functions
48 *
49 * Author:
50 * -------
51 * -------
52 *
53 * ============================================================================
54 * $Log$
55 *
56 * 07 25 2018 jun-ying.huang
57 * [MOLY00342276] [MT6779]Add MT6779 macro for LATIFE
58 * .
59 *
60 * 05 30 2018 jun-ying.huang
61 * [MOLY00325066] [MT3967][PLL]Update PLL golden setting
62 * Remove redundant define
63 *
64 * 05 16 2018 jun-ying.huang
65 * [MOLY00325066] [MT3967][PLL]Update PLL golden setting
66 * Update 26M settle time and remove redundant function.
67 *
68 * 12 11 2017 jun-ying.huang
69 * [MOLY00295410] [PLL][MT3967] Add Macro for MT3967
70 * .
71 *
72 * 10 30 2017 jun-ying.huang
73 * [MOLY00286084] [MT6295][PLL] Update BR_EXT section for BootRom
74 * .
75 *
76 * 08 29 2017 jun-ying.huang
77 * [MOLY00261263] [MT6295M]Update PLL driver
78 * Add PLL driver for BootRom
79 *
80 * 07 10 2017 jun-ying.huang
81 * [MOLY00261263] [MT6295M]Update PLL driver
82 * 1st version for MT6295M=EIGER
83 *
84 * 05 23 2017 jun-ying.huang
85 * [MOLY00244448] [MT6295M]Update PLL driver for MT6295M
86 * Fix build error
87 *
88 * 05 15 2017 jun-ying.huang
89 * [MOLY00244448] [MT6295M]Update PLL driver for MT6295M
90 * .
91 *
92 * 04 28 2017 jun-ying.huang
93 * [MOLY00244448] [MT6295M]Update PLL driver for MT6295M
94 * temp driver for 6295
95 *
96 *
97 ****************************************************************************/
98
99#ifndef __PLL_MT6295_H__
100#define __PLL_MT6295_H__
101
102/*******************************************************************************
103 * Locally Used Options
104 ******************************************************************************/
105#define PLL_REG32(addr) *(volatile kal_uint32 *)(addr)
106#define PLL_TYPE (volatile kal_uint32 *)
107
108/*******************************************************************************
109 * Define macro for boot code
110 ******************************************************************************/
111#define __SECTION__(S) __attribute__((__section__(#S)))
112#define __PLL_CODE_IN_BOOT__ __SECTION__(BR_EXT)/* "BR_EXT" section for bootROM */
113
114/*******************************************************************************
115 * Register Define
116 ******************************************************************************/
117
118///////////////////////////////////////////////////////////////////////////////
119/// PLLMIXED (0xA0140000)
120///////////////////////////////////////////////////////////////////////////////
121/* ==========PLL setting========== */
122#define REG_MDTOP_PLLMIXED_CODA_VERSION (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x0))
123#define REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4))
124#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8))
125#define REG_MDTOP_PLLMIXED_DCXO_MODE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC))
126#define REG_MDTOP_PLLMIXED_PLL_ON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10))
127#define REG_MDTOP_PLLMIXED_PLL_SW_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x14))
128#define REG_MDTOP_PLLMIXED_PLL_SW_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x18))
129#define REG_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x1C))
130#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30))
131#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x34))
132#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x38))
133
134/* ==========PLL frequency control==> PCW & POSDIV========== */
135#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x40))
136#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x44))
137#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x48))
138#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4C))
139#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50))
140#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54))
141//#define REG_MDTOP_PLLMIXED_MDTXPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x58))
142//#define REG_MDTOP_PLLMIXED_MDTXPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C))
143#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x60))
144#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x64))
145#define REG_MDTOP_PLLMIXED_MDPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x100))
146#define REG_MDTOP_PLLMIXED_MDPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x104))
147#define REG_MDTOP_PLLMIXED_MDPLL_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x108))
148
149#define REG_MDTOP_PLLMIXED_PLL_RESERVE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10C))
150#define REG_MDTOP_PLLMIXED_PLL_RESERVE2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x110))
151#define REG_MDTOP_PLLMIXED_PLL_DIV_RSTB (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x114))
152#define REG_MDTOP_PLLMIXED_PLL_DIV_EN (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x118))
153#define REG_MDTOP_PLLMIXED_PLL_SRC_SEL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x120))
154#define REG_MDTOP_PLLMIXED_PLL_FHCTL_RST (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x200))
155//#define REG_MDTOP_PLLMIXED_CONN_DSNS_INTF (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x204))
156
157/* ==========PLL IRQ related========== */
158#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x300))
159#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x304))
160#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x308))
161#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30C))
162#define REG_MDTOP_PLLMIXED_PLL_REQ_ABNORM_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x310))
163#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x314))
164 #define PLLMIXED_MDMCUPLL_HP_RDY_IRQ_OFFSET (1)
165 #define PLLMIXED_MDVDSPPLL_HP_RDY_IRQ_OFFSET (2)
166 #define PLLMIXED_MDBRPPLL_HP_RDY_IRQ_OFFSET (4)
167
168#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x318))
169#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x31C))
170
171/* PLL IRQ related macro */
172#define PLLMIXED_PLL_HP_RDY_IRQ_MASK (0x1)/* mask bit numbers for each IRQ */
173
174/* ==========PLL FHCTL========== */
175#define REG_MDTOP_PLLMIXED_MDMCUPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x400))
176#define REG_MDTOP_PLLMIXED_MDMCUPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x404))
177#define REG_MDTOP_PLLMIXED_MDMCUPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x408))
178#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x410))
179#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x414))
180#define REG_MDTOP_PLLMIXED_MDVDSPPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x418))
181#define REG_MDTOP_PLLMIXED_MDBRPPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x430))
182#define REG_MDTOP_PLLMIXED_MDBRPPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x434))
183#define REG_MDTOP_PLLMIXED_MDBRPPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x438))
184//#define REG_MDTOP_PLLMIXED_MDTXPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x440))
185//#define REG_MDTOP_PLLMIXED_MDTXPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x444))
186//#define REG_MDTOP_PLLMIXED_MDTXPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x448))
187#define REG_MDTOP_PLLMIXED_MDBPIPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x450))
188#define REG_MDTOP_PLLMIXED_MDBPIPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x454))
189#define REG_MDTOP_PLLMIXED_MDBPIPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x458))
190
191/* ==========PLL Gear Set========== */
192#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x500))
193#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x504))
194#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x508))
195#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50C))
196#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x540))
197#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x544))
198#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x548))
199#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54C))
200#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C0))
201#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C4))
202#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C8))
203#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5CC))
204//#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x600))
205//#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x604))
206//#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x608))
207//#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x60C))
208
209/* ==========PLL Status========== */
210#define REG_MDTOP_PLLMIXED_MDMCUPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC00))
211#define REG_MDTOP_PLLMIXED_MDVDSPPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC04))
212#define REG_MDTOP_PLLMIXED_MDBRPPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC08))
213//#define REG_MDTOP_PLLMIXED_MDTXPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC0C))
214#define REG_MDTOP_PLLMIXED_MDBPIBPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC10))
215
216#define REG_MDTOP_PLLMIXED_MDMCUPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC14))
217#define REG_MDTOP_PLLMIXED_MDVDSPPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC18))
218#define REG_MDTOP_PLLMIXED_MDBRPPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC1C))
219#define REG_MDTOP_PLLMIXED_MDBPIPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC24))
220
221#define REG_MDTOP_PLLMIXED_MDPLL1_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC40))
222#define REG_MDTOP_PLLMIXED_MDPLL1_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC44))
223
224#define REG_MDTOP_PLLMIXED_FRDDS_OFF_IRQ_MODE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD00))
225#define REG_MDTOP_PLLMIXED_HP_RDY_OFF_IRQ_MODE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD04))
226
227#define REG_MDTOP_PLLMIXED_PLL_DUMMY (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF00))
228#define REG_MDTOP_PLLMIXED_PLL_DUMMY1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF04))
229#define REG_MDTOP_PLLMIXED_PLL_DUMMY2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF08))
230#define REG_MDTOP_PLLMIXED_PLL_DUMMY3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF0C))
231#define REG_MDTOP_PLLMIXED_PLL_STATUS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF10))
232
233
234///////////////////////////////////////////////////////////////////////////////
235/// CLKSW (0xA0150000)
236///////////////////////////////////////////////////////////////////////////////
237#define REG_MDTOP_CLKSW_CODA_VERSION (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x0))
238#define REG_MDTOP_CLKSW_MD_SLEEP_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4))
239#define REG_MDTOP_CLKSW_MDTOPSM_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10))
240#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x14))
241#define REG_MDTOP_CLKSW_CKOFF_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x1C))
242#define REG_MDTOP_CLKSW_CLKON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x20))
243#define REG_MDTOP_CLKSW_CLKSEL_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x24))
244
245/* ==========SDF clock control related========== */
246#define REG_MDTOP_CLKSW_SDF_CK_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x28))
247#define REG_MDTOP_CLKSW_ATB_LOG_SDF_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x2C))
248#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30))
249#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x34))
250
251#define REG_MDTOP_CLKSW_EXTCK_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x3C))
252
253/* ==========FLEXCKGEN_SEL========== */
254#define REG_MDTOP_CLKSW_MDCORE_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40))
255#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x44))
256#define REG_MDTOP_CLKSW_VDSP_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x48))
257#define REG_MDTOP_CLKSW_BRP_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4C))
258#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x50))
259#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x54))
260#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x58))
261#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x5C))
262#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x60))
263#define REG_MDTOP_CLKSW_MML2_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x64))
264#define REG_MDTOP_CLKSW_RXAGC_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x68))
265#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x6C))
266#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x70))
267#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x74))
268#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x78))
269#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x7C))
270
271/* ==========FLEXCKGEN_STS========== */
272#define REG_MDTOP_CLKSW_MDCORE_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA0))
273#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA4))
274#define REG_MDTOP_CLKSW_VDSP_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA8))
275#define REG_MDTOP_CLKSW_BRP_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xAC))
276#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB0))
277#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB4))
278#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB8))
279#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xBC))
280#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC0))
281#define REG_MDTOP_CLKSW_MML2_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC4))
282#define REG_MDTOP_CLKSW_RXAGC_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC8))
283#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xCC))
284#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE0))
285#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE4))
286#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE8))
287#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xEC))
288
289#define REG_MDTOP_CLKSW_CKMUX_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF0))
290#define REG_MDTOP_CLKSW_PLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF4))
291#define REG_MDTOP_CLKSW_DFS_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF8))
292
293/* ==========direct pll request========== */
294#define REG_MDTOP_CLKSW_MDMCU_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x100))
295#define REG_MDTOP_CLKSW_MDBUS_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x104))
296#define REG_MDTOP_CLKSW_VDSP_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x108))
297#define REG_MDTOP_CLKSW_BRP_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10C))
298
299/* ==========Frequency Meter========== */
300#define REG_MDTOP_CLKSW_CKMON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x200))
301#define REG_MDTOP_CLKSW_FREQ_METER_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x204))
302#define REG_MDTOP_CLKSW_FREQ_METER_XTAL_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x208))
303#define REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x20C))
304#define REG_MDTOP_CLKSW_FREQ_METER_H (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x210))
305#define REG_MDTOP_CLKSW_FREQ_METER_L (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x214))
306
307/* ==========DUMMY & STATUS========== */
308#define REG_MDTOP_CLKSW_CLK_DUMMY (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF00))
309#define REG_MDTOP_CLKSW_CLK_STATUS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF04))
310
311
312/*******************************************************************************
313 * Define Macro
314 ******************************************************************************/
315#define MD_PLL_MAGIC_NUM 0x62950000
316#define MD_PLL_MAGIC_26M 0x62950026
317#define MD_PLL_MAGIC_MD 0x62951111
318
319/**
320 * PLL divider definition
321 */
322#if defined(MT6295M) || defined(MT3967) || defined(MT6779)
323 #define MDBPIPLL_DIVIDER (1) /* /2 /3 /4 /5 /6 /7 */
324 #define MDBRPPLL_DIVIDER (6)
325 #define MDVDSPPLL_DIVIDER (4)
326 #define MDMCUPLL_DIVIDER (4)
327#else
328 #error "Unsupported Chip Target in PLL Module"
329#endif
330
331 /*------------------------------------------------------------------------
332 * Purpose: Transfer PCW in xxxPLL_STS to Mhz. This macro is porting from md_dvfs_pll_freq_get(const PLL_SOURCE pll).
333 * Parameters:
334 * Input: pcw: The PCW value in xxxPLL_STS.
335 * divier: The divier for this PLL(EX: ICCPLL_DIVIDER, IMCPLL_DIVIDER...).
336 * Output: None.
337 * returns : Mhz.
338 * Note : This macr is only used to transfer pcw in xxxPLL_STS to Mhz.
339 * You should not used this macro to transfer pcw in xxxPLL_CTL0 to Mhz due to the meaning is different.
340 * (PCW in xxxPLL_STS is bit [21:7] of xxxPLL_CTL0.)
341 *------------------------------------------------------------------------
342 */
343#define PLLMIXED_PLL_STS_SDM_PCW_TO_MHZ(pcw, divier) ((((pcw) * 26) / (1 << 7)) / divier)
344
345/*******************************************************************************
346 * ENUM
347 ******************************************************************************/
348// frequency meter index list (debug only)
349typedef enum {
350 PLL_FM_SOURCE_START = 0x4,
351 PLL_FM_MDBPI_PLL_D4 = 0x4,
352 PLL_FM_MDBPI_PLL_D6 = 0x5,
353 PLL_FM_MDSYS_MML2_CLOCK = 0x6,
354 PLL_FM_FESYS_RXAGC_CLOCK = 0x7,
355 PLL_FM_MDRXSYS_DFESYNC_CLOCK = 0x8,
356 PLL_FM_FESYS_F208M_CLOCK = 0x9,
357 PLL_FM_TRACE_MON_CLOCK = 0xA,
358 PLL_FM_MDSYS_208M_CLOCK = 0xB,
359 PLL_FM_MDRXSYS_RAKE_CLOCK = 0xC,
360 PLL_FM_MDRXSYS_BRP_CLOCK = 0xD,
361 PLL_FM_MDRXSYS_VDSP_CLOCK = 0xE,
362 PLL_FM_MDTOP_LOG_ATB_CLOCK = 0xF,
363 PLL_FM_FESYS_CSYS_CLOCK = 0x10,
364// PLL_FM_FESYS_TXSYS_CLOCK = 0x11,
365 PLL_FM_FESYS_BSI_CLOCK = 0x12,
366 PLL_FM_MDSYS_MDCORE_CLOCK = 0x13,
367 PLL_FM_MDSYS_BUS2X_NODCM_CLOCK = 0x14,
368 PLL_FM_MDSYS_BUS2X_CLOCK = 0x15,
369 PLL_FM_MDTOP_DBG_CLOCK = 0x16,
370 PLL_FM_MDTOP_F32K_CLOCK = 0x17,
371 PLL_FM_AD_MDBPI_PLL_D7 = 0x18, /* AD means "analog to digital" */
372 PLL_FM_AD_MDBPI_PLL_D5 = 0x19,
373 PLL_FM_AD_MDBPI_PLL_D4 = 0x1A,
374 PLL_FM_AD_MDBPI_PLL_D3 = 0x1B,
375 PLL_FM_AD_MDBPI_PLL_D2 = 0x1C,
376 PLL_FM_AD_MDBRP_PLL = 0x1D,
377 PLL_FM_AD_MDVDSP_PLL = 0x1E,
378 PLL_FM_AD_MDMCU_PLL = 0x1F,
379 PLL_FM_SOURCE_END = 0x1F
380} PLL_FM_SOURCE;
381
382typedef enum {
383 CLKSW_SDF_SRC_BPIPLL_DIV8 = 0,
384 CLKSW_SDF_SRC_BPIPLL_DIV4 = 1,
385 CLKSW_SDF_SRC_BPIPLL = 2,
386 CLKSW_SDF_SRC_BPIPLL_DIV2 = 3,
387 /*CLKSW_SDF_SRC_USB_PhyLink = 4,*/ /* HW didn't support. */
388 CLKSW_SDF_SRC_26M,
389 CLKSW_SDF_SRC_END
390} PLL_CLKSW_SDF_SRC;
391
392/* Below for debugging */
393
394#define PLL_FM_NUM 30 /* Note: This number should also sync to EE owner. */
395typedef struct {
396 kal_uint32 MDBPI_PLL_D4; /* 0 */
397 kal_uint32 MDBPI_PLL_D6;
398 kal_uint32 MDSYS_MML2_CLOCK;
399 kal_uint32 FESYS_RXAGC_CLOCK;
400 kal_uint32 MDRXSYS_DFESYNC_CLOCK;
401 kal_uint32 FESYS_F208M_CLOCK; /* 5 */
402 kal_uint32 TRACE_MON_CLOCK;
403 kal_uint32 MDSYS_208M_CLOCK;
404 kal_uint32 MDRXSYS_RAKE_CLOCK;
405 kal_uint32 MDRXSYS_BRP_CLOCK;
406 kal_uint32 MDRXSYS_VDSP_CLOCK; /* 10 */
407 kal_uint32 MDTOP_LOG_ATB_CLOCK;
408 kal_uint32 FESYS_CSYS_CLOCK;
409 kal_uint32 FESYS_BSI_CLOCK;
410 kal_uint32 MDSYS_MDCORE_CLOCK;
411 kal_uint32 MDSYS_BUS2X_NODCM_CLOCK; /* 15 */
412 kal_uint32 MDSYS_BUS2X_CLOCK;
413 kal_uint32 MDTOP_DBG_CLOCK;
414 kal_uint32 AD_MDBPI_PLL_D7;
415 kal_uint32 AD_MDBPI_PLL_D5;
416 kal_uint32 AD_MDBPI_PLL_D4; /* 20 */
417 kal_uint32 AD_MDBPI_PLL_D3;
418 kal_uint32 AD_MDBPI_PLL_D2;
419 kal_uint32 AD_MDBRP_PLL;
420 kal_uint32 AD_MDVDSP_PLL;
421 kal_uint32 AD_MDMCU_PLL; /* 25 */
422/* below no use */
423 kal_uint32 NULL_26;
424 kal_uint32 NULL_27;
425 kal_uint32 NULL_28;
426 kal_uint32 NULL_29;
427} PLL_CLK_INFO;
428
429extern PLL_CLK_INFO g_pll_info;
430extern const char PLL_FM_clock[PLL_FM_NUM][32];
431
432/* Above for debugging */
433
434/*******************************************************************************
435 * Include header files
436 ******************************************************************************/
437extern void PLL_MD_Pll_Init(void);
438extern void PLL_Set_CLK_To_26M(void);
439
440extern void PLL_exception_dump(void);
441extern kal_uint32 PLL_FrequencyMeter_GetFreq(PLL_FM_SOURCE index);
442
443/* For SDF user in driver/sib_drv/sdf/src/md95/drv_sdf_95.c */
444extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Get();
445extern kal_bool PLL_CLKSW_SDF_SRC_CKSEL_Set(PLL_CLKSW_SDF_SRC src_ck);
446
447#endif /* !__PLL_MT6295_H__ */
448