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192.168.1.100 / T800_MD / b0f5b85a5b9d69cbfa1dd990d559a4a9c7d8f2a6 / . / mcu / interface / driver / storage / flash_sf.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2007
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*******************************************************************************
37 *
38 * Filename:
39 * ---------
40 * flash_mtd.h
41 *
42 * Project:
43 * --------
44 * MAUI
45 *
46 * Description:
47 * ------------
48 * This is a flash MTD driver header file
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *==============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
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167 *
168 *------------------------------------------------------------------------------
169 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
170 *==============================================================================
171 *******************************************************************************/
172
173#ifndef _FLASH_SF_H
174#define _FLASH_SF_H
175
176#ifdef __SF_DVT__
177#include "flash_mtd_sf_dvt.h"
178#else
179#include "kal_general_types.h"
180#endif
181#include "sfi_hw.h"
182
183/*-------------------------------------------------------
184 * Serial Flash Device Parameters
185 *-------------------------------------------------------*/
186
187// Parameters
188#define SF_MAX_PAGE_PROG_SIZE (256)
189#define SF_ADDRESS_MASK (0x07FFFFFF)
190
191typedef enum {
192 SF_SR_BUSY = 0
193 ,SF_SR_WEL
194 ,SF_SR_WSE
195 ,SF_SR_WSP
196 ,SF_SR_BP
197 ,SF_SR_SRWD
198 ,SF_SR_OTPLOCK
199 ,SF_SR_FAIL
200 ,SF_SR_COUNT // Number of SR map entries
201} SF_Status_Enum;
202
203typedef enum {
204 SF_SST_SR_WEL = 0x02 // Write Enable Latch
205 ,SF_SST_SR_WSE = 0x04 // Write Suspend Erase Status
206 ,SF_SST_SR_WSP = 0x08 // Write Suspend Program Status
207 ,SF_SST_SR_WPLD = 0x10 // Write Protection Lockdown Status (Resets to 0 after a power cycle)
208 ,SF_SST_SR_SEC = 0x20 // Security ID status (Once set by Lock Security ID (0x85h) it can not be reset)
209 ,SF_SST_SR_BUSY = 0x80 // Write operation status (Write In Progress Bit)
210 ,SF_SST_SR_ALL = 0xFF
211} SF_SST_Status_Indication_Enum;
212
213typedef enum {
214 SF_MXIC_SR_BUSY = 0x01 // Write operation status (Write In Progress Bit)
215 ,SF_MXIC_SR_WEL = 0x02 // Write Enable Latch
216 ,SF_MXIC_SR_WSE = 0x08 // Write Suspend Erase Status (in security register)
217 ,SF_MXIC_SR_WSP = 0x04 // Write Suspend Program Status (in security register)
218 ,SF_MXIC_SR_BP = 0x3C // Block protection (MXIC only)
219 ,SF_MXIC_SR_SRWD = 0x80 // Status register write disable (MXIC only)
220 ,SF_MXIC_SR_ALL = 0xFF
221} SF_MXIC_Status_Indication_Enum;
222
223typedef enum {
224 SF_MXIC_SSR_OTP = 0x01
225 ,SF_MXIC_SSR_LDSO = 0x02
226 ,SF_MXIC_SSR_WSP = 0x04
227 ,SF_MXIC_SSR_WSE = 0x08
228 ,SF_MXIC_SSR_PFAIL = 0x20
229 ,SF_MXIC_SSR_EFAIL = 0x40
230 ,SF_MXIC_SSR_WPSEL = 0x80
231} SF_MXIC_Security_Indication_Enum;
232
233typedef enum {
234 SF_EON_SSR_WSE = 0x04
235 ,SF_EON_SSR_WSP = 0x08
236} SF_EON_Suspend_Indication_Enum;
237
238typedef enum {
239 SF_WINBOND_SSR_SUS = 0x80
240 ,SF_WINBOND_SSR_OTP = 0x3C //Security register lock bits (LB0, LB1, LB2, LB3)
241} SF_WINBOND_Suspend_Indication_Enum;
242
243typedef enum {
244 SF_NUMONYX_SSR_WSP = 0x04
245 ,SF_NUMONYX_SSR_WSE = 0x40
246} SF_NUMONYX_Suspend_Indication_Enum;
247
248typedef enum {
249 SF_UNDEF = 0
250 ,SPI = 1
251 ,SPIQ = 2
252 ,QPI = 3
253} SF_MODE_Enum;
254
255typedef kal_uint8 SF_Status;
256
257/*-------------------------------------------------------
258 * Serial Flash Device Commands
259 *-------------------------------------------------------*/
260
261// Serial Flash commands (General for SPI)
262#define SF_CMD_WRITE_SR (0x01)
263#define SF_CMD_PAGE_PROG (0x02)
264#define SF_CMD_READ (0x03)
265#define SF_CMD_NORMAL_READ (0x00030000) // for direct mode usage
266#define SF_CMD_READ_SR (0x05)
267#define SF_CMD_WREN (0x06)
268#define SF_CMD_FAST_READ (0x000B0000) // for direct mode usage
269#define SF_CMD_RESUME (0x30)
270#define SF_CMD_WBPR (0x42)
271#define SF_CMD_RSTEN (0x66)
272#define SF_CMD_RBPR (0x72)
273#define SF_CMD_RST (0x99)
274#define SF_CMD_SUSPEND (0xB0)
275#define SF_CMD_ERASE_CHIP (0xC7)
276#define SF_CMD_ERASE_BLOCK (0xD8)
277#define SF_CMD_ERASE_SMALL_BLOCK (0x52)
278#define SF_CMD_ERASE_SECTOR (0x20)
279#define SF_CMD_READ_ID (0x9F)
280
281// Serial Flash commands (General for QPI)
282#define SF_CMD_READ_ID_QPI (0xAF)
283
284// Serial Flash commands (SST specific)
285#define SF_CMD_SST_QPIEN (0x38) // for SST only
286#define SF_CMD_SST_QPIRST (0xFF)
287#define SF_CMD_SST_SET_BURST_LENGTH (0xC0)
288#define SF_CMD_SST_BURST_LENGTH_32_BYTE (0x02)
289#define SF_CMD_SST_FAST_READ (0x0B)
290#define SF_CMD_SST_FAST_READ_WRAP (0x0C)
291#define SF_CMD_SST_READ_SECURITY_ID (0x88) // SST: Read OTP registers
292#define SF_CMD_SST_PROG_SECURITY_ID (0xA5) // SST: Program OTP registers
293#define SF_CMD_SST_LOCK_SECURITY_ID (0x85) // SST: Lock OTP registers
294
295
296// Serial Flash commands (MXIC specific)
297#define SF_CMD_MXIC_QPIEN (0x35)
298#define SF_CMD_MXIC_RSTQPI (0xF5)
299#define SF_CMD_MXIC_READ_SEC_SR (0x2B) // OTP Read status
300#define SF_CMD_MXIC_WRITE_SEC_SR (0x2F) // OTP write status
301#define SF_CMD_MXIC_SET_BURST_LENGTH (0xC0)
302#define SF_CMD_MXIC_BURST_LENGTH_32_BYTE (0x02)
303#define SF_CMD_MXIC_BURST_LENGTH_DISABLE (0x10)
304#define SF_CMD_MXIC_FAST_READ_WRAP (0x0B) // for direct mode usage
305#define SF_CMD_MXIC_FAST_READ_ENH (0xEB) // for direct mode usage
306#define SF_CMD_MXIC_ENTER_SECURED_OTP (0xB1) // Enter OTP Access
307#define SF_CMD_MXIC_EXIT_SECURED_OTP (0xC1) // Exit OTP Access
308
309// Serial Flash commands (EON specific)
310#define SF_CMD_EON_READ_SUSPEND_SR (0x09) // Suspend status register
311
312// Serial Flash commands (WINBOND specific)
313#define SF_CMD_WINBOND_READ_SUSPEND_SR (0x35) // Suspend status register
314#define SF_CMD_WINBOND_SUSPEND (0x75) // Suspend
315#define SF_CMD_WINBOND_RESUME (0x7A) // Resume
316#define SF_CMD_WINBOND_READ_SECURITY_REG (0x48) // Winbond: Read OTP registers
317#define SF_CMD_WINBOND_PROG_SECURITY_REG (0x42) // Winbond: Program OTP registers
318#define SF_CMD_WINBOND_READ_UNIQUE_ID (0x4B) // Read unique ID number (4 dummy bytes)
319
320// Serial Flash commands (NUMONYX specific)
321#define SF_CMD_NUMONYX_READ_FLAG_SR (0x70) // Numonyx: Read flag status register
322#define SF_CMD_NUMONYX_WRITE_FLAG_SR (0x50) // Numonyx: Write flag status register
323#define SF_CMD_NUMONYX_READ_LOCK_SR (0xE8) // Numonyx: Read lock status register
324#define SF_CMD_NUMONYX_WRITE_LOCK_SR (0xE5) // Numonyx: Write lock status register
325#define SF_CMD_NUMONYX_READ_CONFIG_SR (0x85) // Numonyx: Read volatile config status register
326#define SF_CMD_NUMONYX_WRITE_CONFIG_SR (0x81) // Numonyx: Write volatile config status register
327
328// Serial Flash commands (GIGADEVICE specific)
329#define SF_CMD_GIGADEVICE_HPM_ENTER (0xA3000000) // GIGA Device: Enter high performance mode + 3 dummy
330#define SF_CMD_GIGADEVICE_HPM_ENTER_CMD (0xA3) // GIGA Device: Enter high performance mode cmd
331#define SF_CMD_GIGADEVICE_HPM_EXIT (0xAB) // GIGA Device: Exit high performance mode
332
333// Serial flash device characteriscs
334#define SF_WRAP_ENABLE (1) // wrap burst read should be enabled by default
335#define SF_FLASH_ID_LENGTH (3) // The number of bytes for flash ID
336
337
338
339/*-------------------------------------------------------
340 * Serial Flash Common APIs
341 * API Body is in "flash_mtd_sf_common.c"
342 *-------------------------------------------------------*/
343extern void SFI_BlankCheck(void *MTDData, kal_uint32 BlockIndex);
344extern void SFI_MacEnable(void);
345extern void SFI_MacWaitReady(void);
346extern kal_uint32 SFI_ReverseByteOrder(kal_uint32 num);
347extern void SFI_ReadDeviceID(kal_uint8 *id, kal_uint8 cmd);
348extern void SFI_ReadDeviceID_SPI(kal_uint8 *id);
349// Device Command functions
350extern void SFI_Dev_Command(const kal_uint32 cmd);
351extern void SFI_Dev_CommandAddress(const kal_uint8 cmd, const kal_uint32 address, const kal_uint32 address_bytes);
352extern void SFI_Dev_Command_List(const kal_uint8 *cmdlist);
353extern void SFI_Dev_Command_Ext(const kal_uint8 *cmd, kal_uint8 *data, const kal_uint16 outl, const kal_uint16 inl);
354extern kal_bool SFI_Dev_SupportUpHopping(void);
355extern kal_bool SFI_Dev_IsModemTimingRecoveryRequired(void);
356extern void SFI_Dev_SupportDelayResume(kal_bool flag);
357// GPRAM access functions
358extern void SFI_GPRAM_Write(kal_uint32 gpram_offset, void* buff, kal_int32 length);
359extern kal_uint32 SFI_GPRAM_Write_C1A3(const kal_uint32 cmd, const kal_uint32 address);
360extern kal_uint32 SFI_GPRAM_Write_C1A4(const kal_uint32 cmd, const kal_uint32 address, kal_uint8 **p_data, kal_uint32 *length);
361
362#endif /* _FLASH_SF_H */
363