Blame - mcu/interface/l1/cl1/common/HW/cphc2krxdfefcimm.h - T800_MD

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2022-11-30 14:33:01 +0800

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/*****************************************************************************

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* Copyright Statement:

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* --------------------

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* This software is protected by Copyright and the information contained

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* herein is confidential. The software may not be copied and the information

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* contained herein may not be used or disclosed except with the written

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*

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* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES

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* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")

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* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON

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* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,

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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF

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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.

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* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE

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* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR

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* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH

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* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO

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* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S

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* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.

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*

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* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE

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* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,

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* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,

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* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO

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* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.

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*

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* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE

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* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF

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* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND

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* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER

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* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).

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*

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*****************************************************************************/

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#ifndef _CPH_C2K_RXDFE_FCIMM_H_

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#define _CPH_C2K_RXDFE_FCIMM_H_

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typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */

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typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */

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typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */

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typedef volatile unsigned short APBDATA; /* APB data is 16 bits */

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typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */

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typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */

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typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */

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typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */

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typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */

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#define RXDFE_FC_IMM_REG_BASE (0xA70C0000)

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#define RXDFE_FC_IMM_end (RXDFE_FC_IMM_REG_BASE + 0xFFFC + 1*4)

#define RXDFE_FC_DATE ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8000))

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#define RXDFE_FC_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8004))

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#define RXDFE_FC_MIXED_IF_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8008))

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#define RXDFE_FC_TEST_IN_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x800C))

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#define RXDFE_FC_TEST_IN_STEP_SIZE ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8010))

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#define RXDFE_FC_TEST_IN_STEP_INIT ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8014))

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#define RXDFE_FC_TEST_IN_CON_IQ ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8018))

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#define RXDFE_FC_TEST_IN_DC ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x801C))

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#define RXDFE_FC_TEST_MUQ_IN_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8020))

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#define RXDFE_FC_TEST_MUQ_IN_STEP ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8024))

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#define RXDFE_FC_TEST_MUQ_IN_DC ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8028))

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#define RXDFE_FC_TEST_OUT_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x802C))

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#define RXDFE_FC_TEST_OUT_ALPHA ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8030))

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#define RXDFE_FC_TEST_FORCE_OFF ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8034))

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#define RXDFE_FC_SW_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8038))

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#define RXDFE_FC_SW_INI_TRG ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x803C))

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8040))

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#define RXDFE_FC_TEST_NBIF_INI_I_P0_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8044))

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#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8048))

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x804C))

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#define RXDFE_FC_TEST_NBIF_INI_I_P0_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8050))

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#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8054))

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8058))

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#define RXDFE_FC_TEST_NBIF_INI_I_P1_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x805C))

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#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8060))

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8064))

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#define RXDFE_FC_TEST_NBIF_INI_I_P1_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8068))

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#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x806C))

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#define RXDFE_FC_TEST_NCO_INI_PH_C0_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8070))

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#define RXDFE_FC_TEST_NCO_INI_PH_C0_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8074))

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#define RXDFE_FC_TEST_NCO_INI_PH_C1_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8078))

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#define RXDFE_FC_TEST_NCO_INI_PH_C1_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x807C))

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#define RXDFE_FC_MS_WB_LPF_0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8800))

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#define RXDFE_FC_MS_WB_LPF_1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8804))

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#define RXDFE_FC_INFO_AGCIF_REG(n) ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9000 + (n)*4)) //n is from 0 to 63

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#define RXDFE_FC_INFO_TEST_OUT_DATA_0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9400))

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#define RXDFE_FC_INFO_TEST_OUT_DATA_1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9404))

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#define RXDFE_FC_INFO_CRC32_OUT ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9408))

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#define RXDFE_FC_INFO_ALPHA_OUT ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x940C))

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_ADC_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9410))

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9414))

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9418))

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_NCO_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x941C))

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_CS_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9420))

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_INI_TRG ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9424))

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_INI_TRG ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9428))

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#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x942C))

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#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9430))

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#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9434))

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#define RXDFE_FC_FPGA ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0xF000))

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#define RXDFE_FC_RESERVED ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0xFFFC))

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#define RXDFE_FC_DATE_RXDFE_FC_DATE_LSB (0)

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#define RXDFE_FC_DATE_RXDFE_FC_DATE_WIDTH (32)

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#define RXDFE_FC_DATE_RXDFE_FC_DATE_MASK (0xFFFFFFFF)

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#define RXDFE_FC_CON_CONFIG_SRC_SEL_LSB (0)

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#define RXDFE_FC_CON_CONFIG_SRC_SEL_WIDTH (1)

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#define RXDFE_FC_CON_CONFIG_SRC_SEL_MASK (0x00000001)

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#define RXDFE_FC_CON_CONFIG_SRC_SEL_BIT (0x00000001)

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#define RXDFE_FC_MIXED_IF_CON_MIXED_IF_RPTR_INI_LSB (0)

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#define RXDFE_FC_MIXED_IF_CON_MIXED_IF_RPTR_INI_WIDTH (3)

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#define RXDFE_FC_MIXED_IF_CON_MIXED_IF_RPTR_INI_MASK (0x00000007)

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#define RXDFE_FC_TEST_IN_CON_TEST_IN_EN_LSB (31)

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#define RXDFE_FC_TEST_IN_CON_TEST_IN_EN_WIDTH (1)

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#define RXDFE_FC_TEST_IN_CON_TEST_IN_EN_MASK (0x80000000)

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#define RXDFE_FC_TEST_IN_CON_TEST_IN_EN_BIT (0x80000000)

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#define RXDFE_FC_TEST_IN_CON_TEST_IN_WIN_LSB (8)

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#define RXDFE_FC_TEST_IN_CON_TEST_IN_WIN_WIDTH (4)

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#define RXDFE_FC_TEST_IN_CON_TEST_IN_WIN_MASK (0x00000F00)

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#define RXDFE_FC_TEST_IN_CON_TEST_IN_RATE_LSB (4)

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#define RXDFE_FC_TEST_IN_CON_TEST_IN_RATE_WIDTH (4)

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#define RXDFE_FC_TEST_IN_CON_TEST_IN_RATE_MASK (0x000000F0)

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#define RXDFE_FC_TEST_IN_CON_TEST_P_IN_EN_LSB (0)

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#define RXDFE_FC_TEST_IN_CON_TEST_P_IN_EN_WIDTH (2)

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#define RXDFE_FC_TEST_IN_CON_TEST_P_IN_EN_MASK (0x00000003)

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#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_Q_STEP_SIZE_LSB (16)

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#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_Q_STEP_SIZE_WIDTH (10)

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#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_Q_STEP_SIZE_MASK (0x03FF0000)

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#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_I_STEP_SIZE_LSB (0)

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#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_I_STEP_SIZE_WIDTH (10)

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#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_I_STEP_SIZE_MASK (0x000003FF)

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#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_Q_STEP_INIT_LSB (16)

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#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_Q_STEP_INIT_WIDTH (10)

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#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_Q_STEP_INIT_MASK (0x03FF0000)

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#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_I_STEP_INIT_LSB (0)

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#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_I_STEP_INIT_WIDTH (10)

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#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_I_STEP_INIT_MASK (0x000003FF)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SCALE_LSB (24)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SCALE_WIDTH (4)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SCALE_MASK (0x0F000000)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_INV_LSB (20)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_INV_WIDTH (1)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_INV_MASK (0x00100000)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_INV_BIT (0x00100000)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SEL_LSB (16)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SEL_WIDTH (2)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SEL_MASK (0x00030000)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SCALE_LSB (8)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SCALE_WIDTH (4)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SCALE_MASK (0x00000F00)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_INV_LSB (4)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_INV_WIDTH (1)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_INV_MASK (0x00000010)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_INV_BIT (0x00000010)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SEL_LSB (0)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SEL_WIDTH (2)

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#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SEL_MASK (0x00000003)

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#define RXDFE_FC_TEST_IN_DC_TEST_IN_Q_DC_LSB (16)

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#define RXDFE_FC_TEST_IN_DC_TEST_IN_Q_DC_WIDTH (15)

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#define RXDFE_FC_TEST_IN_DC_TEST_IN_Q_DC_MASK (0x7FFF0000)

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#define RXDFE_FC_TEST_IN_DC_TEST_IN_I_DC_LSB (0)

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#define RXDFE_FC_TEST_IN_DC_TEST_IN_I_DC_WIDTH (15)

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#define RXDFE_FC_TEST_IN_DC_TEST_IN_I_DC_MASK (0x00007FFF)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_EN_LSB (31)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_EN_WIDTH (1)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_EN_MASK (0x80000000)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_EN_BIT (0x80000000)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SCALE_LSB (24)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SCALE_WIDTH (4)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SCALE_MASK (0x0F000000)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_INV_LSB (20)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_INV_WIDTH (1)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_INV_MASK (0x00100000)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_INV_BIT (0x00100000)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SEL_LSB (16)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SEL_WIDTH (2)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SEL_MASK (0x00030000)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_WIN_LSB (8)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_WIN_WIDTH (4)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_WIN_MASK (0x00000F00)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_RATE_LSB (4)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_RATE_WIDTH (4)

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#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_RATE_MASK (0x000000F0)

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#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_SIZE_LSB (16)

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#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_SIZE_WIDTH (10)

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#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_SIZE_MASK (0x03FF0000)

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#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_INIT_LSB (0)

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#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_INIT_WIDTH (10)

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#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_INIT_MASK (0x000003FF)

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#define RXDFE_FC_TEST_MUQ_IN_DC_TEST_MUQ_IN_DC_LSB (0)

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#define RXDFE_FC_TEST_MUQ_IN_DC_TEST_MUQ_IN_DC_WIDTH (15)

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#define RXDFE_FC_TEST_MUQ_IN_DC_TEST_MUQ_IN_DC_MASK (0x00007FFF)

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#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_EN_LSB (31)

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#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_EN_WIDTH (1)

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#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_EN_MASK (0x80000000)

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#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_EN_BIT (0x80000000)

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#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_WIN_LSB (20)

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#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_WIN_WIDTH (4)

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#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_WIN_MASK (0x00F00000)

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#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_RATE_LSB (16)

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#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_RATE_WIDTH (4)

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#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_RATE_MASK (0x000F0000)

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#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_SEL_LSB (8)

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#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_SEL_WIDTH (5)

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#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_SEL_MASK (0x00001F00)

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#define RXDFE_FC_TEST_OUT_CON_TEST_C_OUT_SEL_LSB (4)

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#define RXDFE_FC_TEST_OUT_CON_TEST_C_OUT_SEL_WIDTH (4)

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#define RXDFE_FC_TEST_OUT_CON_TEST_C_OUT_SEL_MASK (0x000000F0)

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#define RXDFE_FC_TEST_OUT_CON_TEST_P_OUT_SEL_LSB (0)

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#define RXDFE_FC_TEST_OUT_CON_TEST_P_OUT_SEL_WIDTH (4)

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#define RXDFE_FC_TEST_OUT_CON_TEST_P_OUT_SEL_MASK (0x0000000F)

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#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_ABS_LSB (8)

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#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_ABS_WIDTH (1)

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#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_ABS_MASK (0x00000100)

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#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_ABS_BIT (0x00000100)

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#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_LSB (0)

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#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_WIDTH (3)

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#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_MASK (0x00000007)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_ANTI_DROOP_OFF_LSB (4)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_ANTI_DROOP_OFF_WIDTH (1)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_ANTI_DROOP_OFF_MASK (0x00000010)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_ANTI_DROOP_OFF_BIT (0x00000010)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRC_OFF_LSB (3)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRC_OFF_WIDTH (1)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRC_OFF_MASK (0x00000008)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRC_OFF_BIT (0x00000008)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_LWC_DAGC_OFF_LSB (2)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_LWC_DAGC_OFF_WIDTH (1)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_LWC_DAGC_OFF_MASK (0x00000004)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_LWC_DAGC_OFF_BIT (0x00000004)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRRC_PNAAF_OFF_LSB (1)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRRC_PNAAF_OFF_WIDTH (1)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRRC_PNAAF_OFF_MASK (0x00000002)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRRC_PNAAF_OFF_BIT (0x00000002)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_POSTNCO_CIC_OFF_LSB (0)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_POSTNCO_CIC_OFF_WIDTH (1)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_POSTNCO_CIC_OFF_MASK (0x00000001)

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#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_POSTNCO_CIC_OFF_BIT (0x00000001)

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#define RXDFE_FC_SW_WIN_SW_WIN_EN_LSB (31)

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#define RXDFE_FC_SW_WIN_SW_WIN_EN_WIDTH (1)

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#define RXDFE_FC_SW_WIN_SW_WIN_EN_MASK (0x80000000)

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#define RXDFE_FC_SW_WIN_SW_WIN_EN_BIT (0x80000000)

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#define RXDFE_FC_SW_WIN_SW_CS_WIN_LSB (16)

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#define RXDFE_FC_SW_WIN_SW_CS_WIN_WIDTH (4)

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#define RXDFE_FC_SW_WIN_SW_CS_WIN_MASK (0x000F0000)

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#define RXDFE_FC_SW_WIN_SW_NCO_WIN_LSB (12)

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#define RXDFE_FC_SW_WIN_SW_NCO_WIN_WIDTH (4)

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#define RXDFE_FC_SW_WIN_SW_NCO_WIN_MASK (0x0000F000)

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#define RXDFE_FC_SW_WIN_SW_C_WIN_LSB (8)

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#define RXDFE_FC_SW_WIN_SW_C_WIN_WIDTH (4)

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#define RXDFE_FC_SW_WIN_SW_C_WIN_MASK (0x00000F00)

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#define RXDFE_FC_SW_WIN_SW_P_WIN_LSB (4)

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#define RXDFE_FC_SW_WIN_SW_P_WIN_WIDTH (4)

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#define RXDFE_FC_SW_WIN_SW_P_WIN_MASK (0x000000F0)

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#define RXDFE_FC_SW_WIN_SW_ADC_WIN_LSB (0)

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#define RXDFE_FC_SW_WIN_SW_ADC_WIN_WIDTH (4)

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#define RXDFE_FC_SW_WIN_SW_ADC_WIN_MASK (0x0000000F)

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#define RXDFE_FC_SW_INI_TRG_SW_INI_TRG_EN_LSB (31)

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#define RXDFE_FC_SW_INI_TRG_SW_INI_TRG_EN_WIDTH (1)

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#define RXDFE_FC_SW_INI_TRG_SW_INI_TRG_EN_MASK (0x80000000)

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#define RXDFE_FC_SW_INI_TRG_SW_INI_TRG_EN_BIT (0x80000000)

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#define RXDFE_FC_SW_INI_TRG_SW_C_INI_TRG_LSB (4)

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#define RXDFE_FC_SW_INI_TRG_SW_C_INI_TRG_WIDTH (4)

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#define RXDFE_FC_SW_INI_TRG_SW_C_INI_TRG_MASK (0x000000F0)

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#define RXDFE_FC_SW_INI_TRG_SW_P_INI_TRG_LSB (0)

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#define RXDFE_FC_SW_INI_TRG_SW_P_INI_TRG_WIDTH (4)

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#define RXDFE_FC_SW_INI_TRG_SW_P_INI_TRG_MASK (0x0000000F)

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A0_NBIF_INI_SPUR_SEL_P0_A0_LSB (0)

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A0_NBIF_INI_SPUR_SEL_P0_A0_WIDTH (3)

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A0_NBIF_INI_SPUR_SEL_P0_A0_MASK (0x00000007)

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#define RXDFE_FC_TEST_NBIF_INI_I_P0_A0_NBIF_INI_ACCU_I_P0_A0_LSB (0)

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#define RXDFE_FC_TEST_NBIF_INI_I_P0_A0_NBIF_INI_ACCU_I_P0_A0_WIDTH (17)

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#define RXDFE_FC_TEST_NBIF_INI_I_P0_A0_NBIF_INI_ACCU_I_P0_A0_MASK (0x0001FFFF)

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#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A0_NBIF_INI_ACCU_Q_P0_A0_LSB (0)

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#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A0_NBIF_INI_ACCU_Q_P0_A0_WIDTH (17)

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#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A0_NBIF_INI_ACCU_Q_P0_A0_MASK (0x0001FFFF)

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A1_NBIF_INI_SPUR_SEL_P0_A1_LSB (0)

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A1_NBIF_INI_SPUR_SEL_P0_A1_WIDTH (3)

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A1_NBIF_INI_SPUR_SEL_P0_A1_MASK (0x00000007)

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#define RXDFE_FC_TEST_NBIF_INI_I_P0_A1_NBIF_INI_ACCU_I_P0_A1_LSB (0)

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#define RXDFE_FC_TEST_NBIF_INI_I_P0_A1_NBIF_INI_ACCU_I_P0_A1_WIDTH (17)

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#define RXDFE_FC_TEST_NBIF_INI_I_P0_A1_NBIF_INI_ACCU_I_P0_A1_MASK (0x0001FFFF)

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#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A1_NBIF_INI_ACCU_Q_P0_A1_LSB (0)

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#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A1_NBIF_INI_ACCU_Q_P0_A1_WIDTH (17)

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#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A1_NBIF_INI_ACCU_Q_P0_A1_MASK (0x0001FFFF)

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A0_NBIF_INI_SPUR_SEL_P1_A0_LSB (0)

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A0_NBIF_INI_SPUR_SEL_P1_A0_WIDTH (3)

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A0_NBIF_INI_SPUR_SEL_P1_A0_MASK (0x00000007)

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#define RXDFE_FC_TEST_NBIF_INI_I_P1_A0_NBIF_INI_ACCU_I_P1_A0_LSB (0)

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#define RXDFE_FC_TEST_NBIF_INI_I_P1_A0_NBIF_INI_ACCU_I_P1_A0_WIDTH (17)

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#define RXDFE_FC_TEST_NBIF_INI_I_P1_A0_NBIF_INI_ACCU_I_P1_A0_MASK (0x0001FFFF)

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#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A0_NBIF_INI_ACCU_Q_P1_A0_LSB (0)

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#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A0_NBIF_INI_ACCU_Q_P1_A0_WIDTH (17)

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#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A0_NBIF_INI_ACCU_Q_P1_A0_MASK (0x0001FFFF)

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A1_NBIF_INI_SPUR_SEL_P1_A1_LSB (0)

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A1_NBIF_INI_SPUR_SEL_P1_A1_WIDTH (3)

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#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A1_NBIF_INI_SPUR_SEL_P1_A1_MASK (0x00000007)

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#define RXDFE_FC_TEST_NBIF_INI_I_P1_A1_NBIF_INI_ACCU_I_P1_A1_LSB (0)

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#define RXDFE_FC_TEST_NBIF_INI_I_P1_A1_NBIF_INI_ACCU_I_P1_A1_WIDTH (17)

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#define RXDFE_FC_TEST_NBIF_INI_I_P1_A1_NBIF_INI_ACCU_I_P1_A1_MASK (0x0001FFFF)

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#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A1_NBIF_INI_ACCU_Q_P1_A1_LSB (0)

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#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A1_NBIF_INI_ACCU_Q_P1_A1_WIDTH (17)

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#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A1_NBIF_INI_ACCU_Q_P1_A1_MASK (0x0001FFFF)

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#define RXDFE_FC_TEST_NCO_INI_PH_C0_A0_NCO_INI_ACCU_PH_C0_A0_LSB (0)

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#define RXDFE_FC_TEST_NCO_INI_PH_C0_A0_NCO_INI_ACCU_PH_C0_A0_WIDTH (23)

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#define RXDFE_FC_TEST_NCO_INI_PH_C0_A0_NCO_INI_ACCU_PH_C0_A0_MASK (0x007FFFFF)

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#define RXDFE_FC_TEST_NCO_INI_PH_C0_A1_NCO_INI_ACCU_PH_C0_A1_LSB (0)

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#define RXDFE_FC_TEST_NCO_INI_PH_C0_A1_NCO_INI_ACCU_PH_C0_A1_WIDTH (23)

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#define RXDFE_FC_TEST_NCO_INI_PH_C0_A1_NCO_INI_ACCU_PH_C0_A1_MASK (0x007FFFFF)

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#define RXDFE_FC_TEST_NCO_INI_PH_C1_A0_NCO_INI_ACCU_PH_C1_A0_LSB (0)

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#define RXDFE_FC_TEST_NCO_INI_PH_C1_A0_NCO_INI_ACCU_PH_C1_A0_WIDTH (23)

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#define RXDFE_FC_TEST_NCO_INI_PH_C1_A0_NCO_INI_ACCU_PH_C1_A0_MASK (0x007FFFFF)

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#define RXDFE_FC_TEST_NCO_INI_PH_C1_A1_NCO_INI_ACCU_PH_C1_A1_LSB (0)

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#define RXDFE_FC_TEST_NCO_INI_PH_C1_A1_NCO_INI_ACCU_PH_C1_A1_WIDTH (23)

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#define RXDFE_FC_TEST_NCO_INI_PH_C1_A1_NCO_INI_ACCU_PH_C1_A1_MASK (0x007FFFFF)

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#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_3_LSB (24)

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#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_3_WIDTH (7)

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#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_3_MASK (0x7F000000)

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#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_2_LSB (16)

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#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_2_WIDTH (7)

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#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_2_MASK (0x007F0000)

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#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_1_LSB (8)

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#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_1_WIDTH (7)

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#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_1_MASK (0x00007F00)

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#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_0_LSB (0)

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#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_0_WIDTH (7)

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#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_0_MASK (0x0000007F)

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#define RXDFE_FC_MS_WB_LPF_1_WB_COEF_LPF_4_LSB (0)

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#define RXDFE_FC_MS_WB_LPF_1_WB_COEF_LPF_4_WIDTH (7)

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#define RXDFE_FC_MS_WB_LPF_1_WB_COEF_LPF_4_MASK (0x0000007F)

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#define RXDFE_FC_INFO_AGCIF_REG_INFO_AGCIF_REG_LSB (0)

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#define RXDFE_FC_INFO_AGCIF_REG_INFO_AGCIF_REG_WIDTH (32)

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#define RXDFE_FC_INFO_AGCIF_REG_INFO_AGCIF_REG_MASK (0xFFFFFFFF)

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#define RXDFE_FC_INFO_TEST_OUT_DATA_0_INFO_TEST_OUT_DATA_LSB (0)

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#define RXDFE_FC_INFO_TEST_OUT_DATA_0_INFO_TEST_OUT_DATA_WIDTH (32)

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#define RXDFE_FC_INFO_TEST_OUT_DATA_0_INFO_TEST_OUT_DATA_MASK (0xFFFFFFFF)

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#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_Q_LSB (16)

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#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_Q_WIDTH (15)

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#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_Q_MASK (0x7FFF0000)

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#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_I_LSB (0)

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#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_I_WIDTH (15)

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#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_I_MASK (0x00007FFF)

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#define RXDFE_FC_INFO_CRC32_OUT_INFO_CRC32_OUT_LSB (0)

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#define RXDFE_FC_INFO_CRC32_OUT_INFO_CRC32_OUT_WIDTH (32)

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#define RXDFE_FC_INFO_CRC32_OUT_INFO_CRC32_OUT_MASK (0xFFFFFFFF)

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#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_Q_LSB (16)

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#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_Q_WIDTH (15)

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#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_Q_MASK (0x7FFF0000)

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#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_I_LSB (0)

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#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_I_WIDTH (15)

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#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_I_MASK (0x00007FFF)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_ADC_WIN_INFO_EDGE_COUNT_FC_ADC_WIN_LSB (0)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_ADC_WIN_INFO_EDGE_COUNT_FC_ADC_WIN_WIDTH (16)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_ADC_WIN_INFO_EDGE_COUNT_FC_ADC_WIN_MASK (0x0000FFFF)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_WIN_INFO_EDGE_COUNT_FC_P_WIN_LSB (0)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_WIN_INFO_EDGE_COUNT_FC_P_WIN_WIDTH (16)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_WIN_INFO_EDGE_COUNT_FC_P_WIN_MASK (0x0000FFFF)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_WIN_INFO_EDGE_COUNT_FC_C_WIN_LSB (0)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_WIN_INFO_EDGE_COUNT_FC_C_WIN_WIDTH (16)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_WIN_INFO_EDGE_COUNT_FC_C_WIN_MASK (0x0000FFFF)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_NCO_WIN_INFO_EDGE_COUNT_FC_NCO_WIN_LSB (0)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_NCO_WIN_INFO_EDGE_COUNT_FC_NCO_WIN_WIDTH (16)

450

#define RXDFE_FC_INFO_EDGE_COUNT_FC_NCO_WIN_INFO_EDGE_COUNT_FC_NCO_WIN_MASK (0x0000FFFF)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_CS_WIN_INFO_EDGE_COUNT_FC_CS_WIN_LSB (0)

453

#define RXDFE_FC_INFO_EDGE_COUNT_FC_CS_WIN_INFO_EDGE_COUNT_FC_CS_WIN_WIDTH (16)

454

#define RXDFE_FC_INFO_EDGE_COUNT_FC_CS_WIN_INFO_EDGE_COUNT_FC_CS_WIN_MASK (0x0000FFFF)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_INI_TRG_INFO_EDGE_COUNT_FC_P_INI_TRG_LSB (0)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_INI_TRG_INFO_EDGE_COUNT_FC_P_INI_TRG_WIDTH (16)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_INI_TRG_INFO_EDGE_COUNT_FC_P_INI_TRG_MASK (0x0000FFFF)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_INI_TRG_INFO_EDGE_COUNT_FC_C_INI_TRG_LSB (0)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_INI_TRG_INFO_EDGE_COUNT_FC_C_INI_TRG_WIDTH (16)

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#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_INI_TRG_INFO_EDGE_COUNT_FC_C_INI_TRG_MASK (0x0000FFFF)

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#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_AGCDC_FC_REQ_LSB (8)

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#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_AGCDC_FC_REQ_WIDTH (8)

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#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_AGCDC_FC_REQ_MASK (0x0000FF00)

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#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_CQ_CONFIG_VLD_LSB (0)

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#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_CQ_CONFIG_VLD_WIDTH (8)

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#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_CQ_CONFIG_VLD_MASK (0x000000FF)

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#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_TTIMER_MUQ_VLD_LSB (16)

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#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_TTIMER_MUQ_VLD_WIDTH (8)

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#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_TTIMER_MUQ_VLD_MASK (0x00FF0000)

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#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_WTIMER_MUQ_VLD_LSB (8)

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#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_WTIMER_MUQ_VLD_WIDTH (8)

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#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_WTIMER_MUQ_VLD_MASK (0x0000FF00)

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#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_LTIMER_PRE_S_VLD_LSB (0)

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#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_LTIMER_PRE_S_VLD_WIDTH (8)

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#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_LTIMER_PRE_S_VLD_MASK (0x000000FF)

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#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_CDOTIMER_MUQ_VLD_LSB (8)

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#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_CDOTIMER_MUQ_VLD_WIDTH (8)

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#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_CDOTIMER_MUQ_VLD_MASK (0x0000FF00)

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#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_C1XTIMER_MUQ_VLD_LSB (0)

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#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_C1XTIMER_MUQ_VLD_WIDTH (8)

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#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_C1XTIMER_MUQ_VLD_MASK (0x000000FF)

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#define RXDFE_FC_FPGA_FPGA_CTRL_LSB (0)

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#define RXDFE_FC_FPGA_FPGA_CTRL_WIDTH (32)

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#define RXDFE_FC_FPGA_FPGA_CTRL_MASK (0xFFFFFFFF)

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#endif //#ifndef _CPH_C2K_RXDFE_FCIMM_H_