Blame - mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg0.h - T800_MD

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/*****************************************************************************

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* Copyright Statement:

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* --------------------

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* This software is protected by Copyright and the information contained

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* herein is confidential. The software may not be copied and the information

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* contained herein may not be used or disclosed except with the written

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*

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* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES

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* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")

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* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON

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* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,

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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF

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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.

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* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE

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* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR

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* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH

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* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO

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* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S

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* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.

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*

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* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE

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* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,

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* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,

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* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO

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* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.

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*

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* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE

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* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF

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* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND

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* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER

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* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).

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*

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*****************************************************************************/

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#ifndef _CPH_DFESYS_GLBCON_CONFIG0_H_

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#define _CPH_DFESYS_GLBCON_CONFIG0_H_

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typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */

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typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */

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typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */

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typedef volatile unsigned short APBDATA; /* APB data is 16 bits */

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typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */

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typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */

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typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */

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typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */

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typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */

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#define DFESYS_GLB_CON_CONFIG0_REG_BASE (0xA8990000)

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#define DFESYS_GLB_CON_CONFIG0_end (DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0114 + 1*4)

#define DIV_TXBRP ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0000))

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#define DIV_TXCRP ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0004))

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#define DEBUG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x001C))

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#define F208M_DEBUG_BUS ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0024))

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#define F208M_DEBUG_BUS2 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0028))

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#define TXBSRP_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x002c))

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#define RG_SW_ADDR_DATA_VLD ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0034))

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#define TXBSRP_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0038))

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#define TXBSRP_PCK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0040))

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#define TXBSRP_PCK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0044))

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#define TX_SRP_CRP_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0048))

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#define TX_SRP_CRP_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x004c))

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#define TXCRP_PCK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0050))

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#define TXCRP_PCK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0054))

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#define TXCRP_SP_WCRP_APB_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0064))

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#define TXCRP_RG_TAPB_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0068))

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#define TXCRP_RG_C1X_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x006C))

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#define TXCRP_RG_CDO_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0070))

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#define TXCRP_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0074))

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#define TXCRP_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0078))

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#define TXBSRP_MAS_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0080))

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#define TXBSRP_SLV_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0084))

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#define SW_CK_IDLE_DIV ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0090))

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#define MASK_TXBSRP_CK_IDLE_DIV ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0094))

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#define R2TX_SW_DISABLE_HW ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0100))

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#define R2T_RDATA1 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0104))

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#define R2T_RDATA2 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0108))

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#define R2T_RDATA3 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x010c))

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#define R2T_RDATA4 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0110))

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#define R2T_RDATA5 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0114))

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#define DIV_TXBRP_DIV_TXBRP_LSB (0)

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#define DIV_TXBRP_DIV_TXBRP_WIDTH (1)

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#define DIV_TXBRP_DIV_TXBRP_MASK (0x00000001)

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#define DIV_TXBRP_DIV_TXBRP_BIT (0x00000001)

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#define DIV_TXCRP_DIV_TXCRP_LSB (0)

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#define DIV_TXCRP_DIV_TXCRP_WIDTH (2)

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#define DIV_TXCRP_DIV_TXCRP_MASK (0x00000003)

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#define DEBUG_SEL_DEBUG_SEL_3_LSB (24)

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#define DEBUG_SEL_DEBUG_SEL_3_WIDTH (5)

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#define DEBUG_SEL_DEBUG_SEL_3_MASK (0x1F000000)

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#define DEBUG_SEL_DEBUG_SEL_2_LSB (16)

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#define DEBUG_SEL_DEBUG_SEL_2_WIDTH (5)

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#define DEBUG_SEL_DEBUG_SEL_2_MASK (0x001F0000)

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#define DEBUG_SEL_DEBUG_SEL_1_LSB (8)

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#define DEBUG_SEL_DEBUG_SEL_1_WIDTH (5)

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#define DEBUG_SEL_DEBUG_SEL_1_MASK (0x00001F00)

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#define DEBUG_SEL_DEBUG_SEL_0_LSB (0)

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#define DEBUG_SEL_DEBUG_SEL_0_WIDTH (5)

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#define DEBUG_SEL_DEBUG_SEL_0_MASK (0x0000001F)

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#define F208M_DEBUG_BUS_F208M_DEBUG_BUS_LSB (0)

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#define F208M_DEBUG_BUS_F208M_DEBUG_BUS_WIDTH (32)

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#define F208M_DEBUG_BUS_F208M_DEBUG_BUS_MASK (0xFFFFFFFF)

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#define F208M_DEBUG_BUS2_F208M_DEBUG_BUS2_LSB (0)

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#define F208M_DEBUG_BUS2_F208M_DEBUG_BUS2_WIDTH (32)

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#define F208M_DEBUG_BUS2_F208M_DEBUG_BUS2_MASK (0xFFFFFFFF)

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#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_LSB (0)

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#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_WIDTH (1)

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#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_MASK (0x00000001)

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#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_BIT (0x00000001)

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#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_LSB (8)

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#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_WIDTH (11)

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#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_MASK (0x0007FF00)

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#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_LSB (4)

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#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_WIDTH (4)

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#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_MASK (0x000000F0)

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#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_LSB (1)

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#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_WIDTH (3)

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#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_MASK (0x0000000E)

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#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_LSB (0)

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#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_WIDTH (1)

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#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_MASK (0x00000001)

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#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_BIT (0x00000001)

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#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_LSB (16)

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#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_WIDTH (1)

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#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_MASK (0x00010000)

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#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_BIT (0x00010000)

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#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_LSB (1)

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#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_WIDTH (1)

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#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_MASK (0x00000002)

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#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_BIT (0x00000002)

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#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_LSB (0)

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#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_WIDTH (1)

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#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_MASK (0x00000001)

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#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_BIT (0x00000001)

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#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_LSB (0)

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#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_WIDTH (1)

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#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_MASK (0x00000001)

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#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_BIT (0x00000001)

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#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_LSB (0)

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#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_WIDTH (1)

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#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_MASK (0x00000001)

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#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_BIT (0x00000001)

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#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_LSB (0)

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#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_WIDTH (1)

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#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_MASK (0x00000001)

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#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_BIT (0x00000001)

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#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_LSB (0)

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#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_WIDTH (1)

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#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_MASK (0x00000001)

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#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_BIT (0x00000001)

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#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_LSB (0)

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#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_WIDTH (1)

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#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_MASK (0x00000001)

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#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_BIT (0x00000001)

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#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_LSB (0)

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#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_WIDTH (1)

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#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_MASK (0x00000001)

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#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_BIT (0x00000001)

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#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_LSB (0)

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#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_WIDTH (1)

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#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_MASK (0x00000001)

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#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_BIT (0x00000001)

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#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_LSB (0)

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#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_WIDTH (1)

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#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_MASK (0x00000001)

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#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_BIT (0x00000001)

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#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_LSB (0)

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#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_WIDTH (1)

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#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_MASK (0x00000001)

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#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_BIT (0x00000001)

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#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_LSB (0)

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#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_WIDTH (1)

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#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_MASK (0x00000001)

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#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_BIT (0x00000001)

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#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_LSB (0)

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#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_WIDTH (1)

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#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_MASK (0x00000001)

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#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_BIT (0x00000001)

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#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_LSB (0)

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#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_WIDTH (1)

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#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_MASK (0x00000001)

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#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_BIT (0x00000001)

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#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_LSB (0)

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#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_WIDTH (1)

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#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_MASK (0x00000001)

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#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_BIT (0x00000001)

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#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_LSB (0)

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#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_WIDTH (1)

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#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_MASK (0x00000001)

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#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_BIT (0x00000001)

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#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_LSB (0)

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#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_WIDTH (1)

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#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_MASK (0x00000001)

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#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_BIT (0x00000001)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_LSB (3)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_WIDTH (1)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_MASK (0x00000008)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_BIT (0x00000008)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_LSB (2)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_WIDTH (1)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_MASK (0x00000004)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_BIT (0x00000004)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_LSB (1)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_WIDTH (1)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_MASK (0x00000002)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_BIT (0x00000002)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_LSB (0)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_WIDTH (1)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_MASK (0x00000001)

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#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_BIT (0x00000001)

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#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_LSB (0)

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#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_WIDTH (1)

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#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_MASK (0x00000001)

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#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_BIT (0x00000001)

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#define R2T_RDATA1_R2T_RDATA1_LSB (0)

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#define R2T_RDATA1_R2T_RDATA1_WIDTH (32)

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#define R2T_RDATA1_R2T_RDATA1_MASK (0xFFFFFFFF)

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#define R2T_RDATA2_R2T_RDATA2_LSB (0)

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#define R2T_RDATA2_R2T_RDATA2_WIDTH (32)

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#define R2T_RDATA2_R2T_RDATA2_MASK (0xFFFFFFFF)

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#define R2T_RDATA3_R2T_RDATA3_LSB (0)

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#define R2T_RDATA3_R2T_RDATA3_WIDTH (32)

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#define R2T_RDATA3_R2T_RDATA3_MASK (0xFFFFFFFF)

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#define R2T_RDATA4_R2T_RDATA4_LSB (0)

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#define R2T_RDATA4_R2T_RDATA4_WIDTH (32)

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#define R2T_RDATA4_R2T_RDATA4_MASK (0xFFFFFFFF)

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#define R2T_RDATA5_R2T_RDATA5_LSB (0)

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#define R2T_RDATA5_R2T_RDATA5_WIDTH (32)

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#define R2T_RDATA5_R2T_RDATA5_MASK (0xFFFFFFFF)

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#endif //#ifndef _EL1D_REG_ELBRUS_H_