| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2016 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | #ifndef _CPH_RX_DFE_FCCALTC_H_ |
| 36 | #define _CPH_RX_DFE_FCCALTC_H_ |
| 37 | |
| 38 | |
| 39 | typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| 40 | typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| 41 | typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| 42 | typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| 43 | typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| 44 | typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| 45 | typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| 46 | typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| 47 | typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| 48 | |
| 49 | |
| 50 | #define RXDFE_FCCALTC_REG_BASE (0xA70B0000) |
| 51 | |
| 52 | #define RXDFE_FCCALTC_end (RXDFE_FCCALTC_REG_BASE + 0x00000A00 + 1*4) |
| 53 | |
| 54 | |
| 55 | |
| 56 | #define RG_RXDFE_FCCALTC_OFFSET(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000000 + (n)*4)) //n is from 0 to 4 |
| 57 | #define RG_RXDFE_FCCALTC_TQ_SEL(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000200 + (n)*4)) //n is from 0 to 11 |
| 58 | #define RG_RXDFE_FCCALTC_TQ_TRG(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000280 + (n)*4)) //n is from 0 to 11 |
| 59 | #define RG_RXDFE_FCCALTC_TQ_RO(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000300 + (n)*4)) //n is from 0 to 11 |
| 60 | #define RG_RXDFE_FCCALTC_TQ_ALL_RO ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000600)) |
| 61 | #define RG_RXDFE_FCCALTC_LPM_CFG ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000800)) |
| 62 | #define RG_RXDFE_FCCALTC_LPM_RO(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000810 + (n)*4)) //n is from 0 to 1 |
| 63 | #define RG_RXDFE_FCCALTC_LPM_SW_MODE(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000820 + (n)*4)) //n is from 0 to 1 |
| 64 | #define RG_RXDFE_FCCALTC_IRQ ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000A00)) |
| 65 | |
| 66 | |
| 67 | #define RG_RXDFE_FCCALTC_OFFSET_offset_2_LSB (16) |
| 68 | #define RG_RXDFE_FCCALTC_OFFSET_offset_2_WIDTH (8) |
| 69 | #define RG_RXDFE_FCCALTC_OFFSET_offset_2_MASK (0x00FF0000) |
| 70 | |
| 71 | #define RG_RXDFE_FCCALTC_OFFSET_offset_1_LSB (8) |
| 72 | #define RG_RXDFE_FCCALTC_OFFSET_offset_1_WIDTH (8) |
| 73 | #define RG_RXDFE_FCCALTC_OFFSET_offset_1_MASK (0x0000FF00) |
| 74 | |
| 75 | #define RG_RXDFE_FCCALTC_OFFSET_offset_0_LSB (0) |
| 76 | #define RG_RXDFE_FCCALTC_OFFSET_offset_0_WIDTH (8) |
| 77 | #define RG_RXDFE_FCCALTC_OFFSET_offset_0_MASK (0x000000FF) |
| 78 | |
| 79 | #define RG_RXDFE_FCCALTC_TQ_SEL_tq_atimer_sel_LSB (24) |
| 80 | #define RG_RXDFE_FCCALTC_TQ_SEL_tq_atimer_sel_WIDTH (2) |
| 81 | #define RG_RXDFE_FCCALTC_TQ_SEL_tq_atimer_sel_MASK (0x03000000) |
| 82 | |
| 83 | #define RG_RXDFE_FCCALTC_TQ_SEL_tq_stimer_sel_LSB (16) |
| 84 | #define RG_RXDFE_FCCALTC_TQ_SEL_tq_stimer_sel_WIDTH (5) |
| 85 | #define RG_RXDFE_FCCALTC_TQ_SEL_tq_stimer_sel_MASK (0x001F0000) |
| 86 | |
| 87 | #define RG_RXDFE_FCCALTC_TQ_SEL_tq_offset_sel_LSB (8) |
| 88 | #define RG_RXDFE_FCCALTC_TQ_SEL_tq_offset_sel_WIDTH (5) |
| 89 | #define RG_RXDFE_FCCALTC_TQ_SEL_tq_offset_sel_MASK (0x00001F00) |
| 90 | |
| 91 | #define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_LSB (0) |
| 92 | #define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_WIDTH (1) |
| 93 | #define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_MASK (0x00000001) |
| 94 | #define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_BIT (0x00000001) |
| 95 | |
| 96 | #define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_LSB (31) |
| 97 | #define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_WIDTH (1) |
| 98 | #define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_MASK (0x80000000) |
| 99 | #define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_BIT (0x80000000) |
| 100 | |
| 101 | #define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_LSB (30) |
| 102 | #define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_WIDTH (1) |
| 103 | #define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_MASK (0x40000000) |
| 104 | #define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_BIT (0x40000000) |
| 105 | |
| 106 | #define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_LSB (24) |
| 107 | #define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_WIDTH (1) |
| 108 | #define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_MASK (0x01000000) |
| 109 | #define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_BIT (0x01000000) |
| 110 | |
| 111 | #define RG_RXDFE_FCCALTC_TQ_RO_tq_pointer_LSB (0) |
| 112 | #define RG_RXDFE_FCCALTC_TQ_RO_tq_pointer_WIDTH (8) |
| 113 | #define RG_RXDFE_FCCALTC_TQ_RO_tq_pointer_MASK (0x000000FF) |
| 114 | |
| 115 | #define RG_RXDFE_FCCALTC_TQ_ALL_RO_all_tq_fsm_LSB (0) |
| 116 | #define RG_RXDFE_FCCALTC_TQ_ALL_RO_all_tq_fsm_WIDTH (12) |
| 117 | #define RG_RXDFE_FCCALTC_TQ_ALL_RO_all_tq_fsm_MASK (0x00000FFF) |
| 118 | |
| 119 | #define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_LSB (4) |
| 120 | #define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_WIDTH (1) |
| 121 | #define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_MASK (0x00000010) |
| 122 | #define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_BIT (0x00000010) |
| 123 | |
| 124 | #define RG_RXDFE_FCCALTC_LPM_CFG_lpm_fsm_LSB (0) |
| 125 | #define RG_RXDFE_FCCALTC_LPM_CFG_lpm_fsm_WIDTH (4) |
| 126 | #define RG_RXDFE_FCCALTC_LPM_CFG_lpm_fsm_MASK (0x0000000F) |
| 127 | |
| 128 | #define RG_RXDFE_FCCALTC_LPM_RO_lpm_fsm_LSB (0) |
| 129 | #define RG_RXDFE_FCCALTC_LPM_RO_lpm_fsm_WIDTH (4) |
| 130 | #define RG_RXDFE_FCCALTC_LPM_RO_lpm_fsm_MASK (0x0000000F) |
| 131 | |
| 132 | #define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_LSB (16) |
| 133 | #define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_WIDTH (1) |
| 134 | #define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_MASK (0x00010000) |
| 135 | #define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_BIT (0x00010000) |
| 136 | |
| 137 | #define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_LSB (0) |
| 138 | #define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_WIDTH (1) |
| 139 | #define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_MASK (0x00000001) |
| 140 | #define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_BIT (0x00000001) |
| 141 | |
| 142 | #define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_LSB (16) |
| 143 | #define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_WIDTH (1) |
| 144 | #define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_MASK (0x00010000) |
| 145 | #define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_BIT (0x00010000) |
| 146 | |
| 147 | #define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_LSB (0) |
| 148 | #define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_WIDTH (1) |
| 149 | #define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_MASK (0x00000001) |
| 150 | #define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_BIT (0x00000001) |
| 151 | |
| 152 | |
| 153 | #endif //#ifndef _CPH_RX_DFE_FCCALTC_H_ |