rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2016 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | #ifndef _CL1_RCAPI_H_ |
| 37 | #define _CL1_RCAPI_H_ |
| 38 | |
| 39 | /*********************************************************************************** |
| 40 | * |
| 41 | * FILE NAME : cl1rcapi.h |
| 42 | * |
| 43 | * DESCRIPTION : extern RC API |
| 44 | * |
| 45 | * |
| 46 | ************************************************************************************/ |
| 47 | #include "cl1rcreq.h" |
| 48 | |
| 49 | #if defined(__FPGA__) || defined(CL1_RC_DRV_DSP_SLEEP_FLOW_ONLY) |
| 50 | #define CL1_RC_DRV_BOOTUP_TEMP |
| 51 | #endif |
| 52 | |
| 53 | #if defined(MT6739) /* if ZION */ |
| 54 | #define C2K_DVFS_TX_CONTROL |
| 55 | #endif |
| 56 | |
| 57 | typedef enum |
| 58 | { |
| 59 | CL1_RC_SEQ_RAKE_DEACT_NULL, |
| 60 | CL1_RC_SEQ_RAKE_DEACT_WAIT, |
| 61 | CL1_RC_SEQ_RAKE_DEACT_SCHE, |
| 62 | CL1_RC_SEQ_RAKE_DEACT_EXE, |
| 63 | CL1_RC_SEQ_RAKE_DEACT_STAT_NUM |
| 64 | }Cl1RcSeqRakeDeactStateT; |
| 65 | |
| 66 | typedef enum |
| 67 | { |
| 68 | CL1_RC_SEQ_RAKE_DEACT_RCOFF_EVT, |
| 69 | CL1_RC_SEQ_RAKE_DEACT_D2BIFOFF_EVT, |
| 70 | CL1_RC_SEQ_RAKE_DEACT_CLR_EVT, |
| 71 | CL1_RC_SEQ_RAKE_DEACT_EVT_NUM |
| 72 | }Cl1RcSeqRakeDeactEvtT; |
| 73 | |
| 74 | extern void Cl1RcInit(void); |
| 75 | |
| 76 | extern void Cl1RcReqInit(void); |
| 77 | |
| 78 | extern void Cl1ShRcSeqRttPeriodicalTrigger(void); |
| 79 | |
| 80 | extern void Cl1ShRcSeqEvdoPeriodicalTrigger(void); |
| 81 | |
| 82 | #if (defined(__MTK_TARGET__)&&(defined(__MD97__)||defined(__MD97P__))&&defined(CL1_RC_DRV_BOOTUP_TEMP)) || (defined(MT6763)||defined(MT6739)) |
| 83 | extern void Cl1RcdForceAllOn(void); |
| 84 | #endif |
| 85 | |
| 86 | #if defined(__MD93__)||defined(__MD95__) |
| 87 | extern void Cl1RcdTxRcOnNsftMode(void); |
| 88 | #endif |
| 89 | |
| 90 | extern kal_uint8 Cl1RcReqRxOn(Cl1RcReqRxOnT *RxOn); |
| 91 | |
| 92 | extern void Cl1RcReqRxOff(Cl1RcReqRxOffT *RxOff); |
| 93 | |
| 94 | extern kal_uint8 Cl1RcReqTxOn(Cl1RcReqTxOnOffT *TxOn); |
| 95 | |
| 96 | extern void Cl1RcReqTxOff(Cl1RcReqTxOnOffT *TxOff); |
| 97 | |
| 98 | extern void Cl1RcReqSchOff(Cl1RcReqSchOffT *SchOff); |
| 99 | |
| 100 | extern void Cl1RcUtilGetRfOnTime(Cl1RcReqRxOnT *RxOn,SysSFrameTimeT * RfActionTime); |
| 101 | |
| 102 | extern void Cl1ShRcRakeOffTrigger(SysAirInterfaceT Mode); |
| 103 | |
| 104 | extern void Cl1RcdRakeOff(SysAirInterfaceT Mode); |
| 105 | |
| 106 | extern void Cl1RcdHwInit(void); |
| 107 | |
| 108 | extern void Cl1RcdBrpsysDvitReset(SysAirInterfaceT Mode); |
| 109 | |
| 110 | extern void Cl1RcSeqRakeDeactSchedule(SysAirInterfaceT Mode, Cl1RcSeqRakeDeactEvtT Evt); |
| 111 | |
| 112 | extern void Cl1RcdBrpsysTurboReset(SysAirInterfaceT Mode); |
| 113 | |
| 114 | extern void Cl1RcUtilRfOnMergeNotification(SysAirInterfaceT Mode); |
| 115 | |
| 116 | extern void Cl1RcdPartialBypassConf(SysAirInterfaceT Mode, kal_uint32 Conf1, kal_uint32 Conf2, kal_uint32 Conf3); |
| 117 | |
| 118 | extern void Cl1RcReqModemDvfsScenSet(SysAirInterfaceT Mode, Cl1RcReqModemDvfsUsrT Usr, Cl1RcdDvfsScenT Scen); |
| 119 | |
| 120 | extern void Cl1RcReqModemDvfsScenCancel(SysAirInterfaceT Mode, Cl1RcReqModemDvfsUsrT Usr); |
| 121 | |
| 122 | extern void Cl1RcdCssysSramOnOff(SysAirInterfaceT Mode,kal_bool Off); |
| 123 | #endif |
| 124 | |
| 125 | |