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rjw6c1fd8f2022-11-30 14:33:01 +08001/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
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7* permission of MediaTek Inc. (C) 2016
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34*****************************************************************************/
35
36#ifndef _CL1_RCAPI_H_
37#define _CL1_RCAPI_H_
38
39/***********************************************************************************
40*
41* FILE NAME : cl1rcapi.h
42*
43* DESCRIPTION : extern RC API
44*
45*
46************************************************************************************/
47#include "cl1rcreq.h"
48
49#if defined(__FPGA__) || defined(CL1_RC_DRV_DSP_SLEEP_FLOW_ONLY)
50#define CL1_RC_DRV_BOOTUP_TEMP
51#endif
52
53#if defined(MT6739) /* if ZION */
54#define C2K_DVFS_TX_CONTROL
55#endif
56
57typedef enum
58{
59 CL1_RC_SEQ_RAKE_DEACT_NULL,
60 CL1_RC_SEQ_RAKE_DEACT_WAIT,
61 CL1_RC_SEQ_RAKE_DEACT_SCHE,
62 CL1_RC_SEQ_RAKE_DEACT_EXE,
63 CL1_RC_SEQ_RAKE_DEACT_STAT_NUM
64}Cl1RcSeqRakeDeactStateT;
65
66typedef enum
67{
68 CL1_RC_SEQ_RAKE_DEACT_RCOFF_EVT,
69 CL1_RC_SEQ_RAKE_DEACT_D2BIFOFF_EVT,
70 CL1_RC_SEQ_RAKE_DEACT_CLR_EVT,
71 CL1_RC_SEQ_RAKE_DEACT_EVT_NUM
72}Cl1RcSeqRakeDeactEvtT;
73
74extern void Cl1RcInit(void);
75
76extern void Cl1RcReqInit(void);
77
78extern void Cl1ShRcSeqRttPeriodicalTrigger(void);
79
80extern void Cl1ShRcSeqEvdoPeriodicalTrigger(void);
81
82#if (defined(__MTK_TARGET__)&&(defined(__MD97__)||defined(__MD97P__))&&defined(CL1_RC_DRV_BOOTUP_TEMP)) || (defined(MT6763)||defined(MT6739))
83extern void Cl1RcdForceAllOn(void);
84#endif
85
86#if defined(__MD93__)||defined(__MD95__)
87extern void Cl1RcdTxRcOnNsftMode(void);
88#endif
89
90extern kal_uint8 Cl1RcReqRxOn(Cl1RcReqRxOnT *RxOn);
91
92extern void Cl1RcReqRxOff(Cl1RcReqRxOffT *RxOff);
93
94extern kal_uint8 Cl1RcReqTxOn(Cl1RcReqTxOnOffT *TxOn);
95
96extern void Cl1RcReqTxOff(Cl1RcReqTxOnOffT *TxOff);
97
98extern void Cl1RcReqSchOff(Cl1RcReqSchOffT *SchOff);
99
100extern void Cl1RcUtilGetRfOnTime(Cl1RcReqRxOnT *RxOn,SysSFrameTimeT * RfActionTime);
101
102extern void Cl1ShRcRakeOffTrigger(SysAirInterfaceT Mode);
103
104extern void Cl1RcdRakeOff(SysAirInterfaceT Mode);
105
106extern void Cl1RcdHwInit(void);
107
108extern void Cl1RcdBrpsysDvitReset(SysAirInterfaceT Mode);
109
110extern void Cl1RcSeqRakeDeactSchedule(SysAirInterfaceT Mode, Cl1RcSeqRakeDeactEvtT Evt);
111
112extern void Cl1RcdBrpsysTurboReset(SysAirInterfaceT Mode);
113
114extern void Cl1RcUtilRfOnMergeNotification(SysAirInterfaceT Mode);
115
116extern void Cl1RcdPartialBypassConf(SysAirInterfaceT Mode, kal_uint32 Conf1, kal_uint32 Conf2, kal_uint32 Conf3);
117
118extern void Cl1RcReqModemDvfsScenSet(SysAirInterfaceT Mode, Cl1RcReqModemDvfsUsrT Usr, Cl1RcdDvfsScenT Scen);
119
120extern void Cl1RcReqModemDvfsScenCancel(SysAirInterfaceT Mode, Cl1RcReqModemDvfsUsrT Usr);
121
122extern void Cl1RcdCssysSramOnOff(SysAirInterfaceT Mode,kal_bool Off);
123#endif
124
125