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192.168.1.100 / T800_MD / b0f5b85a5b9d69cbfa1dd990d559a4a9c7d8f2a6 / . / mcu / interface / l1 / cl1 / common / cph1xsch.h
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2016
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
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13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
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15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
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19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
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22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
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24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
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28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37
38 FILE NAME: Cph1xsch.h
39
40 DESCRIPTION:
41
42 This include file provides searcher constants.
43
44*****************************************************************************/
45#ifndef _CPH1XSCH_H_
46#define _CPH1XSCH_H_
47
48#include "kal_general_types.h"
49
50#if (defined(MTK_C2K_COSIM))||(defined(MTK_C2K_L1_TST))
51#define SR1X_MAX_PAGES 12
52#else
53#define SR1X_MAX_PAGES 11
54#endif
55/* default register assignment, TBD */
56#define DEFAULT_CTL_REG 0
57#define DEFAULT_CORR_REG 0
58#define DEFAULT_NCOH_REG 0
59#define DEFAULT_AUXPILOT_REG 0
60#define DEFAULT_WIN_REG 0
61#define DEFAULT_D1TH_REG 0
62#define DEFAULT_TEST_REG 0
63#define DEFAULT_OFFSET_REG 0
64
65#define DWELL_LEN_MASK 0x3F
66#define DWELL2_CORR_SHIFT 6
67#define DWELL2_CNT_SHIFT 6
68#define SR1X_SINGLE_BUF_SZ 1024
69#define SR1X_DOUBLE_BUF_SZ 2048
70
71/* searcher constant */
72#define FULL_PN_CIR 32767 /* 2^15 - 1 */
73#define FULL_PN_CIR_2X 0 /* 2^16 = 0x10000 = (unit 16) 0 */
74#define SR1X_MAX_HITS 10
75#define DEFAULT_WIN_SIZ 32
76#define SR1X_SEARCHQ_SIZE 32
77#define SR1X_PN_BUF_SIZ 32
78#define SR1X_PN_BUF_SIZ_HALF (SR1X_PN_BUF_SIZ >> 1)
79#define SR1X_CIAQ_WIN_SIZE 1
80#define SR1X_FFT_SIZE 128
81#define SR1X_FFT_BIN_WTH_HZ 600
82
83/* Aflt Constant */
84#define SR1X_AFLT_SPY_PWR_BUF_SZ 55 // 1 + 3*10 + 3*8
85#define SR1X_AFLT_DBG_BUF_SZ (SYS_MAX_AFLT_LIST_PILOTS*9)
86#define SR1X_AFLT_1CHIP_UNIT_IN_TC16 16
87#define SR1X_AFLT_1CHIP_MASK_IN_TC16 (1 * SR1X_AFLT_1CHIP_UNIT_IN_TC16 - 1)
88#define SR1X_AFLT_2CHIP_MASK_IN_TC16 (2 * SR1X_AFLT_1CHIP_UNIT_IN_TC16 - 1)
89#define SR1X_AFLT_3CHIP_MASK_IN_TC16 (3 * SR1X_AFLT_1CHIP_UNIT_IN_TC16 - 1)
90
91/* Different or Candidate Frequency Search */
92#define SR1X_CFS_SRCH_VALID_MSK 0xC000
93#define SR1X_CFS_RSLT_DBG_SZ 15
94
95/** Input buffer test address, i.e. offset relative to input buffer start: valid value is 0~2047. */
96#define INBUF_TST_ADDR 0x0000
97
98typedef enum
99{
100 SCH_INPUT_SEL_C0A0,
101 SCH_INPUT_SEL_C0A1,
102 SCH_INPUT_SEL_C1A0,
103 SCH_INPUT_SEL_C1A1
104}SchInputSelT;
105
106typedef struct
107{
108 SchInputSelT SchInputSel;
109 kal_uint32 SchCtrlRegVal;
110 kal_uint32 SchCorrRegVal;
111 kal_uint32 SchNCohRegVal;
112 kal_uint32 SchAuxPilotRegVal;
113 kal_uint32 SchD1ThreshRegVal;
114 kal_uint32 SchAuxOffRegVal;
115 kal_uint32 SchTestRegVal;
116 kal_uint32 SchTest2RegVal;
117 kal_uint32 SchCtrl2RegVal;
118 kal_uint32 SchStatusRegVal;
119 kal_uint32 SchThresRegVal;
120 kal_uint32 SchInBufTstCtrlRegVal;
121 kal_uint32 SchInBufTstDataRegVal;
122}Cph1xSchHwCfgT;
123
124typedef struct
125{
126 kal_uint32 SchStartPnOffset;
127 kal_uint32 SchWinSize;
128}Cph1xSchWinCfgT;
129
130extern void Cph1xSchHwInit(kal_bool InitAll);
131extern void Cph1xSchHwReset(kal_bool ResetAll);
132extern void Cph1xSchHwCfg(Cph1xSchHwCfgT *AdsPtr);
133extern void Cph1xSchWinCfg(kal_uint32 PnNum, Cph1xSchWinCfgT *AdsPtr);
134extern void Cph1xSchFakeCfg(kal_bool Start);
135extern void Cph1xSchDlyStartEnable(kal_bool Enable);
136extern void Cph1xSchDlyStartTimeSet(kal_uint32 SysTime);
137extern kal_uint8 Cph1xSchObfStateGet(void);
138extern kal_uint8 Cph1xSchDoneStateGet(void);
139extern void Cph1xSchDoneStateClr(void);
140extern void Cph1xSchObfStateClr(void);
141extern kal_uint8 Cph1xSchMemShareBitGet(void);
142extern kal_bool Cph1xSchClockStateGet(void);
143extern void Cph1xSchRsltRead(kal_bool InitialAcq,
144 kal_bool UseSorter,
145 kal_bool TimeDomain,
146 kal_uint8 SchMode,
147 kal_uint16 *Buf1Ptr,
148 kal_uint16 *Buf2Ptr);
149extern void Cph1xSchIQDumpCfg(kal_uint16 StartOffset);
150extern void Cph1xSchIQDump(kal_uint16 *BufPtr, kal_uint16 IQLength);
151extern void Cph1xSchInputBufClr(void);
152extern void Cph1xSchInputBufDump(void);
153extern void Cph1xSchHwStallRegDump(void);
154extern void Cph1xSchRegValDump(void);
155#endif