| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /******************************************************************************* |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * l1cal.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * Maui_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * The structure definition of L1 calibration data |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * ------- |
| 54 | * |
| 55 | *============================================================================== |
| 56 | * HISTORY |
| 57 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
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| 539 | *------------------------------------------------------------------------------ |
| 540 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 541 | *============================================================================== |
| 542 | *******************************************************************************/ |
| 543 | #ifndef L1CAL_H |
| 544 | #define L1CAL_H |
| 545 | |
| 546 | #include "kal_general_types.h" |
| 547 | #include "l1_option.h" |
| 548 | #include "l1_types_public.h" |
| 549 | #if MD_DRV_IS_2G_MIPI_SUPPORT |
| 550 | #include "l1d_mipi_data_common.h" |
| 551 | #endif |
| 552 | #include "l1d_rf_data_common.h" |
| 553 | #include "l1_public_defs.h" |
| 554 | #if defined(__TAS_SUPPORT__) |
| 555 | #include "l1_types_public.h" |
| 556 | #if (defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)) |
| 557 | #include "l1d_rf_utas_typedef.h" |
| 558 | #else |
| 559 | #include "l1d_rf_tas_typedef.h" |
| 560 | #endif |
| 561 | #endif |
| 562 | #if MD_DRV_IS_TX_POWER_OFFSET_SUPPORT |
| 563 | #include "mmrf_cc_global.h" |
| 564 | #endif |
| 565 | |
| 566 | #if IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT //defined(__DYNAMIC_ANTENNA_TUNING__) |
| 567 | #include "l1_types_public.h" |
| 568 | #include "l1d_rf_dat_typedef.h" |
| 569 | #endif//__DYNAMIC_ANTENNA_TUNING__ |
| 570 | /* ------------------------------------------------------------------------- */ |
| 571 | |
| 572 | unsigned long L1D_RF_GetID( void ); |
| 573 | void L1D_RF_SetImmediateBSI( unsigned long bsidata ); |
| 574 | void L1D_RF_GetImmediateBSI( unsigned long bsi_addr, unsigned long *bsi_data ); |
| 575 | void L1D_RF_PowerOn( void ); |
| 576 | void L1D_RF_PowerOff( void ); |
| 577 | |
| 578 | /* ------------------------------------------------------------------------- */ |
| 579 | |
| 580 | typedef struct |
| 581 | { |
| 582 | signed short status; |
| 583 | signed short tadc_dac; |
| 584 | signed short temperature; |
| 585 | signed short temp_idx; |
| 586 | }L1D_TEMPINFO_T; |
| 587 | void L1D_RF_GetTemperatureInfo(L1D_TEMPINFO_T* tempinfo); |
| 588 | |
| 589 | /* ------------------------------------------------------------------------- */ |
| 590 | |
| 591 | /* |
| 592 | This enum has been move to l1_public_defs.h for proper location |
| 593 | #ifndef l1_types_public_h |
| 594 | typedef enum |
| 595 | { |
| 596 | FrequencyBand400, |
| 597 | FrequencyBand850, |
| 598 | FrequencyBand900, |
| 599 | FrequencyBand1800, |
| 600 | FrequencyBand1900, |
| 601 | |
| 602 | FrequencyBandCount |
| 603 | |
| 604 | } FrequencyBand; |
| 605 | #endif |
| 606 | */ |
| 607 | |
| 608 | #define PLTABLE_SIZE (13) |
| 609 | |
| 610 | typedef struct |
| 611 | { |
| 612 | short max_arfcn; |
| 613 | signed char gain_offset; |
| 614 | |
| 615 | } sAGCGAINOFFSET; |
| 616 | |
| 617 | typedef struct |
| 618 | { |
| 619 | sAGCGAINOFFSET agcPathLoss[FrequencyBandCount][PLTABLE_SIZE]; |
| 620 | }l1cal_agcPathLoss_T; |
| 621 | |
| 622 | /* ------------------------------------------------------------------------- */ |
| 623 | |
| 624 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 625 | typedef enum |
| 626 | { |
| 627 | L1D_LNA_HIGH_SENSITIVITY, //elna+g6 |
| 628 | L1D_LNA_HIGH, |
| 629 | L1D_LNA_MIDDLE, |
| 630 | L1D_LNA_LOW, |
| 631 | L1D_LNA_LOW_MAXPIN, //elna_bypass+g1 |
| 632 | } L1D_LNA_TYPE_E; |
| 633 | #endif |
| 634 | |
| 635 | #if IS_GSM_TX_DETECTOR_SUPPORT |
| 636 | typedef enum |
| 637 | { |
| 638 | L1D_TXD_DISABLE, |
| 639 | L1D_TXD_ENABLE, |
| 640 | } L1D_TXD_E; |
| 641 | #endif |
| 642 | |
| 643 | |
| 644 | typedef struct |
| 645 | { |
| 646 | signed char gain_offset_middle; |
| 647 | signed char gain_offset_middle_sawless; |
| 648 | signed char gain_offset_low; |
| 649 | signed char gain_offset_high_sensitivity; //elna+g6 |
| 650 | signed char gain_offset_low_maxpin; //elna_bypass+g1 |
| 651 | } sLNAGAINOFFSET; |
| 652 | |
| 653 | typedef struct |
| 654 | { |
| 655 | sLNAGAINOFFSET lnaPathLoss[FrequencyBandCount][PLTABLE_SIZE]; |
| 656 | } sLNAPATHLOSS_L1CAL; |
| 657 | |
| 658 | typedef sLNAPATHLOSS_L1CAL l1cal_lnaPathLoss_T; |
| 659 | |
| 660 | void L1D_RF_SetPathLossTable( int rf_band, void *table ); |
| 661 | #if defined(__RX_POWER_OFFSET_SUPPORT__) |
| 662 | void L1D_RF_SetPathLoss_Offset_Table( int rf_band, void *table ); |
| 663 | void L1D_RF_GetPathLoss_Offset_Table( int rf_band, void *table ); |
| 664 | #endif |
| 665 | |
| 666 | void L1D_RF_SetLnaPathLossTable( sLNAPATHLOSS_L1CAL *table ); |
| 667 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 668 | void L1D_RF_GetPathLossTable( int rf_band, void *table ); |
| 669 | #endif |
| 670 | void L1D_RF_GetLnaPathLossTable( sLNAPATHLOSS_L1CAL *table ); |
| 671 | |
| 672 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 673 | void L1D_RF_SetPathLossTable_RXD( int rf_band, void *table ); |
| 674 | void L1D_RF_SetPathLoss_Offset_Table_RXD( int rf_band, void *table ); |
| 675 | void L1D_RF_SetLnaPathLossTable_RXD( sLNAPATHLOSS_L1CAL *table ); |
| 676 | |
| 677 | void L1D_RF_GetPathLossTable_RXD( int rf_band, void *table ); |
| 678 | void L1D_RF_GetPathLoss_Offset_Table_RXD( int rf_band, void *table ); |
| 679 | void L1D_RF_GetLnaPathLossTable_RXD( sLNAPATHLOSS_L1CAL *table ); |
| 680 | #endif |
| 681 | |
| 682 | |
| 683 | /* ------------------------------------------------------------------------- */ |
| 684 | /*****************************************************************************/ |
| 685 | /***************************RX Power Offset Begin*******************************/ |
| 686 | /*****************************************************************************/ |
| 687 | #if defined(__RX_POWER_OFFSET_SUPPORT__) |
| 688 | typedef struct |
| 689 | { |
| 690 | short max_arfcn; |
| 691 | signed char gain_offset; |
| 692 | #if defined(__MULTI_LNA_MODE_CALIBRATION_SUPPORT__) |
| 693 | signed char gain_offset_middle; |
| 694 | signed char gain_offset_low; |
| 695 | #endif |
| 696 | } sAGCLNAGAINOFFSET; |
| 697 | |
| 698 | typedef struct |
| 699 | { |
| 700 | sAGCLNAGAINOFFSET agcPathLoss[FrequencyBandCount][PLTABLE_SIZE]; |
| 701 | }l1cal_agclnaPathLoss_T; |
| 702 | |
| 703 | |
| 704 | typedef struct |
| 705 | { |
| 706 | sAGCLNAGAINOFFSET* agcPathLoss[FrequencyBandCount]; |
| 707 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 708 | sAGCLNAGAINOFFSET* agcPathLoss_RXD[FrequencyBandCount]; |
| 709 | #endif |
| 710 | }sL1D_AGCLNA_Gain_Offset_Data; |
| 711 | |
| 712 | #endif/*__RX_POWER_OFFSET_SUPPORT__*/ |
| 713 | |
| 714 | |
| 715 | /*****************************************************************************/ |
| 716 | /***************************RX Power Offset End*********************************/ |
| 717 | /*****************************************************************************/ |
| 718 | |
| 719 | #if defined(__ANT_RXPWR_OFFSET_SUPPORT__) |
| 720 | typedef struct |
| 721 | { |
| 722 | kal_int16 arfcn; |
| 723 | kal_int16 threshold; |
| 724 | kal_int16 offset; |
| 725 | |
| 726 | }sANTENNARXPWROFFSET_DATA; |
| 727 | |
| 728 | typedef struct |
| 729 | { |
| 730 | kal_uint32 pcell_id; |
| 731 | sANTENNARXPWROFFSET_DATA arfcn_list[PLTABLE_SIZE]; |
| 732 | |
| 733 | }sANTENNARXPWROFFSET_PLIST; |
| 734 | |
| 735 | typedef struct |
| 736 | { |
| 737 | kal_bool is_enable; |
| 738 | sANTENNARXPWROFFSET_PLIST pcell_list[PLTABLE_SIZE]; |
| 739 | |
| 740 | }sL1D_ANT_RxPWR_Offset_T; |
| 741 | #endif |
| 742 | |
| 743 | /*****************************************************************************/ |
| 744 | |
| 745 | #define PROFILE_NUM 16 |
| 746 | #define ARFCN_SECTION_NUM 12 |
| 747 | |
| 748 | typedef struct |
| 749 | { |
| 750 | unsigned char point[2][16]; |
| 751 | |
| 752 | } sRAMPAREADATA; |
| 753 | |
| 754 | typedef struct |
| 755 | { |
| 756 | signed short max_arfcn; |
| 757 | unsigned short mid_level; |
| 758 | unsigned short hi_weight; |
| 759 | unsigned short low_weight; |
| 760 | |
| 761 | } sARFCN_SECTION; |
| 762 | |
| 763 | typedef struct |
| 764 | { |
| 765 | signed long lowest_power; |
| 766 | unsigned short power[16]; |
| 767 | sRAMPAREADATA ramp[ PROFILE_NUM ]; |
| 768 | sARFCN_SECTION arfcn_weight[ ARFCN_SECTION_NUM ]; |
| 769 | #if IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT |
| 770 | unsigned short battery_compensate[5/*volt*/][5/*temp*/]; |
| 771 | #else |
| 772 | unsigned short battery_compensate[3/*volt*/][3/*temp*/]; |
| 773 | #endif |
| 774 | } sRAMPDATA; |
| 775 | |
| 776 | typedef struct |
| 777 | { |
| 778 | sRAMPDATA rampData; |
| 779 | }l1cal_rampTable_T; |
| 780 | |
| 781 | void L1D_RF_SetRampTable( int rf_band, void *table ); |
| 782 | #if MD_DRV_IS_TX_POWER_OFFSET_SUPPORT |
| 783 | void L1D_RF_SetTxPowerOffsetData_GMSK( int rf_band, void *table ); |
| 784 | #if MD_DRV_IS_EPSK_TX_SUPPORT |
| 785 | void L1D_RF_SetTxPowerOffsetData_EPSK( int rf_band, void *table ); |
| 786 | #endif |
| 787 | #endif // IS_TX_POWER_OFFSET_SUPPORT |
| 788 | #if MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT |
| 789 | void L1D_RF_SetAdjustTPOData_GMSK( int rf_band, void *table ); |
| 790 | #if MD_DRV_IS_EPSK_TX_SUPPORT |
| 791 | void L1D_RF_SetAdjustTPOData_EPSK( int rf_band, void *table ); |
| 792 | #endif |
| 793 | #endif // __NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__ |
| 794 | |
| 795 | unsigned long L1D_RF_GetITC_PCL(void); |
| 796 | |
| 797 | #if MD_DRV_IS_EPSK_TX_SUPPORT |
| 798 | void L1D_RF_SetRampTableEPSK( int rf_band, void *table ); |
| 799 | void L1D_RF_SetPAGainTable( int rf_band, void *table ); |
| 800 | #endif |
| 801 | |
| 802 | /* ------------------------------------------------------------------------- */ |
| 803 | |
| 804 | typedef struct |
| 805 | { |
| 806 | #if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT |
| 807 | kal_uint32 dacValue; |
| 808 | #else |
| 809 | kal_uint16 dacValue; |
| 810 | #endif /* IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT */ |
| 811 | kal_int32 slopeInv; |
| 812 | }l1cal_afcData_T; |
| 813 | |
| 814 | void L1D_RF_SetCrystalAFCData( void *table ); |
| 815 | void L1D_RF_SetCrystalCap( int cap_no ); |
| 816 | #if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT |
| 817 | void L1D_RF_SetCrystalDac( int32 dacValue ); |
| 818 | #else |
| 819 | void L1D_RF_SetCrystalDac( short dacValue ); |
| 820 | #endif /* IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT */ |
| 821 | |
| 822 | /* ------------------------------------------------------------------------- */ |
| 823 | |
| 824 | typedef struct |
| 825 | { |
| 826 | kal_int16 filter_coefficient[60]; |
| 827 | }l1spfc_T; |
| 828 | |
| 829 | /* ------------------------------------------------------------------------- */ |
| 830 | |
| 831 | typedef struct |
| 832 | { |
| 833 | unsigned char bbtx_common_mode_voltage; |
| 834 | unsigned char bbtx_gain; |
| 835 | unsigned char bbtx_calrcsel; |
| 836 | unsigned char bbtx_trimI; // need to set |
| 837 | unsigned char bbtx_trimQ; // need to set |
| 838 | unsigned char bbtx_dccoarseI; // need to set |
| 839 | unsigned char bbtx_dccoarseQ; // need to set |
| 840 | unsigned char bbtx_offsetI; // need to set |
| 841 | unsigned char bbtx_offsetQ; // need to set |
| 842 | unsigned char bbtx_isCalibrated; // need to set |
| 843 | #if IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT |
| 844 | int apc_bat_voltage_threshold[4]; |
| 845 | int apc_bat_temperature_threshold[4]; |
| 846 | #else |
| 847 | int apc_bat_low_voltage; |
| 848 | int apc_bat_high_voltage; |
| 849 | int apc_bat_low_temperature; |
| 850 | int apc_bat_high_temperature; |
| 851 | #endif |
| 852 | int ap_update_volinfo_period; |
| 853 | unsigned char bbtx_common_mode_voltage_h; |
| 854 | unsigned char bbtx_gain_h; |
| 855 | unsigned char bbtx_calrcsel_h; |
| 856 | unsigned char bbtx_trimI_h; |
| 857 | unsigned char bbtx_trimQ_h; |
| 858 | unsigned char bbtx_dccoarseI_h; |
| 859 | unsigned char bbtx_dccoarseQ_h; |
| 860 | unsigned char bbtx_offsetI_h; |
| 861 | unsigned char bbtx_offsetQ_h; |
| 862 | unsigned char bbtx_phsel; |
| 863 | unsigned char bbtx_phsel_h; |
| 864 | unsigned char bbrx_gsm850_gsm900_swap; |
| 865 | unsigned char bbrx_dcs1800_pcs1900_swap; |
| 866 | } sBBTXParameters; |
| 867 | |
| 868 | typedef struct |
| 869 | { |
| 870 | sBBTXParameters BBTXParameters; |
| 871 | }l1cal_txiq_T; |
| 872 | |
| 873 | |
| 874 | typedef unsigned char sMIDRAMPDATA[16]; |
| 875 | |
| 876 | |
| 877 | void L1D_RF_SetInterSlotRampTable( int rf_band, void *table ); |
| 878 | |
| 879 | #if MD_DRV_IS_EPSK_TX_SUPPORT |
| 880 | void L1D_RF_EPSK_SetInterSlotRampTable( int rf_band, int _8G_mode, void *table ); |
| 881 | #endif |
| 882 | |
| 883 | /* ------------------------------------------------------------------------- */ |
| 884 | |
| 885 | typedef struct |
| 886 | { |
| 887 | kal_uint8 interRampData[16]; |
| 888 | }l1cal_interRampData_T; |
| 889 | |
| 890 | #define InterRampData_count 4 |
| 891 | /* ------------------------------------------------------------------------- */ |
| 892 | |
| 893 | #if MD_DRV_IS_EPSK_TX_SUPPORT |
| 894 | typedef struct |
| 895 | { |
| 896 | kal_uint8 EPSK_interRampData[4][16]; |
| 897 | }l1cal_EPSK_interRampData_T; |
| 898 | #endif |
| 899 | |
| 900 | /* ------------------------------------------------------------------------- */ |
| 901 | |
| 902 | #if MD_DRV_IS_VCXO_LC_SUPPORT |
| 903 | #define XO_SlopeArea_Num 33 |
| 904 | #else |
| 905 | #define XO_SlopeArea_Num 4 |
| 906 | #endif |
| 907 | |
| 908 | typedef struct |
| 909 | { |
| 910 | long min_freq; |
| 911 | short min_dac; |
| 912 | // long inv_slope; |
| 913 | } XO_SLOPE_AREA_DATA; |
| 914 | |
| 915 | typedef struct |
| 916 | { |
| 917 | XO_SLOPE_AREA_DATA XO_SlopeAreaData[XO_SlopeArea_Num]; |
| 918 | }l1cal_crystalAfcData_T; |
| 919 | |
| 920 | typedef struct |
| 921 | { |
| 922 | kal_int32 cap_id; |
| 923 | }l1cal_crystalCapData_T; |
| 924 | |
| 925 | extern const XO_SLOPE_AREA_DATA XO_SlopeAreaData_RO[XO_SlopeArea_Num]; |
| 926 | |
| 927 | |
| 928 | /* ------------------------------------------------------------------------- */ |
| 929 | |
| 930 | #if MD_DRV_IS_FHC_SUPPORT |
| 931 | void L1D_RF_GetAFCDacTRxOffset( short *afcdactrxoffset ); |
| 932 | void L1D_RF_SetAFCDacTRxOffset( short *afcdactrxoffset ); |
| 933 | #endif |
| 934 | |
| 935 | /* ------------------------------------------------------------------------- */ |
| 936 | |
| 937 | typedef struct |
| 938 | { |
| 939 | unsigned long icorrection; |
| 940 | unsigned long qcorrection; |
| 941 | } skyip2coef; |
| 942 | |
| 943 | typedef struct |
| 944 | { |
| 945 | unsigned long ipol; |
| 946 | unsigned long qpol; |
| 947 | } sky117ip2pol; |
| 948 | |
| 949 | typedef struct |
| 950 | { |
| 951 | unsigned long acode; |
| 952 | unsigned long amcode; |
| 953 | } mt6139ip2coef; |
| 954 | |
| 955 | typedef struct |
| 956 | { |
| 957 | signed short w_re; |
| 958 | signed short w_im; |
| 959 | } w_coef; |
| 960 | |
| 961 | typedef struct |
| 962 | { |
| 963 | unsigned char map[16]; |
| 964 | } gain_rf_map; |
| 965 | |
| 966 | |
| 967 | #define WCTABLE_SIZE 19 |
| 968 | typedef union |
| 969 | { |
| 970 | struct |
| 971 | { |
| 972 | skyip2coef data[5/*band*/]; |
| 973 | } skyip2; //for sky74045 |
| 974 | struct |
| 975 | { |
| 976 | skyip2coef data[5/*band*/]; |
| 977 | sky117ip2pol pol[5/*band*/]; |
| 978 | } sky117ip2; |
| 979 | struct |
| 980 | { |
| 981 | mt6139ip2coef data[5/*band*/]; |
| 982 | unsigned long rxamcalmode; |
| 983 | } mt6139ip2; |
| 984 | struct |
| 985 | { |
| 986 | unsigned char fixgain_enable; |
| 987 | } sky74137; //for sky74137 |
| 988 | struct |
| 989 | { // borrowed for mpll_fh chip, should not have rf rx_coff |
| 990 | unsigned char fixed_mpll_clk; |
| 991 | unsigned short mpll_freq_idx; |
| 992 | unsigned char fixed_spll_clk; |
| 993 | unsigned short spll_freq_idx; |
| 994 | } mpll_fh; |
| 995 | struct |
| 996 | { // reserved for mpll_fh |
| 997 | unsigned char fixed_mpll_clk; |
| 998 | unsigned short mpll_freq_idx; |
| 999 | w_coef w_data[WCTABLE_SIZE]; |
| 1000 | } mt6256_51rf; |
| 1001 | struct |
| 1002 | { // reserved for mpll_fh |
| 1003 | unsigned char fixed_mpll_clk; |
| 1004 | unsigned short mpll_freq_idx; |
| 1005 | unsigned short is_md2g_log_on; |
| 1006 | } md2g_log; // for chip support md2g logger |
| 1007 | struct |
| 1008 | { // reserved for mpll_fh |
| 1009 | unsigned char fixed_mpll_clk; |
| 1010 | unsigned short mpll_freq_idx; |
| 1011 | unsigned short is_md2g_log_on; |
| 1012 | gain_rf_map gain_rf_table[4/*band*/]; |
| 1013 | } mt6162_gain_rf; |
| 1014 | #if MD_DRV_IS_DUAL_LOOP_AFC_CONTROL_SUPPORT |
| 1015 | //Fix AFC Enable Setting move to MMRF after UMOLY/TK6291. |
| 1016 | #endif |
| 1017 | } sRxip2; |
| 1018 | |
| 1019 | /*...................................*/ |
| 1020 | |
| 1021 | typedef struct |
| 1022 | { |
| 1023 | unsigned long word6_4_0; |
| 1024 | unsigned long word6_5_0; |
| 1025 | unsigned long word6_6_0; |
| 1026 | unsigned long word6_7_0; |
| 1027 | unsigned long bvmode; |
| 1028 | unsigned long c3mode; |
| 1029 | unsigned long wordC3; |
| 1030 | } b5ptxcoef; |
| 1031 | |
| 1032 | typedef struct |
| 1033 | { |
| 1034 | short pcl_index; |
| 1035 | unsigned char pa_vbias; |
| 1036 | #if MD_DRV_IS_RF_MT6280RF || MD_DRV_IS_RF_MT6169 || MD_DRV_IS_RF_MT6166 || MD_DRV_IS_RF_MT6165 || MD_DRV_IS_RF_MT6176 || MD_DRV_IS_RF_MT6179 || MD_DRV_IS_RF_MT6177L || MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T || MD_DRV_IS_RF_MT6177M |
| 1037 | unsigned short pa_gain; |
| 1038 | #endif |
| 1039 | } pa_vbias; |
| 1040 | |
| 1041 | typedef struct |
| 1042 | { |
| 1043 | pa_vbias GSM850_pa_vbias[8]; |
| 1044 | pa_vbias GSM900_pa_vbias[8]; |
| 1045 | pa_vbias DCS1800_pa_vbias[8]; |
| 1046 | pa_vbias PCS1900_pa_vbias[8]; |
| 1047 | } mt6140tx_pa_vbias; |
| 1048 | |
| 1049 | typedef struct |
| 1050 | { |
| 1051 | pa_vbias GSM850_pa_vbias[8]; |
| 1052 | pa_vbias GSM900_pa_vbias[8]; |
| 1053 | pa_vbias DCS1800_pa_vbias[8]; |
| 1054 | pa_vbias PCS1900_pa_vbias[8]; |
| 1055 | } mt6162tx_pa_vbias; |
| 1056 | |
| 1057 | typedef struct |
| 1058 | { |
| 1059 | pa_vbias GSM850_pa_vbias[8]; |
| 1060 | pa_vbias GSM900_pa_vbias[8]; |
| 1061 | pa_vbias DCS1800_pa_vbias[8]; |
| 1062 | pa_vbias PCS1900_pa_vbias[8]; |
| 1063 | } mt6256tx_pa_vbias; |
| 1064 | |
| 1065 | typedef struct |
| 1066 | { |
| 1067 | pa_vbias GSM850_pa_vbias[16]; |
| 1068 | pa_vbias GSM900_pa_vbias[16]; |
| 1069 | pa_vbias DCS1800_pa_vbias[16]; |
| 1070 | pa_vbias PCS1900_pa_vbias[16]; |
| 1071 | } orionRFtx_pa_vbias; |
| 1072 | |
| 1073 | typedef struct |
| 1074 | { |
| 1075 | unsigned char REFDET_SLOPE_SKEW; |
| 1076 | unsigned char AM_FB_DAC; |
| 1077 | } ad6546txcoef; |
| 1078 | |
| 1079 | typedef struct |
| 1080 | { |
| 1081 | signed char MID_GAMA_THRESHOLD; |
| 1082 | signed char LOW_GAMA_THRESHOLD; |
| 1083 | signed char MID_DELTA_SLOPE_SKEW; |
| 1084 | signed char LOW_DELTA_SLOPE_SKEW; |
| 1085 | signed char MID_DELTA_APC_CAP; |
| 1086 | signed char LOW_DELTA_APC_CAP; |
| 1087 | } ad6546tx_reg8_highband_delta; |
| 1088 | |
| 1089 | typedef union |
| 1090 | { |
| 1091 | #if MD_DRV_IS_RF_MT6280RF || MD_DRV_IS_RF_MT6169 || MD_DRV_IS_RF_MT6166 || MD_DRV_IS_RF_MT6165 || MD_DRV_IS_RF_MT6176 || MD_DRV_IS_RF_MT6179 || MD_DRV_IS_RF_MT6177L || MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T || MD_DRV_IS_RF_MT6177M |
| 1092 | struct |
| 1093 | { |
| 1094 | orionRFtx_pa_vbias data; |
| 1095 | } mt6280tx; /* Reserve mt6280tx for META Backward Capability */ |
| 1096 | struct |
| 1097 | { |
| 1098 | orionRFtx_pa_vbias data; |
| 1099 | } orionRFtx; |
| 1100 | #else |
| 1101 | struct |
| 1102 | { |
| 1103 | b5ptxcoef data; |
| 1104 | } b5ptx; |
| 1105 | struct |
| 1106 | { |
| 1107 | mt6140tx_pa_vbias data; |
| 1108 | } mt6140tx; |
| 1109 | struct |
| 1110 | { |
| 1111 | unsigned char ref_temp; |
| 1112 | unsigned char LB_GMSK_TX_PGA_GC; |
| 1113 | unsigned char HB_GMSK_TX_PGA_GC; |
| 1114 | char isDCXO; |
| 1115 | } CMOSEDGEtx; |
| 1116 | struct |
| 1117 | { |
| 1118 | ad6546txcoef CalData[4]; |
| 1119 | unsigned long Reg8_default[4]; |
| 1120 | ad6546tx_reg8_highband_delta AMLoopDelta; |
| 1121 | } ad6546tx; |
| 1122 | struct |
| 1123 | { |
| 1124 | mt6162tx_pa_vbias data; |
| 1125 | } mt6162tx; |
| 1126 | struct |
| 1127 | { |
| 1128 | mt6256tx_pa_vbias data; |
| 1129 | } mt6256tx; |
| 1130 | /* struct |
| 1131 | { |
| 1132 | unsigned long dummy; |
| 1133 | } sTXdummy; |
| 1134 | */ |
| 1135 | #endif |
| 1136 | } sTxepsk; |
| 1137 | |
| 1138 | typedef struct |
| 1139 | { |
| 1140 | sRxip2 rx; |
| 1141 | sTxepsk tx; |
| 1142 | } sRFSpecialCoef; |
| 1143 | |
| 1144 | typedef struct |
| 1145 | { |
| 1146 | sRFSpecialCoef RFSpecialCoef; |
| 1147 | }l1cal_rfspecialcoef_T; |
| 1148 | |
| 1149 | typedef struct |
| 1150 | { |
| 1151 | w_coef Wcoef_data[WCTABLE_SIZE]; |
| 1152 | }l1cal_wcoef_T; |
| 1153 | |
| 1154 | extern sRFSpecialCoef RFSpecialCoef; |
| 1155 | |
| 1156 | void L1D_RF_SetRFSpecialCoef( void *table ); |
| 1157 | |
| 1158 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 1159 | extern l1cal_wcoef_T RFSpecial_wcoef_rxd; |
| 1160 | |
| 1161 | void L1D_RF_SetWCoef_RXD( void *table ); |
| 1162 | |
| 1163 | void L1D_RF_SetRASParameters( void *table ); |
| 1164 | #endif |
| 1165 | /* ------------------------------------------------------------------------- */ |
| 1166 | |
| 1167 | typedef struct |
| 1168 | { |
| 1169 | signed char rollback_2t; /* Rollback (2t/F2I_Resolution) dB when 2 TX slots */ |
| 1170 | signed char rollback_3t; /* Rollback (3t/F2I_Resolution) dB when 3 TX slots */ |
| 1171 | signed char rollback_4t; /* Rollback (4t/F2I_Resolution) dB when 4 TX slots */ |
| 1172 | signed char rollback_5t; /* Rollback (5t/F2I_Resolution) dB when 5 TX slots */ |
| 1173 | } sTX_POWER_ROLLBACK; |
| 1174 | |
| 1175 | typedef struct |
| 1176 | { |
| 1177 | sTX_POWER_ROLLBACK rollback_data[FrequencyBandCount]; |
| 1178 | }l1cal_tx_power_rollback_T; |
| 1179 | |
| 1180 | #if MD_DRV_IS_GPRS |
| 1181 | void L1D_RF_SetTxPowerRollbackData( int rf_band, void *table ); |
| 1182 | #if MD_DRV_IS_EGPRS |
| 1183 | void L1D_RF_SetTxPowerRollbackData_EPSK( int rf_band, void *table ); |
| 1184 | #endif |
| 1185 | #endif |
| 1186 | |
| 1187 | /* ------------------------------------------------------------------------- */ |
| 1188 | |
| 1189 | typedef struct |
| 1190 | { |
| 1191 | unsigned short data[16]; /* for closed-loop AUXADC/BSI TXPC */ |
| 1192 | } sTXPC_ADCDATA; |
| 1193 | |
| 1194 | typedef struct |
| 1195 | { |
| 1196 | unsigned short data[8]; /* for closed-loop BSI TXPC */ |
| 1197 | } sTXPC_TEMPDATA; |
| 1198 | |
| 1199 | typedef struct |
| 1200 | { |
| 1201 | char is_calibrated; |
| 1202 | sTXPC_ADCDATA adc[FrequencyBandCount]; |
| 1203 | short temperature; |
| 1204 | sTXPC_TEMPDATA temp[FrequencyBandCount]; |
| 1205 | } sTXPC_L1CAL; |
| 1206 | |
| 1207 | typedef sTXPC_L1CAL l1cal_txpc_T; |
| 1208 | |
| 1209 | void L1D_RF_TXPC_SET_CAL( sTXPC_L1CAL *cal, int is_EPSK, int update_type ); |
| 1210 | void L1D_RF_TXPC_GET_L1_SETTING( sTXPC_L1CAL *buff, int is_EPSK ); |
| 1211 | |
| 1212 | /* ------------------------------------------------------------------------- */ |
| 1213 | |
| 1214 | typedef struct |
| 1215 | { |
| 1216 | unsigned short data[8]; /* for temperature ADC */ |
| 1217 | } sTEMPERATURE_ADC_L1CAL; |
| 1218 | |
| 1219 | typedef sTEMPERATURE_ADC_L1CAL l1cal_temperatureADC_T; |
| 1220 | |
| 1221 | void L1D_RF_TXPC_Get_Temp_ADC( sTEMPERATURE_ADC_L1CAL *buff ); |
| 1222 | |
| 1223 | /* ------------------------------------------------------------------------- */ |
| 1224 | /* API for meta DCS 2nd path TX power check */ |
| 1225 | void L1D_RF_Set_TX_Notch_Path( kal_uint8 notch_en ); |
| 1226 | /* ------------------------------------------------------------------------- */ |
| 1227 | |
| 1228 | #if MD_DRV_IS_BPI_DATA_48_BIT_CHIP |
| 1229 | typedef unsigned long long BPI_DATA_SIZE; /* unsigned 64 bits */ |
| 1230 | #elif MD_DRV_IS_BPI_DATA_32_BIT_CHIP |
| 1231 | typedef signed long BPI_DATA_SIZE; |
| 1232 | #else |
| 1233 | typedef signed short BPI_DATA_SIZE; |
| 1234 | #endif |
| 1235 | |
| 1236 | #if MD_DRV_IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2 |
| 1237 | typedef struct |
| 1238 | { |
| 1239 | signed short P_SR0; /* BPI data sent at SR0 */ |
| 1240 | signed short P_SR3; /* BPI data sent at SR3 */ |
| 1241 | signed short P_ST0; /* BPI data sent at ST0 */ |
| 1242 | signed short P_ST3; /* BPI data sent at ST3 */ |
| 1243 | }sRF_PDATA_OFFCHIP_ITEM; |
| 1244 | |
| 1245 | typedef struct |
| 1246 | { |
| 1247 | sRF_PDATA_OFFCHIP_ITEM GSM850; |
| 1248 | sRF_PDATA_OFFCHIP_ITEM GSM; |
| 1249 | sRF_PDATA_OFFCHIP_ITEM DCS; |
| 1250 | sRF_PDATA_OFFCHIP_ITEM PCS; |
| 1251 | }sRF_PDATA_OFFCHIP; |
| 1252 | |
| 1253 | #if (defined(__MD93__) || defined(__MD95__)) |
| 1254 | typedef struct |
| 1255 | { |
| 1256 | BPI_DATA_SIZE xPDATA_GSM850_PR1; |
| 1257 | BPI_DATA_SIZE xPDATA_GSM850_PR2; |
| 1258 | BPI_DATA_SIZE xPDATA_GSM850_PR2B; |
| 1259 | BPI_DATA_SIZE xPDATA_GSM850_PR3; |
| 1260 | BPI_DATA_SIZE xPDATA_GSM850_PR3A; |
| 1261 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 1262 | BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR1; |
| 1263 | BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR2; |
| 1264 | BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR2B; |
| 1265 | BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR3; |
| 1266 | BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR3A; |
| 1267 | #endif |
| 1268 | BPI_DATA_SIZE xPDATA_GSM850_PT1; |
| 1269 | BPI_DATA_SIZE xPDATA_GSM850_PT2; |
| 1270 | BPI_DATA_SIZE xPDATA_GSM850_PT2B; |
| 1271 | BPI_DATA_SIZE xPDATA_GSM850_PT3; |
| 1272 | BPI_DATA_SIZE xPDATA_GSM850_PT3A; |
| 1273 | BPI_DATA_SIZE xPDATA_GSM_PR1; |
| 1274 | BPI_DATA_SIZE xPDATA_GSM_PR2; |
| 1275 | BPI_DATA_SIZE xPDATA_GSM_PR2B; |
| 1276 | BPI_DATA_SIZE xPDATA_GSM_PR3; |
| 1277 | BPI_DATA_SIZE xPDATA_GSM_PR3A; |
| 1278 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 1279 | BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR1; |
| 1280 | BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR2; |
| 1281 | BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR2B; |
| 1282 | BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR3; |
| 1283 | BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR3A; |
| 1284 | #endif |
| 1285 | BPI_DATA_SIZE xPDATA_GSM_PT1; |
| 1286 | BPI_DATA_SIZE xPDATA_GSM_PT2; |
| 1287 | BPI_DATA_SIZE xPDATA_GSM_PT2B; |
| 1288 | BPI_DATA_SIZE xPDATA_GSM_PT3; |
| 1289 | BPI_DATA_SIZE xPDATA_GSM_PT3A; |
| 1290 | BPI_DATA_SIZE xPDATA_DCS_PR1; |
| 1291 | BPI_DATA_SIZE xPDATA_DCS_PR2; |
| 1292 | BPI_DATA_SIZE xPDATA_DCS_PR2B; |
| 1293 | BPI_DATA_SIZE xPDATA_DCS_PR3; |
| 1294 | BPI_DATA_SIZE xPDATA_DCS_PR3A; |
| 1295 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 1296 | BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR1; |
| 1297 | BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR2; |
| 1298 | BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR2B; |
| 1299 | BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR3; |
| 1300 | BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR3A; |
| 1301 | #endif |
| 1302 | BPI_DATA_SIZE xPDATA_DCS_PT1; |
| 1303 | BPI_DATA_SIZE xPDATA_DCS_PT2; |
| 1304 | BPI_DATA_SIZE xPDATA_DCS_PT2B; |
| 1305 | BPI_DATA_SIZE xPDATA_DCS_PT3; |
| 1306 | BPI_DATA_SIZE xPDATA_DCS_PT3A; |
| 1307 | BPI_DATA_SIZE xPDATA_PCS_PR1; |
| 1308 | BPI_DATA_SIZE xPDATA_PCS_PR2; |
| 1309 | BPI_DATA_SIZE xPDATA_PCS_PR2B; |
| 1310 | BPI_DATA_SIZE xPDATA_PCS_PR3; |
| 1311 | BPI_DATA_SIZE xPDATA_PCS_PR3A; |
| 1312 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 1313 | BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR1; |
| 1314 | BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR2; |
| 1315 | BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR2B; |
| 1316 | BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR3; |
| 1317 | BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR3A; |
| 1318 | #endif |
| 1319 | BPI_DATA_SIZE xPDATA_PCS_PT1; |
| 1320 | BPI_DATA_SIZE xPDATA_PCS_PT2; |
| 1321 | BPI_DATA_SIZE xPDATA_PCS_PT2B; |
| 1322 | BPI_DATA_SIZE xPDATA_PCS_PT3; |
| 1323 | BPI_DATA_SIZE xPDATA_PCS_PT3A; |
| 1324 | BPI_DATA_SIZE xPDATA_GSM850_PR2M1; |
| 1325 | BPI_DATA_SIZE xPDATA_GSM850_PR2M2; |
| 1326 | BPI_DATA_SIZE xPDATA_GSM850_PR2M3; |
| 1327 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 1328 | BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR2M1; |
| 1329 | BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR2M2; |
| 1330 | BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR2M3; |
| 1331 | #endif |
| 1332 | BPI_DATA_SIZE xPDATA_GSM850_PT2M1_G8; |
| 1333 | BPI_DATA_SIZE xPDATA_GSM850_PT2M2_G8; |
| 1334 | BPI_DATA_SIZE xPDATA_GSM850_PT2M3_G8; |
| 1335 | BPI_DATA_SIZE xPDATA_GSM850_PT2M1_8G; |
| 1336 | BPI_DATA_SIZE xPDATA_GSM850_PT2M2_8G; |
| 1337 | BPI_DATA_SIZE xPDATA_GSM850_PT2M3_8G; |
| 1338 | BPI_DATA_SIZE xPDATA_GSM_PR2M1; |
| 1339 | BPI_DATA_SIZE xPDATA_GSM_PR2M2; |
| 1340 | BPI_DATA_SIZE xPDATA_GSM_PR2M3; |
| 1341 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 1342 | BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR2M1; |
| 1343 | BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR2M2; |
| 1344 | BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR2M3; |
| 1345 | #endif |
| 1346 | BPI_DATA_SIZE xPDATA_GSM_PT2M1_G8; |
| 1347 | BPI_DATA_SIZE xPDATA_GSM_PT2M2_G8; |
| 1348 | BPI_DATA_SIZE xPDATA_GSM_PT2M3_G8; |
| 1349 | BPI_DATA_SIZE xPDATA_GSM_PT2M1_8G; |
| 1350 | BPI_DATA_SIZE xPDATA_GSM_PT2M2_8G; |
| 1351 | BPI_DATA_SIZE xPDATA_GSM_PT2M3_8G; |
| 1352 | BPI_DATA_SIZE xPDATA_DCS_PR2M1; |
| 1353 | BPI_DATA_SIZE xPDATA_DCS_PR2M2; |
| 1354 | BPI_DATA_SIZE xPDATA_DCS_PR2M3; |
| 1355 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 1356 | BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR2M1; |
| 1357 | BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR2M2; |
| 1358 | BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR2M3; |
| 1359 | #endif |
| 1360 | BPI_DATA_SIZE xPDATA_DCS_PT2M1_G8; |
| 1361 | BPI_DATA_SIZE xPDATA_DCS_PT2M2_G8; |
| 1362 | BPI_DATA_SIZE xPDATA_DCS_PT2M3_G8; |
| 1363 | BPI_DATA_SIZE xPDATA_DCS_PT2M1_8G; |
| 1364 | BPI_DATA_SIZE xPDATA_DCS_PT2M2_8G; |
| 1365 | BPI_DATA_SIZE xPDATA_DCS_PT2M3_8G; |
| 1366 | BPI_DATA_SIZE xPDATA_PCS_PR2M1; |
| 1367 | BPI_DATA_SIZE xPDATA_PCS_PR2M2; |
| 1368 | BPI_DATA_SIZE xPDATA_PCS_PR2M3; |
| 1369 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 1370 | BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR2M1; |
| 1371 | BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR2M2; |
| 1372 | BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR2M3; |
| 1373 | #endif |
| 1374 | BPI_DATA_SIZE xPDATA_PCS_PT2M1_G8; |
| 1375 | BPI_DATA_SIZE xPDATA_PCS_PT2M2_G8; |
| 1376 | BPI_DATA_SIZE xPDATA_PCS_PT2M3_G8; |
| 1377 | BPI_DATA_SIZE xPDATA_PCS_PT2M1_8G; |
| 1378 | BPI_DATA_SIZE xPDATA_PCS_PT2M2_8G; |
| 1379 | BPI_DATA_SIZE xPDATA_PCS_PT2M3_8G; |
| 1380 | BPI_DATA_SIZE xPDATA_INIT; |
| 1381 | BPI_DATA_SIZE xPDATA_IDLE; |
| 1382 | BPI_DATA_SIZE xPDATA_GMSK; |
| 1383 | BPI_DATA_SIZE xPDATA_8PSK; |
| 1384 | sRF_PDATA_OFFCHIP xPDATA_OFFCHIP; |
| 1385 | }sRF_BPI_VARIABLE; |
| 1386 | #endif |
| 1387 | /*...................................*/ |
| 1388 | |
| 1389 | typedef struct |
| 1390 | { |
| 1391 | signed short xQB_RX_FENA_2_FSYNC; |
| 1392 | signed short xQB_RX_FSYNC_2_FENA; |
| 1393 | signed short xQB_TX_FENA_2_FSYNC; |
| 1394 | signed short xQB_TX_FSYNC_2_FENA; |
| 1395 | signed short xQB_SR0; //OH |
| 1396 | signed short xQB_SR1; |
| 1397 | signed short xQB_SR2; |
| 1398 | signed short xQB_SR3; |
| 1399 | signed short xQB_SR2M; |
| 1400 | #if defined(__MD97__) |
| 1401 | #else |
| 1402 | signed short xQB_PR1; |
| 1403 | signed short xQB_PR2; |
| 1404 | signed short xQB_PR2B; |
| 1405 | signed short xQB_PR3; |
| 1406 | signed short xQB_PR3A; |
| 1407 | signed short xQB_PR2M1; |
| 1408 | signed short xQB_PR2M2; |
| 1409 | #endif |
| 1410 | signed short xQB_ST0; //OH |
| 1411 | signed short xQB_ST1; |
| 1412 | signed short xQB_ST2; |
| 1413 | signed short xQB_ST2B; |
| 1414 | signed short xQB_ST3; |
| 1415 | signed short xQB_ST2M_G8; |
| 1416 | signed short xQB_ST2M_8G; |
| 1417 | #if defined(__MD97__) |
| 1418 | #else |
| 1419 | signed short xQB_PT1; |
| 1420 | signed short xQB_PT2; |
| 1421 | signed short xQB_PT2B; |
| 1422 | signed short xQB_PT3; |
| 1423 | signed short xQB_PT3A; |
| 1424 | signed short xQB_PT2M1_G8; |
| 1425 | signed short xQB_PT2M2_G8; |
| 1426 | signed short xQB_PT2M3_G8; |
| 1427 | signed short xQB_PT2M1_8G; |
| 1428 | signed short xQB_PT2M2_8G; |
| 1429 | signed short xQB_PT2M3_8G; |
| 1430 | #endif |
| 1431 | signed short xQB_APCON; |
| 1432 | signed short xQB_APCMID; |
| 1433 | signed short xQB_APCOFF; |
| 1434 | signed short xQB_APCDACON; //OH |
| 1435 | signed short xQR_BOFF_2_IDLE; |
| 1436 | } sRF_TIMING_VARIABLE; |
| 1437 | |
| 1438 | /*...................................*/ |
| 1439 | |
| 1440 | typedef struct |
| 1441 | { |
| 1442 | int xBAT_VOLTAGE_SAMPLE_PERIOD; |
| 1443 | int xBAT_VOLTAGE_AVERAGE_COUNT; |
| 1444 | int xBAT_TEMPERATURE_SAMPLE_PERIOD; |
| 1445 | int xBAT_TEMPERATURE_AVERAGE_COUNT; |
| 1446 | //int xBAT_LOW_VOLTAGE; |
| 1447 | //int xBAT_HIGH_VOLTAGE; |
| 1448 | //int xBAT_LOW_TEMPERATURE; |
| 1449 | //int xBAT_HIGH_TEMPERATURE; |
| 1450 | int xRF_TEMPERATURE_SAMPLE_PERIOD; //OH |
| 1451 | int xRF_TEMPERATURE_AVERAGE_COUNT; //OH |
| 1452 | } sRF_APC_COMPENSATE_VARIABLE; |
| 1453 | |
| 1454 | /*...................................*/ |
| 1455 | |
| 1456 | typedef struct |
| 1457 | { |
| 1458 | signed short txios_highpcl_850_GMSK; |
| 1459 | signed short txios_highpcl_900_GMSK; |
| 1460 | signed short txios_highpcl_DCS_GMSK; |
| 1461 | signed short txios_highpcl_PCS_GMSK; |
| 1462 | signed short txios_highpcl_850_EPSK; |
| 1463 | signed short txios_highpcl_900_EPSK; |
| 1464 | signed short txios_highpcl_DCS_EPSK; |
| 1465 | signed short txios_highpcl_PCS_EPSK; |
| 1466 | signed short txios_lowpcl_850_GMSK; |
| 1467 | signed short txios_lowpcl_900_GMSK; |
| 1468 | signed short txios_lowpcl_DCS_GMSK; |
| 1469 | signed short txios_lowpcl_PCS_GMSK; |
| 1470 | signed short txios_lowpcl_850_EPSK; |
| 1471 | signed short txios_lowpcl_900_EPSK; |
| 1472 | signed short txios_lowpcl_DCS_EPSK; |
| 1473 | signed short txios_lowpcl_PCS_EPSK; |
| 1474 | |
| 1475 | }sRF_PCL_VARIABLE; |
| 1476 | |
| 1477 | /*...................................*/ |
| 1478 | |
| 1479 | typedef struct |
| 1480 | { |
| 1481 | signed short lbmod_gc_highpcl_850_GMSK; |
| 1482 | signed short lbmod_gc_highpcl_900_GMSK; |
| 1483 | signed short lbmod_gc_highpcl_DCS_GMSK; |
| 1484 | signed short lbmod_gc_highpcl_PCS_GMSK; |
| 1485 | signed short lbmod_gc_highpcl_850_EPSK; |
| 1486 | signed short lbmod_gc_highpcl_900_EPSK; |
| 1487 | signed short lbmod_gc_highpcl_DCS_EPSK; |
| 1488 | signed short lbmod_gc_highpcl_PCS_EPSK; |
| 1489 | signed short lbmod_gc_lowpcl_850_GMSK; |
| 1490 | signed short lbmod_gc_lowpcl_900_GMSK; |
| 1491 | signed short lbmod_gc_lowpcl_DCS_GMSK; |
| 1492 | signed short lbmod_gc_lowpcl_PCS_GMSK; |
| 1493 | signed short lbmod_gc_lowpcl_850_EPSK; |
| 1494 | signed short lbmod_gc_lowpcl_900_EPSK; |
| 1495 | signed short lbmod_gc_lowpcl_DCS_EPSK; |
| 1496 | signed short lbmod_gc_lowpcl_PCS_EPSK; |
| 1497 | }sRF_LBMOD_GC_VARIABLE; |
| 1498 | |
| 1499 | /*...................................*/ |
| 1500 | |
| 1501 | typedef struct |
| 1502 | { |
| 1503 | signed short hbmod_gc_highpcl_850_GMSK; |
| 1504 | signed short hbmod_gc_highpcl_900_GMSK; |
| 1505 | signed short hbmod_gc_highpcl_DCS_GMSK; |
| 1506 | signed short hbmod_gc_highpcl_PCS_GMSK; |
| 1507 | signed short hbmod_gc_highpcl_850_EPSK; |
| 1508 | signed short hbmod_gc_highpcl_900_EPSK; |
| 1509 | signed short hbmod_gc_highpcl_DCS_EPSK; |
| 1510 | signed short hbmod_gc_highpcl_PCS_EPSK; |
| 1511 | signed short hbmod_gc_lowpcl_850_GMSK; |
| 1512 | signed short hbmod_gc_lowpcl_900_GMSK; |
| 1513 | signed short hbmod_gc_lowpcl_DCS_GMSK; |
| 1514 | signed short hbmod_gc_lowpcl_PCS_GMSK; |
| 1515 | signed short hbmod_gc_lowpcl_850_EPSK; |
| 1516 | signed short hbmod_gc_lowpcl_900_EPSK; |
| 1517 | signed short hbmod_gc_lowpcl_DCS_EPSK; |
| 1518 | signed short hbmod_gc_lowpcl_PCS_EPSK; |
| 1519 | |
| 1520 | }sRF_HBMOD_GC_VARIABLE; |
| 1521 | |
| 1522 | /*...................................*/ |
| 1523 | |
| 1524 | typedef struct |
| 1525 | { |
| 1526 | signed short txitc_highpcl_850_GMSK; |
| 1527 | signed short txitc_highpcl_900_GMSK; |
| 1528 | signed short txitc_highpcl_DCS_GMSK; |
| 1529 | signed short txitc_highpcl_PCS_GMSK; |
| 1530 | signed short txitc_highpcl_850_EPSK; |
| 1531 | signed short txitc_highpcl_900_EPSK; |
| 1532 | signed short txitc_highpcl_DCS_EPSK; |
| 1533 | signed short txitc_highpcl_PCS_EPSK; |
| 1534 | signed short txitc_lowpcl_850_GMSK; |
| 1535 | signed short txitc_lowpcl_900_GMSK; |
| 1536 | signed short txitc_lowpcl_DCS_GMSK; |
| 1537 | signed short txitc_lowpcl_PCS_GMSK; |
| 1538 | signed short txitc_lowpcl_850_EPSK; |
| 1539 | signed short txitc_lowpcl_900_EPSK; |
| 1540 | signed short txitc_lowpcl_DCS_EPSK; |
| 1541 | signed short txitc_lowpcl_PCS_EPSK; |
| 1542 | }sRF_ITC_PCL_VARIABLE; |
| 1543 | |
| 1544 | /*...................................*/ |
| 1545 | |
| 1546 | typedef struct |
| 1547 | { |
| 1548 | signed char xCLOSED_LOOP_TXPC_TYPE; //OH |
| 1549 | signed short xQB_TX_SAMPLE_OFFSET_GMSK; //OH |
| 1550 | signed short xQB_TX_SAMPLE_OFFSET_EPSK; //OH |
| 1551 | signed short xTXPC_EPSK_TP_SLOPE_LB; //OH |
| 1552 | signed short xTXPC_EPSK_TP_SLOPE_HB; //OH |
| 1553 | } sRF_TX_POWERFEEDBACK_VARIABLE; //OH |
| 1554 | |
| 1555 | /*...................................*/ |
| 1556 | |
| 1557 | typedef struct |
| 1558 | { |
| 1559 | //int xXO_CapID; |
| 1560 | //signed short xafc_dac_default; |
| 1561 | //signed short xafc_inv_slope; |
| 1562 | signed char xEGSM_DISABLE; |
| 1563 | //unsigned char xGSM850_GSM900_SWAP; |
| 1564 | //unsigned char xDCS1800_PCS1900_SWAP; |
| 1565 | unsigned char xGSM_ERR_DET_ID; //OH |
| 1566 | signed short xTX_PROPAGATION_DELAY; |
| 1567 | signed short xTQ_EPSK_TX_DELAY; |
| 1568 | char xIS_RAMPPROFILE_ROLLBACK_ENABLE; |
| 1569 | } sRF_OTHERS_VARIABLE; |
| 1570 | |
| 1571 | /*...................................*/ |
| 1572 | |
| 1573 | typedef struct |
| 1574 | { |
| 1575 | sTX_POWER_ROLLBACK GSM850_tx_power_rollback_gmsk; |
| 1576 | sTX_POWER_ROLLBACK GSM_tx_power_rollback_gmsk; |
| 1577 | sTX_POWER_ROLLBACK DCS_tx_power_rollback_gmsk; |
| 1578 | sTX_POWER_ROLLBACK PCS_tx_power_rollback_gmsk; |
| 1579 | sTX_POWER_ROLLBACK GSM850_tx_power_rollback_epsk; |
| 1580 | sTX_POWER_ROLLBACK GSM_tx_power_rollback_epsk; |
| 1581 | sTX_POWER_ROLLBACK DCS_tx_power_rollback_epsk; |
| 1582 | sTX_POWER_ROLLBACK PCS_tx_power_rollback_epsk; |
| 1583 | }sRF_TX_POWER_ROLLBACK_VARIABLE; |
| 1584 | |
| 1585 | /*...................................*/ |
| 1586 | |
| 1587 | #if IS_CHIP_MT6297_AND_LATTER_VERSION |
| 1588 | #else |
| 1589 | typedef struct |
| 1590 | { |
| 1591 | //PRIMARARY |
| 1592 | GGE_IORX_E xGSM850_PATH_SEL; |
| 1593 | GGE_IORX_E xGSM_PATH_SEL; |
| 1594 | GGE_IORX_E xDCS_PATH_SEL; |
| 1595 | GGE_IORX_E xPCS_PATH_SEL; |
| 1596 | |
| 1597 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 1598 | //DIVERSITY |
| 1599 | GGE_IORX_E xGSM850_DIVERSITY_PATH_SEL; |
| 1600 | GGE_IORX_E xGSM_DIVERSITY_PATH_SEL; |
| 1601 | GGE_IORX_E xDCS_DIVERSITY_PATH_SEL; |
| 1602 | GGE_IORX_E xPCS_DIVERSITY_PATH_SEL; |
| 1603 | #endif |
| 1604 | }sRF_RX_BAND_VARIABLE; |
| 1605 | #endif |
| 1606 | /*...................................*/ |
| 1607 | |
| 1608 | typedef struct |
| 1609 | { |
| 1610 | unsigned char xAFC_PREDICTION_ON; |
| 1611 | unsigned short xAFC_PREDICTION_INTERVAL; |
| 1612 | unsigned char xAFC_PREDICTION_DECAYING_FACTOR; |
| 1613 | }sRF_AFC_TRACKING_VARIABLE; |
| 1614 | |
| 1615 | /*...................................*/ |
| 1616 | |
| 1617 | typedef struct |
| 1618 | { |
| 1619 | unsigned char xCLK1_EN; |
| 1620 | unsigned char xCLK2_EN; |
| 1621 | unsigned char xCLK3_EN; |
| 1622 | unsigned char xCLK4_EN; |
| 1623 | }sRF_CLK_BUFFER_VARIABLE; |
| 1624 | |
| 1625 | /*...................................*/ |
| 1626 | |
| 1627 | #if IS_GSM_TX_DETECTOR_SUPPORT |
| 1628 | typedef struct |
| 1629 | { |
| 1630 | L1D_TXD_E TXD_ENABLE[FrequencyBandCount]; |
| 1631 | }sRF_TX_POWER_DETECT_VARIABLE; |
| 1632 | #endif |
| 1633 | |
| 1634 | /*...................................*/ |
| 1635 | |
| 1636 | typedef struct |
| 1637 | { |
| 1638 | int start; // the special pattern of start position |
| 1639 | int version; // Struct Version ID |
| 1640 | int RF_Type; // RF type |
| 1641 | char is_data_update; // default is false, and will be changed as true after tool update |
| 1642 | #if defined(__MD97__) |
| 1643 | #else |
| 1644 | sRF_BPI_VARIABLE RF_BPI_Variable; |
| 1645 | #endif |
| 1646 | sRF_TIMING_VARIABLE RF_Timing_Variable; |
| 1647 | sRF_APC_COMPENSATE_VARIABLE RF_APC_Compensate_Variable; |
| 1648 | sRF_PCL_VARIABLE RF_PCL_Varaible; |
| 1649 | sRF_LBMOD_GC_VARIABLE RF_Lbmod_GC_Variable; |
| 1650 | sRF_HBMOD_GC_VARIABLE RF_Hbmod_GC_Variable; |
| 1651 | sRF_ITC_PCL_VARIABLE RF_ITC_PCL_Variable; |
| 1652 | sRF_TX_POWERFEEDBACK_VARIABLE RF_TX_PowerFeedback_Variable; |
| 1653 | //sRF_TX_POWER_ROLLBACK_VARIABLE RF_TX_Power_Rollback_Variable; |
| 1654 | #if IS_CHIP_MT6297_AND_LATTER_VERSION |
| 1655 | #else |
| 1656 | sRF_RX_BAND_VARIABLE RF_RX_Band_Variable; |
| 1657 | #endif |
| 1658 | sRF_OTHERS_VARIABLE RF_Others_Variable; |
| 1659 | sRF_AFC_TRACKING_VARIABLE RF_AFC_Tracking_Variable; |
| 1660 | sRF_CLK_BUFFER_VARIABLE RF_CLK_Buffer_Variable; |
| 1661 | #if defined(__GSM_INCREASE_RACH_TX_POWER_SUPPORT__) |
| 1662 | int RACH_Tx_Offset[FrequencyBandCount - 1];//For RACH TX OFFSET |
| 1663 | #endif |
| 1664 | #if IS_GSM_TX_DETECTOR_SUPPORT |
| 1665 | sRF_TX_POWER_DETECT_VARIABLE RF_TX_PowerDetect_Variable; |
| 1666 | #endif |
| 1667 | #if defined(__2G_FAST_TIMING_ADJUST_SUPPORT__) |
| 1668 | bool Fast_Timing_Control; |
| 1669 | #endif |
| 1670 | int end; // the special pattern of end1 position |
| 1671 | }sL1D_RF_CUSTOM_INPUT_DATA; |
| 1672 | |
| 1673 | typedef sL1D_RF_CUSTOM_INPUT_DATA l1d_rf_custom_input_data_T; |
| 1674 | |
| 1675 | #endif |
| 1676 | |
| 1677 | void L1D_RF_CAPID_Update( void ); |
| 1678 | void L1D_RF_Custom_BBTXParameter_Update( void ); |
| 1679 | void L1D_RF_Custom_TX_Power_Rollback_Table_Update_GPRS( void ); |
| 1680 | void L1D_RF_Custom_TX_Power_Rollback_Table_Update_EGPRS( void ); |
| 1681 | |
| 1682 | /* ------------------------------------------------------------------------- */ |
| 1683 | |
| 1684 | typedef struct |
| 1685 | { |
| 1686 | kal_int32 cload_freq_offset; |
| 1687 | }l1cal_cload_freq_offset_T; |
| 1688 | |
| 1689 | #if MD_DRV_IS_32K_CRYSTAL_REMOVAL_SUPPORT |
| 1690 | void L1D_RF_GetCLoadFreqOffset( int* buff ); |
| 1691 | #endif |
| 1692 | /* ------------------------------------------------------------------------- */ |
| 1693 | |
| 1694 | #if MD_DRV_IS_TX_GAIN_RF_CALIBRATION_SUPPORT |
| 1695 | #if MD_DRV_IS_RF_MT6165 |
| 1696 | #define TX_GAIN_STEP_NUM 13 |
| 1697 | #else |
| 1698 | #error "please define TX_GAIN_STEP_NUM for this RF" |
| 1699 | #endif |
| 1700 | #else |
| 1701 | #define TX_GAIN_STEP_NUM 13 |
| 1702 | #endif |
| 1703 | |
| 1704 | typedef struct |
| 1705 | { |
| 1706 | kal_int16 gain_rf[FrequencyBandCount][TX_GAIN_STEP_NUM]; |
| 1707 | }l1cal_gainrf_T; |
| 1708 | |
| 1709 | typedef struct |
| 1710 | { |
| 1711 | short data[TX_GAIN_STEP_NUM]; |
| 1712 | } sTXGAIN_RFDATA; |
| 1713 | |
| 1714 | |
| 1715 | typedef enum |
| 1716 | { |
| 1717 | EPSKTxGainNormalState, |
| 1718 | EPSKTxGainCalibrationState, |
| 1719 | |
| 1720 | } TXGainRFState; |
| 1721 | |
| 1722 | /* ------------------------------------------------------------------------- */ |
| 1723 | |
| 1724 | #if MD_DRV_IS_2G_MIPI_SUPPORT |
| 1725 | |
| 1726 | typedef struct |
| 1727 | { |
| 1728 | unsigned short mipi_data_st; //mipi data start index |
| 1729 | unsigned short mipi_data_sp; //mipi data stop index |
| 1730 | } sGGE_MIPIDATA_STSP; |
| 1731 | |
| 1732 | typedef struct |
| 1733 | { |
| 1734 | unsigned short mipi_elm_type; //mipi element type |
| 1735 | sGGE_MIPIDATA_STSP mipi_data_stsp; //mipi data table start index and end index |
| 1736 | unsigned short mipi_evt_type; //event type |
| 1737 | signed short mipi_evt_timing; //event timing |
| 1738 | } sGGE_MIPIEVENT; |
| 1739 | |
| 1740 | typedef struct |
| 1741 | { |
| 1742 | unsigned short mipi_elm_type; //mipi element type |
| 1743 | unsigned short mipi_port_sel; //port where data to send |
| 1744 | unsigned short mipi_data_seq; //data write sequence format |
| 1745 | unsigned long mipi_data; //mipi data |
| 1746 | } sGGE_MIPIDATA; |
| 1747 | |
| 1748 | typedef struct |
| 1749 | { |
| 1750 | signed short subband_arfcn; //subband arfcn |
| 1751 | unsigned short mipi_addr; //mipi address |
| 1752 | unsigned long mipi_data; //mipi data |
| 1753 | } sGGE_MIPISUBDATA; |
| 1754 | |
| 1755 | typedef struct |
| 1756 | { |
| 1757 | unsigned short mipi_elm_type; //mipi element type |
| 1758 | unsigned short mipi_port_sel; //port where data to send |
| 1759 | unsigned short mipi_data_seq; //data write sequence format |
| 1760 | unsigned short mipi_usid; //mipi usid |
| 1761 | sGGE_MIPISUBDATA mipi_subband_data[GGE_MIPI_SUBBAND_NUM]; //mipi subband data |
| 1762 | } sGGE_MIPIDATA_SUBBAND; |
| 1763 | |
| 1764 | typedef struct |
| 1765 | { |
| 1766 | unsigned long mipi_gmsk_data[GGE_MIPI_SUBBAND_PA_DATA_NUM][GGE_MIPI_SUBBAND_NUM]; //PA GMSK data |
| 1767 | unsigned long mipi_8psk_data[GGE_MIPI_SUBBAND_PA_DATA_NUM][GGE_MIPI_SUBBAND_NUM]; //PA 8PSK data |
| 1768 | } sGGE_MIPIPADATA; |
| 1769 | |
| 1770 | typedef struct { |
| 1771 | sGGE_MIPIEVENT mipi_rxctrl_event[GGE_MIPI_RTX_EVENT_NUM]; |
| 1772 | sGGE_MIPIDATA_SUBBAND mipi_rxctrl_data[GGE_MIPI_RTX_DATA_NUM]; |
| 1773 | }sGGE_MIPI_RXCTRL_TABLE; |
| 1774 | |
| 1775 | typedef struct { |
| 1776 | sGGE_MIPIEVENT mipi_txctrl_event[GGE_MIPI_RTX_EVENT_NUM]; |
| 1777 | sGGE_MIPIDATA_SUBBAND mipi_txctrl_data[GGE_MIPI_RTX_DATA_NUM]; |
| 1778 | sGGE_MIPIPADATA mipi_txctrl_pa_data; |
| 1779 | }sGGE_MIPI_TXCTRL_TABLE; |
| 1780 | |
| 1781 | typedef struct { |
| 1782 | sGGE_MIPIEVENT mipi_txmidctrl_event[GGE_MIPI_TXMID_TYPE_NUM][GGE_MIPI_TXMID_EVENT_NUM]; |
| 1783 | sGGE_MIPIDATA_SUBBAND mipi_txmidctrl_data[GGE_MIPI_TXMID_DATA_NUM]; |
| 1784 | }sGGE_MIPI_TXMIDCTRL_TABLE; |
| 1785 | |
| 1786 | typedef struct |
| 1787 | { |
| 1788 | sGGE_MIPI_RXCTRL_TABLE mipi_rx_ctrl_table; |
| 1789 | sGGE_MIPI_TXCTRL_TABLE mipi_tx_ctrl_table; |
| 1790 | sGGE_MIPI_TXMIDCTRL_TABLE mipi_txmid_ctrl_table; |
| 1791 | }sGGE_MIPI_CTRL_TABLE_BAND; |
| 1792 | |
| 1793 | #if MD_DRV_IS_2G_TAS_SUPPORT |
| 1794 | typedef struct { |
| 1795 | sGGE_MIPIEVENT tas_mipi_rtxctrl_event[L1D_TAS_FE_CAT_MAX_NUM*L1D_TAS_MAX_MIPI_EVNET_NUM]; |
| 1796 | sGGE_MIPIDATA_SUBBAND tas_mipi_rtxctrl_data[L1D_TAS_FE_CAT_MAX_NUM*L1D_TAS_MAX_MIPI_DATA_NUM]; |
| 1797 | }sGGE_TAS_MIPI_RTXCTRL_TABLE; |
| 1798 | #endif |
| 1799 | |
| 1800 | #if defined(__DYNAMIC_ANTENNA_TUNING__) |
| 1801 | typedef struct |
| 1802 | { |
| 1803 | sGGE_MIPIEVENT dat_mipi_rtxctrl_event[L1D_DAT_FE_CAT_MAX_NUM*L1D_DAT_MAX_MIPI_EVNET_NUM]; |
| 1804 | sGGE_MIPIDATA_SUBBAND dat_mipi_rtxctrl_data[L1D_DAT_FE_CAT_MAX_NUM*L1D_DAT_MAX_MIPI_DATA_NUM]; |
| 1805 | }sGGE_DAT_MIPI_RTXCTRL_TABLE; |
| 1806 | |
| 1807 | typedef sGGE_DAT_MIPI_RTXCTRL_TABLE l1cal_dat_mipi_ctrl_table_T; |
| 1808 | #endif//__DYNAMIC_ANTENNA_TUNING__ |
| 1809 | |
| 1810 | typedef struct |
| 1811 | { |
| 1812 | sGGE_MIPI_CTRL_TABLE_BAND* band400_mipi_table; |
| 1813 | sGGE_MIPI_CTRL_TABLE_BAND* band850_mipi_table; |
| 1814 | sGGE_MIPI_CTRL_TABLE_BAND* band900_mipi_table; |
| 1815 | sGGE_MIPI_CTRL_TABLE_BAND* band1800_mipi_table; |
| 1816 | sGGE_MIPI_CTRL_TABLE_BAND* band1900_mipi_table; |
| 1817 | }sGGE_MIPI_CTRL_TABLE_SET; |
| 1818 | |
| 1819 | typedef sGGE_MIPI_CTRL_TABLE_BAND l1cal_mipi_ctrl_table_band_T; |
| 1820 | |
| 1821 | #endif |
| 1822 | |
| 1823 | typedef struct |
| 1824 | { |
| 1825 | unsigned short l1d_drdi_status; |
| 1826 | |
| 1827 | /* for Index debug */ |
| 1828 | unsigned short l1d_combined_config_index; |
| 1829 | unsigned char l1d_first_config_index_base; |
| 1830 | unsigned char l1d_second_config_index_base; |
| 1831 | unsigned char l1d_third_config_index_base; |
| 1832 | |
| 1833 | /* for GPIO debug */ |
| 1834 | unsigned long l1d_gpio_get_pin_rpc_status; |
| 1835 | unsigned long l1d_gpio_combined_pin_value; |
| 1836 | |
| 1837 | /* for ADC debug */ |
| 1838 | signed long l1d_adc_get_ch_num_rpc_status; |
| 1839 | signed long l1d_adc_dcl_handle_status; |
| 1840 | signed long l1d_adc_cal_dcl_handle_status; |
| 1841 | unsigned long l1d_adc_get_ch_num; |
| 1842 | unsigned long l1d_adc_dac_read_result; |
| 1843 | unsigned long l1d_adc_volt_translate_result; |
| 1844 | unsigned char l1d_adc_volt_level; |
| 1845 | |
| 1846 | /* for Barcode debug */ |
| 1847 | unsigned char l1d_barcode_lid_read_status; |
| 1848 | unsigned char l1d_barcode_digit_read_result; |
| 1849 | |
| 1850 | unsigned short l1d_custom_2grfparameters_lid_wr_status; |
| 1851 | unsigned short l1d_custom_gsm850_mipitable_lid_wr_status; |
| 1852 | unsigned short l1d_custom_gsm900_mipitable_lid_wr_status; |
| 1853 | unsigned short l1d_custom_dcs1800_mipitable_lid_wr_status; |
| 1854 | unsigned short l1d_custom_pcs1900_mipitable_lid_wr_status; |
| 1855 | |
| 1856 | /* for Band support debug */ |
| 1857 | unsigned char l1d_band_support_switch; |
| 1858 | |
| 1859 | /* for PDATA debug */ |
| 1860 | unsigned long l1d_custom_pdata_txport_debug[4][2]; |
| 1861 | |
| 1862 | signed long l1d_custom_pdata_gmsk_debug; |
| 1863 | signed long l1d_custom_pdata_8psk_debug; |
| 1864 | signed long l1d_custom_pdata_init_debug; |
| 1865 | signed long l1d_custom_pdata_idle_debug; |
| 1866 | |
| 1867 | #if defined (__RX_POWER_OFFSET_SUPPORT__) |
| 1868 | unsigned short l1d_custom_rxpoweroffset_lid_wr_status; |
| 1869 | unsigned short l1d_custom_2grf_rx_parameters_ext_lid_wr_status; |
| 1870 | #endif/*__RX_POWER_OFFSET_SUPPORT__*/ |
| 1871 | }sl1CustomDRDIStautaDebugInfo; |
| 1872 | |
| 1873 | typedef struct |
| 1874 | { |
| 1875 | unsigned char bandsupport_gsm850; |
| 1876 | unsigned char bandsupport_gsm900; |
| 1877 | unsigned char bandsupport_dcs1800; |
| 1878 | unsigned char bandsupport_pcs1900; |
| 1879 | }sl1CustomBandSupport; |
| 1880 | typedef sl1CustomDRDIStautaDebugInfo l1cal_l1CustomDRDIStautaDebugInfo_T; |
| 1881 | |
| 1882 | typedef sl1CustomBandSupport l1cal_l1CustomBandSupport_T; |
| 1883 | extern sl1CustomDRDIStautaDebugInfo l1d_custom_drdi_status_debug_info; |
| 1884 | |
| 1885 | #if MD_DRV_IS_TX_POWER_OFFSET_SUPPORT || defined (__SAR_TX_POWER_BACKOFF_SUPPORT__) |
| 1886 | |
| 1887 | #define TPO_2G_TABLE_NUM (1) |
| 1888 | #define L1D_TAS_ANT_NUM (4) |
| 1889 | |
| 1890 | #if defined (__SAR_TX_POWER_BACKOFF_SUPPORT__) |
| 1891 | typedef enum |
| 1892 | { |
| 1893 | GGE_SAR_RF_STATE_DEFAULT = 0, /* 0, apply default table (table 0) */ |
| 1894 | GGE_SAR_RF_STATE_1, |
| 1895 | GGE_SAR_RF_STATE_2, |
| 1896 | GGE_SAR_RF_STATE_3, |
| 1897 | GGE_SAR_RF_STATE_4, |
| 1898 | GGE_SAR_RF_STATE_5, |
| 1899 | GGE_SAR_RF_STATE_6, |
| 1900 | GGE_SAR_RF_STATE_7, |
| 1901 | GGE_SAR_RF_STATE_8, |
| 1902 | GGE_SAR_RF_STATE_9, |
| 1903 | GGE_SAR_RF_STATE_10, |
| 1904 | GGE_SAR_RF_STATE_11, |
| 1905 | GGE_SAR_RF_STATE_12, |
| 1906 | GGE_SAR_RF_STATE_13, |
| 1907 | GGE_SAR_RF_STATE_14, |
| 1908 | GGE_SAR_RF_STATE_15, |
| 1909 | GGE_SAR_RF_STATE_16, |
| 1910 | GGE_SAR_RF_STATE_17, |
| 1911 | GGE_SAR_RF_STATE_18, |
| 1912 | GGE_SAR_RF_STATE_19, |
| 1913 | GGE_SAR_RF_STATE_20, |
| 1914 | GGE_SAR_RF_STATE_END = 21, /* >=21, apply default table (table 0) */ |
| 1915 | |
| 1916 | } GGE_TPO_SAR_STATE_INDEX; /* SAR STATE INDEX from AP*/ |
| 1917 | #endif//__SAR_TX_POWER_BACKOFF_SUPPORT__ |
| 1918 | |
| 1919 | #if defined(__TX_POWER_OFFSET_SUPPORT__)&&(defined(__TAS_SUPPORT__)) |
| 1920 | |
| 1921 | #if (defined(__MD97__) || defined(__MD97P__)) |
| 1922 | #define SAR_TPO_ANT_NUM MMRFD_MAX_ANT_SUPPORT_NUM |
| 1923 | #elif defined(__MD95__) |
| 1924 | #define SAR_TPO_ANT_NUM MMRFD_PHYSICAL_ANT_MAX_NUM |
| 1925 | #elif defined(__MD93__) |
| 1926 | #define SAR_TPO_ANT_NUM L1D_TAS_ANT_NUM //For TAS2.0, ANT0/ANT1/ANT2 |
| 1927 | #endif |
| 1928 | typedef struct |
| 1929 | { |
| 1930 | unsigned short hi_weight; |
| 1931 | unsigned short low_weight; |
| 1932 | }s_Weight_Power_Offset; |
| 1933 | |
| 1934 | typedef struct |
| 1935 | { |
| 1936 | signed short max_arfcn; |
| 1937 | unsigned short mid_level; |
| 1938 | s_Weight_Power_Offset wt[SAR_TPO_ANT_NUM]; |
| 1939 | } sARFCN_SECTION_Power_Offset; |
| 1940 | |
| 1941 | typedef struct |
| 1942 | { |
| 1943 | short power_offset[SAR_TPO_ANT_NUM][16]; /* unit:DAC */ |
| 1944 | sARFCN_SECTION_Power_Offset arfcn_weight[ ARFCN_SECTION_NUM ]; |
| 1945 | } sTX_POWER_OFFSET_TABLE; |
| 1946 | #else |
| 1947 | typedef struct |
| 1948 | { |
| 1949 | short power_offset[16]; /* unit:DAC */ |
| 1950 | sARFCN_SECTION arfcn_weight[ ARFCN_SECTION_NUM ]; |
| 1951 | } sTX_POWER_OFFSET_TABLE; |
| 1952 | #endif /* defined(__TX_POWER_OFFSET_SUPPORT__) && defined(__TAS_SUPPORT__) */ |
| 1953 | |
| 1954 | typedef struct |
| 1955 | { |
| 1956 | sTX_POWER_OFFSET_TABLE table[TPO_2G_TABLE_NUM]; |
| 1957 | } sTX_POWER_OFFSET; |
| 1958 | |
| 1959 | typedef sTX_POWER_OFFSET tx_power_offset_t; |
| 1960 | |
| 1961 | #if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__) |
| 1962 | #define MOD_TYPE_COUNT (2) |
| 1963 | #define TX_SLOT_COUNT (4) |
| 1964 | #if (defined(__MD97__) || defined(__MD97P__)) |
| 1965 | #define SAR_TPB_ANT_NUM MMRFD_MAX_ANT_SUPPORT_NUM |
| 1966 | #elif defined(__MD95__) |
| 1967 | #define SAR_TPB_ANT_NUM MMRFD_PHYSICAL_ANT_MAX_NUM |
| 1968 | #elif defined(__MD93__) |
| 1969 | #define SAR_TPB_ANT_NUM L1D_TAS_ANT_NUM //For TAS2.0, ANT0/ANT1/ANT2 |
| 1970 | #endif |
| 1971 | typedef struct |
| 1972 | { |
| 1973 | int power_decrement[FrequencyBandCount-1][SAR_TPB_ANT_NUM][MOD_TYPE_COUNT][TX_SLOT_COUNT]; |
| 1974 | } SAR_TX_BACKOFF_TABLE_Params; |
| 1975 | |
| 1976 | |
| 1977 | typedef struct |
| 1978 | { |
| 1979 | SAR_TX_BACKOFF_TABLE_Params SAR_RF_STATE[GGE_SAR_RF_STATE_END - 1]; |
| 1980 | } SAR_TX_BACKOFF_STATE_Params; |
| 1981 | |
| 1982 | typedef SAR_TX_BACKOFF_STATE_Params L1D_CUSTOM_SAR_TX_BACKOFF_DB_NVRAM_T; |
| 1983 | |
| 1984 | #endif |
| 1985 | #endif /* MD_DRV_IS_TX_POWER_OFFSET_SUPPORT || __SAR_TX_POWER_BACKOFF_SUPPORT__*/ |
| 1986 | /* ------------------------------------------------------------------------- */ |
| 1987 | |
| 1988 | /* ------------------------------------------------------------------------- */ |
| 1989 | #if defined(__RX_POWER_OFFSET_SUPPORT__) |
| 1990 | |
| 1991 | typedef struct |
| 1992 | { |
| 1993 | kal_uint16 RPO_enable; /* Enable Rx power offset */ |
| 1994 | kal_uint16 RPO_meta_enable; /* The main purpose of "meta_Rx_power_offset_enable" is to disable power offset during calibration */ |
| 1995 | } sRX_POWER_OFFSET_SETTING; |
| 1996 | |
| 1997 | typedef struct |
| 1998 | { |
| 1999 | sRX_POWER_OFFSET_SETTING rx_power_offset_setting; |
| 2000 | } s2G_RF_RX_PARAMETER_EXT; |
| 2001 | |
| 2002 | typedef s2G_RF_RX_PARAMETER_EXT l1_2g_rf_rx_parameter_ext_t; |
| 2003 | |
| 2004 | #endif /* __RX_POWER_OFFSET_SUPPORT__ */ |
| 2005 | #if MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT |
| 2006 | #define NSFT_ADJUST_TPO_TABLE_NUM (1) |
| 2007 | |
| 2008 | typedef struct |
| 2009 | { |
| 2010 | short power_apcdac_offset[16]; /* unit:DAC */ |
| 2011 | short power_dB_offset[16]; /* unit:0.125dB */ |
| 2012 | sARFCN_SECTION arfcn_weight[ ARFCN_SECTION_NUM ]; |
| 2013 | } sNSFT_ADJUST_TPO_TABLE; |
| 2014 | |
| 2015 | typedef struct |
| 2016 | { |
| 2017 | sNSFT_ADJUST_TPO_TABLE table[NSFT_ADJUST_TPO_TABLE_NUM]; |
| 2018 | } sNSFT_ADJUST_TPO; |
| 2019 | |
| 2020 | typedef sNSFT_ADJUST_TPO nsft_adjust_tpo_t; |
| 2021 | |
| 2022 | #endif /* MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT */ |
| 2023 | #if MD_DRV_IS_RF_MT6176 || MD_DRV_IS_RF_MT6179 || MD_DRV_IS_RF_MT6177L || MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T || MD_DRV_IS_RF_MT6177M |
| 2024 | typedef struct |
| 2025 | { |
| 2026 | int version; |
| 2027 | unsigned short is_calibrated; |
| 2028 | unsigned short lf_fine[4]; |
| 2029 | MMRFC_GSM_RESULT_PER_BAND_T g_result[4]; |
| 2030 | #if MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T |
| 2031 | MMRFC_GSM_POC_PGA_BIAS_T gsm_tx_pga_bias[4]; |
| 2032 | #endif |
| 2033 | } MMRFC_GSM_RESULT_T; |
| 2034 | |
| 2035 | typedef MMRFC_GSM_RESULT_T l1cal_mmrfc_result_T; |
| 2036 | |
| 2037 | void L1D_RF_RFCData_Init_Pcore(void); |
| 2038 | void L1D_RF_Get_RFC_Result(MMRFC_GSM_RESULT_T *buff); |
| 2039 | #endif |
| 2040 | /* ------------------------------------------------------------------------- */ |
| 2041 | /* TX gain table */ |
| 2042 | #if MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T |
| 2043 | typedef struct |
| 2044 | { |
| 2045 | unsigned int slice_group; |
| 2046 | signed int gain_step; |
| 2047 | unsigned long cw_setting; |
| 2048 | } L1D_TX_GAIN_SETTING_T; |
| 2049 | |
| 2050 | typedef struct |
| 2051 | { |
| 2052 | L1D_TX_GAIN_SETTING_T lb_tx_gain_setting[MMRFC_GSM_TX_DNL_PGA_TOTAL_GAIN_STEPS]; /* LB TX gain setting */ |
| 2053 | L1D_TX_GAIN_SETTING_T hb_tx_gain_setting[MMRFC_GSM_TX_DNL_PGA_TOTAL_GAIN_STEPS]; /* HB TX gain setting */ |
| 2054 | }L1D_TX_GAIN_TABLE_T; |
| 2055 | |
| 2056 | #endif |
| 2057 | /* ------------------------------------------------------------------------- */ |
| 2058 | |
| 2059 | #if defined(__TAS_SUPPORT__) |
| 2060 | #if (defined(__MD93__) || defined(__MD95__)) /*Not supported for Gen97*/ |
| 2061 | typedef struct |
| 2062 | { |
| 2063 | #if MD_DRV_IS_2G_Gen95_UTAS_SUPPORT |
| 2064 | L1D_CUSTOM_TAS_SPLIT_CONFIG_T l1d_custom_tas_split_database[FrequencyBandCount]; |
| 2065 | #else |
| 2066 | L1D_CUSTOM_TAS_FE_DATABASE_T l1d_custom_tas_fe_database; |
| 2067 | L1D_CUSTOM_TAS_FE_CAT_A_T* l1d_custom_tas_fe_cat_a_ptr; |
| 2068 | L1D_CUSTOM_TAS_FE_CAT_A_T l1d_custom_tas_fe_cat_a; |
| 2069 | #if MD_DRV_IS_2G_MIPI_SUPPORT |
| 2070 | sGGE_MIPIEVENT* l1d_tas_cat_a_mipi_event_ptr[L1D_TAS_MAX_CAT_A_CONFIG_NUM]; |
| 2071 | sGGE_MIPIEVENT l1d_tas_cat_a_mipi_event[L1D_TAS_MAX_CAT_A_CONFIG_NUM][L1D_TAS_MAX_MIPI_EVNET_NUM]; |
| 2072 | sGGE_MIPIDATA_SUBBAND* l1d_tas_cat_a_mipi_data_ptr[L1D_TAS_MAX_CAT_A_CONFIG_NUM]; |
| 2073 | sGGE_MIPIDATA_SUBBAND l1d_tas_cat_a_mipi_data[L1D_TAS_MAX_CAT_A_CONFIG_NUM][L1D_TAS_MAX_MIPI_DATA_NUM]; |
| 2074 | #endif |
| 2075 | L1D_CUSTOM_TAS_FE_CAT_B_T* l1d_custom_tas_fe_cat_b_ptr; |
| 2076 | L1D_CUSTOM_TAS_FE_CAT_B_T l1d_custom_tas_fe_cat_b; |
| 2077 | #if MD_DRV_IS_2G_MIPI_SUPPORT |
| 2078 | sGGE_MIPIEVENT* l1d_tas_cat_b_mipi_event_ptr[L1D_TAS_MAX_CAT_B_CONFIG_NUM]; |
| 2079 | sGGE_MIPIEVENT l1d_tas_cat_b_mipi_event[L1D_TAS_MAX_CAT_B_CONFIG_NUM][L1D_TAS_MAX_MIPI_EVNET_NUM]; |
| 2080 | sGGE_MIPIDATA_SUBBAND* l1d_tas_cat_b_mipi_data_ptr[L1D_TAS_MAX_CAT_B_CONFIG_NUM]; |
| 2081 | sGGE_MIPIDATA_SUBBAND l1d_tas_cat_b_mipi_data[L1D_TAS_MAX_CAT_B_CONFIG_NUM][L1D_TAS_MAX_MIPI_DATA_NUM]; |
| 2082 | #endif |
| 2083 | L1D_CUSTOM_TAS_FE_CAT_C_T* l1d_custom_tas_fe_cat_c_ptr; |
| 2084 | L1D_CUSTOM_TAS_FE_CAT_C_T l1d_custom_tas_fe_cat_c; |
| 2085 | #if MD_DRV_IS_2G_MIPI_SUPPORT |
| 2086 | sGGE_MIPIEVENT* l1d_tas_cat_c_mipi_event_ptr[L1D_TAS_MAX_CAT_C_CONFIG_NUM]; |
| 2087 | sGGE_MIPIEVENT l1d_tas_cat_c_mipi_event[L1D_TAS_MAX_CAT_C_CONFIG_NUM][L1D_TAS_MAX_MIPI_EVNET_NUM]; |
| 2088 | sGGE_MIPIDATA_SUBBAND* l1d_tas_cat_c_mipi_data_ptr[L1D_TAS_MAX_CAT_C_CONFIG_NUM]; |
| 2089 | sGGE_MIPIDATA_SUBBAND l1d_tas_cat_c_mipi_data[L1D_TAS_MAX_CAT_C_CONFIG_NUM][L1D_TAS_MAX_MIPI_DATA_NUM]; |
| 2090 | #endif |
| 2091 | #endif |
| 2092 | }L1D_CUSTOM_TAS_FE_NVRAM_T; |
| 2093 | |
| 2094 | typedef struct |
| 2095 | { |
| 2096 | #if MD_DRV_IS_2G_Gen95_UTAS_SUPPORT |
| 2097 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_ENABLE[FrequencyBandCount]; |
| 2098 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE0_ENABLE[FrequencyBandCount]; |
| 2099 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE1_ENABLE[FrequencyBandCount]; |
| 2100 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE2_ENABLE[FrequencyBandCount]; |
| 2101 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE3_ENABLE[FrequencyBandCount]; |
| 2102 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE4_ENABLE[FrequencyBandCount]; |
| 2103 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE5_ENABLE[FrequencyBandCount]; |
| 2104 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE6_ENABLE[FrequencyBandCount]; |
| 2105 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE7_ENABLE[FrequencyBandCount]; |
| 2106 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE8_ENABLE[FrequencyBandCount]; |
| 2107 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE9_ENABLE[FrequencyBandCount]; |
| 2108 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE10_ENABLE[FrequencyBandCount]; |
| 2109 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE11_ENABLE[FrequencyBandCount]; |
| 2110 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE12_ENABLE[FrequencyBandCount]; |
| 2111 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE13_ENABLE[FrequencyBandCount]; |
| 2112 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE14_ENABLE[FrequencyBandCount]; |
| 2113 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE15_ENABLE[FrequencyBandCount]; |
| 2114 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE16_ENABLE[FrequencyBandCount]; |
| 2115 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE17_ENABLE[FrequencyBandCount]; |
| 2116 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE18_ENABLE[FrequencyBandCount]; |
| 2117 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE19_ENABLE[FrequencyBandCount]; |
| 2118 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE20_ENABLE[FrequencyBandCount]; |
| 2119 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE21_ENABLE[FrequencyBandCount]; |
| 2120 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE22_ENABLE[FrequencyBandCount]; |
| 2121 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE23_ENABLE[FrequencyBandCount]; |
| 2122 | #else |
| 2123 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_ENABLE[FrequencyBandCount]; |
| 2124 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE0_ENABLE[FrequencyBandCount]; |
| 2125 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE1_ENABLE[FrequencyBandCount]; |
| 2126 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE2_ENABLE[FrequencyBandCount]; |
| 2127 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 2128 | L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE3_ENABLE[FrequencyBandCount]; |
| 2129 | #endif /* __2G_RX_DIVERSITY_PATH_SUPPORT__ */ |
| 2130 | #endif |
| 2131 | }L1D_CUSTOM_TAS_TST_T; |
| 2132 | #endif |
| 2133 | |
| 2134 | #if MD_DRV_IS_2G_TAS_INHERIT_4G_ANT |
| 2135 | typedef struct |
| 2136 | { |
| 2137 | LTE_Band inherit_lte_band; |
| 2138 | }L1D_CUSTOM_TAS_INHERIT_LTE_BAND_T; |
| 2139 | |
| 2140 | typedef struct |
| 2141 | { |
| 2142 | L1D_CUSTOM_TAS_INHERIT_LTE_BAND_T* l1_inherit_lte_ant_gsmBand_ptr; |
| 2143 | kal_uint32 inherit_lte_band_bitmap[L1D_TAS_INHERIT_LTE_BAND_BITMAP_NUM]; |
| 2144 | }L1D_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_T; |
| 2145 | |
| 2146 | typedef struct |
| 2147 | { |
| 2148 | L1D_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_T inherit_lte_band_bitmap_table[FrequencyBandCount]; |
| 2149 | }L1D_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_T; |
| 2150 | #endif |
| 2151 | #endif |
| 2152 | |
| 2153 | #if IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT //defined(__DYNAMIC_ANTENNA_TUNING__) |
| 2154 | typedef enum |
| 2155 | { |
| 2156 | L1D_DAT_DISABLE, |
| 2157 | L1D_DAT_ENABLE, |
| 2158 | }L1D_CUSTOM_DAT_SWITCH_E; |
| 2159 | |
| 2160 | typedef struct |
| 2161 | { |
| 2162 | L1D_CUSTOM_DAT_SWITCH_E l1d_dat_enable; |
| 2163 | }L1D_CUSTOM_DAT_DATABASE_T; |
| 2164 | |
| 2165 | #if MD_DRV_IS_2G_DAT_SUPPORT || MD_DRV_IS_2G_Gen95_UDAT_SUPPORT |
| 2166 | typedef struct |
| 2167 | { |
| 2168 | #if MD_DRV_IS_2G_Gen95_UDAT_SUPPORT |
| 2169 | L1D_CUSTOM_DAT_SPLIT_CONFIG_T l1d_custom_dat_split_database[FrequencyBandCount]; |
| 2170 | #else |
| 2171 | L1D_CUSTOM_SB_DAT_FE_DATABASE_T l1d_dat_sb_fe_db[FrequencyBandCount]; |
| 2172 | #endif |
| 2173 | }L1D_CUSTOM_DAT_FE_DATABASE_T; |
| 2174 | #endif |
| 2175 | |
| 2176 | typedef struct |
| 2177 | { |
| 2178 | L1D_CUSTOM_DAT_SWITCH_E L1_DAT_ENABLE; /* 0: off 1: DAT force mode */ |
| 2179 | #if MD_DRV_IS_2G_DAT_SUPPORT || MD_DRV_IS_2G_Gen95_UDAT_SUPPORT |
| 2180 | L1D_CUSTOM_DAT_FE_DATABASE_T l1d_custom_dat_fe_database; |
| 2181 | #endif |
| 2182 | }L1D_CUSTOM_DAT_FE_ROUTE_NVRAM_T; |
| 2183 | |
| 2184 | |
| 2185 | typedef struct |
| 2186 | { |
| 2187 | L1D_CUSTOM_DAT_FE_CAT_A_T* l1d_custom_dat_fe_cat_a_ptr; |
| 2188 | L1D_CUSTOM_DAT_FE_CAT_A_T l1d_custom_dat_fe_cat_a; |
| 2189 | #if MD_DRV_IS_2G_MIPI_SUPPORT |
| 2190 | sGGE_MIPIEVENT* l1d_dat_cat_a_mipi_event_ptr[L1D_DAT_MAX_CAT_A_CONFIG_NUM]; |
| 2191 | sGGE_MIPIEVENT l1d_dat_cat_a_mipi_event[L1D_DAT_MAX_CAT_A_CONFIG_NUM][L1D_DAT_MAX_MIPI_EVNET_NUM]; |
| 2192 | sGGE_MIPIDATA_SUBBAND* l1d_dat_cat_a_mipi_data_ptr[L1D_DAT_MAX_CAT_A_CONFIG_NUM]; |
| 2193 | sGGE_MIPIDATA_SUBBAND l1d_dat_cat_a_mipi_data[L1D_DAT_MAX_CAT_A_CONFIG_NUM][L1D_DAT_MAX_MIPI_DATA_NUM]; |
| 2194 | #endif |
| 2195 | }L1D_CUSTOM_DAT_FE_CAT_A_NVRAM_T; |
| 2196 | |
| 2197 | typedef struct |
| 2198 | { |
| 2199 | L1D_CUSTOM_DAT_FE_CAT_B_T* l1d_custom_dat_fe_cat_b_ptr; |
| 2200 | L1D_CUSTOM_DAT_FE_CAT_B_T l1d_custom_dat_fe_cat_b; |
| 2201 | #if MD_DRV_IS_2G_MIPI_SUPPORT |
| 2202 | sGGE_MIPIEVENT* l1d_dat_cat_b_mipi_event_ptr[L1D_DAT_MAX_CAT_B_CONFIG_NUM]; |
| 2203 | sGGE_MIPIEVENT l1d_dat_cat_b_mipi_event[L1D_DAT_MAX_CAT_B_CONFIG_NUM][L1D_DAT_MAX_MIPI_EVNET_NUM]; |
| 2204 | sGGE_MIPIDATA_SUBBAND* l1d_dat_cat_b_mipi_data_ptr[L1D_DAT_MAX_CAT_B_CONFIG_NUM]; |
| 2205 | sGGE_MIPIDATA_SUBBAND l1d_dat_cat_b_mipi_data[L1D_DAT_MAX_CAT_B_CONFIG_NUM][L1D_DAT_MAX_MIPI_DATA_NUM]; |
| 2206 | #endif |
| 2207 | }L1D_CUSTOM_DAT_FE_CAT_B_NVRAM_T; |
| 2208 | |
| 2209 | typedef L1D_CUSTOM_DAT_FE_ROUTE_NVRAM_T l1_dat_custom_fe_route_params_T; |
| 2210 | #if defined(__MD93__) |
| 2211 | typedef L1D_CUSTOM_DAT_FE_CAT_A_NVRAM_T l1_dat_custom_fe_cata_params_T; |
| 2212 | typedef L1D_CUSTOM_DAT_FE_CAT_B_NVRAM_T l1_dat_custom_fe_catb_params_T; |
| 2213 | #endif |
| 2214 | #endif |
| 2215 | /*------------------------------Start UMOLY DRDI struct define--------------------*/ |
| 2216 | |
| 2217 | typedef struct |
| 2218 | { |
| 2219 | #if IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT |
| 2220 | int BAT_VOLTAGE_THRESHOLD[4]; |
| 2221 | int BAT_TEMPERATURE_THRESHOLD[4]; |
| 2222 | #else |
| 2223 | int BAT_LOW_VOLTAGE; |
| 2224 | int BAT_HIGH_VOLTAGE; |
| 2225 | int BAT_LOW_TEMPERATURE; |
| 2226 | int BAT_HIGH_TEMPERATURE; |
| 2227 | #endif |
| 2228 | int AP_UPDATE_VOLTINFO_PERIOD; |
| 2229 | }sTX_POWER_VOLTAGE_COMPENSATION; |
| 2230 | |
| 2231 | typedef struct |
| 2232 | { |
| 2233 | /*capid*/ |
| 2234 | long AFC_XO_CapID; |
| 2235 | |
| 2236 | }sCrystalParameter; |
| 2237 | |
| 2238 | #if MD_DRV_IS_32K_CRYSTAL_REMOVAL_SUPPORT |
| 2239 | typedef struct |
| 2240 | { |
| 2241 | /*cload freqoffset*/ |
| 2242 | int CLoad_FreqOffset; |
| 2243 | }sCloadParameter; |
| 2244 | |
| 2245 | typedef sCloadParameter l1cal_CloadParameter_T; |
| 2246 | #endif |
| 2247 | |
| 2248 | |
| 2249 | |
| 2250 | #if MD_DRV_IS_2G_MIPI_SUPPORT |
| 2251 | /*DRDI MIPI point define*/ |
| 2252 | typedef struct |
| 2253 | { |
| 2254 | sGGE_MIPI_CTRL_TABLE_BAND* GGE_MIPI_CTRL_TABLE[FrequencyBandCount]; |
| 2255 | }sGGE_DRDI_MIPI_CTRL_TABLE; |
| 2256 | #endif |
| 2257 | |
| 2258 | /*DRDI Calibration Data Struct define*/ |
| 2259 | |
| 2260 | #if defined(__RX_POWER_OFFSET_SUPPORT__) |
| 2261 | typedef struct |
| 2262 | { |
| 2263 | s2G_RF_RX_PARAMETER_EXT* RX_Power_Offset_Setting; |
| 2264 | sL1D_AGCLNA_Gain_Offset_Data RX_Power_Offset_Table; |
| 2265 | } sL1D_RX_POWER_OFFSET_DATA; |
| 2266 | #endif /* __RX_POWER_OFFSET_SUPPORT__ */ |
| 2267 | |
| 2268 | #if MD_DRV_IS_TX_POWER_OFFSET_SUPPORT |
| 2269 | typedef struct |
| 2270 | { |
| 2271 | sTX_POWER_OFFSET* Tx_Power_Offset_GMSK[FrequencyBandCount]; |
| 2272 | #if MD_DRV_IS_EPSK_TX_SUPPORT |
| 2273 | sTX_POWER_OFFSET* Tx_Power_Offset_EPSK[FrequencyBandCount]; |
| 2274 | #endif |
| 2275 | } sL1D_TX_POWER_OFFSET_DATA; |
| 2276 | #endif /*__TX_POWER_OFFSET_SUPPORT__ || __SAR_TX_POWER_BACKOFF_SUPPORT__*/ |
| 2277 | #if MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT |
| 2278 | typedef struct |
| 2279 | { |
| 2280 | sNSFT_ADJUST_TPO* Adjust_TPO_GMSK[FrequencyBandCount]; |
| 2281 | #if MD_DRV_IS_EPSK_TX_SUPPORT |
| 2282 | #if defined(__EPSK_ADJUST_TPO_SUPPORT__) |
| 2283 | sNSFT_ADJUST_TPO* Adjust_TPO_EPSK[FrequencyBandCount]; |
| 2284 | #endif//__EPSK_ADJUST_TPO_SUPPORT__ |
| 2285 | #endif |
| 2286 | } sL1D_ADJUST_TPO_DATA; |
| 2287 | #endif /*MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT*/ |
| 2288 | |
| 2289 | typedef struct |
| 2290 | { |
| 2291 | sAGCGAINOFFSET* AGC_PATHLOSS_TABLE[FrequencyBandCount]; |
| 2292 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 2293 | sAGCGAINOFFSET* AGC_PATHLOSS_RXD_TABLE[FrequencyBandCount]; |
| 2294 | #endif |
| 2295 | sRAMPDATA* RampData[FrequencyBandCount]; |
| 2296 | #if MD_DRV_IS_EPSK_TX_SUPPORT |
| 2297 | sRAMPDATA* RampData_EPSK[FrequencyBandCount]; |
| 2298 | #endif |
| 2299 | sTX_POWER_VOLTAGE_COMPENSATION* tx_apc_voltage_compensation; |
| 2300 | sMIDRAMPDATA* InterRampData[FrequencyBandCount]; |
| 2301 | #if MD_DRV_IS_EPSK_TX_SUPPORT |
| 2302 | sMIDRAMPDATA** EPSK_InterRampData[FrequencyBandCount]; |
| 2303 | #endif |
| 2304 | sCrystalParameter* afc_crystal_data; |
| 2305 | #if MD_DRV_IS_32K_CRYSTAL_REMOVAL_SUPPORT |
| 2306 | sCloadParameter* Cload_FreqOffset_Data; |
| 2307 | #endif |
| 2308 | #if MD_DRV_IS_GPRS |
| 2309 | sTX_POWER_ROLLBACK* tx_power_rollback_gmsk[FrequencyBandCount]; |
| 2310 | #if MD_DRV_IS_EGPRS |
| 2311 | sTX_POWER_ROLLBACK* tx_power_rollback_epsk[FrequencyBandCount]; |
| 2312 | #endif |
| 2313 | #endif |
| 2314 | #if MD_DRV_IS_TX_POWER_CONTROL_SUPPORT |
| 2315 | #if MD_DRV_IS_TXPC_CL_AUXADC_SUPPORT || IS_TXPC_CL_BSI_SUPPORT |
| 2316 | sTXPC_ADCDATA* TXADC_Data[FrequencyBandCount]; |
| 2317 | sTXPC_TEMPDATA* TXTEMP_Data[FrequencyBandCount]; |
| 2318 | #if MD_DRV_IS_EPSK_TX_SUPPORT |
| 2319 | sTXPC_ADCDATA* TXADC_Data_EPSK[FrequencyBandCount]; |
| 2320 | sTXPC_TEMPDATA* TXTEMP_Data_EPSK[FrequencyBandCount]; |
| 2321 | #endif |
| 2322 | #endif |
| 2323 | #endif |
| 2324 | sLNAGAINOFFSET* LNA_PATHLOSS_TABLE[FrequencyBandCount]; |
| 2325 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 2326 | sLNAGAINOFFSET* LNA_PATHLOSS_RXD_TABLE[FrequencyBandCount]; |
| 2327 | #endif |
| 2328 | l1cal_afcData_T* afc_crystal_data_dac_slop; |
| 2329 | w_coef* w_coef_data; |
| 2330 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 2331 | w_coef* w_coef_rxd_data; |
| 2332 | #endif |
| 2333 | orionRFtx_pa_vbias* pa_data; |
| 2334 | }sL1D_CAL_DATA; |
| 2335 | |
| 2336 | /*DRDI Front End data*/ |
| 2337 | typedef struct |
| 2338 | { |
| 2339 | #if defined(__2G_RF_CUSTOM_TOOL_SUPPORT__) |
| 2340 | sL1D_RF_CUSTOM_INPUT_DATA* l1d_rf_custom_input_data; |
| 2341 | #endif |
| 2342 | #if defined(__TAS_SUPPORT__) |
| 2343 | L1D_CUSTOM_TAS_NVRAM_T* L1_TAS_Custom_NVRAM; |
| 2344 | #if (defined(__MD93__) || defined(__MD95__)) /*Not supported for Gen97*/ |
| 2345 | L1D_CUSTOM_TAS_FE_NVRAM_T* L1_TAS_Custom_FE_NVRAM; |
| 2346 | L1D_CUSTOM_TAS_TST_T* L1_TAS_Custom_TST; |
| 2347 | #endif |
| 2348 | #if IS_2G_TAS_INHERIT_4G_ANT |
| 2349 | L1D_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_T* L1_TAS_Custom_InheritLteAntTable; |
| 2350 | #endif |
| 2351 | #endif |
| 2352 | #if IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT //defined(__DYNAMIC_ANTENNA_TUNING__) |
| 2353 | L1D_CUSTOM_DAT_FE_ROUTE_NVRAM_T* L1_DAT_Custom_FE_ROUTE_NVRAM; |
| 2354 | #if defined(__MD93__) |
| 2355 | L1D_CUSTOM_DAT_FE_CAT_A_NVRAM_T* L1_DAT_Custom_FE_CAT_A_NVRAM; |
| 2356 | L1D_CUSTOM_DAT_FE_CAT_B_NVRAM_T* L1_DAT_Custom_FE_CAT_B_NVRAM; |
| 2357 | #endif |
| 2358 | #endif |
| 2359 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) |
| 2360 | L1D_CUSTOM_RAS_NVRAM_T* L1_RAS_Custom_NVRAM; |
| 2361 | #endif |
| 2362 | char dummy; //avoid build error |
| 2363 | } sL1D_FRONT_END_DATA; |
| 2364 | |
| 2365 | typedef struct |
| 2366 | { |
| 2367 | #if defined(__RX_POWER_OFFSET_SUPPORT__) |
| 2368 | sL1D_RX_POWER_OFFSET_DATA L1D_RX_Power_Offset_Data; |
| 2369 | #endif |
| 2370 | #if MD_DRV_IS_TX_POWER_OFFSET_SUPPORT |
| 2371 | sL1D_TX_POWER_OFFSET_DATA L1D_TX_Power_Offset_Data; |
| 2372 | #endif |
| 2373 | #if MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT |
| 2374 | sL1D_ADJUST_TPO_DATA adjust_tpo_data; |
| 2375 | #endif |
| 2376 | #if defined(__ANT_RXPWR_OFFSET_SUPPORT__) |
| 2377 | sL1D_ANT_RxPWR_Offset_T* L1D_ANT_RxPWR_Offset_NVRAM; |
| 2378 | #endif |
| 2379 | #if defined(__GSM_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT__) |
| 2380 | L1D_RF_INTERFERENCE_ARFCN_INDICATION_T* L1_Custom_HW_CLK_NVRAM; |
| 2381 | #endif |
| 2382 | #if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__) |
| 2383 | L1D_CUSTOM_SAR_TX_BACKOFF_DB_NVRAM_T* L1_Custom_SAR_TX_BACKOFF_DB_NVRAM; |
| 2384 | #endif |
| 2385 | char dummy; //avoid build error |
| 2386 | }sL1D_CUSTOM_FEATURE_DATA; |
| 2387 | |
| 2388 | /*-----------------------------------End UMOLY DRDI Struct define-----------------------*/ |
| 2389 | #endif |