| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /******************************************************************************* |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * l1d_cid.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * MT6208 |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * Compile option definitoin |
| 49 | * |
| 50 | * Author: |
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| 52 | * ------- |
| 53 | * |
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| 2710 | *******************************************************************************/ |
| 2711 | |
| 2712 | #ifndef _L1D_CID_H_ |
| 2713 | #define _L1D_CID_H_ |
| 2714 | |
| 2715 | /*===================================================================*/ |
| 2716 | /* UMOLY Build Error Bypass before New Feature Ready. */ |
| 2717 | /*===================================================================*/ |
| 2718 | |
| 2719 | #define IS_TK6291_BYPASS_BUILD_ERR_DRDI 1 |
| 2720 | |
| 2721 | |
| 2722 | /*===============================================================================================*/ |
| 2723 | |
| 2724 | /*------------------------------------------*/ |
| 2725 | /* Compile Option : */ |
| 2726 | /* (1) MODE_GSM */ |
| 2727 | /* (2) MODE_GPRS */ |
| 2728 | /* (3) MODE_EGPRS */ |
| 2729 | /* ------------- */ |
| 2730 | /* (*) MTK_EGPRS_ENABLE */ |
| 2731 | /* (*) __EGPRS_MODE__ */ |
| 2732 | /* (*) MTK_GPRS_ENABLE */ |
| 2733 | /* (*) __PS_SERVICE__ */ |
| 2734 | /* (*) GPRS==1 */ |
| 2735 | /*------------------------------------------*/ |
| 2736 | /* Use in L1D : */ |
| 2737 | /* (1) IS_GSM */ |
| 2738 | /* (2) IS_GPRS */ |
| 2739 | /* (3) IS_EGPRS */ |
| 2740 | /*------------------------------------------*/ |
| 2741 | |
| 2742 | #define MODE_ID_GSM 0x0001 |
| 2743 | #define MODE_ID_GPRS 0x0002 |
| 2744 | #define MODE_ID_EGPRS 0x0004 |
| 2745 | |
| 2746 | #ifdef MODE_GSM |
| 2747 | #define MODE_ID MODE_ID_GSM |
| 2748 | #endif |
| 2749 | #ifdef MODE_GPRS |
| 2750 | #define MODE_ID MODE_ID_GPRS |
| 2751 | #endif |
| 2752 | #ifdef MODE_EGPRS |
| 2753 | #define MODE_ID MODE_ID_EGPRS |
| 2754 | #endif |
| 2755 | |
| 2756 | #define IS_GSM (MODE_ID==MODE_ID_GSM ) |
| 2757 | #define IS_GPRS ((MODE_ID==MODE_ID_GPRS) || (MODE_ID==MODE_ID_EGPRS)) |
| 2758 | #define IS_EGPRS (MODE_ID==MODE_ID_EGPRS) |
| 2759 | /*.......................................................*/ |
| 2760 | |
| 2761 | #ifndef MODE_ID |
| 2762 | #ifdef __EGPRS_MODE__ |
| 2763 | /*EGPRS*/ #define MODE_ID MODE_ID_EGPRS |
| 2764 | #endif |
| 2765 | #endif |
| 2766 | |
| 2767 | #ifndef MODE_ID |
| 2768 | #ifdef MTK_EGPRS_ENABLE |
| 2769 | /*EGPRS*/ #define MODE_ID MODE_ID_EGPRS |
| 2770 | #endif |
| 2771 | #endif |
| 2772 | |
| 2773 | #ifndef MODE_ID |
| 2774 | #ifdef __PS_SERVICE__ |
| 2775 | /*GPRS*/ #define MODE_ID MODE_ID_GPRS |
| 2776 | #endif |
| 2777 | #endif |
| 2778 | |
| 2779 | #ifndef MODE_ID |
| 2780 | #ifdef MTK_GPRS_ENABLE |
| 2781 | /*GPRS*/ #define MODE_ID MODE_ID_GPRS |
| 2782 | #endif |
| 2783 | #endif |
| 2784 | |
| 2785 | #ifndef MODE_ID |
| 2786 | #ifdef GPRS |
| 2787 | #if GPRS==1 |
| 2788 | /*GPRS*/ #define MODE_ID MODE_ID_GPRS |
| 2789 | #else |
| 2790 | /*GSM*/ #define MODE_ID MODE_ID_GSM |
| 2791 | #endif |
| 2792 | #endif |
| 2793 | #endif |
| 2794 | |
| 2795 | /* default setting */ |
| 2796 | #ifndef MODE_ID |
| 2797 | /*GSM*/ #define MODE_ID MODE_ID_GSM |
| 2798 | #endif |
| 2799 | /*===============================================================================================*/ |
| 2800 | |
| 2801 | /*---------------------------------------------------*/ |
| 2802 | /* Compile Option : */ |
| 2803 | /* (1) FPGA */ |
| 2804 | /* (2) CHIP_MT6208 */ |
| 2805 | /* (3) CHIP_MT6205 (A) */ |
| 2806 | /* (4) CHIP_MT6205B (B) */ |
| 2807 | /* (5) CHIP_MT6218 (A) */ |
| 2808 | /* (6) CHIP_MT6218B (B) */ |
| 2809 | /* (7) CHIP_MT6219 */ |
| 2810 | /* (8) CHIP_MT6217 */ |
| 2811 | /* (9) CHIP_MT6227 */ |
| 2812 | /* (10)CHIP_MT6228 */ |
| 2813 | /* (11)CHIP_MT6229 */ |
| 2814 | /* (12)CHIP_MT6225 */ |
| 2815 | /* (13)CHIP_MT6223 */ |
| 2816 | /* (14)CHIP_MT6238 */ |
| 2817 | /* --------------- */ |
| 2818 | /* (*) CHIP_TARGET */ |
| 2819 | /*---------------------------------------------------*/ |
| 2820 | /* Use in L1D : */ |
| 2821 | /* (1) IS_FPGA_TARGET */ |
| 2822 | /* (2) IS_CHIP_TARGET */ |
| 2823 | /* (3) IS_CHIP_MT6208 */ |
| 2824 | /* (4) IS_CHIP_MT6205A */ |
| 2825 | /* (5) IS_CHIP_MT6205B */ |
| 2826 | /* (6) IS_CHIP_MT6205 (A/B) */ |
| 2827 | /* (7) IS_CHIP_MT6218A */ |
| 2828 | /* (8) IS_CHIP_MT6218B */ |
| 2829 | /* (9) IS_CHIP_MT6218 */ |
| 2830 | /* (10)IS_CHIP_MT6219 */ |
| 2831 | /* (11)IS_CHIP_MT6228 */ |
| 2832 | /* (12)IS_CHIP_MT6229 */ |
| 2833 | /* (13)IS_CHIP_MT6227 */ |
| 2834 | /* (14)IS_CHIP_MT6208_AND_LATTER_VERSION */ |
| 2835 | /* (15)IS_CHIP_MT6205_AND_LATTER_VERSION (A/B) */ |
| 2836 | /* (16)IS_CHIP_MT6205A_AND_LATTER_VERSION (A/B) */ |
| 2837 | /* (17)IS_CHIP_MT6205B_AND_LATTER_VERSION */ |
| 2838 | /* (18)IS_CHIP_MT6218_AND_LATTER_VERSION (A/B) */ |
| 2839 | /* (19)IS_CHIP_MT6218A_AND_LATTER_VERSION (A/B) */ |
| 2840 | /* (20)IS_CHIP_MT6218B_AND_LATTER_VERSION */ |
| 2841 | /* (21)IS_CHIP_MT6219_AND_LATTER_VERSION */ |
| 2842 | /* (22)IS_CHIP_MT6228_AND_LATTER_VERSION */ |
| 2843 | /* (23)IS_CHIP_MT6227_AND_LATTER_VERSION */ |
| 2844 | /* (24)IS_CHIP_MT6218B_AN2DN */ |
| 2845 | /* (25)IS_CHIP_MT6218B_EN */ |
| 2846 | /* (26)IS_CHIP_MT6218B_FN */ |
| 2847 | /* (27)IS_CHIP_MT6219_AV */ |
| 2848 | /* (28)IS_CHIP_MT6219_BV */ |
| 2849 | /* (29)IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION */ |
| 2850 | /* (30)IS_CHIP_MT6225 */ |
| 2851 | /* (31)IS_CHIP_MT6225_AND_LATTER_VERSION */ |
| 2852 | /* (32)IS_CHIP_MT6223 */ |
| 2853 | /* (33)IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION */ |
| 2854 | /* (34)IS_CHIP_MT6238 */ |
| 2855 | /* (35)IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION */ |
| 2856 | /*---------------------------------------------------*/ |
| 2857 | |
| 2858 | #define CHIP_ID_FPGA 0x00000000 |
| 2859 | |
| 2860 | /* Divide chips into Series+Number */ |
| 2861 | |
| 2862 | #define CHIP_SER(ID) (0xFFFFFF00&ID) |
| 2863 | #define CHIP_NUM(ID) (0x000000FF&ID) |
| 2864 | |
| 2865 | /*---------------------*/ |
| 2866 | /* For GSM/GPRS Group */ |
| 2867 | /*---------------------*/ |
| 2868 | /* GSM */ /* 0x00000100+number */ |
| 2869 | #define CHIP_ID_MT6208 0x00000101 //0x00000001 |
| 2870 | #define CHIP_ID_MT6205A 0x00000102 //0x00000002 |
| 2871 | #define CHIP_ID_MT6205B 0x00000103 //0x00000004 |
| 2872 | /* GPRS */ /* 0x00000200+number */ |
| 2873 | #define CHIP_ID_MT6218A 0x00000201 //0x00000008 |
| 2874 | #define CHIP_ID_MT6218B 0x00000202 //0x00000010 |
| 2875 | #define CHIP_ID_MT6219 0x00000203 //0x00000020 |
| 2876 | /* AMR */ /* 0x00000400+number */ |
| 2877 | #define CHIP_ID_MT6227 0x00000401 //0x00000100 |
| 2878 | #define CHIP_ID_MT6228 0x00000402 //0x00000040 |
| 2879 | #define CHIP_ID_MT6225 0x00000403 //0x00000200 |
| 2880 | |
| 2881 | /*----------------------------------*/ |
| 2882 | /* For Dual DSP Group (EGPRS Group) */ |
| 2883 | /*----------------------------------*/ |
| 2884 | /* EDGE */ /* 0x00000800+number */ |
| 2885 | #define CHIP_ID_MT6229 0x00000801 //0x00000080 |
| 2886 | #define CHIP_ID_MT6268T 0x00000802 //0x00000400 |
| 2887 | /* GPRS SAIC */ /* 0x00001000+number */ |
| 2888 | #define CHIP_ID_MT6223 0x00001001 //0x00000800 |
| 2889 | /* EDGE SAIC */ /* 0x00002000+number */ |
| 2890 | #define CHIP_ID_MT6235 0x00002001 //0x00001000 |
| 2891 | #define CHIP_ID_MT6238 0x00002002 //0x00002000 |
| 2892 | #define CHIP_ID_TK6516 0x00002003 //0x00004000 |
| 2893 | #define CHIP_ID_MT6268A 0x00002004 //0x00008000 |
| 2894 | #define CHIP_ID_MT6516 0x00002005 //0x00010000 |
| 2895 | #define CHIP_ID_MT6268 0x00002006 //0x00040000 |
| 2896 | #define CHIP_ID_MT6236 0x00002007 //0x00100000 |
| 2897 | /* SOC */ /* 0x00004000+number */ |
| 2898 | #define CHIP_ID_MT6253T 0x00004001 //0x00020000 |
| 2899 | #define CHIP_ID_MT6253 0x00004002 //0x00080000 |
| 2900 | #define CHIP_ID_MT6252L 0x00004003 |
| 2901 | #define CHIP_ID_MT6252H 0x00004004 |
| 2902 | /* Dual MAC DSP */ /* 0x00008000+number */ |
| 2903 | #define CHIP_ID_MT6268T_DMAC 0x00008001 //0x00200000 |
| 2904 | #define CHIP_ID_MT6270A 0x00008002 //0x00400000 |
| 2905 | #define CHIP_ID_MT6276 0x00008003 //0x00800000 |
| 2906 | #define CHIP_ID_MT6573 0x00008004 //0x00000000 |
| 2907 | #define CHIP_ID_MT6575 0x00008005 //0x00000000 |
| 2908 | #define CHIP_ID_MT6577 0x00008006 //0x00000000 |
| 2909 | /* DLIF */ /* 0x00010000+number */ |
| 2910 | #define CHIP_ID_MT6256 0x00010001 //0x01000000 |
| 2911 | #define CHIP_ID_MT6251 0x00010002 //0x02000000 |
| 2912 | #define CHIP_ID_MT6255 0x00010003 |
| 2913 | #define CHIP_ID_MT6250 0x00010004 |
| 2914 | #define CHIP_ID_MT6260 0x00010005 |
| 2915 | #define CHIP_ID_MT6261 0x00010006 |
| 2916 | #define CHIP_ID_MT6280 0x00010080 |
| 2917 | #define CHIP_ID_MT6583_MD1 0x00010081 |
| 2918 | #define CHIP_ID_MT6583_MD2 0x00010082 |
| 2919 | #define CHIP_ID_MT6572 0x00010083 |
| 2920 | #define CHIP_ID_MT6582 0x00010084 |
| 2921 | #define CHIP_ID_MT6290 0x00010085 |
| 2922 | #define CHIP_ID_MT6595 0x00010088 |
| 2923 | #define CHIP_ID_MT6752_MD1 0x00010089 |
| 2924 | #define CHIP_ID_MT6752_MD2 0x00010090 |
| 2925 | #define CHIP_ID_TK6291 0x00010091 |
| 2926 | #define CHIP_ID_MT6755 0x00010092 |
| 2927 | #define CHIP_ID_MT6292 0x000100A0 |
| 2928 | #define CHIP_ID_MT6799 0x000100A1 |
| 2929 | #define CHIP_ID_MT6293 0x000100B0 |
| 2930 | #define CHIP_ID_MT6763 0X000100B1 |
| 2931 | #define CHIP_ID_MT6739 0X000100B2 |
| 2932 | #define CHIP_ID_TRINITYE1 0X000100B3 |
| 2933 | #define CHIP_ID_TRINITYL 0X000100B4 |
| 2934 | #define CHIP_ID_MT6771 0x000100B5 |
| 2935 | #define CHIP_ID_MT6765 0x000100B6 |
| 2936 | #define CHIP_ID_MT6295M 0X000100C0 |
| 2937 | #define CHIP_ID_MT3967 0X000100C1 |
| 2938 | #define CHIP_ID_MT6779 0X000100C2 |
| 2939 | #define CHIP_ID_MT6297 0X000100D0 |
| 2940 | #define CHIP_ID_MT6885 0X000100D1 |
| 2941 | #define CHIP_ID_MERCURY 0X000100D2 |
| 2942 | #define CHIP_ID_MT6873 0X000100D3 |
| 2943 | #define CHIP_ID_MT6853 0X000100D4 |
| 2944 | #define CHIP_ID_MT6833 0X000100D5 |
| 2945 | #define CHIP_ID_MT6880 0X000100D6 |
| 2946 | #define CHIP_ID_MT6890 0X000100D7 |
| 2947 | #define CHIP_ID_MT2735 0X000100D8 |
| 2948 | #define CHIP_ID_MT6893 0X000100D9/*D6, D7, D8 is used for Colgin*/ |
| 2949 | #define CHIP_ID_MT6877 0X000100DA |
| 2950 | #define CHIP_ID_MT6855 0X000100DB |
| 2951 | #ifdef FPGA |
| 2952 | #define CHIP_ID CHIP_ID_FPGA |
| 2953 | #endif |
| 2954 | #ifdef CHIP_MT6208 |
| 2955 | #define CHIP_ID CHIP_ID_MT6208 |
| 2956 | #endif |
| 2957 | #ifdef CHIP_MT6205 |
| 2958 | #define CHIP_ID CHIP_ID_MT6205A |
| 2959 | #endif |
| 2960 | #ifdef CHIP_MT6205B |
| 2961 | #define CHIP_ID CHIP_ID_MT6205B |
| 2962 | #endif |
| 2963 | #ifdef CHIP_MT6218 |
| 2964 | #define CHIP_ID CHIP_ID_MT6218A |
| 2965 | #endif |
| 2966 | #ifdef CHIP_MT6218B |
| 2967 | #define CHIP_ID CHIP_ID_MT6218B |
| 2968 | #endif |
| 2969 | #ifdef CHIP_MT6217 |
| 2970 | #define CHIP_ID CHIP_ID_MT6218B |
| 2971 | #endif |
| 2972 | #ifdef CHIP_MT6219 |
| 2973 | #define CHIP_ID CHIP_ID_MT6219 |
| 2974 | #endif |
| 2975 | #ifdef CHIP_MT6228 |
| 2976 | #define CHIP_ID CHIP_ID_MT6228 |
| 2977 | #endif |
| 2978 | #ifdef CHIP_MT6229 |
| 2979 | #define CHIP_ID CHIP_ID_MT6229 |
| 2980 | #endif |
| 2981 | #ifdef CHIP_MT6230 |
| 2982 | #define CHIP_ID CHIP_ID_MT6229 /* For L1 MT6230==MT6229 */ |
| 2983 | #endif |
| 2984 | #ifdef CHIP_MT6226 |
| 2985 | #define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6226==MT6227 */ |
| 2986 | #endif |
| 2987 | #ifdef CHIP_MT6227 |
| 2988 | #define CHIP_ID CHIP_ID_MT6227 |
| 2989 | #endif |
| 2990 | #ifdef CHIP_MT6226M |
| 2991 | #define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6226M==MT6227 */ |
| 2992 | #endif |
| 2993 | #ifdef CHIP_MT6226D |
| 2994 | #define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6226D==MT6227 */ |
| 2995 | #endif |
| 2996 | #ifdef CHIP_MT6227D |
| 2997 | #define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6227D==MT6227 */ |
| 2998 | #endif |
| 2999 | #ifdef CHIP_MT6226DS |
| 3000 | #define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6226DS==MT6227 */ |
| 3001 | #endif |
| 3002 | #ifdef CHIP_MT6227DS |
| 3003 | #define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6227DS==MT6227 */ |
| 3004 | #endif |
| 3005 | #ifdef CHIP_MT6225 |
| 3006 | #define CHIP_ID CHIP_ID_MT6225 |
| 3007 | #endif |
| 3008 | #ifdef CHIP_MT6268T |
| 3009 | #ifdef __DSP_FCORE4__ |
| 3010 | #define CHIP_ID CHIP_ID_MT6268T_DMAC |
| 3011 | #else |
| 3012 | #define CHIP_ID CHIP_ID_MT6268T |
| 3013 | #endif |
| 3014 | #endif |
| 3015 | #ifdef CHIP_MT6268H |
| 3016 | #define CHIP_ID CHIP_ID_MT6268T/* For L1 MT6268H==MT6268T*/ |
| 3017 | #endif |
| 3018 | #ifdef CHIP_MT6223 |
| 3019 | #define CHIP_ID CHIP_ID_MT6223 |
| 3020 | #endif |
| 3021 | #ifdef CHIP_MT6223P |
| 3022 | #define CHIP_ID CHIP_ID_MT6223 /* For L1 MT6223P==MT6223 */ |
| 3023 | #endif |
| 3024 | #ifdef CHIP_MT6235 |
| 3025 | #define CHIP_ID CHIP_ID_MT6238 /* For L1 MT6235==MT6238 */ |
| 3026 | #endif |
| 3027 | #ifdef CHIP_MT6238 |
| 3028 | #define CHIP_ID CHIP_ID_MT6238 |
| 3029 | #endif |
| 3030 | #ifdef CHIP_MT6235B |
| 3031 | #define CHIP_ID CHIP_ID_MT6238 /* For L1 MT6235B==MT6238 */ |
| 3032 | #endif |
| 3033 | #ifdef CHIP_MT6239 |
| 3034 | #define CHIP_ID CHIP_ID_MT6238 |
| 3035 | #endif |
| 3036 | #ifdef CHIP_TK6516 |
| 3037 | #define CHIP_ID CHIP_ID_TK6516 |
| 3038 | #endif |
| 3039 | #ifdef CHIP_MT6268A |
| 3040 | #define CHIP_ID CHIP_ID_MT6268A |
| 3041 | #endif |
| 3042 | #ifdef CHIP_MT6268 |
| 3043 | #define CHIP_ID CHIP_ID_MT6268 |
| 3044 | #endif |
| 3045 | #ifdef CHIP_MT6516 |
| 3046 | #define CHIP_ID CHIP_ID_MT6516 |
| 3047 | #endif |
| 3048 | #ifdef CHIP_MT6253T |
| 3049 | #define CHIP_ID CHIP_ID_MT6253T |
| 3050 | #endif |
| 3051 | #ifdef CHIP_MT6253 |
| 3052 | #define CHIP_ID CHIP_ID_MT6253 |
| 3053 | #endif |
| 3054 | #ifdef CHIP_MT6253E |
| 3055 | #define CHIP_ID CHIP_ID_MT6252H |
| 3056 | #endif |
| 3057 | #ifdef CHIP_MT6253L |
| 3058 | #define CHIP_ID CHIP_ID_MT6252L |
| 3059 | #endif |
| 3060 | #ifdef CHIP_MT6252 |
| 3061 | #define CHIP_ID CHIP_ID_MT6252L |
| 3062 | #endif |
| 3063 | #ifdef CHIP_MT6252H |
| 3064 | #define CHIP_ID CHIP_ID_MT6252H |
| 3065 | #endif |
| 3066 | #ifdef CHIP_MT6236 |
| 3067 | #define CHIP_ID CHIP_ID_MT6236 |
| 3068 | #endif |
| 3069 | #ifdef CHIP_MT6236B |
| 3070 | #define CHIP_ID CHIP_ID_MT6236 /* For L1 MT6236B==MT6236 */ |
| 3071 | #endif |
| 3072 | #ifdef CHIP_MT6270A |
| 3073 | #define CHIP_ID CHIP_ID_MT6270A |
| 3074 | #endif |
| 3075 | #ifdef CHIP_MT6276 |
| 3076 | #define CHIP_ID CHIP_ID_MT6276 |
| 3077 | #endif |
| 3078 | #ifdef CHIP_MT6256 |
| 3079 | #define CHIP_ID CHIP_ID_MT6256 |
| 3080 | #endif |
| 3081 | #ifdef CHIP_MT6255 |
| 3082 | #define CHIP_ID CHIP_ID_MT6255 |
| 3083 | #endif |
| 3084 | #ifdef CHIP_MT6251 |
| 3085 | #define CHIP_ID CHIP_ID_MT6251 |
| 3086 | #endif |
| 3087 | #ifdef CHIP_MT6573 |
| 3088 | #define CHIP_ID CHIP_ID_MT6573 |
| 3089 | #endif |
| 3090 | #ifdef CHIP_MT6575 |
| 3091 | #define CHIP_ID CHIP_ID_MT6575 |
| 3092 | #endif |
| 3093 | #ifdef CHIP_MT6577 |
| 3094 | #define CHIP_ID CHIP_ID_MT6577 |
| 3095 | #endif |
| 3096 | #ifdef CHIP_MT6250 |
| 3097 | #define CHIP_ID CHIP_ID_MT6250 |
| 3098 | #endif |
| 3099 | #ifdef CHIP_MT6280 |
| 3100 | #define CHIP_ID CHIP_ID_MT6280 |
| 3101 | #endif |
| 3102 | #ifdef CHIP_TK6280 |
| 3103 | #define CHIP_ID CHIP_ID_MT6270A /* For TK6280 FPGA development, The 2G part is similar to MT6270A FPGA */ |
| 3104 | #endif |
| 3105 | #ifdef CHIP_MT6583 |
| 3106 | #if defined(__MD1__) |
| 3107 | #define CHIP_ID CHIP_ID_MT6583_MD1 |
| 3108 | #elif defined(__MD2__) |
| 3109 | #define CHIP_ID CHIP_ID_MT6583_MD2 |
| 3110 | #else |
| 3111 | #error |
| 3112 | #endif |
| 3113 | #endif |
| 3114 | #ifdef CHIP_MT6752 |
| 3115 | #if defined(__MD1__) |
| 3116 | #define CHIP_ID CHIP_ID_MT6752_MD1 |
| 3117 | #elif defined(__MD2__) |
| 3118 | #define CHIP_ID CHIP_ID_MT6752_MD2 |
| 3119 | #else |
| 3120 | #error |
| 3121 | #endif |
| 3122 | #endif |
| 3123 | #ifdef CHIP_MT6572 |
| 3124 | #define CHIP_ID CHIP_ID_MT6572 |
| 3125 | #endif |
| 3126 | #ifdef CHIP_MT6582 |
| 3127 | #define CHIP_ID CHIP_ID_MT6582 |
| 3128 | #endif |
| 3129 | #ifdef CHIP_MT6290 |
| 3130 | #define CHIP_ID CHIP_ID_MT6290 |
| 3131 | #endif |
| 3132 | #ifdef CHIP_MT6595 |
| 3133 | #define CHIP_ID CHIP_ID_MT6595 |
| 3134 | #endif |
| 3135 | #ifdef MT6293 |
| 3136 | #define CHIP_ID CHIP_ID_MT6293 |
| 3137 | #endif |
| 3138 | #ifdef MT6763 |
| 3139 | #define CHIP_ID CHIP_ID_MT6763 |
| 3140 | #endif |
| 3141 | #ifdef MT6739 |
| 3142 | #define CHIP_ID CHIP_ID_MT6739 |
| 3143 | #endif |
| 3144 | #ifdef MT6771 |
| 3145 | #define CHIP_ID CHIP_ID_MT6771 |
| 3146 | #endif |
| 3147 | #ifdef MT6765 |
| 3148 | #define CHIP_ID CHIP_ID_MT6765 |
| 3149 | #endif |
| 3150 | #ifdef MT6295M |
| 3151 | #define CHIP_ID CHIP_ID_MT6295M |
| 3152 | #endif |
| 3153 | #ifdef MT3967 |
| 3154 | #define CHIP_ID CHIP_ID_MT3967 |
| 3155 | #endif |
| 3156 | #ifdef MT6779 |
| 3157 | #define CHIP_ID CHIP_ID_MT6779 |
| 3158 | #endif |
| 3159 | #ifdef MT6297 |
| 3160 | #define CHIP_ID CHIP_ID_MT6297 |
| 3161 | #endif |
| 3162 | #ifdef MT6885 |
| 3163 | #define CHIP_ID CHIP_ID_MT6885 |
| 3164 | #endif |
| 3165 | #ifdef MERCURY |
| 3166 | #define CHIP_ID CHIP_ID_MERCURY |
| 3167 | #endif |
| 3168 | #ifdef MT6873 |
| 3169 | #define CHIP_ID CHIP_ID_MT6873 |
| 3170 | #endif |
| 3171 | #ifdef MT6853 |
| 3172 | #define CHIP_ID CHIP_ID_MT6853 |
| 3173 | #endif |
| 3174 | #ifdef MT6833 |
| 3175 | #define CHIP_ID CHIP_ID_MT6833 |
| 3176 | #endif |
| 3177 | #if (defined(MT6880) || ((defined(MT6880) && defined(CHIP10992)))) |
| 3178 | #define CHIP_ID CHIP_ID_MT6880 |
| 3179 | #endif |
| 3180 | #if (defined(MT6890) || ((defined(MT6890) && defined(CHIP10992)))) |
| 3181 | #define CHIP_ID CHIP_ID_MT6890 |
| 3182 | #endif |
| 3183 | #if (defined(MT2735) || ((defined(MT2735) && defined(CHIP10992)))) |
| 3184 | #define CHIP_ID CHIP_ID_MT2735 |
| 3185 | #endif |
| 3186 | #ifdef MT6893 |
| 3187 | #undef CHIP_ID /* we are undefining the chip id since MT6885 is also enabled for MT6893 project*/ |
| 3188 | #define CHIP_ID CHIP_ID_MT6893 |
| 3189 | #endif |
| 3190 | #ifdef MT6877 |
| 3191 | #define CHIP_ID CHIP_ID_MT6877 |
| 3192 | #endif |
| 3193 | #ifdef MT6855 |
| 3194 | #define CHIP_ID CHIP_ID_MT6855 |
| 3195 | #endif |
| 3196 | |
| 3197 | #if defined(L1_SIM) || (defined(ESIM_BUILD_CONFIG) && (ESIM_BUILD_CONFIG == ESIM_MULTI_MODE_ON_FIBERS)) |
| 3198 | #ifdef L1D_TEST |
| 3199 | #undef CHIP_ID |
| 3200 | #define CHIP_ID CHIP_ID_MT6293 |
| 3201 | |
| 3202 | #else |
| 3203 | |
| 3204 | #if (defined __MD93__) |
| 3205 | #undef CHIP_ID |
| 3206 | #define CHIP_ID CHIP_ID_MT6292 |
| 3207 | #endif |
| 3208 | #endif |
| 3209 | #endif |
| 3210 | |
| 3211 | |
| 3212 | #define IS_CHIP_SER(ID) ( CHIP_SER(CHIP_ID)==CHIP_SER(ID) ) |
| 3213 | #define IS_CHIP_SER_AND_LATTER(ID) ( CHIP_NUM(CHIP_ID)>=CHIP_NUM(ID) && IS_CHIP_SER(ID) ) |
| 3214 | #define IS_CHIP_SER_AND_BEFORE(ID) ( CHIP_NUM(CHIP_ID)<=CHIP_NUM(ID) && IS_CHIP_SER(ID) ) |
| 3215 | |
| 3216 | #define IS_FPGA_TARGET ( CHIP_ID==CHIP_ID_FPGA ) |
| 3217 | #define IS_CHIP_TARGET ( CHIP_ID!=CHIP_ID_FPGA ) |
| 3218 | |
| 3219 | #define IS_CHIP_MT6208 ( CHIP_ID==CHIP_ID_MT6208 ) |
| 3220 | #define IS_CHIP_MT6205A ( CHIP_ID==CHIP_ID_MT6205A) |
| 3221 | #define IS_CHIP_MT6205B ( CHIP_ID==CHIP_ID_MT6205B) |
| 3222 | #define IS_CHIP_MT6205 ((CHIP_ID==CHIP_ID_MT6205A) || (CHIP_ID==CHIP_ID_MT6205B)) |
| 3223 | #define IS_CHIP_MT6218A ( CHIP_ID==CHIP_ID_MT6218A) |
| 3224 | #define IS_CHIP_MT6218B ( CHIP_ID==CHIP_ID_MT6218B) |
| 3225 | #define IS_CHIP_MT6218 ((CHIP_ID==CHIP_ID_MT6218A) || (CHIP_ID==CHIP_ID_MT6218B)) |
| 3226 | #define IS_CHIP_MT6219 ( CHIP_ID==CHIP_ID_MT6219 ) |
| 3227 | #define IS_CHIP_MT6228 ( CHIP_ID==CHIP_ID_MT6228 ) |
| 3228 | #define IS_CHIP_MT6229 ( CHIP_ID==CHIP_ID_MT6229 ) |
| 3229 | #define IS_CHIP_MT6227 ( CHIP_ID==CHIP_ID_MT6227 ) |
| 3230 | #define IS_CHIP_MT6225 ( CHIP_ID==CHIP_ID_MT6225 ) |
| 3231 | #define IS_CHIP_MT6268T ( CHIP_ID==CHIP_ID_MT6268T) |
| 3232 | #define IS_CHIP_MT6268T_DMAC ( CHIP_ID==CHIP_ID_MT6268T_DMAC ) |
| 3233 | #define IS_CHIP_MT6268H ((CHIP_ID==CHIP_ID_MT6268T) && (defined MT6268H) ) |
| 3234 | #define IS_CHIP_MT6223 ( CHIP_ID==CHIP_ID_MT6223 ) |
| 3235 | #define IS_CHIP_MT6238 ( CHIP_ID==CHIP_ID_MT6238 ) |
| 3236 | #define IS_CHIP_TK6516 ( CHIP_ID==CHIP_ID_TK6516 ) |
| 3237 | #define IS_CHIP_MT6268A ( CHIP_ID==CHIP_ID_MT6268A) |
| 3238 | #define IS_CHIP_MT6268B ( CHIP_ID==CHIP_ID_MT6268 ) |
| 3239 | #define IS_CHIP_MT6268 ((CHIP_ID==CHIP_ID_MT6268A) || (CHIP_ID==CHIP_ID_MT6268)) /* MT6268 includes MT6268A and MT6268 */ |
| 3240 | #define IS_CHIP_MT6516 ( CHIP_ID==CHIP_ID_MT6516 ) |
| 3241 | #define IS_CHIP_MT6253T ( CHIP_ID==CHIP_ID_MT6253T) |
| 3242 | #define IS_CHIP_MT6253 ((CHIP_ID==CHIP_ID_MT6253T) || (CHIP_ID==CHIP_ID_MT6253) || (CHIP_ID==CHIP_ID_MT6252L) || (CHIP_ID==CHIP_ID_MT6252H)) /* MT6253 includes MT6253T,MT6253,MT6252L,MT6252H */ |
| 3243 | #define IS_CHIP_MT6252L ( CHIP_ID==CHIP_ID_MT6252L) |
| 3244 | #define IS_CHIP_MT6252H ( CHIP_ID==CHIP_ID_MT6252H) |
| 3245 | #define IS_CHIP_MT6252 ((CHIP_ID==CHIP_ID_MT6252L) || (CHIP_ID==CHIP_ID_MT6252H)) |
| 3246 | #define IS_CHIP_MT6253EL ( IS_CHIP_MT6252 ) |
| 3247 | #define IS_CHIP_MT6236 ( CHIP_ID==CHIP_ID_MT6236 ) |
| 3248 | #define IS_CHIP_MT6270A ( CHIP_ID==CHIP_ID_MT6270A) |
| 3249 | #define IS_CHIP_MT6276 ( CHIP_ID==CHIP_ID_MT6276 ) |
| 3250 | #define IS_CHIP_MT6256 ( CHIP_ID==CHIP_ID_MT6256 ) |
| 3251 | #define IS_CHIP_MT6251 ( CHIP_ID==CHIP_ID_MT6251 ) |
| 3252 | #define IS_CHIP_MT6573 ( CHIP_ID==CHIP_ID_MT6573 ) |
| 3253 | #define IS_CHIP_MT6575 ((CHIP_ID==CHIP_ID_MT6575) || (CHIP_ID==CHIP_ID_MT6577)) |
| 3254 | #define IS_CHIP_MT6577 ( CHIP_ID==CHIP_ID_MT6577 ) |
| 3255 | #define IS_CHIP_MT6250 ( CHIP_ID==CHIP_ID_MT6250 ) |
| 3256 | #define IS_CHIP_MT6280 ( CHIP_ID==CHIP_ID_MT6280 ) |
| 3257 | #define IS_CHIP_MT6925 ( CHIP_ID==CHIP_ID_MT6229 ) /* Temp add for MT6925 simulation */ |
| 3258 | #define IS_CHIP_TK6280 ( CHIP_ID==CHIP_ID_MT6270A) /* For TK6280 FPGA */ |
| 3259 | #define IS_CHIP_MT6583_MD1 ( CHIP_ID==CHIP_ID_MT6583_MD1 ) |
| 3260 | #define IS_CHIP_MT6583_MD2 ( CHIP_ID==CHIP_ID_MT6583_MD2 ) |
| 3261 | #define IS_CHIP_MT6572 ((CHIP_ID==CHIP_ID_MT6572) || (CHIP_ID==CHIP_ID_MT6582)) |
| 3262 | #define IS_CHIP_MT6582 ( CHIP_ID==CHIP_ID_MT6582 ) |
| 3263 | #define IS_CHIP_MT6290 ( CHIP_ID==CHIP_ID_MT6290 ) |
| 3264 | #define IS_CHIP_MT6595 ( CHIP_ID==CHIP_ID_MT6595 ) |
| 3265 | #define IS_CHIP_MT6752_MD1 ( CHIP_ID==CHIP_ID_MT6752_MD1 ) |
| 3266 | #define IS_CHIP_MT6752_MD2 ( CHIP_ID==CHIP_ID_MT6752_MD2 ) |
| 3267 | #define IS_CHIP_TK6291 ( CHIP_ID==CHIP_ID_TK6291 ) |
| 3268 | #define IS_CHIP_MT6755 ( CHIP_ID==CHIP_ID_MT6755 ) |
| 3269 | #define IS_CHIP_MT6292 (( CHIP_ID==CHIP_ID_MT6292 ) || (CHIP_ID==CHIP_ID_MT6799)) |
| 3270 | #define IS_CHIP_MT6799 ( CHIP_ID==CHIP_ID_MT6799 ) |
| 3271 | #define IS_CHIP_MT6293 ((CHIP_ID==CHIP_ID_MT6293) || (CHIP_ID==CHIP_ID_MT6763) || (CHIP_ID==CHIP_ID_MT6739) || (CHIP_ID==CHIP_ID_MT6771) || (CHIP_ID==CHIP_ID_MT6765) || (CHIP_ID==CHIP_ID_TRINITYE1) || (CHIP_ID==CHIP_ID_TRINITYL)) |
| 3272 | #define IS_CHIP_MT6763 (CHIP_ID==CHIP_ID_MT6763) |
| 3273 | #define IS_CHIP_MT6739 (CHIP_ID==CHIP_ID_MT6739) |
| 3274 | #define IS_CHIP_MT6771 (CHIP_ID==CHIP_ID_MT6771) |
| 3275 | #define IS_CHIP_MT6765 (CHIP_ID==CHIP_ID_MT6765) |
| 3276 | #define IS_CHIP_MT6295 ((CHIP_ID==CHIP_ID_MT6295M) || (CHIP_ID==CHIP_ID_MT3967) || (CHIP_ID==CHIP_ID_MT6779)) |
| 3277 | #define IS_CHIP_MT3967 (CHIP_ID==CHIP_ID_MT3967) |
| 3278 | #define IS_CHIP_MT6779 (CHIP_ID==CHIP_ID_MT6779) |
| 3279 | #define IS_CHIP_MT6297 ((CHIP_ID==CHIP_ID_MT6297) || (CHIP_ID==CHIP_ID_MT6885) || (CHIP_ID==CHIP_ID_MERCURY) || (CHIP_ID==CHIP_ID_MT6873) || (CHIP_ID==CHIP_ID_MT6853) || (CHIP_ID==CHIP_ID_MT6833) || (CHIP_ID==CHIP_ID_MT6880) || (CHIP_ID==CHIP_ID_MT6890) || (CHIP_ID==CHIP_ID_MT2735) || (CHIP_ID==CHIP_ID_MT6893) || (CHIP_ID==CHIP_ID_MT6877) || (CHIP_ID==CHIP_ID_MT6855)) |
| 3280 | #define IS_CHIP_MT6885 ((CHIP_ID==CHIP_ID_MT6885) || (CHIP_ID==CHIP_ID_MERCURY) || (CHIP_ID==CHIP_ID_MT6873) || (CHIP_ID==CHIP_ID_MT6853) || (CHIP_ID==CHIP_ID_MT6833) || (CHIP_ID==CHIP_ID_MT6880) || (CHIP_ID==CHIP_ID_MT6890) || (CHIP_ID==CHIP_ID_MT2735) || (CHIP_ID==CHIP_ID_MT6893) || (CHIP_ID==CHIP_ID_MT6877) || (CHIP_ID==CHIP_ID_MT6855)) |
| 3281 | #define IS_CHIP_MERCURY (CHIP_ID==CHIP_ID_MERCURY) |
| 3282 | #define IS_CHIP_MT6873 (CHIP_ID==CHIP_ID_MT6873) |
| 3283 | #define IS_CHIP_MT6853 (CHIP_ID==CHIP_ID_MT6853) |
| 3284 | #define IS_CHIP_MT6833 (CHIP_ID==CHIP_ID_MT6833) |
| 3285 | #define IS_CHIP_MT6880 (CHIP_ID==CHIP_ID_MT6880) |
| 3286 | #define IS_CHIP_MT6890 (CHIP_ID==CHIP_ID_MT6890) |
| 3287 | #define IS_CHIP_MT2735 (CHIP_ID==CHIP_ID_MT2735) |
| 3288 | #define IS_CHIP_MT6893 (CHIP_ID==CHIP_ID_MT6893) |
| 3289 | #define IS_CHIP_MT6877 (CHIP_ID==CHIP_ID_MT6877) |
| 3290 | #define IS_CHIP_MT6855 (CHIP_ID==CHIP_ID_MT6855) |
| 3291 | |
| 3292 | /* For L1C usage */ |
| 3293 | /* CS3 requirement, CS3 would request us to update them */ |
| 3294 | #define IS_CHIP_MT623538 IS_CHIP_MT6238 |
| 3295 | #define IS_CHIP_MT6235_SER defined(MT6235B) |
| 3296 | #define IS_CHIP_MT6238_SER ( IS_CHIP_MT623538 && !IS_CHIP_MT6235_SER ) |
| 3297 | #define IS_HYPER_SLEEP_MODE_CHIP ((IS_CHIP_MT6238_SER || IS_CHIP_MT6516 || IS_CHIP_MT6268B || IS_CHIP_MT6253 || IS_CHIP_MT6236 || IS_CHIP_MT6256 || IS_CHIP_MT6251 || IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297) && !defined(MT6516_S00) ) |
| 3298 | // SM_EINT_ABORT_DEFECT: 27, 28, 25, 29, 23, (35,38), 6516 |
| 3299 | #define IS_SM_EINT_ABORT_DEFECT ( IS_CHIP_MT6227 || IS_CHIP_MT6228 || IS_CHIP_MT6225 || IS_CHIP_MT6229 || IS_CHIP_MT6223 || IS_CHIP_MT6238 ) |
| 3300 | // Total settling time = 26M settling time + PLL settling time |
| 3301 | #define IS_SEPARATE_PLL_SETTLING_CHIP ( IS_CHIP_MT6256 || IS_CHIP_MT6251 || IS_CHIP_MT6255 ) |
| 3302 | |
| 3303 | #ifdef __HYPER_SLEEP_MODE_CHIP__ |
| 3304 | #undef IS_HYPER_SLEEP_MODE_CHIP |
| 3305 | #define IS_HYPER_SLEEP_MODE_CHIP 1 |
| 3306 | #endif |
| 3307 | |
| 3308 | /*--------------------*/ |
| 3309 | /* For Dual MAC Group */ |
| 3310 | /*--------------------*/ |
| 3311 | #define IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6270A) ) |
| 3312 | |
| 3313 | /*------------------*/ |
| 3314 | /* For New 2G Modem */ |
| 3315 | /*------------------*/ |
| 3316 | #define IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6256) ) |
| 3317 | |
| 3318 | /*---------------------*/ |
| 3319 | /* For GSM/GPRS Group */ |
| 3320 | /*---------------------*/ |
| 3321 | #define IS_CHIP_MT6208_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6208) || IS_CHIP_SER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) ) |
| 3322 | #define IS_CHIP_MT6205_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6205A) || IS_CHIP_SER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) ) |
| 3323 | #define IS_CHIP_MT6205A_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6205A) || IS_CHIP_SER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) ) |
| 3324 | #define IS_CHIP_MT6205B_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6205B) || IS_CHIP_SER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) ) |
| 3325 | #define IS_CHIP_MT6218_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) ) |
| 3326 | #define IS_CHIP_MT6218A_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) ) |
| 3327 | #define IS_CHIP_MT6218B_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6218B) || IS_CHIP_SER(CHIP_ID_MT6227) ) |
| 3328 | #define IS_CHIP_MT6219_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6219) || IS_CHIP_SER(CHIP_ID_MT6227) ) |
| 3329 | #define IS_CHIP_MT6227_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6227) ) |
| 3330 | #define IS_CHIP_MT6228_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6228) ) |
| 3331 | #define IS_CHIP_MT6225_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6225) ) |
| 3332 | #define IS_CHIP_MT6295_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6295M) ) |
| 3333 | #define IS_CHIP_MT6297_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6297) ) |
| 3334 | #define IS_CHIP_MT6885_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6885) ) |
| 3335 | #define IS_CHIP_MT6853_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6853) ) |
| 3336 | |
| 3337 | |
| 3338 | /*----------------------------------*/ |
| 3339 | /* For Dual DSP Group (EGPRS Group) */ |
| 3340 | /*----------------------------------*/ |
| 3341 | #define IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6229) || IS_CHIP_SER(CHIP_ID_MT6223) || IS_CHIP_SER(CHIP_ID_MT6238) || IS_CHIP_SER(CHIP_ID_MT6253) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) ) |
| 3342 | /* For SAIC group */ |
| 3343 | /* Be careful!! MT6223 is a special chip without EDGE */ |
| 3344 | #define IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6223) || IS_CHIP_SER(CHIP_ID_MT6238) || IS_CHIP_SER(CHIP_ID_MT6253) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) ) |
| 3345 | #define IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6238) || IS_CHIP_SER(CHIP_ID_MT6253) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) ) |
| 3346 | #define IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6268A) || IS_CHIP_SER(CHIP_ID_MT6253) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) ) |
| 3347 | /* Be careful!! MT6253(T) is a special chip without EDGE */ |
| 3348 | #define IS_SAIC_CHIP_MT6253T_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6253T) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6236) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) ) |
| 3349 | #define IS_SAIC_CHIP_MT6253_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6253) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6236) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) ) |
| 3350 | #define IS_EDGE_SAIC_CHIP_MT6236_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6236) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) ) |
| 3351 | |
| 3352 | /*-------------------*/ |
| 3353 | /* For 2G RxD Group */ |
| 3354 | /*-------------------*/ |
| 3355 | #define IS_2GRXD_CHIP_MT6765_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6765) ) |
| 3356 | |
| 3357 | /*----------------------*/ |
| 3358 | /* For 2G MMDFE Group */ |
| 3359 | /*----------------------*/ |
| 3360 | #define IS_MMDFE_CHIP_MT6297_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6297) ) |
| 3361 | |
| 3362 | /*--------------------*/ |
| 3363 | /* For Specific Group */ |
| 3364 | /*--------------------*/ |
| 3365 | /* For SmartPhone Group */ |
| 3366 | #define IS_SMARTPHONE_CHIP_TK6516_AND_LATTER_VERSION ( IS_CHIP_TK6516 || IS_CHIP_MT6516 ) |
| 3367 | /* For 65NM chip Group */ |
| 3368 | #define IS_65NM_CHIP ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6268A) || IS_CHIP_SER(CHIP_ID_MT6256) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6276) ) |
| 3369 | /* For 65NM with BSI/BPI power down group*/ |
| 3370 | #define IS_65NM_CHIP_BSI_BPI_PWN ( IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_SER(CHIP_ID_MT6256) ) |
| 3371 | /* For Support us counter chip Group */ |
| 3372 | #define IS_USC_CHIP ( IS_CHIP_MT6268B || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6270A) || IS_CHIP_MT6268H || IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) ) |
| 3373 | /* For TDMA 8R/(6T), AuxADC chip */ |
| 3374 | #define IS_NEW_TDMA_CHIP ( IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) || IS_CHIP_MT6252 ) |
| 3375 | /* For chip with 32-bit of BSI_ENA */ |
| 3376 | #define IS_BSI_REG_32_BIT_CHIP ( IS_CHIP_MT6268T || IS_CHIP_MT6268 || IS_CHIP_MT6268H || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) ) |
| 3377 | /* For chip with 32-bit of BPI_ENA */ |
| 3378 | #define IS_BPI_REG_32_BIT_CHIP ( IS_CHIP_MT6268T || IS_CHIP_MT6268 || IS_CHIP_MT6268H || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) ) |
| 3379 | /* For chip with 48-bit of BPI_DATA */ |
| 3380 | #define IS_BPI_DATA_48_BIT_CHIP ( IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 ) |
| 3381 | /* For chip with 32-bit of BPI_DATA */ |
| 3382 | #define IS_BPI_DATA_32_BIT_CHIP ( !IS_BPI_DATA_48_BIT_CHIP ) |
| 3383 | /* For chip with 32-bit of BSI_CON */ |
| 3384 | #define IS_BSI_CON_32_BIT_CHIP ( IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293) |
| 3385 | /* For HW 8RWIN PM chip */ |
| 3386 | #define IS_HW_8RXWIN_PM_SUPPORT_CHIP ( IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) || IS_CHIP_MT6252 ) |
| 3387 | /* For SOC chip Group */ |
| 3388 | #define IS_SOC_CHIP ( IS_CHIP_SER(CHIP_ID_MT6253) || (IS_CHIP_SER(CHIP_ID_MT6256)&&(!IS_CHIP_MT6583_MD1)&&(!IS_CHIP_MT6583_MD2)&&(!IS_CHIP_MT6572)&&(!IS_CHIP_MT6290)&&(!IS_CHIP_MT6595)&&(!IS_CHIP_MT6752_MD1)&&(!IS_CHIP_MT6752_MD2)&&(!IS_CHIP_TK6291)&&(!IS_CHIP_MT6755)&&(!IS_CHIP_MT6292)&&(!IS_CHIP_MT6293)) ) |
| 3389 | /* For 3G group */ |
| 3390 | #define IS_3G_CHIP ( IS_CHIP_MT6268 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6276) ) |
| 3391 | /* For EDGE MTBF PSHO group */ |
| 3392 | #define IS_EDGE_MTBF_PSHO_CHIP ( IS_CHIP_SER(CHIP_ID_MT6270A) ) |
| 3393 | /* For EDGE RTTI FANR group */ |
| 3394 | #define IS_EDGE_RTTI_FANR_CHIP ( 0 ) // temp, RTTI and FANR is still under development |
| 3395 | |
| 3396 | #define IS_FM_ON_26M_CHIP ( IS_CHIP_MT6268 || IS_CHIP_MT6236 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) ) |
| 3397 | #define IS_DUAL_DSP_CHIP ( IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION && !(IS_CACHE_DSP_SUPPORT || IS_DSP_ARCHITECTURE_V4_SUPPORT) ) |
| 3398 | #define IS_DUAL_MAC_DSP_CHIP ( IS_CHIP_SER(CHIP_ID_MT6270A) ) |
| 3399 | #define IS_FD216_DSP_CHIP ( !IS_DUAL_MAC_DSP_CHIP ) |
| 3400 | /*IS_CHIP_EQ34311 (DSP central weighting window) is defined for L1C to adjust the upper bound to recalibrate 32k Xtal : 1=> upper bound 24; 0=> upper bound 32*/ |
| 3401 | #define IS_CHIP_EQ34311 ( IS_CHIP_MT6225 || IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION ) |
| 3402 | /* Modified By James, to avoid VC++ bug of that defined(MT6217) is always false */ |
| 3403 | #define IS_CHIP_MT6218B_AN2DN ( (defined MT6218B_AN) || (defined MT6218B_BN) || (defined MT6218B_CN) || (defined MT6218B_DN) ) |
| 3404 | #define IS_CHIP_MT6218B_EN ( (defined MT6218B_EN) ) |
| 3405 | #define IS_CHIP_MT6218B_FN ( (defined MT6218B_FN) ) |
| 3406 | #define IS_CHIP_MT6219_AV ( (defined MT6219_AV) ) |
| 3407 | #define IS_CHIP_MT6219_BV ( (defined MT6219_BV) ) |
| 3408 | #define IS_CHIP_MT6219_EV ( (defined MT6219_EV) ) |
| 3409 | #define IS_CHIP_MT6217 ( (defined CHIP_MT6217) || (defined MT6217) ) |
| 3410 | #define IS_CHIP_MT6227_S00 ( (defined MT6227_S00) || (defined MT6226_S00) || (defined MT6226M_S00) ) |
| 3411 | #define IS_CHIP_MT6227_S01 ( (defined MT6227_S01) || (defined MT6226_S01) || (defined MT6226M_S01) ) // !Caution:Plz also take care of chip MT6226 & MT6226M as using this compile option |
| 3412 | #define IS_CHIP_MT6227_S02 ( (defined MT6227_S02) || (defined MT6226_S02) || (defined MT6226M_S02) ) // !Caution:Plz also take care of chip MT6226 & MT6226M as using this compile option |
| 3413 | #define IS_CHIP_MT6227_D00 ( (defined MT6227D_S00) || (defined MT6226D_S00) || (defined MT6227DS_S00) || (defined MT6226DS_S00) ) |
| 3414 | #define IS_CHIP_MT6228_S00 ( (defined MT6228_S00) ) |
| 3415 | #define IS_CHIP_MT6228_S01 ( (defined MT6228_S01) ) |
| 3416 | #define IS_CHIP_MT6228_S02 ( (defined MT6228_S02) ) |
| 3417 | #define IS_CHIP_MT6225_S00 ( (defined MT6225_S00) ) |
| 3418 | #define IS_CHIP_MT6229_FPGA1 ( defined MT6229_FPGA1 ) |
| 3419 | #define IS_CHIP_MT6229_FPGA2 ( defined MT6229_FPGA2 ) |
| 3420 | #define IS_CHIP_MT6229_FPGA3 ( defined MT6229_FPGA3 ) |
| 3421 | #define IS_CHIP_MT6229_S00 ( (defined MT6229_S00) || (defined MT6230_S00) ) |
| 3422 | #define IS_CHIP_MT6229_S01 ( (defined MT6229_S01) || (defined MT6230_S01) ) |
| 3423 | #define IS_CHIP_MT6229_S02 ( (defined MT6229_S02) || (defined MT6230_S02) ) |
| 3424 | #define IS_CHIP_MT6223_S00 ( (defined MT6223_S00) || (defined MT6223P_S00) ) |
| 3425 | #define IS_CHIP_MT6268_S00 ( (defined MT6268_S00) ) |
| 3426 | #define IS_CHIP_MT6256_S00 ( (defined MT6256_S00) ) |
| 3427 | #define IS_CHIP_MT6256_S01 ( (defined MT6256_S01) ) |
| 3428 | #define IS_CHIP_MT6256_S02 ( (defined MT6256_S02) ) |
| 3429 | #define IS_CHIP_MT6251_S00 ( (defined MT6251_S00) ) |
| 3430 | #define IS_CHIP_MT6252_S00 ( (defined MT6253E_S00) || (defined MT6253L_S00) || (defined MT6252_S00) || (defined MT6252H_S00) ) |
| 3431 | #define IS_CHIP_MT6252_S01 ( (defined MT6253E_S01) || (defined MT6253L_S01) || (defined MT6252_S01) || (defined MT6252H_S01) ) |
| 3432 | #define IS_CHIP_MT6270A_E1 ( (defined MT6270A_S00) && !(defined __MT6270A_FPGA_HW_VER_E2__) ) |
| 3433 | #define IS_CHIP_MT6270A_E2 ( (defined MT6270A_S00) && (defined __MT6270A_FPGA_HW_VER_E2__) ) |
| 3434 | #define IS_CHIP_MT6276_S00 ( (defined MT6276_S00) ) |
| 3435 | #define IS_CHIP_MT6276_S01 ( (defined MT6276_S01) ) |
| 3436 | #define IS_CHIP_MT6573_S00 ( (defined MT6573_S00) ) |
| 3437 | #define IS_CHIP_MT6573_S01 ( (defined MT6573_S01) ) |
| 3438 | #define IS_CHIP_MT6575_S00 ( (defined MT6575_S00) ) |
| 3439 | #define IS_CHIP_MT6280_S00 ( (defined MT6280_S00) ) |
| 3440 | #define IS_CHIP_MT6280_S01 ( (defined MT6280_S01) ) |
| 3441 | #define IS_CHIP_MT6290_S00 ( (defined MT6290_S00) ) |
| 3442 | #define IS_CHIP_MT6290_S01 ( (defined MT6290_S01) ) |
| 3443 | |
| 3444 | /* For temparially modification */ |
| 3445 | /* Remove the compile option once MT6229 has been verified */ |
| 3446 | /* For FPGA old architecture without IR and Exchange Buffer on External SRAM */ |
| 3447 | /* 1: Full Function 6229 0: For FPGA old architecture */ |
| 3448 | #define IS_DSP_FULLFUNCTION_OF_6229 0 |
| 3449 | #define IS_EPSK_TX_SUPPORT (defined __EPSK_TX__) |
| 3450 | #define IS_PS_EPSK_TX_DISABLE (defined __EPSK_TX_SW_SWITCH_OFF__) |
| 3451 | /*.......................................................*/ |
| 3452 | |
| 3453 | #ifndef CHIP_ID |
| 3454 | #ifdef FPGA |
| 3455 | /*FPGA*/ #define CHIP_ID CHIP_ID_FPGA |
| 3456 | #endif |
| 3457 | #ifdef MT6208 |
| 3458 | /*MT6208*/ #define CHIP_ID CHIP_ID_MT6208 |
| 3459 | #endif |
| 3460 | #ifdef MT6205 |
| 3461 | /*MT6205*/ #define CHIP_ID CHIP_ID_MT6205A |
| 3462 | #endif |
| 3463 | #ifdef MT6205A |
| 3464 | /*MT6205A*/ #define CHIP_ID CHIP_ID_MT6205A |
| 3465 | #endif |
| 3466 | #ifdef MT6205B |
| 3467 | /*MT6205B*/ #define CHIP_ID CHIP_ID_MT6205B |
| 3468 | #endif |
| 3469 | #ifdef MT6218 |
| 3470 | /*MT6218*/ #define CHIP_ID CHIP_ID_MT6218A |
| 3471 | #endif |
| 3472 | #ifdef MT6218A |
| 3473 | /*MT6218A*/ #define CHIP_ID CHIP_ID_MT6218A |
| 3474 | #endif |
| 3475 | #ifdef MT6218B |
| 3476 | /*MT6218B*/ #define CHIP_ID CHIP_ID_MT6218B |
| 3477 | #endif |
| 3478 | #ifdef MT6219 |
| 3479 | /*MT6219*/ #define CHIP_ID CHIP_ID_MT6219 |
| 3480 | #endif |
| 3481 | #ifdef MT6217 |
| 3482 | /*MT6217*/ #define CHIP_ID CHIP_ID_MT6218B |
| 3483 | #endif |
| 3484 | #ifdef MT6228 |
| 3485 | /*MT6228*/ #define CHIP_ID CHIP_ID_MT6228 |
| 3486 | #endif |
| 3487 | #ifdef MT6229 |
| 3488 | /*MT6229*/ #define CHIP_ID CHIP_ID_MT6229 |
| 3489 | #endif |
| 3490 | #ifdef MT6230 |
| 3491 | /*MT6229*/ #define CHIP_ID CHIP_ID_MT6229 |
| 3492 | #endif |
| 3493 | #ifdef MT6226 /* For L1 MT6226==MT6227 */ |
| 3494 | /*MT6226*/ #define CHIP_ID CHIP_ID_MT6227 |
| 3495 | #endif |
| 3496 | #ifdef MT6227 |
| 3497 | /*MT6227*/ #define CHIP_ID CHIP_ID_MT6227 |
| 3498 | #endif |
| 3499 | #ifdef MT6226M /* For L1 MT6226M==MT6227 */ |
| 3500 | /*MT6226M*/ #define CHIP_ID CHIP_ID_MT6227 |
| 3501 | #endif |
| 3502 | #ifdef MT6226D /* For L1 MT6226D==MT6227 */ |
| 3503 | /*MT6226*/ #define CHIP_ID CHIP_ID_MT6227 |
| 3504 | #endif |
| 3505 | #ifdef MT6227D /* For L1 MT6227D==MT6227 */ |
| 3506 | /*MT6227*/ #define CHIP_ID CHIP_ID_MT6227 |
| 3507 | #endif |
| 3508 | #ifdef MT6226DS /* For L1 MT6226DS==MT6227 */ |
| 3509 | /*MT6226*/ #define CHIP_ID CHIP_ID_MT6227 |
| 3510 | #endif |
| 3511 | #ifdef MT6227DS /* For L1 MT6227DS==MT6227 */ |
| 3512 | /*MT6227*/ #define CHIP_ID CHIP_ID_MT6227 |
| 3513 | #endif |
| 3514 | #ifdef MT6225 |
| 3515 | /*MT6225*/ #define CHIP_ID CHIP_ID_MT6225 |
| 3516 | #endif |
| 3517 | #ifdef MT6268T |
| 3518 | #ifdef __DSP_FCORE4__ |
| 3519 | /*MT6268T*/ #define CHIP_ID CHIP_ID_MT6268T_DMAC |
| 3520 | #else |
| 3521 | /*MT6268T*/ #define CHIP_ID CHIP_ID_MT6268T |
| 3522 | #endif |
| 3523 | #endif |
| 3524 | #ifdef MT6268H /* For L1 MT6268H==MT6268T*/ |
| 3525 | /*MT6268H*/ #define CHIP_ID CHIP_ID_MT6268T |
| 3526 | #endif |
| 3527 | #ifdef MT6223 |
| 3528 | /*MT6223*/ #define CHIP_ID CHIP_ID_MT6223 |
| 3529 | #endif |
| 3530 | #ifdef MT6223P /* For L1 MT6223P==MT6223 */ |
| 3531 | /*MT6223*/ #define CHIP_ID CHIP_ID_MT6223 |
| 3532 | #endif |
| 3533 | #ifdef MT6238 |
| 3534 | /*MT6238*/ #define CHIP_ID CHIP_ID_MT6238 |
| 3535 | #endif |
| 3536 | #ifdef MT6235B /* For L1 MT6235B==MT6238 */ |
| 3537 | /*MT6235B*/ #define CHIP_ID CHIP_ID_MT6238 |
| 3538 | #endif |
| 3539 | #ifdef MT6239 /* For L1 MT6239==MT6238 */ |
| 3540 | /*MT6239*/ #define CHIP_ID CHIP_ID_MT6238 |
| 3541 | #endif |
| 3542 | #ifdef TK6516 |
| 3543 | /*TK6516*/ #define CHIP_ID CHIP_ID_TK6516 |
| 3544 | #endif |
| 3545 | #ifdef MT6268A |
| 3546 | /*MT6268A*/ #define CHIP_ID CHIP_ID_MT6268A |
| 3547 | #endif |
| 3548 | #ifdef MT6268 |
| 3549 | /*MT6268*/ #define CHIP_ID CHIP_ID_MT6268 |
| 3550 | #endif |
| 3551 | #ifdef MT6516 |
| 3552 | /*MT6516*/ #define CHIP_ID CHIP_ID_MT6516 |
| 3553 | #endif |
| 3554 | #ifdef MT6253T |
| 3555 | /*MT6253T*/ #define CHIP_ID CHIP_ID_MT6253T |
| 3556 | #endif |
| 3557 | #ifdef MT6253L |
| 3558 | /*MT6253*/ #define CHIP_ID CHIP_ID_MT6252L |
| 3559 | #endif |
| 3560 | #ifdef MT6270A |
| 3561 | /*MT6270A*/ #define CHIP_ID CHIP_ID_MT6270A |
| 3562 | #endif |
| 3563 | #ifdef TK6280 |
| 3564 | /*TK6280*/ #define CHIP_ID CHIP_ID_MT6270A /* For TK6280 FPGA development, The 2G part is similar to MT6270A FPGA */ |
| 3565 | #endif |
| 3566 | #ifdef MT6583 |
| 3567 | #if defined(__MD1__) |
| 3568 | /*MT6583*/ #define CHIP_ID CHIP_ID_MT6583_MD1 |
| 3569 | #elif defined(__MD2__) |
| 3570 | /*MT6583*/ #define CHIP_ID CHIP_ID_MT6583_MD2 |
| 3571 | #else |
| 3572 | #error |
| 3573 | #endif |
| 3574 | #endif |
| 3575 | #ifdef MT6752 |
| 3576 | #if defined(__MD1__) |
| 3577 | /*MT6583*/ #define CHIP_ID CHIP_ID_MT6752_MD1 |
| 3578 | #elif defined(__MD2__) |
| 3579 | /*MT6583*/ #define CHIP_ID CHIP_ID_MT6752_MD2 |
| 3580 | #else |
| 3581 | #error |
| 3582 | #endif |
| 3583 | #endif |
| 3584 | |
| 3585 | /* UESIM-MOLY */ |
| 3586 | #if defined(__UE_SIMULATOR__) |
| 3587 | #ifdef L1D_TEST |
| 3588 | /*MT6290*/ #undef CHIP_ID |
| 3589 | /*MT6290*/ #define CHIP_ID CHIP_ID_MT6290 |
| 3590 | #else |
| 3591 | /*MT6280*/ #undef CHIP_ID |
| 3592 | /*MT6280*/ #define CHIP_ID CHIP_ID_MT6280 |
| 3593 | #endif |
| 3594 | #endif |
| 3595 | #endif |
| 3596 | |
| 3597 | /* default setting */ |
| 3598 | #ifndef CHIP_ID |
| 3599 | #ifdef CHIP_TARGET |
| 3600 | /*CHIP*/ #define CHIP_ID CHIP_ID_MT6208 |
| 3601 | #else |
| 3602 | /*FPGA*/ #define CHIP_ID CHIP_ID_FPGA |
| 3603 | #endif |
| 3604 | #endif |
| 3605 | |
| 3606 | //CH modify for simulation environment |
| 3607 | #ifdef L1_SIM |
| 3608 | #if defined(MT6205) |
| 3609 | #define SIM_MT6205 MT6205 |
| 3610 | #elif defined(MT6208) |
| 3611 | #define SIM_MT6208 MT6208 |
| 3612 | #elif defined(MT6218) |
| 3613 | #define SIM_MT6218 MT6218 |
| 3614 | #elif defined(MT6229) |
| 3615 | #define SIM_MT6229 MT6229 |
| 3616 | #elif defined(MT6268T) |
| 3617 | #define SIM_MT6229 MT6268T |
| 3618 | #elif defined(MT6268) |
| 3619 | #define SIM_MT6229 MT6268 |
| 3620 | #elif defined(MT6268H) |
| 3621 | #define SIM_MT6229 MT6268T |
| 3622 | #elif defined(MT6583) |
| 3623 | #define SIM_MT6229 MT6583 |
| 3624 | #elif defined(MT6752) |
| 3625 | #define SIM_MT6229 MT6752 |
| 3626 | #elif defined(MT6291) |
| 3627 | #define SIM_MT6229 TK6291 |
| 3628 | #elif defined(MT6293) |
| 3629 | #define SIM_MT6229 MT6293 |
| 3630 | #elif defined(MT6763) |
| 3631 | #define SIM_MT6229 MT6763 |
| 3632 | #elif defined(MT6739) |
| 3633 | #define SIM_MT6229 MT6739 |
| 3634 | #elif defined(MT6771) |
| 3635 | #define SIM_MT6229 MT6771 |
| 3636 | #elif defined(MT6765) |
| 3637 | #define SIM_MT6229 MT6765 |
| 3638 | #elif defined(MT6295M) |
| 3639 | #define SIM_MT6229 MT6295M |
| 3640 | #elif defined(MT3967) |
| 3641 | #define SIM_MT6229 MT3967 |
| 3642 | #elif defined(MT6779) |
| 3643 | #define SIM_MT6229 MT6779 |
| 3644 | #elif ((defined(MT6297)) || (defined MT6885) || (defined MERCURY) || (defined MT6873) || (defined MT6853) || (defined MT6833) || (defined MT6880) || (defined MT6890) || (defined MT2735) || (defined MT6893) || (defined MT6877) || (defined MT6855)) |
| 3645 | #define SIM_MT6229 MT3967 |
| 3646 | // #else |
| 3647 | //#error |
| 3648 | #endif |
| 3649 | #endif |
| 3650 | |
| 3651 | /*===============================================================================================*/ |
| 3652 | |
| 3653 | /*------------------------------------------*/ |
| 3654 | /* Compile Option : */ |
| 3655 | /* ( 1) RF_BRIGHT2 */ |
| 3656 | /* ( 2) RF_BRIGHT4 */ |
| 3657 | /* ( 3) RF_AERO */ |
| 3658 | /* ( 4) RF_AERO1PLUS */ |
| 3659 | /* ( 5) RF_MT6116 */ |
| 3660 | /* ( 6) RF_MT6119 */ |
| 3661 | /* ( 7) RF_MT6119C */ |
| 3662 | /* ( 8) RF_MT6129A */ |
| 3663 | /* ( 9) RF_MT6129B */ |
| 3664 | /* (10) RF_MT6129C */ |
| 3665 | /* (11) RF_MT6129D */ |
| 3666 | /* (12) RF_MT6139B */ |
| 3667 | /* (13) RF_MT6139C */ |
| 3668 | /* (14) RF_MT6140A */ |
| 3669 | /* (16) RF_MT6139E */ |
| 3670 | /* ------------- */ |
| 3671 | /* (*) BRIGHT2_RF */ |
| 3672 | /*------------------------------------------*/ |
| 3673 | /* Use in L1D : */ |
| 3674 | /* ( 1) IS_RF_BRIGHT2 */ |
| 3675 | /* ( 2) IS_RF_BRIGHT4 */ |
| 3676 | /* ( 3) IS_RF_AERO */ |
| 3677 | /* ( 4) IS_RF_AERO1PLUS */ |
| 3678 | /* ( 5) IS_RF_MT6116 */ |
| 3679 | /* ( 6) IS_RF_MT6119 */ |
| 3680 | /* ( 7) IS_RF_MT6119C */ |
| 3681 | /* ( 8) IS_RF_MT6129A */ |
| 3682 | /* ( 9) IS_RF_MT6129B */ |
| 3683 | /* (10) IS_RF_MT6129C */ |
| 3684 | /* (11) IS_RF_MT6129D */ |
| 3685 | /*------------------------------------------*/ |
| 3686 | |
| 3687 | #define RF_ID_BRIGHT2 0x00000001 |
| 3688 | #define RF_ID_BRIGHT4 0x00000002 |
| 3689 | #define RF_ID_AERO 0x00000004 |
| 3690 | #define RF_ID_AERO1PLUS 0x00000008 |
| 3691 | #define RF_ID_POLARIS1 0x00000010 |
| 3692 | #define RF_ID_POLARIS2 0x00000020 |
| 3693 | #define RF_ID_SKY74045 0x00000040 |
| 3694 | #define RF_ID_BRIGHT5P 0x00000080 |
| 3695 | #define RF_ID_MT6116 0x00000100 |
| 3696 | #define RF_ID_MT6119 0x00000200 |
| 3697 | #define RF_ID_MT6119C 0x00000400 |
| 3698 | #define RF_ID_MT6129A 0x00000800 |
| 3699 | #define RF_ID_MT6129B 0x00001000 |
| 3700 | #define RF_ID_MT6129C 0x00002000 |
| 3701 | #define RF_ID_MT6129D 0x00004000 |
| 3702 | #define RF_ID_MT6139B 0x00008000 |
| 3703 | #define RF_ID_MT6139C 0x00010000 |
| 3704 | #define RF_ID_MT6140A 0x00020000 |
| 3705 | #define RF_ID_SKY74117 0x00040000 |
| 3706 | #define RF_ID_SKY74400 0x00080000 |
| 3707 | #define RF_ID_AERO2 0x00100000 |
| 3708 | #define RF_ID_MT6140B 0x00200000 |
| 3709 | #define RF_ID_MT6139E 0x00800000 |
| 3710 | #define RF_ID_SKY74137 0x01000000 |
| 3711 | #define RF_ID_MT6140C 0x02000000 |
| 3712 | #define RF_ID_GRF6201 0x04000000 |
| 3713 | #define RF_ID_IRFS3001 0x08000000 |
| 3714 | #define RF_ID_MT6140D 0x10000000 |
| 3715 | #define RF_ID_AG2550 0x10000001 |
| 3716 | #define RF_ID_AERO2E 0x10000002 |
| 3717 | #define RF_ID_QS1000 0x10000003 |
| 3718 | #define RF_ID_QS1001 0x10000004 |
| 3719 | #define RF_ID_AD6548 0x10000005 |
| 3720 | #define RF_ID_AD6546 0x10000006 |
| 3721 | #define RF_ID_CMOSEDGE 0x10000007 |
| 3722 | #define RF_ID_MTKSOC1 0x10000008 |
| 3723 | #define RF_ID_MT6256RF 0x10000009 |
| 3724 | #define RF_ID_MT6251RF 0x1000000a |
| 3725 | #define RF_ID_MT6253ELRF 0x1000000b // the same as MT6252RF |
| 3726 | #define RF_ID_MT6252RF 0x1000000c |
| 3727 | #define RF_ID_MT6162 0x1000000d |
| 3728 | #define RF_ID_MT6163 0x1000000e |
| 3729 | #define RF_ID_MT6255RF 0x1000000f |
| 3730 | #define RF_ID_MT6250RF 0x10000010 |
| 3731 | #define RF_ID_MT6280RF 0x10000011 |
| 3732 | #define RF_ID_MT6167 0x10000012 |
| 3733 | #define RF_ID_MT6160 0x10000013 |
| 3734 | #define RF_ID_MT6166 0x10000014 |
| 3735 | #define RF_ID_MT6169 0x10000015 |
| 3736 | #define RF_ID_MT6165 0x10000016 |
| 3737 | #define RF_ID_MT6261RF 0x10000017 |
| 3738 | #define RF_ID_MT6580RF 0x10000018 |
| 3739 | #define RF_ID_MT6176 0x10000019 |
| 3740 | #define RF_ID_MT6179 0x1000001a |
| 3741 | #define RF_ID_MT6570RF 0x1000001b |
| 3742 | #define RF_ID_MT6177L 0x1000001c |
| 3743 | #define RF_ID_MT6177M 0x1000001d |
| 3744 | #define RF_ID_TRINITYE1 0x1000001e |
| 3745 | #define RF_ID_TRINITYL 0x1000001f |
| 3746 | #define RF_ID_MT6186 0x10000020 |
| 3747 | #define RF_ID_MT6186M 0x10000021 |
| 3748 | #define RF_ID_MT6190T 0x10000022 |
| 3749 | #define RF_ID_MT6190 0x10000023 |
| 3750 | #define RF_ID_MT6190M 0x10000024 |
| 3751 | #define RF_ID_MT6195 0x10000025 |
| 3752 | |
| 3753 | |
| 3754 | |
| 3755 | |
| 3756 | |
| 3757 | /* ------------------------------------------- */ |
| 3758 | /* Note that the RF ID should be named */ |
| 3759 | /* as a variable rather than BITMask */ |
| 3760 | /* from 0x10000000, */ |
| 3761 | /* the next RF ID should be 0x10000007...etc */ |
| 3762 | /* ------------------------------------------- */ |
| 3763 | |
| 3764 | #ifdef L1_SIM |
| 3765 | #ifdef BRIGHT2_EVB |
| 3766 | /*BRIGHT2*/ #define RF_ID RF_ID_BRIGHT2 |
| 3767 | #endif |
| 3768 | #ifdef BRIGHT4_EVB |
| 3769 | /*BRIGHT4*/ #define RF_ID RF_ID_BRIGHT4 |
| 3770 | #endif |
| 3771 | #ifdef BRIGHT5P_EVB |
| 3772 | /*BRIGHT5P*/#define RF_ID RF_ID_BRIGHT5P |
| 3773 | #endif |
| 3774 | #ifdef AERO_EVB |
| 3775 | /*AERO*/ #define RF_ID RF_ID_AERO |
| 3776 | #endif |
| 3777 | #ifdef SPRING_EVB |
| 3778 | /*AERO*/ #define RF_ID RF_ID_AERO |
| 3779 | #endif |
| 3780 | #ifdef POLARIS1_EVB |
| 3781 | /*RFMD*/ #define RF_ID RF_ID_POLARIS1 |
| 3782 | #endif |
| 3783 | #ifdef MT6119_EVB |
| 3784 | /*MT6119*/ #define RF_ID RF_ID_MT6119 |
| 3785 | #endif |
| 3786 | #ifdef FOUNTAIN_EVB |
| 3787 | /*MT6119*/ #define RF_ID RF_ID_MT6119 |
| 3788 | #endif |
| 3789 | #ifdef FOUNTAIN2_EVB |
| 3790 | /*MT6119*/ #define RF_ID RF_ID_MT6119C |
| 3791 | #endif |
| 3792 | #ifdef MT6129A_EVB |
| 3793 | /*MT6129A*/ #define RF_ID RF_ID_MT6129A |
| 3794 | #endif |
| 3795 | #ifdef OCEAN_EVB |
| 3796 | /*MT6129C*/ #define RF_ID RF_ID_MT6129C |
| 3797 | #endif |
| 3798 | #ifdef MT6139B_EVB |
| 3799 | /*MT6139B*/ #define RF_ID RF_ID_MT6139B |
| 3800 | #endif |
| 3801 | #ifdef MT6139C_EVB |
| 3802 | /*MT6139C*/ #define RF_ID RF_ID_MT6139C |
| 3803 | #endif |
| 3804 | #ifdef MT6139E_EVB |
| 3805 | /*MT6139E*/ #define RF_ID RF_ID_MT6139E |
| 3806 | #endif |
| 3807 | #ifdef MT6140A_EVB |
| 3808 | /*MT6140A*/ #define RF_ID RF_ID_MT6140A |
| 3809 | #endif |
| 3810 | #ifdef SKY74045_EVB |
| 3811 | /*SKY74045*/#define RF_ID RF_ID_SKY74045 |
| 3812 | #endif |
| 3813 | #ifdef SKY74117_EVB |
| 3814 | /*SKY74117*/#define RF_ID RF_ID_SKY74117 |
| 3815 | #endif |
| 3816 | #ifdef SKY74137_EVB |
| 3817 | /*SKY74137*/#define RF_ID RF_ID_SKY74137 |
| 3818 | #endif |
| 3819 | #ifdef GRF6201_EVB |
| 3820 | /*GRF6201*/ #define RF_ID RF_ID_GRF6201 |
| 3821 | #endif |
| 3822 | #ifdef IRFS3001_EVB |
| 3823 | /*IRFS3001*/#define RF_ID RF_ID_IRFS3001 |
| 3824 | #endif |
| 3825 | #ifdef AD6546_EVB |
| 3826 | /*AD6546*/ #define RF_ID RF_ID_AD6546 |
| 3827 | #endif |
| 3828 | #endif |
| 3829 | |
| 3830 | #define IS_RF_BRIGHT2 ( RF_ID==RF_ID_BRIGHT2 ) |
| 3831 | #define IS_RF_BRIGHT4 ( RF_ID==RF_ID_BRIGHT4 ) |
| 3832 | #define IS_RF_BRIGHT5P ( RF_ID==RF_ID_BRIGHT5P ) |
| 3833 | #define IS_RF_AERO ( RF_ID==RF_ID_AERO ) |
| 3834 | #define IS_RF_AERO1PLUS ( RF_ID==RF_ID_AERO1PLUS ) |
| 3835 | #define IS_RF_POLARIS1 ( RF_ID==RF_ID_POLARIS1 ) |
| 3836 | #define IS_RF_MT6116 ( RF_ID==RF_ID_MT6116 ) |
| 3837 | #define IS_RF_MT6119 ( RF_ID==RF_ID_MT6119 ) |
| 3838 | #define IS_RF_MT6119C ( RF_ID==RF_ID_MT6119C ) |
| 3839 | #define IS_RF_MT6129A ( RF_ID==RF_ID_MT6129A ) |
| 3840 | #define IS_RF_MT6129B ( RF_ID==RF_ID_MT6129B ) |
| 3841 | #define IS_RF_MT6129C ( RF_ID==RF_ID_MT6129C ) |
| 3842 | #define IS_RF_MT6129D ( RF_ID==RF_ID_MT6129D ) |
| 3843 | #define IS_RF_MT6139B ( RF_ID==RF_ID_MT6139B ) |
| 3844 | #define IS_RF_MT6139C ( RF_ID==RF_ID_MT6139C ) |
| 3845 | #define IS_RF_MT6139E ( RF_ID==RF_ID_MT6139E ) |
| 3846 | #define IS_RF_MT6140A ( RF_ID==RF_ID_MT6140A ) |
| 3847 | #define IS_RF_MT6140B ( RF_ID==RF_ID_MT6140B ) |
| 3848 | #define IS_RF_MT6140C ( RF_ID==RF_ID_MT6140C ) |
| 3849 | #define IS_RF_MT6140D ( RF_ID==RF_ID_MT6140D ) |
| 3850 | #define IS_RF_CMOSEDGE ( RF_ID==RF_ID_CMOSEDGE ) |
| 3851 | #define IS_RF_MTKSOC1 ( RF_ID==RF_ID_MTKSOC1 && CHIP_ID==CHIP_ID_MT6253 ) |
| 3852 | #define IS_RF_MTKSOC1T ( RF_ID==RF_ID_MTKSOC1 && CHIP_ID==CHIP_ID_MT6253T ) |
| 3853 | #define IS_RF_MT6253ELRF ( RF_ID==RF_ID_MT6252RF ) |
| 3854 | #define IS_RF_MT6252RF ( RF_ID==RF_ID_MT6252RF ) |
| 3855 | #define IS_RF_SKY74045 ( RF_ID==RF_ID_SKY74045 ) |
| 3856 | #define IS_RF_SKY74117 ( RF_ID==RF_ID_SKY74117 ) |
| 3857 | #define IS_RF_SKY74400 ( RF_ID==RF_ID_SKY74400 ) |
| 3858 | #define IS_RF_AERO2 ( RF_ID==RF_ID_AERO2 ) |
| 3859 | #define IS_RF_SKY74137 ( RF_ID==RF_ID_SKY74137 ) |
| 3860 | #define IS_RF_GRF6201 ( RF_ID==RF_ID_GRF6201 ) |
| 3861 | #define IS_RF_IRFS3001 ( RF_ID==RF_ID_IRFS3001 ) |
| 3862 | #define IS_RF_AD6548 ( RF_ID==RF_ID_AD6548 ) |
| 3863 | #define IS_RF_AD6546 ( RF_ID==RF_ID_AD6546 ) |
| 3864 | #define IS_RF_MT6256RF ( RF_ID==RF_ID_MT6256RF ) |
| 3865 | #define IS_RF_MT6255RF ( RF_ID==RF_ID_MT6255RF ) |
| 3866 | #define IS_RF_MT6251RF ( RF_ID==RF_ID_MT6251RF ) |
| 3867 | #define IS_RF_MT6162 ( ((defined RF_ID) && RF_ID==RF_ID_MT6162) || ((defined UL1D_RF_ID) && UL1D_RF_ID==UL1D_RF_ID_MT6162) ) |
| 3868 | #define IS_RF_MT6163 ( RF_ID==RF_ID_MT6163 ) |
| 3869 | #define IS_RF_MT6250RF ( RF_ID==RF_ID_MT6250RF ) |
| 3870 | #define IS_RF_MT6280RF ( RF_ID==RF_ID_MT6280RF ) |
| 3871 | #define IS_RF_MT6167 ( RF_ID==RF_ID_MT6167 ) |
| 3872 | #define IS_RF_MT6166 ( RF_ID==RF_ID_MT6166 ) |
| 3873 | #define IS_RF_MT6169 ( RF_ID==RF_ID_MT6169 ) |
| 3874 | #define IS_RF_MT6165 ( RF_ID==RF_ID_MT6165 ) |
| 3875 | #define IS_RF_MT6176 ( RF_ID==RF_ID_MT6176 ) |
| 3876 | #define IS_RF_MT6179 ( RF_ID==RF_ID_MT6179 ) |
| 3877 | #define IS_RF_MT6177L ( RF_ID==RF_ID_MT6177L ) |
| 3878 | #define IS_RF_MT6177M ( RF_ID==RF_ID_MT6177M ) |
| 3879 | #define IS_RF_TRINITYE1 ( RF_ID==RF_ID_TRINITYE1 ) |
| 3880 | #define IS_RF_TRINITYL ( RF_ID==RF_ID_TRINITYL ) |
| 3881 | #define IS_RF_MT6186 ( RF_ID==RF_ID_MT6186 ) |
| 3882 | #define IS_RF_MT6186M ( RF_ID==RF_ID_MT6186M ) |
| 3883 | #define IS_RF_MT6190T (( RF_ID==RF_ID_MT6190T )||( RF_ID==RF_ID_MT6190 )||( RF_ID==RF_ID_MT6190M )) || ( RF_ID == RF_ID_MT6195 ) |
| 3884 | #define IS_RF_MT6190 (( RF_ID==RF_ID_MT6190 )||( RF_ID==RF_ID_MT6190M )) || ( RF_ID == RF_ID_MT6195 ) |
| 3885 | #define IS_RF_MT6190M ( RF_ID==RF_ID_MT6190M ) |
| 3886 | #define IS_RF_MT6195 ( RF_ID==RF_ID_MT6195 ) |
| 3887 | |
| 3888 | /*.......................................................*/ |
| 3889 | |
| 3890 | #ifndef RF_ID |
| 3891 | #ifdef BRIGHT2_RF |
| 3892 | /*BRIGHT2*/ #define RF_ID RF_ID_BRIGHT2 |
| 3893 | #endif |
| 3894 | #ifdef BRIGHT4_RF |
| 3895 | /*BRIGHT4*/ #define RF_ID RF_ID_BRIGHT4 |
| 3896 | #endif |
| 3897 | #ifdef BRIGHT5P_RF |
| 3898 | /*BRIGHT5P*/#define RF_ID RF_ID_BRIGHT5P |
| 3899 | #endif |
| 3900 | #ifdef AERO_RF |
| 3901 | /*AERO*/ #define RF_ID RF_ID_AERO |
| 3902 | #endif |
| 3903 | #ifdef AERO1PLUS_RF |
| 3904 | /*AERO*/ #define RF_ID RF_ID_AERO1PLUS |
| 3905 | #endif |
| 3906 | #ifdef POLARIS1_RF |
| 3907 | /*RFMD*/ #define RF_ID RF_ID_POLARIS1 |
| 3908 | #endif |
| 3909 | #ifdef MT6116_RF |
| 3910 | /*MT6116*/ #define RF_ID RF_ID_MT6116 |
| 3911 | #endif |
| 3912 | #ifdef MT6119_RF |
| 3913 | /*MT6119*/ #define RF_ID RF_ID_MT6119 |
| 3914 | #endif |
| 3915 | #ifdef MT6119C_RF |
| 3916 | /*MT6119*/ #define RF_ID RF_ID_MT6119C |
| 3917 | #endif |
| 3918 | #ifdef MT6129A_RF |
| 3919 | /*MT6129A*/ #define RF_ID RF_ID_MT6129A |
| 3920 | #endif |
| 3921 | #ifdef MT6129B_RF |
| 3922 | /*MT6129B*/ #define RF_ID RF_ID_MT6129B |
| 3923 | #endif |
| 3924 | #ifdef MT6129C_RF |
| 3925 | /*MT6129C*/ #define RF_ID RF_ID_MT6129C |
| 3926 | #endif |
| 3927 | #ifdef MT6129D_RF |
| 3928 | /*MT6129D*/ #define RF_ID RF_ID_MT6129D |
| 3929 | #endif |
| 3930 | #ifdef MT6139B_RF |
| 3931 | /*MT6139B*/ #define RF_ID RF_ID_MT6139B |
| 3932 | #endif |
| 3933 | #ifdef MT6139C_RF |
| 3934 | /*MT6139C*/ #define RF_ID RF_ID_MT6139C |
| 3935 | #endif |
| 3936 | #ifdef MT6139E_RF |
| 3937 | /*MT6139E*/ #define RF_ID RF_ID_MT6139E |
| 3938 | #endif |
| 3939 | #ifdef MT6140A_RF |
| 3940 | /*MT6140A*/ #define RF_ID RF_ID_MT6140A |
| 3941 | #endif |
| 3942 | #ifdef MT6140B_RF |
| 3943 | /*MT6140B*/ #define RF_ID RF_ID_MT6140B |
| 3944 | #endif |
| 3945 | #ifdef MT6140C_RF |
| 3946 | /*MT6140C*/ #define RF_ID RF_ID_MT6140C |
| 3947 | #endif |
| 3948 | #ifdef MT6140D_RF |
| 3949 | /*MT6140D*/ #define RF_ID RF_ID_MT6140D |
| 3950 | #endif |
| 3951 | #ifdef CMOSEDGE_RF |
| 3952 | /*CMOSEDGE*/#define RF_ID RF_ID_CMOSEDGE |
| 3953 | #endif |
| 3954 | #ifdef MTKSOC1_RF |
| 3955 | /*MTKSOC1*/ #define RF_ID RF_ID_MTKSOC1 |
| 3956 | #endif |
| 3957 | #ifdef MT6256RF_RF |
| 3958 | /*MT6256RF*/#define RF_ID RF_ID_MT6256RF |
| 3959 | #endif |
| 3960 | #ifdef MT6255RF_RF |
| 3961 | /*MT6255RF*/#define RF_ID RF_ID_MT6255RF |
| 3962 | #endif |
| 3963 | #ifdef MT6250RF_RF |
| 3964 | /*MT6250RF*/#define RF_ID RF_ID_MT6250RF |
| 3965 | #endif |
| 3966 | #ifdef MT6280RF_2G_RF |
| 3967 | /*MT6280RF*/#define RF_ID RF_ID_MT6280RF |
| 3968 | #endif |
| 3969 | #ifdef MT6169_2G_RF |
| 3970 | /*MT6169*/ #define RF_ID RF_ID_MT6169 |
| 3971 | #endif |
| 3972 | #ifdef MT6166_2G_RF |
| 3973 | /*MT6166*/ #define RF_ID RF_ID_MT6166 |
| 3974 | #endif |
| 3975 | #ifdef MT6165_2G_RF |
| 3976 | /*MT6165*/ #define RF_ID RF_ID_MT6165 |
| 3977 | #endif |
| 3978 | #ifdef MT6176_2G_RF |
| 3979 | /*MT6176*/ #define RF_ID RF_ID_MT6176 |
| 3980 | #endif |
| 3981 | #ifdef MT6179_2G_RF |
| 3982 | /*MT6179*/ #define RF_ID RF_ID_MT6179 |
| 3983 | #endif |
| 3984 | #ifdef MT6177L_2G_RF |
| 3985 | /*MT6177L*/ #define RF_ID RF_ID_MT6177L |
| 3986 | #endif |
| 3987 | #ifdef MT6177M_2G_RF |
| 3988 | /*MT6177M*/ #define RF_ID RF_ID_MT6177M |
| 3989 | #endif |
| 3990 | #ifdef TRINITYE1_2G_RF |
| 3991 | /*Trinity*/ #define RF_ID RF_ID_TRINITYE1 |
| 3992 | #endif |
| 3993 | #ifdef TRINITYL_2G_RF |
| 3994 | /*Trinity*/ #define RF_ID RF_ID_TRINITYL |
| 3995 | #endif |
| 3996 | #ifdef MT6185M_2G_RF |
| 3997 | /*Trinity*/ #define RF_ID RF_ID_TRINITYL |
| 3998 | #endif |
| 3999 | #ifdef MT6186_2G_RF |
| 4000 | /*Trinity*/ #define RF_ID RF_ID_MT6186 |
| 4001 | #endif |
| 4002 | #ifdef MT6186M_2G_RF |
| 4003 | /*Trinity*/ #define RF_ID RF_ID_MT6186M |
| 4004 | #endif |
| 4005 | #ifdef TRINITYE1_RF |
| 4006 | // #define RF_ID RF_ID_TRINITYE1 |
| 4007 | #endif |
| 4008 | #ifdef MT6190T_2G_RF |
| 4009 | /*MT6190T*/ #define RF_ID RF_ID_MT6190T |
| 4010 | #endif |
| 4011 | #ifdef MT6190_2G_RF |
| 4012 | /*MT6190*/ #define RF_ID RF_ID_MT6190 |
| 4013 | #endif |
| 4014 | #ifdef MT6190M_2G_RF |
| 4015 | /*MT6190M*/ #define RF_ID RF_ID_MT6190M |
| 4016 | #endif |
| 4017 | #ifdef MT6195_2G_RF |
| 4018 | /*COLUMBUSP*/ #define RF_ID RF_ID_MT6195 |
| 4019 | #endif |
| 4020 | #ifdef MT6251RF_RF |
| 4021 | /*MT6251RF*/#define RF_ID RF_ID_MT6251RF |
| 4022 | #endif |
| 4023 | #ifdef MT6253ELRF_RF |
| 4024 | /*MT6253EL*/#define RF_ID RF_ID_MT6252RF |
| 4025 | #endif |
| 4026 | #ifdef MT6252RF_RF |
| 4027 | /*MT6252RF*/#define RF_ID RF_ID_MT6252RF |
| 4028 | #endif |
| 4029 | #ifdef SKY74045_RF |
| 4030 | /*SKY74045*/#define RF_ID RF_ID_SKY74045 |
| 4031 | #endif |
| 4032 | #ifdef SKY74117_RF |
| 4033 | /*SKY74117*/#define RF_ID RF_ID_SKY74117 |
| 4034 | #endif |
| 4035 | #ifdef SKY74400_RF |
| 4036 | /*SKY74400*/#define RF_ID RF_ID_SKY74400 |
| 4037 | #endif |
| 4038 | #ifdef AERO2_RF |
| 4039 | /*AERO2*/ #define RF_ID RF_ID_AERO2 |
| 4040 | #endif |
| 4041 | #ifdef SKY74137_RF |
| 4042 | /*SKY74137*/#define RF_ID RF_ID_SKY74137 |
| 4043 | #endif |
| 4044 | #ifdef GRF6201_RF |
| 4045 | /*GRF6201*/ #define RF_ID RF_ID_GRF6201 |
| 4046 | #endif |
| 4047 | #ifdef IRFS3001_RF |
| 4048 | /*IRFS3001*/#define RF_ID RF_ID_IRFS3001 |
| 4049 | #endif |
| 4050 | #ifdef AD6548_RF |
| 4051 | /*AD6548*/ #define RF_ID RF_ID_AD6548 |
| 4052 | #endif |
| 4053 | #ifdef AD6546_RF |
| 4054 | /*AD6546*/ #define RF_ID RF_ID_AD6546 |
| 4055 | #endif |
| 4056 | #ifdef MT6162_RF |
| 4057 | /*MT6162*/ #define RF_ID RF_ID_MT6162 |
| 4058 | #endif |
| 4059 | #ifdef MT6163_2G_RF |
| 4060 | /*MT6163*/ #define RF_ID RF_ID_MT6163 |
| 4061 | #endif |
| 4062 | #ifdef MT6168_2G_RF |
| 4063 | /*MT6163*/ #define RF_ID RF_ID_MT6163 |
| 4064 | #endif |
| 4065 | #ifdef MT6162_DUAL_RF /* This is used just for TK6280 FPGA from Jay's request */ |
| 4066 | /*MT6162*/ #define RF_ID RF_ID_MT6162 |
| 4067 | #endif |
| 4068 | #endif |
| 4069 | |
| 4070 | /* default setting */ |
| 4071 | #ifndef RF_ID |
| 4072 | /*BRIGHT2*/ #define RF_ID RF_ID_BRIGHT2 |
| 4073 | #endif |
| 4074 | /*...........................................................................................................*/ |
| 4075 | |
| 4076 | #define IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT 1 |
| 4077 | |
| 4078 | #if defined(L1_SIM) && IS_CHIP_MT6292 |
| 4079 | #undef IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT |
| 4080 | #define IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT 0 |
| 4081 | #endif |
| 4082 | |
| 4083 | #if IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT |
| 4084 | #if IS_BPI_DATA_48_BIT_CHIP |
| 4085 | #error "dynamic allocation does not support 48 bits BPI" |
| 4086 | #endif |
| 4087 | #endif |
| 4088 | |
| 4089 | #if IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT && IS_CHIP_MT6297_AND_LATTER_VERSION |
| 4090 | #define IS_GL1D_CDF_SUPPORT 1 |
| 4091 | #else |
| 4092 | #define IS_GL1D_CDF_SUPPORT 0 |
| 4093 | #endif |
| 4094 | |
| 4095 | |
| 4096 | #define TURN_ON_PHONE_CALL_TRACE 0 //mtk13381 |
| 4097 | #define l1D_RXDFE_RCC_SYN_REG_SW_CNTRL 0 |
| 4098 | #define L1D_BASEBAND_MT6297_CHANGES 0 //mtk10455 |
| 4099 | #define TURN_ON_PHONE_CALL_TRACE_97 1 //debug trace for 97 |
| 4100 | |
| 4101 | //Usip restart process same as fd 216 flow |
| 4102 | #if IS_CHIP_MT6297_AND_LATTER_VERSION |
| 4103 | #define IS_L1D_MML1_LPWR_DSP_ENABLE 1 |
| 4104 | #else |
| 4105 | #define IS_L1D_MML1_LPWR_DSP_ENABLE 0 |
| 4106 | #endif |
| 4107 | |
| 4108 | #if defined(L1D_SIM) |
| 4109 | #define IS_GSIM_PATTERN_CHECK_ENABLE 0 |
| 4110 | #else |
| 4111 | #define IS_GSIM_PATTERN_CHECK_ENABLE 0 |
| 4112 | #endif |
| 4113 | |
| 4114 | /*===================================================================*/ |
| 4115 | /* CHIP Feature settings */ |
| 4116 | /*===================================================================*/ |
| 4117 | #if defined(__UMTS_NEW_ARCH__) |
| 4118 | #define L1D_WT_COBIN_ARCHITECTURE_SUPPORT 1 |
| 4119 | #define L1D_WT_COBIN_RUNTIME_SWITCH_SUPPORT 1 |
| 4120 | #else |
| 4121 | #define L1D_WT_COBIN_ARCHITECTURE_SUPPORT 0 |
| 4122 | #define L1D_WT_COBIN_RUNTIME_SWITCH_SUPPORT 0 |
| 4123 | #endif |
| 4124 | |
| 4125 | #if L1D_WT_COBIN_ARCHITECTURE_SUPPORT |
| 4126 | #if defined(L1_SIM) || (IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297) |
| 4127 | #define IS_GL1D_TW_COEXIST_SUPPORT 1 /* This feature can support W and T in SIM1. SIM2 is always W */ |
| 4128 | #else |
| 4129 | #define IS_GL1D_TW_COEXIST_SUPPORT 0 |
| 4130 | #endif /* IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 */ |
| 4131 | #else |
| 4132 | #define IS_GL1D_TW_COEXIST_SUPPORT 0 |
| 4133 | #endif |
| 4134 | |
| 4135 | #if L1D_WT_COBIN_ARCHITECTURE_SUPPORT || L1D_WT_COBIN_RUNTIME_SWITCH_SUPPORT |
| 4136 | #define L1D_WT_COBIN_UT_BEBUG 0 |
| 4137 | #if defined(__UMTS_FDD_MODE__) && !defined(__UMTS_TDD128_MODE__) |
| 4138 | #define L1D_WT_COBIN_UT_W_ONLY_BUILD 1 |
| 4139 | #else |
| 4140 | #define L1D_WT_COBIN_UT_W_ONLY_BUILD 0 |
| 4141 | #endif |
| 4142 | #if !defined(__UMTS_FDD_MODE__) && defined(__UMTS_TDD128_MODE__) |
| 4143 | #define L1D_WT_CBBIN_UT_T_ONLY_BUILD 1 |
| 4144 | #else |
| 4145 | #define L1D_WT_CBBIN_UT_T_ONLY_BUILD 0 |
| 4146 | #endif |
| 4147 | #else |
| 4148 | #define L1D_WT_COBIN_UT_BEBUG 0 |
| 4149 | #define L1D_WT_COBIN_UT_W_ONLY_BUILD 0 |
| 4150 | #define L1D_WT_CBBIN_UT_T_ONLY_BUILD 0 |
| 4151 | #endif |
| 4152 | |
| 4153 | #if L1D_WT_COBIN_ARCHITECTURE_SUPPORT && L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD |
| 4154 | #if !defined(__UMTS_FDD_MODE__) |
| 4155 | #define __UMTS_FDD_MODE__ 1 |
| 4156 | #endif |
| 4157 | #if !defined(__MTK_UL1_FDD__) |
| 4158 | #define __MTK_UL1_FDD__ 1 |
| 4159 | #endif |
| 4160 | #if !defined(__AST_TL1_TDD__) |
| 4161 | #define __AST_TL1_TDD__ 1 |
| 4162 | #endif |
| 4163 | #if !defined(__UMTS_TDD128_MODE__) |
| 4164 | #define __UMTS_TDD128_MODE__ 1 |
| 4165 | #endif |
| 4166 | #endif |
| 4167 | |
| 4168 | #if defined(L1D_SIM) && defined(L1D_TEST) && (IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6260)||IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6583_MD1)) |
| 4169 | #define IS_COSIM_ON_L1SIM_SUPPORT 1 |
| 4170 | #define IS_COSIM_ON_L1SIM_BYPASS_RF 1 |
| 4171 | #else |
| 4172 | #define IS_COSIM_ON_L1SIM_SUPPORT 0 |
| 4173 | #define IS_COSIM_ON_L1SIM_BYPASS_RF 0 |
| 4174 | #endif |
| 4175 | |
| 4176 | #if (IS_CHIP_MT6227_AND_LATTER_VERSION && !IS_CHIP_MT6227_S00 && !IS_CHIP_MT6228_S00 && !IS_CHIP_MT6228_S01) || (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_CHIP_MT6229_S00 && !IS_CHIP_MT6229_S01) |
| 4177 | #define L1D_PCH_2BURST_DECODE 1 |
| 4178 | #else |
| 4179 | #define L1D_PCH_2BURST_DECODE 0 |
| 4180 | #endif |
| 4181 | |
| 4182 | #if IS_CHIP_MT6227_D00 || IS_CHIP_MT6225_AND_LATTER_VERSION || (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_CHIP_MT6229_S00 && !IS_CHIP_MT6229_S01) |
| 4183 | #if defined(__MA_L1__) // MONZA29 and VENUS do not suppport PCH_1BURST_DECODE |
| 4184 | #define L1D_PCH_1BURST_DECODE 0 |
| 4185 | #else |
| 4186 | #if IS_CHIP_MT6223 && defined(L1D_TEST) |
| 4187 | #define L1D_PCH_1BURST_DECODE 0 |
| 4188 | #else |
| 4189 | #define L1D_PCH_1BURST_DECODE 1 |
| 4190 | #endif |
| 4191 | #endif |
| 4192 | #if IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION |
| 4193 | #define L1D_PCH_EMPTY_PATTERN 1 |
| 4194 | #else |
| 4195 | #define L1D_PCH_EMPTY_PATTERN 0 |
| 4196 | #endif |
| 4197 | #else |
| 4198 | #define L1D_PCH_1BURST_DECODE 0 |
| 4199 | #define L1D_PCH_EMPTY_PATTERN 0 |
| 4200 | #endif |
| 4201 | |
| 4202 | #if L1D_PCH_1BURST_DECODE |
| 4203 | #ifdef __MONITOR_PAGE_DURING_TRANSFER__ |
| 4204 | #if IS_NEW_L1D_ARCH_SUPPORT |
| 4205 | #if L1D_WT_COBIN_ARCHITECTURE_SUPPORT |
| 4206 | #define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 1 |
| 4207 | #elif defined(__UMTS_TDD128_MODE__) |
| 4208 | #define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 0 |
| 4209 | #else |
| 4210 | #define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 1 |
| 4211 | #endif |
| 4212 | #else |
| 4213 | #define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 1 |
| 4214 | #endif |
| 4215 | #else |
| 4216 | #define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 0 |
| 4217 | #endif |
| 4218 | #else |
| 4219 | #define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 0 |
| 4220 | #endif |
| 4221 | |
| 4222 | #if defined (__COTMS_TELEMATICS_SUPPORT__) |
| 4223 | #define IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT 1 |
| 4224 | #define IS_TELEMATICS_HIGH_TEMPERATURE_SUPPORT 1 |
| 4225 | #else |
| 4226 | #define IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT 0 |
| 4227 | #define IS_TELEMATICS_HIGH_TEMPERATURE_SUPPORT 0 |
| 4228 | #endif /* __COTMS_TELEMATICS_SUPPORT__ */ |
| 4229 | |
| 4230 | #if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT |
| 4231 | #if IS_TELEMATICS_HIGH_TEMPERATURE_SUPPORT |
| 4232 | #define TURN_ON_TELEMATICS_TRACE 1 |
| 4233 | #endif |
| 4234 | #endif |
| 4235 | |
| 4236 | /* Add for short PM */ |
| 4237 | #if IS_GPRS |
| 4238 | #define L1D_PM_ENHANCE 1 |
| 4239 | #if IS_CHIP_MT6227_D00 || IS_CHIP_MT6225_AND_LATTER_VERSION || (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_CHIP_MT6229_S00 && !IS_CHIP_MT6229_S01) |
| 4240 | #if defined(__MA_L1__) // MONZA29 and VENUS do not suppport 1R7PM |
| 4241 | #define L1D_PM_1R7PM 0 |
| 4242 | #else |
| 4243 | #if IS_CHIP_MT6223 && defined(L1D_TEST) |
| 4244 | #define L1D_PM_1R7PM 0 |
| 4245 | #else |
| 4246 | #define L1D_PM_1R7PM 1 |
| 4247 | #endif |
| 4248 | #endif |
| 4249 | #else |
| 4250 | #define L1D_PM_1R7PM 0 |
| 4251 | #endif |
| 4252 | #else // IS_GSM |
| 4253 | #if IS_HW_8RXWIN_PM_SUPPORT_CHIP |
| 4254 | #define L1D_PM_ENHANCE 1 |
| 4255 | #define L1D_PM_1R7PM 1 |
| 4256 | #else |
| 4257 | #define L1D_PM_ENHANCE 0 |
| 4258 | #define L1D_PM_1R7PM 0 |
| 4259 | #endif |
| 4260 | #endif |
| 4261 | |
| 4262 | #if IS_GPRS || L1D_PM_ENHANCE |
| 4263 | #define IS_RTX_5CWIN_SUPPORT 1 |
| 4264 | #else |
| 4265 | #define IS_RTX_5CWIN_SUPPORT 0 |
| 4266 | #endif |
| 4267 | |
| 4268 | /*Repeated ACCH*/ |
| 4269 | #if IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION |
| 4270 | #define IS_REPEATED_ACCH_SUPPORT 1 |
| 4271 | #else |
| 4272 | #define IS_REPEATED_ACCH_SUPPORT 0 |
| 4273 | #endif |
| 4274 | |
| 4275 | #if defined(FOUNTAIN2_EVB) || defined(MT6129A_EVB) |
| 4276 | #define RFVCO_SW_CONTROL |
| 4277 | #endif |
| 4278 | |
| 4279 | #if IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION |
| 4280 | #define FILLING_BYTES_2ND_DECODE |
| 4281 | #endif |
| 4282 | |
| 4283 | #ifdef __HO_IMPROVE__ |
| 4284 | #define NONSYNC_HO_IMPROVEMENT |
| 4285 | #endif |
| 4286 | |
| 4287 | #if IS_FD216_DSP_CHIP |
| 4288 | #if IS_CHIP_MT6268T || IS_CHIP_MT6268 || IS_EDGE_SAIC_CHIP_MT6236_AND_LATTER_VERSION |
| 4289 | #define IS_UPDATE_TIMESTAMP_FOR_DSP_CHIP 1 |
| 4290 | #else |
| 4291 | #define IS_UPDATE_TIMESTAMP_FOR_DSP_CHIP 0 |
| 4292 | #endif |
| 4293 | #else |
| 4294 | #define IS_UPDATE_TIMESTAMP_FOR_DSP_CHIP 1 |
| 4295 | #endif |
| 4296 | |
| 4297 | #if IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION |
| 4298 | #define IS_PM_DONE_CHECK_SUPPORT 1 |
| 4299 | #elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION |
| 4300 | #if defined(L1_SIM) |
| 4301 | #define IS_PM_DONE_CHECK_SUPPORT 1 |
| 4302 | #else |
| 4303 | #define IS_PM_DONE_CHECK_SUPPORT 0 |
| 4304 | #endif |
| 4305 | #else |
| 4306 | #define IS_PM_DONE_CHECK_SUPPORT 0 |
| 4307 | #endif |
| 4308 | |
| 4309 | #if IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION && !IS_CHIP_TK6516 |
| 4310 | #define IS_HYBRID_SAIC_SUPPORT 1 |
| 4311 | #else |
| 4312 | #define IS_HYBRID_SAIC_SUPPORT 0 |
| 4313 | #endif |
| 4314 | |
| 4315 | #if defined(__GEMINI__) |
| 4316 | |
| 4317 | #if defined(L1_SIM) |
| 4318 | #ifdef IS_GEMINI_SUPPORT |
| 4319 | #undef IS_GEMINI_SUPPORT |
| 4320 | #endif |
| 4321 | #endif |
| 4322 | |
| 4323 | #define IS_GEMINI_SUPPORT 1 |
| 4324 | #else |
| 4325 | #define IS_GEMINI_SUPPORT 0 |
| 4326 | #endif |
| 4327 | |
| 4328 | #if IS_GEMINI_SUPPORT |
| 4329 | #ifdef GEMINI_PLUS_GSM |
| 4330 | #define NUM_OF_SIM GEMINI_PLUS_GSM |
| 4331 | #else |
| 4332 | #define NUM_OF_SIM 2 |
| 4333 | #endif |
| 4334 | #else |
| 4335 | #define NUM_OF_SIM 1 |
| 4336 | #endif |
| 4337 | |
| 4338 | #define IS_GEMINI_1_2_SUPPORT 1 /*Gemini 1.2*/ |
| 4339 | |
| 4340 | #if defined(__GEMINI__) && defined(__UMTS_FDD_MODE__) |
| 4341 | #define IS_GEMINI_WGG_SUPPORT 1 /*WG+G*/ |
| 4342 | #else |
| 4343 | #define IS_GEMINI_WGG_SUPPORT 0 |
| 4344 | #endif |
| 4345 | |
| 4346 | #if defined(__GEMINI__) && defined(__UMTS_TDD128_MODE__) |
| 4347 | #define IS_GEMINI_TGG_SUPPORT 1 /*TG+G*/ |
| 4348 | #else |
| 4349 | #define IS_GEMINI_TGG_SUPPORT 0 |
| 4350 | #endif |
| 4351 | |
| 4352 | #if L1D_WT_COBIN_ARCHITECTURE_SUPPORT |
| 4353 | |
| 4354 | #if L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD && IS_GEMINI_WGG_SUPPORT |
| 4355 | #undef IS_GEMINI_TGG_SUPPORT |
| 4356 | #define IS_GEMINI_TGG_SUPPORT 1 |
| 4357 | #endif |
| 4358 | #if L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD && IS_GEMINI_TGG_SUPPORT |
| 4359 | #undef IS_GEMINI_WGG_SUPPORT |
| 4360 | #define IS_GEMINI_WGG_SUPPORT 1 |
| 4361 | #endif |
| 4362 | |
| 4363 | #if (IS_GEMINI_WGG_SUPPORT && !IS_GEMINI_TGG_SUPPORT) || (!IS_GEMINI_WGG_SUPPORT && IS_GEMINI_TGG_SUPPORT) |
| 4364 | #if L1D_WT_COBIN_UT_W_ONLY_BUILD || L1D_WT_CBBIN_UT_T_ONLY_BUILD |
| 4365 | #else |
| 4366 | #error "IS_GEMINI_WGG_SUPPORT and IS_GEMINI_TGG_SUPPORT should be aligned with WT Co-bin feature!" |
| 4367 | #endif |
| 4368 | #endif |
| 4369 | #endif |
| 4370 | |
| 4371 | #if defined(__GEMINI_WCDMA__) |
| 4372 | #define IS_GEMINI_WCDMA_SUPPORT 1 |
| 4373 | #else |
| 4374 | #define IS_GEMINI_WCDMA_SUPPORT 0 |
| 4375 | #endif |
| 4376 | |
| 4377 | #if IS_GEMINI_SUPPORT |
| 4378 | #if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 4379 | #define IS_FORCE_ENHENCE_PM_SUPPORT 1 |
| 4380 | #else |
| 4381 | #define IS_FORCE_ENHENCE_PM_SUPPORT 0 |
| 4382 | #endif |
| 4383 | #else |
| 4384 | #define IS_FORCE_ENHENCE_PM_SUPPORT 0 |
| 4385 | #endif |
| 4386 | #if defined(__MTK_TARGET__) |
| 4387 | #if IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 4388 | #define IS_SB_ENHANCE_TRACE_SUPPORT 1 |
| 4389 | #else |
| 4390 | #define IS_SB_ENHANCE_TRACE_SUPPORT 0 |
| 4391 | #endif |
| 4392 | #else |
| 4393 | #define IS_SB_ENHANCE_TRACE_SUPPORT 0 |
| 4394 | #endif |
| 4395 | |
| 4396 | // workaround for APC HW bug, APC cannot work when DCM with 13M. In RFTOOL mode, L1D need to disable DCM by itself |
| 4397 | #if IS_CHIP_MT6227 || IS_CHIP_MT6228 |
| 4398 | #define IS_RFTOOL_MODE_DCM_DISABLE 1 |
| 4399 | #define IS_IDLE_MODE_TX_DCM_26M 1 |
| 4400 | #else |
| 4401 | #define IS_RFTOOL_MODE_DCM_DISABLE 0 |
| 4402 | #define IS_IDLE_MODE_TX_DCM_26M 0 |
| 4403 | #endif |
| 4404 | |
| 4405 | #if IS_CHIP_MT6268 |
| 4406 | #define IS_HANDLE_TX_DCM_SUPPORT 1 |
| 4407 | #else |
| 4408 | #define IS_HANDLE_TX_DCM_SUPPORT 0 |
| 4409 | #endif |
| 4410 | |
| 4411 | #if defined(L1D_TEST) // loopback no APC/BSI issue |
| 4412 | #undef IS_RFTOOL_MODE_DCM_DISABLE |
| 4413 | #undef IS_IDLE_MODE_TX_DCM_26M |
| 4414 | #undef IS_HANDLE_TX_DCM_SUPPORT |
| 4415 | #define IS_RFTOOL_MODE_DCM_DISABLE 0 |
| 4416 | #define IS_IDLE_MODE_TX_DCM_26M 0 |
| 4417 | #define IS_HANDLE_TX_DCM_SUPPORT 0 |
| 4418 | #endif |
| 4419 | |
| 4420 | #if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_CHIP_MT6252 |
| 4421 | #define __NEW_L1D_ARCH__ |
| 4422 | #endif |
| 4423 | |
| 4424 | #if IS_COSIM_ON_L1SIM_SUPPORT |
| 4425 | #elif defined(L1D_TEST) // loopback not ready for NEW L1D ARCH |
| 4426 | #undef __NEW_L1D_ARCH__ |
| 4427 | #endif |
| 4428 | |
| 4429 | // new AGC/AFC update scheme |
| 4430 | #if defined(__NEW_L1D_ARCH__) |
| 4431 | #define IS_NEW_L1D_ARCH_SUPPORT 1 |
| 4432 | #if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_CHIP_MT6252 |
| 4433 | #define IS_NEW_L1D_ARCH_6R_SUPPORT 0 |
| 4434 | #define IS_NEW_L1D_ARCH_8R_SUPPORT 1 |
| 4435 | #else |
| 4436 | #define IS_NEW_L1D_ARCH_6R_SUPPORT 1 |
| 4437 | #define IS_NEW_L1D_ARCH_8R_SUPPORT 0 |
| 4438 | #endif |
| 4439 | #if IS_CHIP_MT6256_S00 |
| 4440 | #define IS_NEW_L1D_ARCH_3R_USF_SUPPORT 0 |
| 4441 | #elif IS_CHIP_MT6256 |
| 4442 | #define IS_NEW_L1D_ARCH_3R_USF_SUPPORT 0 |
| 4443 | #else |
| 4444 | #define IS_NEW_L1D_ARCH_3R_USF_SUPPORT 0 |
| 4445 | #endif |
| 4446 | #else |
| 4447 | #define IS_NEW_L1D_ARCH_SUPPORT 0 |
| 4448 | #define IS_NEW_L1D_ARCH_6R_SUPPORT 0 |
| 4449 | #define IS_NEW_L1D_ARCH_8R_SUPPORT 0 |
| 4450 | #define IS_NEW_L1D_ARCH_3R_USF_SUPPORT 0 |
| 4451 | #endif |
| 4452 | |
| 4453 | #define IS_OLD_L1D_ARCH_SUPPORT !IS_NEW_L1D_ARCH_SUPPORT |
| 4454 | |
| 4455 | #if defined(L1_SIM) && IS_NEW_L1D_ARCH_8R_SUPPORT |
| 4456 | #undef IS_NEW_TDMA_CHIP |
| 4457 | #undef IS_HW_8RXWIN_PM_SUPPORT_CHIP |
| 4458 | #define IS_NEW_TDMA_CHIP 1 |
| 4459 | #define IS_HW_8RXWIN_PM_SUPPORT_CHIP 1 |
| 4460 | #endif |
| 4461 | |
| 4462 | #if IS_OLD_L1D_ARCH_SUPPORT && IS_HYPER_SLEEP_MODE_CHIP |
| 4463 | #define IS_OLD_L1D_ARCH_NEW_SLEEP_SUPPORT 1 |
| 4464 | #else |
| 4465 | #define IS_OLD_L1D_ARCH_NEW_SLEEP_SUPPORT 0 |
| 4466 | #endif |
| 4467 | |
| 4468 | // GSM mode slot2, slot3 CCCH handling |
| 4469 | #if IS_GPRS |
| 4470 | #define IS_GSM_ONLY_HANDLE_R23_SUPPORT 0 |
| 4471 | #else |
| 4472 | #if IS_NEW_L1D_ARCH_SUPPORT |
| 4473 | #define IS_GSM_ONLY_HANDLE_R23_SUPPORT 0 |
| 4474 | #else |
| 4475 | #define IS_GSM_ONLY_HANDLE_R23_SUPPORT 1 |
| 4476 | #endif |
| 4477 | #endif |
| 4478 | |
| 4479 | /* 3G RF chip preotection */ |
| 4480 | #if defined(__MTK_UL1_FDD__) && !defined(L1_SIM) && !defined(L1D_TEST) && !defined(UL1D_TEST) |
| 4481 | #ifdef MT6160_RF |
| 4482 | #define IS_3GRF_DETECT 1 |
| 4483 | #else |
| 4484 | #define IS_3GRF_DETECT 0 |
| 4485 | #endif |
| 4486 | #else |
| 4487 | #define IS_3GRF_DETECT 0 |
| 4488 | #endif |
| 4489 | |
| 4490 | /* Align ul1d_cid.h*/ |
| 4491 | #ifdef MT6160_RF |
| 4492 | #define RF_3G_ID_Rev2p1 0x000000F9 |
| 4493 | #define RF_3G_ID_Rev3p0 0x000000EF |
| 4494 | #endif |
| 4495 | |
| 4496 | #if IS_CHIP_MT6276_S00 && defined(__UMTS_RAT__) && !defined(L1D_TEST) // only for MT6276E1 |
| 4497 | #define IS_MT6276_ADCMUX_CHECK_CHIP 1 |
| 4498 | #else |
| 4499 | #define IS_MT6276_ADCMUX_CHECK_CHIP 0 |
| 4500 | #endif |
| 4501 | |
| 4502 | #if IS_CHIP_MT6276_S00 && IS_RF_MT6162 |
| 4503 | #undef IS_MT6276_ADCMUX_CHECK_CHIP |
| 4504 | #define IS_MT6276_ADCMUX_CHECK_CHIP 0 |
| 4505 | #endif |
| 4506 | |
| 4507 | #if IS_CHIP_MT6276_S01 && defined(__UMTS_RAT__) && !defined(L1D_TEST) // only for MT6276E2 |
| 4508 | #define IS_MT6276_DACMODE_CHECK_CHIP 1 |
| 4509 | #else |
| 4510 | #define IS_MT6276_DACMODE_CHECK_CHIP 0 |
| 4511 | #endif |
| 4512 | |
| 4513 | #if IS_CHIP_MT6276 || IS_CHIP_MT6573 |
| 4514 | #define IS_MD2G_LOGGER_SUPPORT_CHIP 1 |
| 4515 | #else |
| 4516 | #define IS_MD2G_LOGGER_SUPPORT_CHIP 0 |
| 4517 | #endif |
| 4518 | |
| 4519 | #if defined(__CACHED_BASE_DSP__) |
| 4520 | #define IS_CACHE_DSP_SUPPORT 1 |
| 4521 | #else |
| 4522 | #define IS_CACHE_DSP_SUPPORT 0 |
| 4523 | #endif |
| 4524 | |
| 4525 | #if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 4526 | #define DSP_ARCHITECTURE_VERSION 4 |
| 4527 | #elif IS_CACHE_DSP_SUPPORT |
| 4528 | #define DSP_ARCHITECTURE_VERSION 3 |
| 4529 | #elif IS_DUAL_MAC_DSP_CHIP |
| 4530 | #define DSP_ARCHITECTURE_VERSION 2 |
| 4531 | #else |
| 4532 | #define DSP_ARCHITECTURE_VERSION 1 |
| 4533 | #endif |
| 4534 | |
| 4535 | #define IS_DSP_ARCHITECTURE_V1_SUPPORT (DSP_ARCHITECTURE_VERSION==1) |
| 4536 | #define IS_DSP_ARCHITECTURE_V2_SUPPORT (DSP_ARCHITECTURE_VERSION==2) |
| 4537 | #define IS_DSP_ARCHITECTURE_V3_SUPPORT (DSP_ARCHITECTURE_VERSION==3) |
| 4538 | #define IS_DSP_ARCHITECTURE_V4_SUPPORT (DSP_ARCHITECTURE_VERSION==4) |
| 4539 | |
| 4540 | // DSP Watchdog configuration |
| 4541 | #if IS_CHIP_MT6225_AND_LATTER_VERSION || (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_CHIP_MT6229_S00 && !IS_CHIP_MT6229_S01) |
| 4542 | #define IS_DSP_WATCHDOG 1 |
| 4543 | #if IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION |
| 4544 | #define IS_DSP2_WATCHDOG 1 |
| 4545 | #else |
| 4546 | #define IS_DSP2_WATCHDOG 0 |
| 4547 | #endif |
| 4548 | #else |
| 4549 | #define IS_DSP_WATCHDOG 0 |
| 4550 | #define IS_DSP2_WATCHDOG 0 |
| 4551 | #endif |
| 4552 | |
| 4553 | #if !IS_DUAL_DSP_CHIP |
| 4554 | #undef IS_DSP2_WATCHDOG |
| 4555 | #define IS_DSP2_WATCHDOG 0 |
| 4556 | #endif |
| 4557 | |
| 4558 | /* For 65NM IRDBG bug group*/ /* MT6268A, MT6516E0 has this bug */ |
| 4559 | #if IS_CHIP_MT6268A // only for MT6268A FT Test, CM is not protected so we have this solution |
| 4560 | #define IS_IRDBG_SW_WORKAROUND 1 |
| 4561 | #else |
| 4562 | #define IS_IRDBG_SW_WORKAROUND 0 |
| 4563 | #endif |
| 4564 | |
| 4565 | /* Disable 65NM in L1Sim */ |
| 4566 | #if IS_COSIM_ON_L1SIM_SUPPORT |
| 4567 | #elif defined(L1_SIM) |
| 4568 | #undef IS_65NM_CHIP |
| 4569 | #define IS_65NM_CHIP 0 |
| 4570 | #endif |
| 4571 | |
| 4572 | /* For Support Centralized Sleep Mode Manager Group */ |
| 4573 | /* We used to define IS_CENTRALIZED_SMM_CHIP as chip option */ |
| 4574 | /* It's better to align with feature option */ |
| 4575 | #if IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 4576 | #define IS_CENTRALIZED_SMM_CHIP 1 |
| 4577 | #else |
| 4578 | #define IS_CENTRALIZED_SMM_CHIP 0 |
| 4579 | #endif |
| 4580 | |
| 4581 | #if defined(ESIM_BUILD_CONFIG) && (ESIM_BUILD_CONFIG == ESIM_MULTI_MODE_ON_FIBERS) && defined(MTK_SLEEP_ENABLE) |
| 4582 | #define IS_TDMAIRQ_TIMING_CHECK_BYPASS_SUPPORT 1 |
| 4583 | #elif ( IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6582 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 ) && defined(MTK_SLEEP_ENABLE) |
| 4584 | #define IS_TDMAIRQ_TIMING_CHECK_BYPASS_SUPPORT 1 |
| 4585 | #else |
| 4586 | #define IS_TDMAIRQ_TIMING_CHECK_BYPASS_SUPPORT 0 |
| 4587 | #endif |
| 4588 | |
| 4589 | /* Dual Mode Chip should always use SW_MODE, MT6516 has problem with HW_MODE */ |
| 4590 | #if IS_65NM_CHIP |
| 4591 | #if IS_CHIP_MT6268 || IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6251 || IS_CHIP_MT6575 || IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 4592 | #if defined(MT6516_S00) || IS_CHIP_MT6251_S00 || IS_CHIP_MT6256_S00 |
| 4593 | #define IS_MD2G_PWD_SUPPORT 0 |
| 4594 | #else |
| 4595 | #define IS_MD2G_PWD_SUPPORT 1 |
| 4596 | #endif |
| 4597 | #if IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 4598 | #define IS_MD2G_PWD_DEFAULT_SW_MODE 0 |
| 4599 | #else |
| 4600 | #define IS_MD2G_PWD_DEFAULT_SW_MODE 1 |
| 4601 | #endif |
| 4602 | #define IS_IRDBG_LOG_STATUS 1 |
| 4603 | #else |
| 4604 | #define IS_MD2G_PWD_SUPPORT 0 |
| 4605 | #define IS_MD2G_PWD_DEFAULT_SW_MODE 0 |
| 4606 | #define IS_IRDBG_LOG_STATUS 1 |
| 4607 | #endif |
| 4608 | |
| 4609 | #if IS_CHIP_MT6268 || IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6251 || IS_CHIP_MT6575 || IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250 //Later chip should apply new control flow |
| 4610 | #define IS_NEW_MD2G_PWD_CONTROL_SUPPORT 0 |
| 4611 | #else //For MT6280 and later chip |
| 4612 | #define IS_NEW_MD2G_PWD_CONTROL_SUPPORT 1 |
| 4613 | #endif |
| 4614 | |
| 4615 | #if IS_CHIP_MT6268 || IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_MT6256_S00 |
| 4616 | #define IS_BACKUP_DPRAM_CHIP 1 |
| 4617 | #define IS_RESTORE_PATCH_RAM_CHIP 1 |
| 4618 | #else |
| 4619 | #define IS_BACKUP_DPRAM_CHIP 0 |
| 4620 | #define IS_RESTORE_PATCH_RAM_CHIP 0 |
| 4621 | #endif |
| 4622 | |
| 4623 | #if IS_CHIP_MT6251_S00 && defined(L1D_TEST) |
| 4624 | #undef IS_BACKUP_DPRAM_CHIP |
| 4625 | #undef IS_RESTORE_PATCH_RAM_CHIP |
| 4626 | #define IS_BACKUP_DPRAM_CHIP 1 |
| 4627 | #define IS_RESTORE_PATCH_RAM_CHIP 1 |
| 4628 | #endif |
| 4629 | |
| 4630 | #if IS_CENTRALIZED_SMM_CHIP |
| 4631 | #define IS_MD2G_STANDALONE_MTCMOS_CHIP 1 |
| 4632 | #elif defined(__UMTS_RAT__) // 68 MD2G MTCMOS |
| 4633 | #define IS_MD2G_STANDALONE_MTCMOS_CHIP 0 |
| 4634 | #else |
| 4635 | #define IS_MD2G_STANDALONE_MTCMOS_CHIP 1 |
| 4636 | #endif |
| 4637 | |
| 4638 | #if IS_CHIP_MT6575 |
| 4639 | #if defined(__UMTS_RAT__) && defined(__MTK_UL1_FDD__) |
| 4640 | #define IS_DEFAULT_TURNOFF_3GMTCMOS 0 |
| 4641 | #else |
| 4642 | #define IS_DEFAULT_TURNOFF_3GMTCMOS 1 |
| 4643 | #endif |
| 4644 | #else |
| 4645 | #define IS_DEFAULT_TURNOFF_3GMTCMOS 0 |
| 4646 | #endif |
| 4647 | #endif |
| 4648 | |
| 4649 | #if defined(MTK_SLEEP_ENABLE) && IS_65NM_CHIP && IS_DSP_ARCHITECTURE_V4_SUPPORT |
| 4650 | #if IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 4651 | #define IS_DSP_INIT_FLOW_V2_SUPPORT 1 |
| 4652 | #else |
| 4653 | #define IS_DSP_INIT_FLOW_V2_SUPPORT 0 |
| 4654 | #endif |
| 4655 | #else |
| 4656 | #define IS_DSP_INIT_FLOW_V2_SUPPORT 0 |
| 4657 | #endif |
| 4658 | #if (L1D_TEST) |
| 4659 | #undef IS_DSP_INIT_FLOW_V2_SUPPORT |
| 4660 | #define IS_DSP_INIT_FLOW_V2_SUPPORT 0 |
| 4661 | #endif |
| 4662 | #if IS_DSP_INIT_FLOW_V2_SUPPORT |
| 4663 | #if IS_BACKUP_DPRAM_CHIP || IS_RESTORE_PATCH_RAM_CHIP || IS_COMPARE_DPRAM_CHIP |
| 4664 | #error "IS_DSP_INIT_FLOW_V2_SUPPORT does not support these feature." |
| 4665 | #endif |
| 4666 | #else |
| 4667 | #if IS_CHIP_MT6280 |
| 4668 | #define IS_AFE_PRESENT 0 |
| 4669 | #else |
| 4670 | #define IS_AFE_PRESENT 1 |
| 4671 | #endif |
| 4672 | #endif |
| 4673 | |
| 4674 | #if defined(__2G_FAST_TIMING_ADJUST_SUPPORT__) |
| 4675 | #define IS_FAST_TIMING_ADJUST_SUPPORT 1 |
| 4676 | #else |
| 4677 | #define IS_FAST_TIMING_ADJUST_SUPPORT 0 |
| 4678 | #endif |
| 4679 | |
| 4680 | #if defined(__2G_FAST_TIMING_ADJUST_ENABLE__) |
| 4681 | #define IS_FAST_TIMING_ADJUST_ENABLE 1 |
| 4682 | #else |
| 4683 | #define IS_FAST_TIMING_ADJUST_ENABLE 0 |
| 4684 | #endif |
| 4685 | |
| 4686 | // For SOC chip MPLL FH Feature |
| 4687 | #if (IS_SOC_CHIP && !defined(__L1D_SOC_NO_MPLLFH__)) || IS_CHIP_MT6236 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 4688 | #define IS_MPLL_FH_SUPPORT 1 |
| 4689 | #if IS_CHIP_MT6252_S00 |
| 4690 | #define IS_MPLL_FH_V2 0 |
| 4691 | #define IS_MPLL_TX_RULE_CHECKED 0 |
| 4692 | #define IS_SPLL_FH_SUPPORT 0 |
| 4693 | #define IS_SPLL_FH_V2 0 |
| 4694 | #elif IS_CHIP_MT6252 |
| 4695 | #define IS_MPLL_FH_V2 1 |
| 4696 | #define IS_MPLL_TX_RULE_CHECKED 1 |
| 4697 | #define IS_SPLL_FH_SUPPORT 1 |
| 4698 | #define IS_SPLL_FH_V2 1 |
| 4699 | #else |
| 4700 | #define IS_MPLL_FH_V2 0 |
| 4701 | #define IS_MPLL_TX_RULE_CHECKED 0 |
| 4702 | #define IS_SPLL_FH_SUPPORT 0 |
| 4703 | #define IS_SPLL_FH_V2 0 |
| 4704 | #endif |
| 4705 | #else |
| 4706 | #define IS_MPLL_FH_SUPPORT 0 |
| 4707 | #define IS_MPLL_FH_V2 0 |
| 4708 | #define IS_MPLL_TX_RULE_CHECKED 0 |
| 4709 | #define IS_SPLL_FH_SUPPORT 0 |
| 4710 | #define IS_SPLL_FH_V2 0 |
| 4711 | #endif |
| 4712 | |
| 4713 | #if IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION |
| 4714 | #define IS_MPLLFH_FREE_RUN_SUPPORT_CHIP 1 |
| 4715 | #else |
| 4716 | #define IS_MPLLFH_FREE_RUN_SUPPORT_CHIP 0 |
| 4717 | #endif |
| 4718 | |
| 4719 | #if IS_MPLLFH_FREE_RUN_SUPPORT_CHIP |
| 4720 | #if IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 4721 | #define IS_MPLLFH_FREE_RUN_ON 1 |
| 4722 | #elif IS_CHIP_MT6251 |
| 4723 | #define IS_MPLLFH_FREE_RUN_ON 0 |
| 4724 | #else |
| 4725 | #define IS_MPLLFH_FREE_RUN_ON 0 |
| 4726 | #endif |
| 4727 | #else |
| 4728 | #define IS_MPLLFH_FREE_RUN_ON 0 |
| 4729 | #endif |
| 4730 | |
| 4731 | #if defined(L1_SIM) |
| 4732 | #undef IS_MPLL_FH_SUPPORT |
| 4733 | #define IS_MPLL_FH_SUPPORT 0 |
| 4734 | #endif |
| 4735 | |
| 4736 | #ifdef __CYCLIC_MPLLFH__ |
| 4737 | #define IS_MPLL_CYCLIC_FH_SUPPORT 1 |
| 4738 | #else |
| 4739 | #define IS_MPLL_CYCLIC_FH_SUPPORT 0 |
| 4740 | #endif |
| 4741 | |
| 4742 | #ifdef __FIXED_MPLLFH__ |
| 4743 | #define IS_MPLL_FIXED_LOWEST_SUPPORT 1 |
| 4744 | #define IS_SPLL_FIXED_LOWEST_SUPPORT 1 |
| 4745 | #else |
| 4746 | #define IS_MPLL_FIXED_LOWEST_SUPPORT 0 |
| 4747 | #define IS_SPLL_FIXED_LOWEST_SUPPORT 0 |
| 4748 | #endif |
| 4749 | |
| 4750 | #if IS_CHIP_MT6276_S00 // For MT6276E1 MPLL FH, MT6276E1 has only partial FH |
| 4751 | #define IS_MT6276E1_TEMP_MPLL_FH_SUPPORT 1 |
| 4752 | #else |
| 4753 | #define IS_MT6276E1_TEMP_MPLL_FH_SUPPORT 0 |
| 4754 | #endif |
| 4755 | |
| 4756 | #if defined(L1_SIM) |
| 4757 | #undef IS_MT6276E1_TEMP_MPLL_FH_SUPPORT |
| 4758 | #define IS_MT6276E1_TEMP_MPLL_FH_SUPPORT 0 |
| 4759 | #endif |
| 4760 | |
| 4761 | #if IS_CHIP_MT6276_S01 |
| 4762 | #define IS_MT6276_FREERUN_SUPPORT 1 |
| 4763 | #else |
| 4764 | #define IS_MT6276_FREERUN_SUPPORT 0 |
| 4765 | #endif |
| 4766 | |
| 4767 | #if defined(L1_SIM) |
| 4768 | #undef IS_MT6276_FREERUN_SUPPORT |
| 4769 | #define IS_MT6276_FREERUN_SUPPORT 0 |
| 4770 | #endif |
| 4771 | |
| 4772 | #if IS_MPLL_FH_SUPPORT |
| 4773 | #if IS_CHIP_MT6251 |
| 4774 | #define IS_MPLL_DYNAMIC_FH_SUPPORT 1 |
| 4775 | #else |
| 4776 | #define IS_MPLL_DYNAMIC_FH_SUPPORT 0 |
| 4777 | #endif |
| 4778 | #endif |
| 4779 | |
| 4780 | #if IS_SOC_CHIP |
| 4781 | #define TX_DCOC_RF_LOOPBACK 1 |
| 4782 | #else |
| 4783 | #define TX_DCOC_RF_LOOPBACK 0 |
| 4784 | #endif |
| 4785 | |
| 4786 | // if need 33 sections calibration |
| 4787 | #if IS_CHIP_MT6253 |
| 4788 | #define IS_VCXO_LC_NEED 1 |
| 4789 | #else |
| 4790 | #define IS_VCXO_LC_NEED 0 |
| 4791 | #endif |
| 4792 | |
| 4793 | // AFC linear compensation support |
| 4794 | #if IS_VCXO_LC_NEED |
| 4795 | #define IS_VCXO_LC_SUPPORT 1 |
| 4796 | #if IS_CHIP_MT6252 |
| 4797 | #define IS_VCXO_LC_TRXOFFSET_COMPENSATE_SUPPORT 1 |
| 4798 | #else |
| 4799 | #define IS_VCXO_LC_TRXOFFSET_COMPENSATE_SUPPORT 0 |
| 4800 | #endif |
| 4801 | #else |
| 4802 | #define IS_VCXO_LC_SUPPORT 0 |
| 4803 | #define IS_VCXO_LC_TRXOFFSET_COMPENSATE_SUPPORT 0 |
| 4804 | #endif |
| 4805 | |
| 4806 | #if IS_CHIP_MT6251 || IS_CHIP_MT6252 || IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 4807 | #define IS_TWO_STEP_AFC_TRACKING_SUPPORT 1 |
| 4808 | #else |
| 4809 | #define IS_TWO_STEP_AFC_TRACKING_SUPPORT 0 |
| 4810 | #endif |
| 4811 | |
| 4812 | // PM with DSP2MCU Interrupt |
| 4813 | #if IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION |
| 4814 | #define IS_PM_DSP2MCU_SUPPORT 1 |
| 4815 | #else |
| 4816 | #define IS_PM_DSP2MCU_SUPPORT 0 |
| 4817 | #endif |
| 4818 | |
| 4819 | // For feature of split binary: MAUI/FACTORY bin |
| 4820 | #if defined(__FACTORY_BIN__) || !defined(__SPLIT_BINARY__) |
| 4821 | #define IS_FOR_FACTORY_MODE_ONLY 1 |
| 4822 | #else |
| 4823 | // This case means only __SPLIT_BINARY__ is defined, which is used for generating MAUI bin. |
| 4824 | #define IS_FOR_FACTORY_MODE_ONLY 0 |
| 4825 | #endif |
| 4826 | |
| 4827 | // Fast Handset Calibration (FHC) Support |
| 4828 | #if IS_FOR_FACTORY_MODE_ONLY && (IS_CHIP_MT6229 || IS_CHIP_MT6238 || IS_CHIP_MT6223 || IS_CHIP_MT6253 || IS_CHIP_MT6225 || IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_MT6268 || IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION) |
| 4829 | #define IS_FHC_SUPPORT 1 |
| 4830 | #else |
| 4831 | #define IS_FHC_SUPPORT 0 |
| 4832 | #endif |
| 4833 | |
| 4834 | // Non-Signaling Final Test (NSFT) Support |
| 4835 | #if IS_FOR_FACTORY_MODE_ONLY |
| 4836 | #define IS_NSFT_SUPPORT 1 |
| 4837 | #else |
| 4838 | #define IS_NSFT_SUPPORT 0 |
| 4839 | #endif |
| 4840 | |
| 4841 | // Single-End BER Support |
| 4842 | #if IS_NSFT_SUPPORT |
| 4843 | #define IS_SINGLE_END_BER_SUPPORT 1 |
| 4844 | #define IS_NSFT_SACCH_TEST_ITEM_SUPPORT 1 |
| 4845 | #else |
| 4846 | #define IS_SINGLE_END_BER_SUPPORT 0 |
| 4847 | #define IS_NSFT_SACCH_TEST_ITEM_SUPPORT 0 |
| 4848 | #endif |
| 4849 | |
| 4850 | //add __UMTS_RAT__, because for 2G Only target, control buffer size = 2K/4K, L1_ALLOC_BUF(sizeof(NsftList_CMD_Q_ENTRY_T)*NsftList_MAX_CMD_QUEUE_SIZE) will overflow |
| 4851 | // size define can reference to "interface/service/config/kal_user_mem.h" 2G only case: RPS_CREATED_CTRL_BUFF_POOLS=8, custom_ctrl_num_buff_pool_size=4096 |
| 4852 | // Note: even if MAX support size=4KB, it may only 2K buffer can use, the supported buffer number of every size pool are decided by project |
| 4853 | #if IS_NSFT_SUPPORT && IS_EPSK_TX_SUPPORT && (defined(__UMTS_RAT__)) |
| 4854 | #define IS_NSFT_LIST_MODE_SUPPORT 1 |
| 4855 | #else |
| 4856 | #define IS_NSFT_LIST_MODE_SUPPORT 0 |
| 4857 | #endif |
| 4858 | |
| 4859 | // MS Capability v2.0 |
| 4860 | #if 1 // use v2.0 by default |
| 4861 | #define IS_MS_CAPABILITY_V2_SUPPORT 1 |
| 4862 | #else |
| 4863 | /* under construction !*/ |
| 4864 | #endif |
| 4865 | |
| 4866 | // Multi-slot TX Support in GSM only |
| 4867 | #if IS_FHC_SUPPORT && IS_GSM |
| 4868 | #if 0 // TBD |
| 4869 | /* under construction !*/ |
| 4870 | #else |
| 4871 | #define IS_MULTISLOT_TX_SUPPORT 0 |
| 4872 | #endif |
| 4873 | #else |
| 4874 | #define IS_MULTISLOT_TX_SUPPORT 0 |
| 4875 | #endif |
| 4876 | |
| 4877 | // FWBW-DCOC support: including DSP FWBW DCOC support and L1 alpha filtering enhance FWBW DCOC feature |
| 4878 | #if (IS_SAIC_CHIP_MT6253_AND_LATTER_VERSION && !IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION) || IS_CHIP_MT6583_MD2 |
| 4879 | // MT6583 modem 2 is the DCR architecture |
| 4880 | #if defined(L1D_TEST) |
| 4881 | #define IS_FWBW_DCOC_SUPPORT 0 |
| 4882 | #define IS_AM_SUPPRESSION_ALPHA_FILTERING_SUPPORT 0 |
| 4883 | #else |
| 4884 | #define IS_FWBW_DCOC_SUPPORT 1 |
| 4885 | #define IS_AM_SUPPRESSION_ALPHA_FILTERING_SUPPORT 1 |
| 4886 | #endif |
| 4887 | #else |
| 4888 | #define IS_FWBW_DCOC_SUPPORT 0 |
| 4889 | #define IS_AM_SUPPRESSION_ALPHA_FILTERING_SUPPORT 0 |
| 4890 | #endif |
| 4891 | |
| 4892 | // Force 2G TDMA and/or RF NO Sleep |
| 4893 | #if IS_CHIP_MT6268A |
| 4894 | #define IS_2G_TDMA_RF_NO_SLEEP 0 // 1 |
| 4895 | #else |
| 4896 | #define IS_2G_TDMA_RF_NO_SLEEP 0 |
| 4897 | #endif |
| 4898 | |
| 4899 | // Define TDMA/RF no Sleep default setting |
| 4900 | #if IS_2G_TDMA_RF_NO_SLEEP |
| 4901 | #if IS_CHIP_MT6268A |
| 4902 | #define IS_2G_TDMA_NO_SLEEP 1 |
| 4903 | #define IS_2G_RF_NO_SLEEP 0 |
| 4904 | #else |
| 4905 | #define IS_2G_TDMA_NO_SLEEP 0 |
| 4906 | #define IS_2G_RF_NO_SLEEP 0 |
| 4907 | #endif |
| 4908 | #else |
| 4909 | #define IS_2G_TDMA_NO_SLEEP 0 |
| 4910 | #define IS_2G_RF_NO_SLEEP 0 |
| 4911 | #endif |
| 4912 | |
| 4913 | #if IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 4914 | #define IS_SLEEP_DSPCLK_GATE 0 |
| 4915 | #elif IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION |
| 4916 | #define IS_SLEEP_DSPCLK_GATE 1 |
| 4917 | #else |
| 4918 | #define IS_SLEEP_DSPCLK_GATE 0 |
| 4919 | #endif |
| 4920 | |
| 4921 | #if IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 |
| 4922 | #define IS_SLEEP_HW_DIVIDER_INIT 1 |
| 4923 | #else |
| 4924 | // For MT6280, MT6572/82, and later chips, the divider will be turned on or off by DIVIDE() and MODULO() defined in Divider_Public.h |
| 4925 | #define IS_SLEEP_HW_DIVIDER_INIT 0 |
| 4926 | #endif |
| 4927 | |
| 4928 | // For 36 latter chips, slave DSP crash is moved to IO(0x7) |
| 4929 | #if IS_EDGE_SAIC_CHIP_MT6236_AND_LATTER_VERSION && !(IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)) |
| 4930 | #define IS_DSP2_CRASH_ON_IO7_CHIP 1 |
| 4931 | #else |
| 4932 | #define IS_DSP2_CRASH_ON_IO7_CHIP 0 |
| 4933 | #endif |
| 4934 | |
| 4935 | #if IS_DUAL_MAC_DSP_CHIP |
| 4936 | #define IS_DSP_CRASH_WORKAROUND 1 |
| 4937 | #else |
| 4938 | #define IS_DSP_CRASH_WORKAROUND 0 |
| 4939 | #endif |
| 4940 | |
| 4941 | #if (IS_CHIP_MT6295_AND_LATTER_VERSION && defined(__MTK_TARGET__)) |
| 4942 | #define IS_GL1D_CAL_DATA_DOWNLOAD_CHECK_SUPPORT 1 |
| 4943 | #else |
| 4944 | #define IS_GL1D_CAL_DATA_DOWNLOAD_CHECK_SUPPORT 0 |
| 4945 | #endif |
| 4946 | #if IS_CHIP_MT6295_AND_LATTER_VERSION |
| 4947 | #define IS_GL1D_DSP_V2_FLOW_SINGLE_USER_SUPPORT 1 |
| 4948 | #else |
| 4949 | #define IS_GL1D_DSP_V2_FLOW_SINGLE_USER_SUPPORT 0 |
| 4950 | #endif |
| 4951 | // IRDMA power control |
| 4952 | #if IS_FD216_DSP_CHIP && (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION || IS_CHIP_MT6225_AND_LATTER_VERSION) |
| 4953 | #define IS_IRDMA_POWER_CTRL_CHIP 1 |
| 4954 | #else |
| 4955 | #define IS_IRDMA_POWER_CTRL_CHIP 0 |
| 4956 | #endif |
| 4957 | |
| 4958 | /* The De-interleaving buffer was moved to external memory */ |
| 4959 | /* So, IRDMA would be used when wake-up, and the IR memory size should be increased */ |
| 4960 | #if IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 4961 | #define IS_DEINTERLEAVING_BUFFER_MOVED_CHIP 1 |
| 4962 | #else |
| 4963 | #define IS_DEINTERLEAVING_BUFFER_MOVED_CHIP 0 |
| 4964 | #endif |
| 4965 | |
| 4966 | #if defined(__MTK_MODEM_REMOVED__) |
| 4967 | #define IS_MTK_MODEM_REMOVED 1 |
| 4968 | #else |
| 4969 | #define IS_MTK_MODEM_REMOVED 0 |
| 4970 | #endif |
| 4971 | |
| 4972 | #if defined(__2G_RF_CUSTOM_TOOL_SUPPORT__) |
| 4973 | #define IS_RF_TOOL_CUSTOMIZATION_SUPPORT 0 |
| 4974 | #define IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2 1 |
| 4975 | #elif IS_CHIP_MT6516 |
| 4976 | #define IS_RF_TOOL_CUSTOMIZATION_SUPPORT 1 |
| 4977 | #define IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2 0 |
| 4978 | #else |
| 4979 | #define IS_RF_TOOL_CUSTOMIZATION_SUPPORT 0 |
| 4980 | #define IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2 0 |
| 4981 | #endif |
| 4982 | |
| 4983 | #if IS_CHIP_MT6236 |
| 4984 | #define IS_BT_CO_CLOCK_SW_SUPPORT 0 |
| 4985 | #define IS_BT_CO_CLOCK_HW_SUPPORT 1 |
| 4986 | #else |
| 4987 | #define IS_BT_CO_CLOCK_SW_SUPPORT 0 |
| 4988 | #define IS_BT_CO_CLOCK_HW_SUPPORT 0 |
| 4989 | #endif |
| 4990 | |
| 4991 | #if IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 4992 | #define IS_SMP_ARCHITECTURE 1 |
| 4993 | #else |
| 4994 | #define IS_SMP_ARCHITECTURE 0 |
| 4995 | #endif |
| 4996 | |
| 4997 | #if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6292) || defined(__UE_SIMULATOR__) |
| 4998 | #define IS_SIMULTANEOUS_L1CD_ENABLE 1 |
| 4999 | #else |
| 5000 | #error "Remove dummy LISR is mandatory feature since LR12" |
| 5001 | #endif |
| 5002 | |
| 5003 | #if IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 5004 | #define IS_MD2G_BUS_LOW_POWER_MODE 1 |
| 5005 | #else |
| 5006 | #define IS_MD2G_BUS_LOW_POWER_MODE 0 |
| 5007 | #endif |
| 5008 | |
| 5009 | #if IS_CHIP_MT6297_AND_LATTER_VERSION |
| 5010 | #define IS_2G_L1D_ROBUST_MODEM_ENABLE 1 |
| 5011 | #else |
| 5012 | #define IS_2G_L1D_ROBUST_MODEM_ENABLE 0 |
| 5013 | #endif |
| 5014 | |
| 5015 | #if IS_CHIP_MT6293 |
| 5016 | #define IS_2G_BANK_B_ENABLE 1 |
| 5017 | #else |
| 5018 | #define IS_2G_BANK_B_ENABLE 0 |
| 5019 | #endif |
| 5020 | |
| 5021 | #if (IS_CHIP_MT6761) && (defined __MTK_TARGET__) |
| 5022 | #define IS_L1D_DELSEL_MEMORY_DUMP_ENABLE 1 |
| 5023 | #else |
| 5024 | #define IS_L1D_DELSEL_MEMORY_DUMP_ENABLE 0 |
| 5025 | #endif |
| 5026 | //FDD Dual Mode Feature Option |
| 5027 | #if defined(__UMTS_FDD_MODE__) |
| 5028 | #define IS_FDD_DUAL_MODE_SUPPORT 1 |
| 5029 | #else |
| 5030 | #define IS_FDD_DUAL_MODE_SUPPORT 0 |
| 5031 | #endif |
| 5032 | |
| 5033 | //TDD Dual Mode Feature Option |
| 5034 | #if defined(__UMTS_TDD128_MODE__) |
| 5035 | #define IS_TDD_DUAL_MODE_SUPPORT 1 |
| 5036 | #else |
| 5037 | #define IS_TDD_DUAL_MODE_SUPPORT 0 //To do TDD dual mode L1S and loopback test, this feature should be opened |
| 5038 | #endif |
| 5039 | |
| 5040 | #if L1D_WT_COBIN_ARCHITECTURE_SUPPORT |
| 5041 | |
| 5042 | #if L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD && IS_FDD_DUAL_MODE_SUPPORT |
| 5043 | #undef IS_TDD_DUAL_MODE_SUPPORT |
| 5044 | #define IS_TDD_DUAL_MODE_SUPPORT 1 |
| 5045 | #endif |
| 5046 | #if L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD && IS_TDD_DUAL_MODE_SUPPORT |
| 5047 | #undef IS_FDD_DUAL_MODE_SUPPORT |
| 5048 | #define IS_FDD_DUAL_MODE_SUPPORT 1 |
| 5049 | #endif |
| 5050 | |
| 5051 | #if (IS_FDD_DUAL_MODE_SUPPORT && !IS_TDD_DUAL_MODE_SUPPORT) || (!IS_FDD_DUAL_MODE_SUPPORT && IS_TDD_DUAL_MODE_SUPPORT) |
| 5052 | #if L1D_WT_COBIN_UT_W_ONLY_BUILD || L1D_WT_CBBIN_UT_T_ONLY_BUILD |
| 5053 | #else |
| 5054 | #error "IS_FDD_DUAL_MODE_SUPPORT and IS_TDD_DUAL_MODE_SUPPORT should be aligned with WT Co-bin feature!" |
| 5055 | #endif |
| 5056 | #endif |
| 5057 | |
| 5058 | #if (IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT) && !defined(__MULTI_RAT_AFC_TADC_SHARE_SUPPORT__) |
| 5059 | #if L1D_WT_COBIN_UT_W_ONLY_BUILD || L1D_WT_CBBIN_UT_T_ONLY_BUILD |
| 5060 | #else |
| 5061 | #error "WT Co-bin feature needs multi-mode AFC Temp ADC sharing feature when dual-mode or multi-mode!" |
| 5062 | #endif |
| 5063 | #endif |
| 5064 | |
| 5065 | #endif |
| 5066 | |
| 5067 | //Multi Mode Feature Option |
| 5068 | #if defined(__UMTS_RAT__) || defined(__LTE_RAT__) |
| 5069 | #define IS_GL1_MULTI_MODE_SUPPORT 1 |
| 5070 | #else |
| 5071 | #define IS_GL1_MULTI_MODE_SUPPORT 0 |
| 5072 | #endif |
| 5073 | |
| 5074 | #if ( IS_GL1_MULTI_MODE_SUPPORT && IS_TDD_DUAL_MODE_SUPPORT ) || IS_GEMINI_TGG_SUPPORT |
| 5075 | #define IS_TDD_5PM_NORMAL_CTIRQ2_SUPPORT 1 |
| 5076 | #else |
| 5077 | #define IS_TDD_5PM_NORMAL_CTIRQ2_SUPPORT 0 |
| 5078 | #endif |
| 5079 | #if defined(L1_SIM)//Here we are undefining the macro IS_MULTI_MODE_AFC_SUPPORT since while running on XL1sim |
| 5080 | #undef IS_MULTI_MODE_AFC_SUPPORT //we are facing the warning as macro is redefined since 3G is also using same macro definition |
| 5081 | #endif |
| 5082 | #if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 5083 | #if IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT |
| 5084 | #define IS_MULTI_MODE_AFC_SUPPORT 1 |
| 5085 | #else |
| 5086 | #define IS_MULTI_MODE_AFC_SUPPORT 0 |
| 5087 | #endif |
| 5088 | #else |
| 5089 | #define IS_MULTI_MODE_AFC_SUPPORT 0 |
| 5090 | #endif |
| 5091 | |
| 5092 | #if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 5093 | #define IS_MULTI_MODE_AFC_WITH_SHM_SUPPORT 1 |
| 5094 | #else |
| 5095 | #define IS_MULTI_MODE_AFC_WITH_SHM_SUPPORT 0 |
| 5096 | #endif |
| 5097 | |
| 5098 | #if defined(__COTMS_TELEMATICS_SUPPORT__) |
| 5099 | #define IS_MULTI_MODE_AFC_IN_32BITS 1 |
| 5100 | #else |
| 5101 | #define IS_MULTI_MODE_AFC_IN_32BITS 0 |
| 5102 | #endif |
| 5103 | |
| 5104 | #if L1D_WT_COBIN_ARCHITECTURE_SUPPORT |
| 5105 | #if (IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT) && !IS_MULTI_MODE_AFC_SUPPORT |
| 5106 | #error "WT Co-bin feature needs multi-mode AFC feature when dual-mode or multi-mode!" |
| 5107 | #endif |
| 5108 | #endif |
| 5109 | |
| 5110 | #if IS_TDD_DUAL_MODE_SUPPORT && (IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297) |
| 5111 | #define IS_AST3002_SUPPORT 1 |
| 5112 | #else |
| 5113 | #define IS_AST3002_SUPPORT 0 |
| 5114 | #endif |
| 5115 | |
| 5116 | #if IS_TDD_DUAL_MODE_SUPPORT |
| 5117 | #if ( IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297) |
| 5118 | #define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */ |
| 5119 | #define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */ |
| 5120 | #define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */ |
| 5121 | #define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 /* Trigger Vrf28 by SRCLKENA instead of SW config */ |
| 5122 | #define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 0 /* Handle init flow of single RF controlled by separate TD/2G BB chips */ |
| 5123 | #define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */ |
| 5124 | #elif IS_CHIP_MT6575 && defined(__AST3001__) |
| 5125 | #define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 1 /* Trigger off-chip BPI pins by sending BSI data */ |
| 5126 | #define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 1 /* Trigger off-chip BSI switch before sending BSI data to RF */ |
| 5127 | #define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 1 /* Trigger off-chip Vrf18 */ |
| 5128 | #define IS_SRCLKENA_TRIG_VRF28_SUPPORT 1 /* Trigger Vrf28 by SRCLKENA instead of SW config */ |
| 5129 | #define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */ |
| 5130 | #define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 1 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */ |
| 5131 | #elif (IS_CHIP_MT6583_MD2 || IS_CHIP_MT6280) && defined(__AST3001__) |
| 5132 | #define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */ |
| 5133 | #define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 1 /* Trigger off-chip BSI switch before sending BSI data to RF */ |
| 5134 | #define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 1 /* Trigger off-chip Vrf18 */ |
| 5135 | #define IS_SRCLKENA_TRIG_VRF28_SUPPORT 1 /* Trigger Vrf28 by SRCLKENA instead of SW config */ |
| 5136 | #define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */ |
| 5137 | #define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 1 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */ |
| 5138 | #elif IS_AST3002_SUPPORT && (IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2) |
| 5139 | #define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */ |
| 5140 | #define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */ |
| 5141 | #define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */ |
| 5142 | #define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 /* Trigger Vrf28 by SRCLKENA instead of SW config */ |
| 5143 | #define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */ |
| 5144 | #define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 1 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */ |
| 5145 | #elif ( IS_CHIP_MT6255 || IS_CHIP_MT6256 ) && defined(__AST3001__) |
| 5146 | #define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */ |
| 5147 | #define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */ |
| 5148 | #define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */ |
| 5149 | #define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 /* Trigger Vrf28 by SRCLKENA instead of SW config */ |
| 5150 | #define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */ |
| 5151 | #define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */ |
| 5152 | #elif IS_GEMINI_TGG_SUPPORT && defined(__AST2001__) |
| 5153 | #define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */ |
| 5154 | #define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */ |
| 5155 | #define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */ |
| 5156 | #define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 /* Trigger Vrf28 by SRCLKENA instead of SW config */ |
| 5157 | #define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */ |
| 5158 | #define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */ |
| 5159 | #else |
| 5160 | #define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 |
| 5161 | #define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 |
| 5162 | #define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 |
| 5163 | #define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 |
| 5164 | #define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 0 |
| 5165 | #define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 |
| 5166 | #endif |
| 5167 | #else |
| 5168 | #if IS_CHIP_MT6583_MD2 |
| 5169 | /* For MT6583_MD2 2G Only Project, VRF28 is trigger by SRCLKENA */ |
| 5170 | #define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */ |
| 5171 | #define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */ |
| 5172 | #define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */ |
| 5173 | #define IS_SRCLKENA_TRIG_VRF28_SUPPORT 1 /* Trigger Vrf28 by SRCLKENA instead of SW config */ |
| 5174 | #define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 0 /* Handle init flow of single RF controlled by separate TD/2G BB chips */ |
| 5175 | #define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */ |
| 5176 | #else |
| 5177 | #define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 |
| 5178 | #define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 |
| 5179 | #define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 |
| 5180 | #define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 |
| 5181 | #define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 0 |
| 5182 | #define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 |
| 5183 | #endif |
| 5184 | #endif |
| 5185 | |
| 5186 | //TDD Dual Mode Feature Option |
| 5187 | #if IS_TDD_DUAL_MODE_SUPPORT |
| 5188 | #if IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250 |
| 5189 | #define IS_AST_B2S_SUPPORT 1 |
| 5190 | #else |
| 5191 | #define IS_AST_B2S_SUPPORT 0 |
| 5192 | #endif |
| 5193 | #else |
| 5194 | #define IS_AST_B2S_SUPPORT 0 |
| 5195 | #endif |
| 5196 | |
| 5197 | //TDD Dual Mode Feature Option |
| 5198 | #if IS_TDD_DUAL_MODE_SUPPORT |
| 5199 | #if IS_CHIP_MT6256 || IS_CHIP_MT6255 || ((IS_CHIP_MT6575||IS_CHIP_MT6280||IS_CHIP_MT6583_MD2) && defined(__AST3001__)) |
| 5200 | #define IS_CO_CRYSTAL_SUPPORT 1 |
| 5201 | #define IS_CO_TEMPADC_SUPPORT 0 |
| 5202 | #elif IS_CHIP_MT6572 |
| 5203 | #define IS_CO_CRYSTAL_SUPPORT 1 |
| 5204 | #define IS_CO_TEMPADC_SUPPORT 1 |
| 5205 | #else |
| 5206 | #define IS_CO_CRYSTAL_SUPPORT 0 |
| 5207 | #define IS_CO_TEMPADC_SUPPORT 0 |
| 5208 | #endif |
| 5209 | #else |
| 5210 | #define IS_CO_CRYSTAL_SUPPORT 0 |
| 5211 | #define IS_CO_TEMPADC_SUPPORT 0 |
| 5212 | #endif |
| 5213 | |
| 5214 | #if defined(__MULTI_RAT_AFC_TADC_SHARE_SUPPORT__) |
| 5215 | #if IS_CHIP_MT6290_S00 |
| 5216 | #define IS_MULTI_RAT_AFC_SHARE_SUPPORT 0 |
| 5217 | #define IS_MULTI_RAT_TADC_SHARE_SUPPORT 0 |
| 5218 | #else |
| 5219 | #define IS_MULTI_RAT_AFC_SHARE_SUPPORT 1 |
| 5220 | #define IS_MULTI_RAT_TADC_SHARE_SUPPORT 1 |
| 5221 | #endif |
| 5222 | #else |
| 5223 | #define IS_MULTI_RAT_AFC_SHARE_SUPPORT 0 |
| 5224 | #define IS_MULTI_RAT_TADC_SHARE_SUPPORT 0 |
| 5225 | #endif |
| 5226 | |
| 5227 | #if IS_CHIP_MT6752_MD2 |
| 5228 | #define IS_2G_ONLY_MODEM_SUPPORT 1 |
| 5229 | #else |
| 5230 | #define IS_2G_ONLY_MODEM_SUPPORT 0 |
| 5231 | #endif |
| 5232 | |
| 5233 | //TDD Dual Mode Short FBSB Feature |
| 5234 | #if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251 |
| 5235 | #define IS_DSP_ENHANCE_SHORT_FBSB_PATCH 0 |
| 5236 | #elif IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6268T) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6223) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6268) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6253) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6276) |
| 5237 | #define IS_DSP_ENHANCE_SHORT_FBSB_PATCH 0 |
| 5238 | #else |
| 5239 | #define IS_DSP_ENHANCE_SHORT_FBSB_PATCH 1 |
| 5240 | #endif |
| 5241 | |
| 5242 | #if IS_TDD_DUAL_MODE_SUPPORT && !IS_DSP_ENHANCE_SHORT_FBSB_PATCH |
| 5243 | #error "DSP enhanced short FB/SB patch is mandatory for TDD dual mode" |
| 5244 | #endif |
| 5245 | |
| 5246 | #if L1D_WT_COBIN_ARCHITECTURE_SUPPORT |
| 5247 | #define IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT 1 |
| 5248 | #else |
| 5249 | #if IS_TDD_DUAL_MODE_SUPPORT |
| 5250 | #define IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT 1 |
| 5251 | #else |
| 5252 | #define IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT 0 |
| 5253 | #endif |
| 5254 | #endif |
| 5255 | |
| 5256 | #if IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT |
| 5257 | #if defined(L1_SIM) |
| 5258 | #define IS_DSP_SHORT_FBSB_V1 0 |
| 5259 | #define IS_DSP_SHORT_FBSB_V2 1 |
| 5260 | #endif |
| 5261 | #define IS_DSP_SHORT_SB_ENABLED 1 |
| 5262 | #endif |
| 5263 | |
| 5264 | #if IS_TDD_DUAL_MODE_SUPPORT |
| 5265 | #ifdef L1_SIM |
| 5266 | #define IS_RRM_TD_GAP_SHORT_FB_WORKAROUND 0 |
| 5267 | #else |
| 5268 | #if IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 5269 | #define IS_RRM_TD_GAP_SHORT_FB_WORKAROUND 1 |
| 5270 | #else |
| 5271 | #define IS_RRM_TD_GAP_SHORT_FB_WORKAROUND 0 |
| 5272 | #endif |
| 5273 | #endif |
| 5274 | #else |
| 5275 | #define IS_RRM_TD_GAP_SHORT_FB_WORKAROUND 0 |
| 5276 | #endif |
| 5277 | //TDD Dual Mode AFC Control Rule |
| 5278 | #if IS_TDD_DUAL_MODE_SUPPORT |
| 5279 | #if defined(__AST2001__) |
| 5280 | #define IS_TDDM_AFC_TRANSFORM_SUPPORT 1 /* TD AFC HW has different DAC/slope from 2G */ |
| 5281 | #else |
| 5282 | #define IS_TDDM_AFC_TRANSFORM_SUPPORT 0 |
| 5283 | #endif |
| 5284 | #else |
| 5285 | #define IS_TDDM_AFC_TRANSFORM_SUPPORT 0 |
| 5286 | #endif |
| 5287 | |
| 5288 | // Define L1D full pm test mode setting |
| 5289 | /* |
| 5290 | #define __L1D_FULL_PM_TEST__ |
| 5291 | #define __L1D_FULL_PM_TEST_DEFAULT_OFF__ |
| 5292 | */ |
| 5293 | #if defined(__L1D_FULL_PM_TEST__) |
| 5294 | #define IS_L1D_FULL_PM_TEST_SUPPORT 1 |
| 5295 | #else |
| 5296 | #define IS_L1D_FULL_PM_TEST_SUPPORT 0 |
| 5297 | #endif |
| 5298 | |
| 5299 | #if IS_L1D_FULL_PM_TEST_SUPPORT |
| 5300 | #if !defined(__L1D_FULL_PM_TEST_DEFAULT_OFF__) |
| 5301 | #define IS_L1D_FULL_PM_TEST_DEFAULT_ON 1 |
| 5302 | #else |
| 5303 | #define IS_L1D_FULL_PM_TEST_DEFAULT_ON 0 |
| 5304 | #endif |
| 5305 | #endif |
| 5306 | |
| 5307 | #if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 5308 | #define IS_WB_AMR_SUPPORT 1 |
| 5309 | #define IS_FB_SNIFFER_SUPPORT 1 |
| 5310 | #else |
| 5311 | #define IS_WB_AMR_SUPPORT 0 |
| 5312 | #define IS_FB_SNIFFER_SUPPORT 0 |
| 5313 | #endif |
| 5314 | |
| 5315 | #if IS_CHIP_MT6583_MD2 |
| 5316 | #define IS_DLIF_CHIP 0 |
| 5317 | #define IS_DCR_IN_DLIF_CHIP 1 /* MT6583_MD2 is DCR but re-uses the DLIF architecture */ |
| 5318 | #define IS_DYNAMIC_SETPOINT_SUPPORT 0 |
| 5319 | #define IS_HEADROOM_DETECTION_SUPPORT 0 |
| 5320 | #define IS_SET_TX_BSI_CW_NEEDED 0 |
| 5321 | #elif IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION |
| 5322 | #define IS_DLIF_CHIP 1 |
| 5323 | #define IS_DCR_IN_DLIF_CHIP 0 |
| 5324 | #define IS_DYNAMIC_SETPOINT_SUPPORT 1 |
| 5325 | #define IS_HEADROOM_DETECTION_SUPPORT 1 |
| 5326 | #if IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 5327 | #define IS_SET_TX_BSI_CW_NEEDED 0 |
| 5328 | #else |
| 5329 | #define IS_SET_TX_BSI_CW_NEEDED 1 |
| 5330 | #endif |
| 5331 | #else |
| 5332 | #define IS_DLIF_CHIP 0 |
| 5333 | #define IS_DCR_IN_DLIF_CHIP 0 |
| 5334 | #define IS_DYNAMIC_SETPOINT_SUPPORT 0 |
| 5335 | #define IS_HEADROOM_DETECTION_SUPPORT 0 |
| 5336 | #define IS_SET_TX_BSI_CW_NEEDED 0 |
| 5337 | #endif |
| 5338 | |
| 5339 | #if IS_HEADROOM_DETECTION_SUPPORT |
| 5340 | #if IS_CHIP_MT6256 || IS_CHIP_MT6251 || IS_CHIP_MT6255 || IS_CHIP_MT6250 |
| 5341 | #define IS_IM_HEADROOM_DETECTION_SUPPORT 1 |
| 5342 | #else |
| 5343 | #define IS_IM_HEADROOM_DETECTION_SUPPORT 0 |
| 5344 | #endif |
| 5345 | #else |
| 5346 | #define IS_IM_HEADROOM_DETECTION_SUPPORT 0 |
| 5347 | #endif |
| 5348 | |
| 5349 | #if IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 5350 | #define IS_INBAND_BLOCKER_DETECTION_SUPPORT 1 |
| 5351 | #else |
| 5352 | #define IS_INBAND_BLOCKER_DETECTION_SUPPORT 0 |
| 5353 | #endif |
| 5354 | |
| 5355 | #if defined(L1_SIM) |
| 5356 | #define IS_OUTBAND_BLOCKER_DETECTION_SUPPORT 0 |
| 5357 | #elif IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M |
| 5358 | #define IS_OUTBAND_BLOCKER_DETECTION_SUPPORT 1 |
| 5359 | #else |
| 5360 | #define IS_OUTBAND_BLOCKER_DETECTION_SUPPORT 0 |
| 5361 | #endif |
| 5362 | |
| 5363 | #if IS_OUTBAND_BLOCKER_DETECTION_SUPPORT |
| 5364 | #define IS_DSP_RX_DCOC_SUPPORT 1 |
| 5365 | #else |
| 5366 | #define IS_DSP_RX_DCOC_SUPPORT 0 |
| 5367 | #endif |
| 5368 | |
| 5369 | #if IS_RF_MT6179 |
| 5370 | #define IS_DUAL_RF_SIP_CHIP_SUPPORT 1 |
| 5371 | #else |
| 5372 | #define IS_DUAL_RF_SIP_CHIP_SUPPORT 0 |
| 5373 | #endif |
| 5374 | |
| 5375 | #if IS_INBAND_BLOCKER_DETECTION_SUPPORT |
| 5376 | #if IS_CHIP_MT6250 |
| 5377 | #define IS_IM_INBAND_BLOCKER_DETECTION_SUPPORT 1 |
| 5378 | #else |
| 5379 | #define IS_IM_INBAND_BLOCKER_DETECTION_SUPPORT 0 |
| 5380 | #endif |
| 5381 | #else |
| 5382 | #define IS_IM_INBAND_BLOCKER_DETECTION_SUPPORT 0 |
| 5383 | #endif |
| 5384 | |
| 5385 | #if IS_RF_MT6256RF || IS_RF_MT6251RF || IS_RF_MT6252RF || IS_RF_MT6255RF || IS_RF_MT6162 || IS_RF_MT6163 || IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M |
| 5386 | #define IS_DYNAMIC_MACRO_SUPPORT 1 |
| 5387 | #else |
| 5388 | #define IS_DYNAMIC_MACRO_SUPPORT 0 |
| 5389 | #endif |
| 5390 | |
| 5391 | #if IS_RF_MT6256RF |
| 5392 | #define IS_DYNAMIC_TC_GAIN_SUPPORT 1 |
| 5393 | #define IS_TEMP_COMP_TC_GAIN_SUPPORT 1 |
| 5394 | #elif IS_RF_MT6255RF |
| 5395 | #define IS_DYNAMIC_TC_GAIN_SUPPORT 0 |
| 5396 | #define IS_TEMP_COMP_TC_GAIN_SUPPORT 0 |
| 5397 | #else |
| 5398 | #define IS_DYNAMIC_TC_GAIN_SUPPORT 0 |
| 5399 | #define IS_TEMP_COMP_TC_GAIN_SUPPORT 0 |
| 5400 | #endif |
| 5401 | |
| 5402 | #if IS_CHIP_MT6583_MD2 |
| 5403 | #define IS_GCMACHINE_SUPPORT 1 |
| 5404 | #elif IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_CHIP_MT6252 |
| 5405 | #define IS_GCMACHINE_SUPPORT 0 |
| 5406 | #else |
| 5407 | #define IS_GCMACHINE_SUPPORT 1 |
| 5408 | #endif |
| 5409 | |
| 5410 | #if IS_CHIP_MT6256 |
| 5411 | #define IS_MT6251_DCR_MODE 0 |
| 5412 | #define IS_MT6256_DCR_MODE 0 |
| 5413 | #define IS_MT6251_E1_FT 0 |
| 5414 | #if IS_MT6256_DCR_MODE |
| 5415 | #define IS_W_CANCELLATION_SUPPORT 0 |
| 5416 | #else |
| 5417 | #define IS_W_CANCELLATION_SUPPORT 1 |
| 5418 | #endif |
| 5419 | #elif IS_CHIP_MT6251 |
| 5420 | #define IS_MT6251_DCR_MODE 0 |
| 5421 | #define IS_MT6256_DCR_MODE 0 |
| 5422 | #define IS_MT6251_E1_FT 0 |
| 5423 | #if IS_MT6251_DCR_MODE |
| 5424 | #define IS_W_CANCELLATION_SUPPORT 0 |
| 5425 | #else |
| 5426 | #define IS_W_CANCELLATION_SUPPORT 1 |
| 5427 | #endif |
| 5428 | #elif IS_CHIP_MT6255 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 5429 | #define IS_MT6251_DCR_MODE 0 |
| 5430 | #define IS_MT6256_DCR_MODE 0 |
| 5431 | #define IS_W_CANCELLATION_SUPPORT 1 |
| 5432 | #define IS_MT6251_E1_FT 0 |
| 5433 | #else |
| 5434 | #define IS_MT6251_DCR_MODE 0 |
| 5435 | #define IS_MT6256_DCR_MODE 0 |
| 5436 | #define IS_W_CANCELLATION_SUPPORT 0 |
| 5437 | #define IS_MT6251_E1_FT 0 |
| 5438 | #endif |
| 5439 | |
| 5440 | #if IS_CHIP_MT6256 |
| 5441 | #if defined(__BT_SUPPORT__) |
| 5442 | #define IS_BT_R_CAL_SUPPORT 1 |
| 5443 | #else |
| 5444 | #define IS_BT_R_CAL_SUPPORT 0 |
| 5445 | #endif |
| 5446 | #else |
| 5447 | #define IS_BT_R_CAL_SUPPORT 0 |
| 5448 | #endif |
| 5449 | |
| 5450 | #if IS_CHIP_MT6256_S00 |
| 5451 | #define IS_SWITD_SUPPORT 0 |
| 5452 | #elif IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 5453 | #define IS_SWITD_SUPPORT 1 |
| 5454 | #else |
| 5455 | #define IS_SWITD_SUPPORT 0 |
| 5456 | #endif |
| 5457 | |
| 5458 | #if IS_SWITD_SUPPORT |
| 5459 | #if IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250 |
| 5460 | #define IS_IM_SWITD_SUPPORT 1 |
| 5461 | #else |
| 5462 | #define IS_IM_SWITD_SUPPORT 0 |
| 5463 | #endif |
| 5464 | #else |
| 5465 | #define IS_IM_SWITD_SUPPORT 0 |
| 5466 | #endif |
| 5467 | |
| 5468 | #if IS_DSP_INIT_FLOW_V2_SUPPORT |
| 5469 | #define IS_POLLING_SHERIF_AFTER_DSP_RESET_NEEDED 1 |
| 5470 | #else |
| 5471 | #define IS_POLLING_SHERIF_AFTER_DSP_RESET_NEEDED 0 |
| 5472 | #endif |
| 5473 | |
| 5474 | /* IS_SPEECH_RESYNC_SUPPORT :L1D inform Audio to trigger VBI-Reset(DSP-Speech reset) */ |
| 5475 | /* IS_SPEECH_RESYNC_SUPPORT_V2:L1D provide API to Audio, Audio query these API to trigger speech resync */ |
| 5476 | /* MT6582 or latter version use IS_SPEECH_RESYNC_SUPPORT_V2*/ |
| 5477 | #if IS_DSP_ARCHITECTURE_V1_SUPPORT || IS_DSP_ARCHITECTURE_V2_SUPPORT || IS_DSP_ARCHITECTURE_V3_SUPPORT |
| 5478 | #define IS_SPEECH_RESYNC_SUPPORT 0 |
| 5479 | #define IS_SPEECH_RESYNC_SUPPORT_V2 0 |
| 5480 | #elif IS_CHIP_MT6582 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 5481 | #define IS_SPEECH_RESYNC_SUPPORT 0 |
| 5482 | #define IS_SPEECH_RESYNC_SUPPORT_V2 1 |
| 5483 | #elif IS_LOCK_AFCDAC_AT_STARTUP_SUPPORT |
| 5484 | #define IS_SPEECH_RESYNC_SUPPORT 0 |
| 5485 | #define IS_SPEECH_RESYNC_SUPPORT_V2 1 |
| 5486 | #else |
| 5487 | #define IS_SPEECH_RESYNC_SUPPORT 1 |
| 5488 | #define IS_SPEECH_RESYNC_SUPPORT_V2 0 |
| 5489 | #endif |
| 5490 | |
| 5491 | #if defined(L1D_TEST) |
| 5492 | #undef IS_HEADROOM_DETECTION_SUPPORT |
| 5493 | #undef IS_INBAND_BLOCKER_DETECTION_SUPPORT |
| 5494 | #undef IS_OUTBAND_BLOCKER_DETECTION_SUPPORT |
| 5495 | #undef IS_DYNAMIC_SETPOINT_SUPPORT |
| 5496 | #undef IS_W_CANCELLATION_SUPPORT |
| 5497 | #undef IS_SWITD_SUPPORT |
| 5498 | #define IS_HEADROOM_DETECTION_SUPPORT 0 |
| 5499 | #define IS_INBAND_BLOCKER_DETECTION_SUPPORT 0 |
| 5500 | #define IS_OUTBAND_BLOCKER_DETECTION_SUPPORT 0 |
| 5501 | #define IS_DYNAMIC_SETPOINT_SUPPORT 0 |
| 5502 | #define IS_W_CANCELLATION_SUPPORT 0 |
| 5503 | #define IS_SWITD_SUPPORT 0 |
| 5504 | #endif |
| 5505 | |
| 5506 | #if defined(L1_SIM) |
| 5507 | #undef IS_W_CANCELLATION_SUPPORT |
| 5508 | #undef IS_SPEECH_RESYNC_SUPPORT |
| 5509 | #define IS_W_CANCELLATION_SUPPORT 0 |
| 5510 | #define IS_SPEECH_RESYNC_SUPPORT 0 |
| 5511 | #endif |
| 5512 | |
| 5513 | #if IS_W_CANCELLATION_SUPPORT |
| 5514 | #define IS_WC_SLOW_TRACKING_SUPPORT 1 |
| 5515 | #if IS_WC_SLOW_TRACKING_SUPPORT |
| 5516 | #define IS_WC_SUB_KEEP_GAIN_DIM 0 |
| 5517 | #else |
| 5518 | #define IS_WC_SUB_KEEP_GAIN_DIM 1 |
| 5519 | #endif |
| 5520 | #if IS_CHIP_MT6251_S00 || IS_CHIP_MT6256_S00 |
| 5521 | #define IS_WC_IMM_MODE_ENABLE 0 |
| 5522 | #else |
| 5523 | #define IS_WC_IMM_MODE_ENABLE 1 |
| 5524 | #endif |
| 5525 | #else |
| 5526 | #define IS_WC_SLOW_TRACKING_SUPPORT 0 |
| 5527 | #define IS_WC_SUB_KEEP_GAIN_DIM 0 |
| 5528 | #define IS_WC_IMM_MODE_ENABLE 0 |
| 5529 | #endif |
| 5530 | |
| 5531 | #if IS_EPSK_TX_SUPPORT |
| 5532 | #if IS_RF_MT6256RF || IS_RF_MT6162 || IS_RF_MT6163 || IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M |
| 5533 | #define IS_EPSK_TX_GAIN_CONTROL_SUPPORT 1 |
| 5534 | #else |
| 5535 | #define IS_EPSK_TX_GAIN_CONTROL_SUPPORT 0 |
| 5536 | #endif |
| 5537 | #else |
| 5538 | #define IS_EPSK_TX_GAIN_CONTROL_SUPPORT 0 |
| 5539 | #endif |
| 5540 | |
| 5541 | #if IS_RF_MT6252RF |
| 5542 | #define IS_RF_VCO_DOO_OFF 0 |
| 5543 | #define IS_RF_VCO_PARTIAL_DOO_ON 1 |
| 5544 | #elif IS_RF_MT6162 |
| 5545 | #define IS_RF_VCO_DOO_OFF 0 |
| 5546 | #define IS_RF_VCO_PARTIAL_DOO_ON 1 |
| 5547 | #elif IS_RF_MT6251RF |
| 5548 | #if IS_MT6251_E1_FT |
| 5549 | #define IS_RF_VCO_DOO_OFF 0 |
| 5550 | #define IS_RF_VCO_PARTIAL_DOO_ON 0 |
| 5551 | #else |
| 5552 | #define IS_RF_VCO_DOO_OFF 0 |
| 5553 | #define IS_RF_VCO_PARTIAL_DOO_ON 1 |
| 5554 | #endif |
| 5555 | #elif IS_RF_MT6255RF |
| 5556 | #define IS_RF_VCO_DOO_OFF 0 |
| 5557 | #define IS_RF_VCO_PARTIAL_DOO_ON 1 |
| 5558 | #else |
| 5559 | #define IS_RF_VCO_DOO_OFF 0 |
| 5560 | #define IS_RF_VCO_PARTIAL_DOO_ON 0 |
| 5561 | #endif |
| 5562 | |
| 5563 | #if IS_CHIP_MT6252_S00 |
| 5564 | #define IS_RF_TX_SLEEP_MODE_SUPPORT 0 |
| 5565 | #elif IS_CHIP_MT6252 |
| 5566 | #define IS_RF_TX_SLEEP_MODE_SUPPORT 1 |
| 5567 | #elif IS_CHIP_MT6251_S00 |
| 5568 | #define IS_RF_TX_SLEEP_MODE_SUPPORT 0 |
| 5569 | #elif IS_CHIP_MT6251 |
| 5570 | #define IS_RF_TX_SLEEP_MODE_SUPPORT 1 |
| 5571 | #else |
| 5572 | #define IS_RF_TX_SLEEP_MODE_SUPPORT 0 |
| 5573 | #endif |
| 5574 | |
| 5575 | #if IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M |
| 5576 | #define IS_OBB_DETECTION_SUPPORT 1 |
| 5577 | #else |
| 5578 | #define IS_OBB_DETECTION_SUPPORT 0 |
| 5579 | #endif |
| 5580 | |
| 5581 | #if IS_CHIP_MT6251_S00 || IS_CHIP_MT6252_S00 |
| 5582 | #define IS_DSP_PIO_GLITCH_FIXED_NEEDED 0 |
| 5583 | #elif IS_CHIP_MT6251 || IS_CHIP_MT6252 |
| 5584 | #define IS_DSP_PIO_GLITCH_FIXED_NEEDED 1 |
| 5585 | #else |
| 5586 | #define IS_DSP_PIO_GLITCH_FIXED_NEEDED 0 |
| 5587 | #endif |
| 5588 | |
| 5589 | #if IS_CHIP_MT6251_S00 || IS_CHIP_MT6256_S00 |
| 5590 | #define IS_FB_LONG_WINDOW_RXWIN_MULTIPLY_SUPPORT 1 |
| 5591 | #else |
| 5592 | #define IS_FB_LONG_WINDOW_RXWIN_MULTIPLY_SUPPORT 0 |
| 5593 | #endif |
| 5594 | |
| 5595 | #if IS_CHIP_MT6256_S00 |
| 5596 | #define IS_RTX_BUFFER_POWER_CTRL_SUPPORT 0 |
| 5597 | #define IS_IDMA_SHORT_PORT_MODE_V2_SUPPORT 0 |
| 5598 | #define IS_ACCESS_SHERIF_BY_IDMA_SUPPORT 0 |
| 5599 | #elif IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 5600 | #define IS_RTX_BUFFER_POWER_CTRL_SUPPORT 1 |
| 5601 | #define IS_IDMA_SHORT_PORT_MODE_V2_SUPPORT 1 |
| 5602 | #define IS_ACCESS_SHERIF_BY_IDMA_SUPPORT 1 |
| 5603 | #else |
| 5604 | #define IS_RTX_BUFFER_POWER_CTRL_SUPPORT 0 |
| 5605 | #define IS_IDMA_SHORT_PORT_MODE_V2_SUPPORT 0 |
| 5606 | #define IS_ACCESS_SHERIF_BY_IDMA_SUPPORT 0 |
| 5607 | #endif |
| 5608 | |
| 5609 | #if IS_CHIP_MT6256_S00 |
| 5610 | #define IS_DYNAMIC_SWITCH_DDS_SUPPORT 0 |
| 5611 | #elif IS_CHIP_MT6256 |
| 5612 | #define IS_DYNAMIC_SWITCH_DDS_SUPPORT 1 |
| 5613 | #else |
| 5614 | #define IS_DYNAMIC_SWITCH_DDS_SUPPORT 0 |
| 5615 | #endif |
| 5616 | |
| 5617 | #if defined(__F32_XOSC_REMOVAL_SUPPORT__) |
| 5618 | #define IS_32K_CRYSTAL_REMOVAL_SUPPORT 1 |
| 5619 | #else |
| 5620 | #define IS_32K_CRYSTAL_REMOVAL_SUPPORT 0 |
| 5621 | #endif |
| 5622 | |
| 5623 | /* IS_CLOAD_CAL_BBLPM_V1_SUPPORT: use BBLPM in FHC and SW LPM in traditional cal */ |
| 5624 | #if IS_32K_CRYSTAL_REMOVAL_SUPPORT |
| 5625 | #if IS_CHIP_MT6755 || IS_CHIP_MT6292 |
| 5626 | #define IS_CLOAD_CAL_BBLPM_V1_SUPPORT 1 |
| 5627 | #elif IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 //&& IS_MML1_PMIC_MT6356 |
| 5628 | #define IS_CLOAD_CAL_BBLPM_V1_SUPPORT 0 |
| 5629 | #else |
| 5630 | #error "Please check CHIP and PMIC version" |
| 5631 | #endif |
| 5632 | #endif |
| 5633 | |
| 5634 | #if IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_MT6577 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 |
| 5635 | #define IS_ABB_HW_CALIBRATION_SUPPORT 1 |
| 5636 | #else |
| 5637 | #define IS_ABB_HW_CALIBRATION_SUPPORT 0 |
| 5638 | #endif |
| 5639 | |
| 5640 | #if IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6252 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 5641 | #define IS_BSI_SX0_SUPPORT 1 |
| 5642 | #else |
| 5643 | #define IS_BSI_SX0_SUPPORT 0 |
| 5644 | #endif |
| 5645 | |
| 5646 | #if IS_CHIP_MT6256 || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6252 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 5647 | #define IS_BPI_V2_SUPPORT 1 |
| 5648 | #else |
| 5649 | #define IS_BPI_V2_SUPPORT 0 |
| 5650 | #endif |
| 5651 | |
| 5652 | #if IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6252 |
| 5653 | #define IS_BSI_V2_SUPPORT 1 |
| 5654 | #else |
| 5655 | #define IS_BSI_V2_SUPPORT 0 |
| 5656 | #endif |
| 5657 | |
| 5658 | #define IS_BPI_V1_SUPPORT (!IS_BPI_V2_SUPPORT) |
| 5659 | #define IS_BSI_V1_SUPPORT (!IS_BSI_V2_SUPPORT) |
| 5660 | |
| 5661 | #if IS_BSI_V2_SUPPORT |
| 5662 | #if IS_CHIP_MT6256 || IS_CHIP_MT6252 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 5663 | #define IS_BSI_V2_ST2_SUPPORT 0 |
| 5664 | #elif IS_CHIP_MT6251 || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6583_MD2 |
| 5665 | #define IS_BSI_V2_ST2_SUPPORT 1 |
| 5666 | #elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION |
| 5667 | #define IS_BSI_V2_ST2_SUPPORT 1 |
| 5668 | #else |
| 5669 | #define IS_BSI_V2_ST2_SUPPORT 0 |
| 5670 | #endif |
| 5671 | #else |
| 5672 | #define IS_BSI_V2_ST2_SUPPORT 0 |
| 5673 | #endif |
| 5674 | |
| 5675 | #if IS_BPI_V2_SUPPORT |
| 5676 | #if defined(__2G_BPI_PT3A_SUPPORT__) |
| 5677 | #define IS_BPI_V2_PT3A_SUPPORT 1 |
| 5678 | #elif defined(L1_SIM) |
| 5679 | #define IS_BPI_V2_PT3A_SUPPORT 1 |
| 5680 | #elif IS_CHIP_MT6582 |
| 5681 | #define IS_BPI_V2_PT3A_SUPPORT 1 |
| 5682 | #else |
| 5683 | #define IS_BPI_V2_PT3A_SUPPORT 0 |
| 5684 | #endif |
| 5685 | #else |
| 5686 | #define IS_BPI_V2_PT3A_SUPPORT 0 |
| 5687 | #endif |
| 5688 | |
| 5689 | #if defined(L1_SIM) && defined(MT6162_DUAL_RF) |
| 5690 | /* Note: for the combination of MT6280+MT6162_DUAL_RF, we should define IS_BSI_V2_ST2_SUPPORT */ |
| 5691 | #undef IS_BSI_V2_ST2_SUPPORT |
| 5692 | #define IS_BSI_V2_ST2_SUPPORT 1 |
| 5693 | #endif |
| 5694 | |
| 5695 | #if IS_BSI_V1_SUPPORT || IS_BSI_V2_ST2_SUPPORT |
| 5696 | #define IS_BSI_ST2_SUPPORT 1 |
| 5697 | #else |
| 5698 | #define IS_BSI_ST2_SUPPORT 0 |
| 5699 | #endif |
| 5700 | |
| 5701 | #if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION |
| 5702 | #define IS_BSI_ST2B_SUPPORT 1 |
| 5703 | #else |
| 5704 | #define IS_BSI_ST2B_SUPPORT 0 |
| 5705 | #endif |
| 5706 | |
| 5707 | #if IS_BSI_V1_SUPPORT && IS_EPSK_TX_SUPPORT |
| 5708 | #define IS_BSI_ST2M_SUPPORT 1 |
| 5709 | #elif IS_BSI_V2_SUPPORT |
| 5710 | #define IS_BSI_ST2M_SUPPORT 1 |
| 5711 | #else |
| 5712 | #define IS_BSI_ST2M_SUPPORT 0 |
| 5713 | #endif |
| 5714 | |
| 5715 | #if IS_GPRS || IS_MULTISLOT_TX_SUPPORT |
| 5716 | #define IS_CALCULATE_PM_TABLE_SUPPORT 1 |
| 5717 | #else |
| 5718 | #define IS_CALCULATE_PM_TABLE_SUPPORT 0 |
| 5719 | #endif |
| 5720 | |
| 5721 | #if IS_RF_MT6162 || IS_RF_MT6163 |
| 5722 | #define IS_RF_RX_DCOC_SUPPORT 1 |
| 5723 | #if IS_CHIP_MT6577 || IS_CHIP_MT6583_MD2 |
| 5724 | #define IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT 1 |
| 5725 | #else |
| 5726 | #define IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT 0 |
| 5727 | #endif |
| 5728 | #if IS_EPSK_TX_SUPPORT |
| 5729 | #define IS_RF_TX_CALIBRATION_SUPPORT 1 |
| 5730 | #else |
| 5731 | #define IS_RF_TX_CALIBRATION_SUPPORT 0 |
| 5732 | #endif |
| 5733 | #else |
| 5734 | #define IS_RF_RX_DCOC_SUPPORT 0 |
| 5735 | #define IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT 0 |
| 5736 | #define IS_RF_TX_CALIBRATION_SUPPORT 0 |
| 5737 | #endif |
| 5738 | |
| 5739 | #if defined(L1_SIM) || IS_CHIP_TK6280 /* TK6280 FPGA not support the following feature */ |
| 5740 | #undef IS_RF_RX_DCOC_SUPPORT |
| 5741 | #undef IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT |
| 5742 | #undef IS_RF_TX_CALIBRATION_SUPPORT |
| 5743 | #define IS_RF_RX_DCOC_SUPPORT 0 |
| 5744 | #define IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT 0 |
| 5745 | #define IS_RF_TX_CALIBRATION_SUPPORT 0 |
| 5746 | #endif |
| 5747 | |
| 5748 | #if IS_CACHE_DSP_SUPPORT || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 5749 | #define IS_SIX_IRDMA_MPU_SETTING_CHIP 0 |
| 5750 | #elif IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6268A) || IS_CHIP_SER(CHIP_ID_MT6256) |
| 5751 | #define IS_SIX_IRDMA_MPU_SETTING_CHIP 1 |
| 5752 | #else |
| 5753 | #define IS_SIX_IRDMA_MPU_SETTING_CHIP 0 |
| 5754 | #endif |
| 5755 | |
| 5756 | #if IS_CHIP_MT6251 |
| 5757 | #define IS_SINGLE_DSP_TRX_REGION_SUPPORT 1 |
| 5758 | #else |
| 5759 | #define IS_SINGLE_DSP_TRX_REGION_SUPPORT 0 |
| 5760 | #endif |
| 5761 | |
| 5762 | #if IS_CHIP_MT6252 |
| 5763 | #define IS_RTX_DATA_MOVED_BY_IRDMA_SUPPORT 0 |
| 5764 | #elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION |
| 5765 | #define IS_RTX_DATA_MOVED_BY_IRDMA_SUPPORT 1 |
| 5766 | #else |
| 5767 | #define IS_RTX_DATA_MOVED_BY_IRDMA_SUPPORT 0 |
| 5768 | #endif |
| 5769 | |
| 5770 | #if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6252 || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION |
| 5771 | #define IS_DSP_FCCH_LENGTH_DYNAMIC_SET_SUPPORT 1 |
| 5772 | #else |
| 5773 | #define IS_DSP_FCCH_LENGTH_DYNAMIC_SET_SUPPORT 0 |
| 5774 | #endif |
| 5775 | |
| 5776 | #if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251_S00 |
| 5777 | #undef IS_DSP_FCCH_LENGTH_DYNAMIC_SET_SUPPORT |
| 5778 | #define IS_DSP_FCCH_LENGTH_DYNAMIC_SET_SUPPORT 0 |
| 5779 | #endif |
| 5780 | |
| 5781 | #if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION |
| 5782 | #define IS_DUAL_MAC_DSP_NEW_EQ_CHECK_SUPPORT 1 |
| 5783 | #else |
| 5784 | #define IS_DUAL_MAC_DSP_NEW_EQ_CHECK_SUPPORT 0 |
| 5785 | #endif |
| 5786 | |
| 5787 | #if IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 5788 | #define IS_6R6T_HW_SUPPORT_CHIP 1 |
| 5789 | #else |
| 5790 | #define IS_6R6T_HW_SUPPORT_CHIP 0 |
| 5791 | #endif |
| 5792 | |
| 5793 | #if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251 |
| 5794 | #define IS_DSP_COSTDOWN_FB_CHIP 0 |
| 5795 | #elif IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6268T) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6223) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6236) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6252H) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6276) |
| 5796 | #define IS_DSP_COSTDOWN_FB_CHIP 0 |
| 5797 | #else |
| 5798 | #define IS_DSP_COSTDOWN_FB_CHIP 1 |
| 5799 | #endif |
| 5800 | |
| 5801 | #if defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__) || defined(__L1_GPS_REF_TIME_SUPPORT__) |
| 5802 | #define L1D_AGPS_TIMING_SYNC_SUPPORT 1 |
| 5803 | #else |
| 5804 | #define L1D_AGPS_TIMING_SYNC_SUPPORT 0 |
| 5805 | #endif |
| 5806 | |
| 5807 | #if IS_CENTRALIZED_SMM_CHIP |
| 5808 | #if IS_CHIP_MT6276_S00 || IS_CHIP_MT6573 |
| 5809 | #define L1D_AGPS_OLD_REGISTER 1 |
| 5810 | #else |
| 5811 | #define L1D_AGPS_OLD_REGISTER 0 |
| 5812 | #endif |
| 5813 | #endif |
| 5814 | |
| 5815 | // HW clock gating |
| 5816 | #if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6297) |
| 5817 | #define IS_HWCG_SUPPORT 0 |
| 5818 | #elif IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 5819 | #define IS_HWCG_SUPPORT 1 |
| 5820 | #else |
| 5821 | #define IS_HWCG_SUPPORT 0 |
| 5822 | #endif |
| 5823 | |
| 5824 | // Modem hard real time recovery enhancement |
| 5825 | #ifdef __MD_HRT_RECOVERY__ |
| 5826 | #define IS_MD_HRT_RECOVERY_SUPPORT 1 |
| 5827 | #else |
| 5828 | #define IS_MD_HRT_RECOVERY_SUPPORT 0 |
| 5829 | #endif |
| 5830 | |
| 5831 | // APC Ramping Profiles support |
| 5832 | #define APC_PROFILE_NUM 7 |
| 5833 | |
| 5834 | #if IS_CHIP_MT6208 |
| 5835 | #undef APC_PROFILE_NUM |
| 5836 | #define APC_PROFILE_NUM 6 |
| 5837 | #endif |
| 5838 | |
| 5839 | #if IS_NEW_L1D_ARCH_SUPPORT |
| 5840 | #undef APC_PROFILE_NUM |
| 5841 | #define APC_PROFILE_NUM 5 |
| 5842 | #endif |
| 5843 | |
| 5844 | #define IS_5_BANK_RAMP_PROFILES_SUPPORT (APC_PROFILE_NUM==5) |
| 5845 | #define IS_6_BANK_RAMP_PROFILES_SUPPORT (APC_PROFILE_NUM==6) |
| 5846 | #define IS_7_BANK_RAMP_PROFILES_SUPPORT (APC_PROFILE_NUM==7) |
| 5847 | |
| 5848 | #if defined (__2G_TX_POWER_CONTROL_SUPPORT__) |
| 5849 | #define IS_TX_POWER_CONTROL_SUPPORT 1 |
| 5850 | #if IS_CHIP_MT6256 |
| 5851 | #define IS_TXPC_CL_AUXADC_SUPPORT 1 /* Closed-loop. Vdet from AUXADC */ |
| 5852 | #define IS_TXPC_CL_BSI_SUPPORT 0 /* Closed-loop. Pdet from BSI HW readback */ |
| 5853 | #define IS_TXPC_OL_AUXADC_SUPPORT 0 /* Open-loop. Ext. temperature from AUXADC */ |
| 5854 | #define IS_TXPC_OL_BSI_SUPPORT 1 /* Open-loop. RF temperature from BSI HW readback */ |
| 5855 | #elif IS_CHIP_MT6575 || IS_CHIP_MT6583_MD2 |
| 5856 | #define IS_TXPC_CL_AUXADC_SUPPORT 0 |
| 5857 | #define IS_TXPC_CL_BSI_SUPPORT 1 |
| 5858 | #define IS_TXPC_OL_AUXADC_SUPPORT 1 |
| 5859 | #define IS_TXPC_OL_BSI_SUPPORT 0 |
| 5860 | #elif IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 5861 | #define IS_TXPC_CL_AUXADC_SUPPORT 0 |
| 5862 | #define IS_TXPC_CL_BSI_SUPPORT 1 |
| 5863 | #define IS_TXPC_OL_AUXADC_SUPPORT 0 |
| 5864 | #define IS_TXPC_OL_BSI_SUPPORT 1 |
| 5865 | #elif IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION |
| 5866 | #define IS_TXPC_CL_AUXADC_SUPPORT 1 |
| 5867 | #define IS_TXPC_CL_BSI_SUPPORT 1 |
| 5868 | #define IS_TXPC_OL_AUXADC_SUPPORT 1 |
| 5869 | #define IS_TXPC_OL_BSI_SUPPORT 0 |
| 5870 | #endif |
| 5871 | #else |
| 5872 | #define IS_TX_POWER_CONTROL_SUPPORT 0 |
| 5873 | #define IS_TXPC_CL_AUXADC_SUPPORT 0 |
| 5874 | #define IS_TXPC_CL_BSI_SUPPORT 0 |
| 5875 | #define IS_TXPC_OL_AUXADC_SUPPORT 0 |
| 5876 | #define IS_TXPC_OL_BSI_SUPPORT 0 |
| 5877 | #endif |
| 5878 | |
| 5879 | #if IS_TX_POWER_CONTROL_SUPPORT && ( IS_RF_MT6177L || IS_RF_MT6177M || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T) |
| 5880 | #define IS_RSSI_TC_SUPPORT 1 /* RSSI Temperature Compensation will reuse TXPC's temperature info */ |
| 5881 | #else |
| 5882 | #define IS_RSSI_TC_SUPPORT 0 |
| 5883 | #endif |
| 5884 | |
| 5885 | #if IS_RF_MT6162 || IS_RF_MT6256RF || IS_RF_MT6163 || IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M |
| 5886 | #define IS_RF_TX_POWER_CONTROL_SUPPORT 1 |
| 5887 | #else |
| 5888 | #define IS_RF_TX_POWER_CONTROL_SUPPORT 0 |
| 5889 | #endif |
| 5890 | |
| 5891 | #if IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M |
| 5892 | #define IS_ORION_RF_SERIES 1 |
| 5893 | #else |
| 5894 | #define IS_ORION_RF_SERIES 0 |
| 5895 | #endif |
| 5896 | |
| 5897 | #if (IS_RF_MT6177L && defined(__IS_2G_DYNAMIC_GAINTABLE_SWITCH_SUPPORT__)) |
| 5898 | #define IS_2G_DYNAMIC_GAINTABLE_SWITCH_SUPPORT 1 //Boost LPF2 Gain for Pin=-96~-102dBm |
| 5899 | #else |
| 5900 | #define IS_2G_DYNAMIC_GAINTABLE_SWITCH_SUPPORT 0 |
| 5901 | #endif |
| 5902 | |
| 5903 | #if IS_GPRS |
| 5904 | #define IS_DECREASE_RF_TX_MAX_POWER_SUPPORT 1 |
| 5905 | #else |
| 5906 | #define IS_DECREASE_RF_TX_MAX_POWER_SUPPORT 0 |
| 5907 | #endif |
| 5908 | |
| 5909 | #if defined(__TAS_SUPPORT__) |
| 5910 | #define IS_TAS_MAX_TXPWR_REDUCTION_SUPPORT 1 |
| 5911 | #else |
| 5912 | #define IS_TAS_MAX_TXPWR_REDUCTION_SUPPORT 0 |
| 5913 | #endif |
| 5914 | |
| 5915 | #if defined (__MULTI_LNA_MODE_CALIBRATION_SUPPORT__) |
| 5916 | #if IS_CHIP_MT6582 |
| 5917 | #define IS_MULTI_LNA_MODE_CALIBRATION_SUPPORT 1 |
| 5918 | #define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT 1 /* pathloss cal with one LNA or multi-lna mode are adjustable by tool config */ |
| 5919 | #define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT_V2 0 /* pathloss cal with one LNA or multi-lna mode are adjustable by tool config, and LNA Mode can be choose by L1 */ |
| 5920 | #else |
| 5921 | #define IS_MULTI_LNA_MODE_CALIBRATION_SUPPORT 1 |
| 5922 | #define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT 0 |
| 5923 | #define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT_V2 0 |
| 5924 | #endif |
| 5925 | #else |
| 5926 | #define IS_MULTI_LNA_MODE_CALIBRATION_SUPPORT 0 |
| 5927 | #define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT 0 |
| 5928 | #define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT_V2 0 |
| 5929 | #endif |
| 5930 | |
| 5931 | #if defined (__2G_TX_GAIN_RF_CALIBRATION__) |
| 5932 | #define IS_TX_GAIN_RF_CALIBRATION_SUPPORT 1 |
| 5933 | #else |
| 5934 | #define IS_TX_GAIN_RF_CALIBRATION_SUPPORT 0 |
| 5935 | #endif |
| 5936 | |
| 5937 | /* for dual talk project, RX LNA > LNA2 which is co-band with 3G need to change to another gain table */ |
| 5938 | #define IS_DUAL_TALK_RX_GAIN_TABLE_CO_BAND_SUPPORT 0 |
| 5939 | |
| 5940 | #if IS_EPSK_TX_SUPPORT |
| 5941 | #if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6583_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 5942 | #define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT 1 /* Change the GMSK and EPSK TX window positions dynamically by slots. */ |
| 5943 | #define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2 0 /* Change the GMSK and EPSK TX window positions dynamically by frames */ |
| 5944 | /* according to the modulation type of the whole TX slot in each frame. */ |
| 5945 | #else |
| 5946 | #define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT 0 |
| 5947 | #define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2 1 |
| 5948 | #endif |
| 5949 | #else |
| 5950 | #define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT 0 |
| 5951 | #define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2 0 |
| 5952 | #endif |
| 5953 | |
| 5954 | #if defined(L1D_TEST) |
| 5955 | #undef IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT |
| 5956 | #undef IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2 |
| 5957 | #define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT 0 |
| 5958 | #define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2 0 |
| 5959 | #endif |
| 5960 | |
| 5961 | //#if IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_MT6177M || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T |
| 5962 | #define IS_RF_DUAL_LOOP_AFC_CONTROL_SUPPORT 1 |
| 5963 | //#else |
| 5964 | //#define IS_RF_DUAL_LOOP_AFC_CONTROL_SUPPORT 0 |
| 5965 | //#endif |
| 5966 | |
| 5967 | #if defined(L1D_TEST) |
| 5968 | #define IS_DUAL_LOOP_AFC_CONTROL_SUPPORT 0 |
| 5969 | #else |
| 5970 | #if IS_VCXO_LC_SUPPORT |
| 5971 | #error "Please implement Dual Loop AFC Control for VCXO" |
| 5972 | #elif IS_RF_DUAL_LOOP_AFC_CONTROL_SUPPORT |
| 5973 | #define IS_DUAL_LOOP_AFC_CONTROL_SUPPORT 1 |
| 5974 | #else |
| 5975 | #error "This RF Chip is not support Fix AFC and GPS Co-Clock" |
| 5976 | #endif |
| 5977 | #endif |
| 5978 | |
| 5979 | #if IS_DUAL_LOOP_AFC_CONTROL_SUPPORT |
| 5980 | #if IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T |
| 5981 | #define IS_FIX_AFC_OFFSET_CW_COMPENSATE_SUPPORT 1 |
| 5982 | #else |
| 5983 | #define IS_FIX_AFC_OFFSET_CW_COMPENSATE_SUPPORT 0 |
| 5984 | #endif |
| 5985 | #endif |
| 5986 | |
| 5987 | #if IS_DUAL_LOOP_AFC_CONTROL_SUPPORT |
| 5988 | #if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 5989 | #define IS_DSP_RX_NBIC_SUPPORT 1 |
| 5990 | #else |
| 5991 | #define IS_DSP_RX_NBIC_SUPPORT 0 |
| 5992 | #endif |
| 5993 | #if defined(L1D_TEST) |
| 5994 | #define IS_DSP_RX_NBIC_SUPPORT 0 |
| 5995 | #endif |
| 5996 | #else |
| 5997 | #define IS_DSP_RX_NBIC_SUPPORT 0 |
| 5998 | #endif |
| 5999 | |
| 6000 | #if IS_DUAL_LOOP_AFC_CONTROL_SUPPORT |
| 6001 | #define IS_LOCK_AFCDAC_AT_STARTUP_SUPPORT 1 |
| 6002 | #else |
| 6003 | #define IS_LOCK_AFCDAC_AT_STARTUP_SUPPORT 0 |
| 6004 | #endif |
| 6005 | |
| 6006 | #if defined(__AUDIO_DSP_LOWPOWER_V2__) |
| 6007 | #define IS_AUDIO_DSP_LOWPOWER_SUPPORT 1 |
| 6008 | #else |
| 6009 | #define IS_AUDIO_DSP_LOWPOWER_SUPPORT 0 |
| 6010 | #endif |
| 6011 | |
| 6012 | /* IS_AFC_EVENT_SUPPORT_CHIP: decide if the chip supports the AFC event register */ |
| 6013 | #if IS_AST_B2S_SUPPORT || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 |
| 6014 | #define IS_AFC_EVENT_SUPPORT_CHIP 1 |
| 6015 | #elif IS_SOC_CHIP || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6016 | #define IS_AFC_EVENT_SUPPORT_CHIP 0 |
| 6017 | #else |
| 6018 | #define IS_AFC_EVENT_SUPPORT_CHIP 1 |
| 6019 | #endif |
| 6020 | |
| 6021 | /* IS_DCXO_SUPPORT_CHIP: decide if the chip supports the way of sending AFCDAC values by BSI */ |
| 6022 | #if IS_SOC_CHIP || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6023 | #define IS_DCXO_SUPPORT_CHIP 1 |
| 6024 | #else |
| 6025 | #define IS_DCXO_SUPPORT_CHIP 0 |
| 6026 | #endif |
| 6027 | |
| 6028 | /* IS_DFM_RF_TIMING_CHECK_SUPPORT: add RF-BFE timing constraints at RX/TX on/off in l1d_data.c */ |
| 6029 | #if IS_RF_MT6252RF || IS_RF_MT6251RF || IS_RF_MT6256RF || IS_RF_MT6255RF || IS_RF_MT6162 || IS_RF_MT6163 || IS_RF_MT6250RF || IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M |
| 6030 | #define IS_DFM_RF_TIMING_CHECK_SUPPORT 1 |
| 6031 | #else |
| 6032 | #define IS_DFM_RF_TIMING_CHECK_SUPPORT 0 |
| 6033 | #endif |
| 6034 | |
| 6035 | /*IS_CONTINUOUS_TDMA_EVENT_TIMING_CHECK_SUPPORT: the timing difference of two succeed TDMA events should be larger than 1QB */ |
| 6036 | #if IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION && (!IS_CHIP_MT6256) && (!IS_CHIP_MT6251) && (!IS_CHIP_MT6255) |
| 6037 | #define IS_CONTINUOUS_TDMA_EVENT_TIMING_CHECK_SUPPORT 1 |
| 6038 | #else |
| 6039 | #define IS_CONTINUOUS_TDMA_EVENT_TIMING_CHECK_SUPPORT 0 |
| 6040 | #endif |
| 6041 | |
| 6042 | #if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6043 | #define IS_IMM_BSI_SEND_DUMMY_READ_ON 1 |
| 6044 | #else |
| 6045 | #define IS_IMM_BSI_SEND_DUMMY_READ_ON 0 |
| 6046 | #endif |
| 6047 | |
| 6048 | #if IS_RF_AD6548 || IS_RF_MT6139E || IS_RF_MTKSOC1 || IS_RF_MT6252RF || IS_RF_MT6251RF || IS_RF_MT6255RF |
| 6049 | #define IS_EPSK_TX_NOT_SUPPORT_RF 1 |
| 6050 | #else |
| 6051 | #define IS_EPSK_TX_NOT_SUPPORT_RF 0 |
| 6052 | #endif |
| 6053 | |
| 6054 | #if defined(L1_SIM) |
| 6055 | #define IS_TDMA_BSI_READBACK_SUPPORT 0 |
| 6056 | #elif IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION |
| 6057 | #define IS_TDMA_BSI_READBACK_SUPPORT 1 |
| 6058 | #else |
| 6059 | #define IS_TDMA_BSI_READBACK_SUPPORT 0 |
| 6060 | #endif |
| 6061 | |
| 6062 | #if defined(__CLASS_33_34__) |
| 6063 | #define IS_MULTISLOT_CLASS_33_34_SUPPORT 1 |
| 6064 | #else |
| 6065 | #define IS_MULTISLOT_CLASS_33_34_SUPPORT 0 |
| 6066 | #endif |
| 6067 | |
| 6068 | #if IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 6069 | #define IS_VAMOS_CAPABILITY 1 |
| 6070 | |
| 6071 | #define IS_VAMOS_SUPPORT 1 |
| 6072 | |
| 6073 | #define IS_SHIFTSACCH_SUPPORT 1 |
| 6074 | |
| 6075 | #else |
| 6076 | #define IS_VAMOS_CAPABILITY 0 |
| 6077 | #define IS_VAMOS_SUPPORT 0 |
| 6078 | #define IS_SHIFTSACCH_SUPPORT 0 |
| 6079 | #endif |
| 6080 | |
| 6081 | #if defined(L1D_TEST) && (IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 ) |
| 6082 | #define IS_COSIM_IRDMA_MPU_FULL_TEST_SUPPORT 1 |
| 6083 | #else |
| 6084 | #define IS_COSIM_IRDMA_MPU_FULL_TEST_SUPPORT 0 |
| 6085 | #endif |
| 6086 | |
| 6087 | #if defined(__UDVT__) && (IS_CHIP_MT6250 || IS_CHIP_MT6280) |
| 6088 | /* move the UDVT FH codes from the meut folder to l1 */ |
| 6089 | #define IS_UDVT_FH_SUPPORT 1 |
| 6090 | #else |
| 6091 | #define IS_UDVT_FH_SUPPORT 0 |
| 6092 | #endif |
| 6093 | |
| 6094 | // Enable TXDFE A-Die Dump |
| 6095 | #define IS_L1D_TXDFE_A_DIE_DUMP_ENABLE 0 |
| 6096 | |
| 6097 | // Enable RXDFE dump API |
| 6098 | #define IS_L1D_RXDFE_DUMP_ENABLE 0 |
| 6099 | // Debug use; for setup of parameters to L1 through catcher |
| 6100 | #define IS_L1D_INJECT_STRING_DEBUG_ON 1 |
| 6101 | |
| 6102 | #if IS_2G_L1D_ROBUST_MODEM_ENABLE |
| 6103 | #define IS_2G_L1D_ROBUST_MODEM_TRACE_ENABLE 1 |
| 6104 | #else |
| 6105 | #define IS_2G_L1D_ROBUST_MODEM_TRACE_ENABLE 0 |
| 6106 | #endif /* IS_2G_L1D_ROBUST_MODEM_ENABLE */ |
| 6107 | /* Enable the patch to compensate DAC when 2g is in stand by , gets |
| 6108 | * dac from active rat but difference is more than thershold |
| 6109 | */ |
| 6110 | // TDMA debug info |
| 6111 | #define IS_2G_TDMA_DEBUG_INFO_ENABLE 1 |
| 6112 | |
| 6113 | #define IS_2G_STANDBY_OWN_DAC_SUPPORT 1 |
| 6114 | |
| 6115 | /*Compensate timing erro based on SIM*/ |
| 6116 | #define IS_2G_TIMING_CORRECT_SIM_BASE 1 |
| 6117 | /* |
| 6118 | * To handle the false alarm for the patch compensating afc dac in standby mode |
| 6119 | */ |
| 6120 | #if IS_2G_STANDBY_OWN_DAC_SUPPORT |
| 6121 | #define IS_2G_STANDBY_DAC_ENHANCEMENT_ENABLE 1 |
| 6122 | #else |
| 6123 | #define IS_2G_STANDBY_DAC_ENHANCEMENT_ENABLE 0 |
| 6124 | #endif |
| 6125 | |
| 6126 | |
| 6127 | #if IS_CHIP_MT6280 |
| 6128 | #if IS_CHIP_MT6280_S00 |
| 6129 | #define IS_DCM_ISSUE_WORKAROUND_ON 1 |
| 6130 | #else |
| 6131 | #define IS_DCM_ISSUE_WORKAROUND_ON 1 |
| 6132 | #endif |
| 6133 | #define IS_USE_INTERNAL_TEMP_SENSOR 1 |
| 6134 | #define IS_LOW_POWER_HQA_PDN_SUPPORT 1 |
| 6135 | #elif IS_CHIP_MT6583_MD1 |
| 6136 | #define IS_DCM_ISSUE_WORKAROUND_ON 0 |
| 6137 | #define IS_USE_INTERNAL_TEMP_SENSOR 1 /* MT6583_MD1 is matched with MT6167 */ |
| 6138 | #define IS_LOW_POWER_HQA_PDN_SUPPORT 1 |
| 6139 | #elif IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6140 | #define IS_DCM_ISSUE_WORKAROUND_ON 0 |
| 6141 | #define IS_USE_INTERNAL_TEMP_SENSOR 1 /* MT6572 is matched with MT6166 */ |
| 6142 | #define IS_LOW_POWER_HQA_PDN_SUPPORT 1 |
| 6143 | #else |
| 6144 | #define IS_DCM_ISSUE_WORKAROUND_ON 0 |
| 6145 | #define IS_USE_INTERNAL_TEMP_SENSOR 0 |
| 6146 | #define IS_LOW_POWER_HQA_PDN_SUPPORT 0 |
| 6147 | #endif |
| 6148 | |
| 6149 | // There are two methods to solve TC21.1 |
| 6150 | // 1. Advance the BFE RX DCOC timing (SW solution) |
| 6151 | // => IS_RX_DCOC_ADVANCED_SUPPORT |
| 6152 | // => This feathure was disable since the side effect of failing FTA in-band block TC. |
| 6153 | // 2. HW adds the NB_ENx field to the RX_TYPE_CONx register (HW solution) |
| 6154 | // to distinguish between NB & SB/FB for RX_TYPEx = 0 |
| 6155 | // => IS_BFE_RX_TYPE_NB_EN_SUPPORT (MT6572 BFE HW adds this new function) |
| 6156 | #if IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6157 | #define IS_RX_DCOC_ADVANCED_SUPPORT 0 |
| 6158 | #define IS_BFE_RX_TYPE_NB_EN_SUPPORT 1 |
| 6159 | #elif IS_CHIP_MT6256_S00 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 6160 | #define IS_RX_DCOC_ADVANCED_SUPPORT 0 |
| 6161 | #define IS_BFE_RX_TYPE_NB_EN_SUPPORT 0 |
| 6162 | #elif IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) |
| 6163 | #define IS_RX_DCOC_ADVANCED_SUPPORT 1 |
| 6164 | #define IS_BFE_RX_TYPE_NB_EN_SUPPORT 0 |
| 6165 | #else |
| 6166 | #define IS_RX_DCOC_ADVANCED_SUPPORT 0 |
| 6167 | #define IS_BFE_RX_TYPE_NB_EN_SUPPORT 0 |
| 6168 | #endif |
| 6169 | |
| 6170 | #if IS_CHIP_MT6280 |
| 6171 | #define IS_ANALOG_RXIQ_DEBUG_MODE_ON 0 |
| 6172 | #define IS_INJECT_SIGNAL2ADC_DEBUG_MODE_ON 0 |
| 6173 | #endif |
| 6174 | |
| 6175 | #ifdef __UE_SIMULATOR__ |
| 6176 | #define IS_UESIM_DM_RF_INIT_SUPPORT 1 |
| 6177 | #else |
| 6178 | #define IS_UESIM_DM_RF_INIT_SUPPORT 0 |
| 6179 | #endif |
| 6180 | |
| 6181 | #if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6583_MD1) |
| 6182 | /* the ADC/DAC control are moved from RF to BB */ |
| 6183 | #define IS_TDMA_AD_DA_WINDOW_SUPPORT 1 |
| 6184 | #else |
| 6185 | #define IS_TDMA_AD_DA_WINDOW_SUPPORT 0 |
| 6186 | #endif |
| 6187 | |
| 6188 | #if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6583_MD1) |
| 6189 | /* the TDMA will do the clipping when tq_count+tq_bias is larger than 16383 */ |
| 6190 | #define IS_TDMA_CLIPPING_SUPPORT 1 |
| 6191 | #else |
| 6192 | #define IS_TDMA_CLIPPING_SUPPORT 0 |
| 6193 | #endif |
| 6194 | |
| 6195 | #if IS_CHIP_MT6297_AND_LATTER_VERSION |
| 6196 | #define IS_APC_HALF_QB_RESOLUTION_SUPPORT 0 |
| 6197 | #elif IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6583_MD1) |
| 6198 | /* the APC supports 1/2 QB resolution */ |
| 6199 | #define IS_APC_HALF_QB_RESOLUTION_SUPPORT 1 |
| 6200 | #else |
| 6201 | #define IS_APC_HALF_QB_RESOLUTION_SUPPORT 0 |
| 6202 | #endif |
| 6203 | |
| 6204 | #if IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) |
| 6205 | #define IS_DSP_P2X_SUPPORT 1 |
| 6206 | #else |
| 6207 | #define IS_DSP_P2X_SUPPORT 0 |
| 6208 | #endif |
| 6209 | |
| 6210 | #if IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6211 | #define IS_WRITE_DSP_PATCH_BY_L1 1 |
| 6212 | #else |
| 6213 | #define IS_WRITE_DSP_PATCH_BY_L1 0 |
| 6214 | #endif |
| 6215 | |
| 6216 | #if IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 |
| 6217 | #if defined(__MODEM_CCCI_EXIST__) |
| 6218 | #define IS_REPORT_RF_TEMPERATURE_SUPPORT 1 |
| 6219 | #else |
| 6220 | #define IS_REPORT_RF_TEMPERATURE_SUPPORT 0 |
| 6221 | #endif |
| 6222 | #else |
| 6223 | #define IS_REPORT_RF_TEMPERATURE_SUPPORT 0 |
| 6224 | #endif |
| 6225 | |
| 6226 | #if IS_CHIP_MT6280 |
| 6227 | #define IS_REPORT_RF_TEMPERATURE_BYATCMD_SUPPORT 1 |
| 6228 | #else |
| 6229 | #define IS_REPORT_RF_TEMPERATURE_BYATCMD_SUPPORT 0 |
| 6230 | #endif |
| 6231 | |
| 6232 | #if defined(__2G_TX_VOLTAGE_COMPENSATION_SUPPORT__) |
| 6233 | #if defined(__MODEM_CCCI_EXIST__) |
| 6234 | #define IS_TX_VOLTAGE_COMPENSATION_SUPPORT 1 |
| 6235 | #else |
| 6236 | #define IS_TX_VOLTAGE_COMPENSATION_SUPPORT 0 |
| 6237 | #endif |
| 6238 | #else |
| 6239 | #define IS_TX_VOLTAGE_COMPENSATION_SUPPORT 0 |
| 6240 | #endif |
| 6241 | |
| 6242 | #if defined(__RF_WIDE_TEMPERATURE_SUPPORT__) |
| 6243 | #define IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT 1 |
| 6244 | #else |
| 6245 | #define IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT 0 |
| 6246 | #endif |
| 6247 | |
| 6248 | #if IS_CHIP_MT6583_MD2 |
| 6249 | #define IS_SW_SECOND_VERSION_NEEDED 1 |
| 6250 | #else |
| 6251 | #define IS_SW_SECOND_VERSION_NEEDED 0 |
| 6252 | #endif |
| 6253 | |
| 6254 | #if IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6255 | #define IS_TDMA_TDD_TIMER_SYNC_SUPPORT 1 |
| 6256 | #else |
| 6257 | #define IS_TDMA_TDD_TIMER_SYNC_SUPPORT 0 |
| 6258 | #endif |
| 6259 | |
| 6260 | #if IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 |
| 6261 | #define IS_GSM_BPI_MASK_NEEDED 1 |
| 6262 | #else |
| 6263 | #define IS_GSM_BPI_MASK_NEEDED 0 |
| 6264 | #endif |
| 6265 | |
| 6266 | #if IS_COSIM_ON_L1SIM_SUPPORT |
| 6267 | #if IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 ||IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6268 | #undef IS_TDMA_BSI_READBACK_SUPPORT |
| 6269 | #define IS_TDMA_BSI_READBACK_SUPPORT 1 |
| 6270 | #endif |
| 6271 | #endif |
| 6272 | |
| 6273 | #if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6274 | #define IS_BSISPI_SEPARATE_SUPPORT 1 |
| 6275 | #else |
| 6276 | #define IS_BSISPI_SEPARATE_SUPPORT 0 |
| 6277 | #endif |
| 6278 | |
| 6279 | /* If IS_MMRF_CONTROL_BSI_TOP_SUPPORT is supported, it means that BSISPI and BPI_TOP control are moved to MMRF driver. */ |
| 6280 | #if IS_BSISPI_SEPARATE_SUPPORT |
| 6281 | #if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6282 | #define IS_MMRF_CONTROL_BSI_TOP_SUPPORT 1 |
| 6283 | #else |
| 6284 | #define IS_MMRF_CONTROL_BSI_TOP_SUPPORT 0 |
| 6285 | #endif |
| 6286 | #else |
| 6287 | #define IS_MMRF_CONTROL_BSI_TOP_SUPPORT 0 |
| 6288 | #endif |
| 6289 | |
| 6290 | #define IS_DUAL_TALK_SUPPORT 0 |
| 6291 | |
| 6292 | #if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6293 | #define IS_DMA_REMOVED 1 |
| 6294 | #else |
| 6295 | #define IS_DMA_REMOVED 0 |
| 6296 | #endif |
| 6297 | |
| 6298 | #if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6299 | #define IS_RF_CENTRAL_CONTROL_SUPPORT 1 |
| 6300 | #else |
| 6301 | #define IS_RF_CENTRAL_CONTROL_SUPPORT 0 |
| 6302 | #endif |
| 6303 | |
| 6304 | #if IS_RF_CENTRAL_CONTROL_SUPPORT && IS_RF_MT6169 |
| 6305 | #define IS_RF_CENTRAL_CONTROL_ENABLE 1 |
| 6306 | #define IS_LTE_POWERON_CALIBRATION_ENABLE 1 |
| 6307 | #elif IS_RF_CENTRAL_CONTROL_SUPPORT && ( IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M) |
| 6308 | #define IS_RF_CENTRAL_CONTROL_ENABLE 1 |
| 6309 | #define IS_LTE_POWERON_CALIBRATION_ENABLE 0 |
| 6310 | #else |
| 6311 | #define IS_RF_CENTRAL_CONTROL_ENABLE 0 |
| 6312 | #define IS_LTE_POWERON_CALIBRATION_ENABLE 0 |
| 6313 | #endif |
| 6314 | |
| 6315 | #if IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M |
| 6316 | #define IS_RF_RAMPPROFILE_ROLLBACK_SUPPORT 1 // adjust ramping profile based on TX power rollback |
| 6317 | #else |
| 6318 | #define IS_RF_RAMPPROFILE_ROLLBACK_SUPPORT 0 |
| 6319 | #endif |
| 6320 | |
| 6321 | #if IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6177M |
| 6322 | /* This compile option will effect NVRAM/Cross-Core Custom Folder Setting, it's always enable for specific RF */ |
| 6323 | #define IS_2G_MMPOC_SUPPORT 1 |
| 6324 | #else |
| 6325 | #define IS_2G_MMPOC_SUPPORT 0 // Bypass 2G RFC data Init and copying and under this compile options for Gen97 |
| 6326 | #endif |
| 6327 | |
| 6328 | #if defined(__2G_MIPI_SUPPORT__) |
| 6329 | /*Check __2G_MIPI_SUPPORT__ setting at option.mak , if platform has been added*/ |
| 6330 | #define IS_MIPI_SUPPORT 1 |
| 6331 | #else |
| 6332 | #define IS_MIPI_SUPPORT 0 |
| 6333 | #endif |
| 6334 | |
| 6335 | #if IS_MIPI_SUPPORT && ( IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297_AND_LATTER_VERSION ) |
| 6336 | #define IS_MIPI_CENTRAL_CONTROL_SUPPORT 1 |
| 6337 | #define IS_MIPI_CENTRAL_CONTROL_ENABLE 1 |
| 6338 | #else |
| 6339 | #define IS_MIPI_CENTRAL_CONTROL_SUPPORT 0 |
| 6340 | #define IS_MIPI_CENTRAL_CONTROL_ENABLE 0 |
| 6341 | #endif |
| 6342 | |
| 6343 | #if IS_MIPI_SUPPORT && defined(__2G_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT__) |
| 6344 | /* Macro IS_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT has been removed from GL1 code after TK6291 */ |
| 6345 | #define IS_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT 1 |
| 6346 | #else |
| 6347 | #define IS_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT 0 |
| 6348 | #endif |
| 6349 | |
| 6350 | #if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6351 | /* the frequency hopping is controled by system service */ |
| 6352 | #define IS_FH_CONTROL_BY_SS 1 |
| 6353 | #else |
| 6354 | #define IS_FH_CONTROL_BY_SS 0 |
| 6355 | #endif |
| 6356 | |
| 6357 | #if IS_FH_CONTROL_BY_SS |
| 6358 | #undef IS_MPLL_FH_SUPPORT |
| 6359 | #undef IS_MPLLFH_FREE_RUN_SUPPORT_CHIP |
| 6360 | #undef IS_MPLLFH_FREE_RUN_ON |
| 6361 | #define IS_MPLL_FH_SUPPORT 0 |
| 6362 | #define IS_MPLLFH_FREE_RUN_SUPPORT_CHIP 0 |
| 6363 | #define IS_MPLLFH_FREE_RUN_ON 0 |
| 6364 | #endif |
| 6365 | |
| 6366 | #if IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6367 | /* to support the DCS-TD co-existence feature */ |
| 6368 | #define IS_DCS_NB_WB_SWITCH_SUPPORT 1 |
| 6369 | #else |
| 6370 | #define IS_DCS_NB_WB_SWITCH_SUPPORT 0 |
| 6371 | #endif |
| 6372 | |
| 6373 | #if IS_CHIP_MT6290 || IS_CHIP_MT6752_MD2 |
| 6374 | #define IS_DSDA_DCS_TX_NOTCH_SWITCH_SUPPORT 1 |
| 6375 | #else |
| 6376 | #define IS_DSDA_DCS_TX_NOTCH_SWITCH_SUPPORT 0 |
| 6377 | #endif |
| 6378 | |
| 6379 | #if IS_CHIP_MT6290 || IS_CHIP_MT6752_MD2 |
| 6380 | #define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_SUPPORT 1 |
| 6381 | #else |
| 6382 | #define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_SUPPORT 0 |
| 6383 | #endif |
| 6384 | |
| 6385 | #if IS_DSDA_DCS_TX_NOTCH_SWITCH_SUPPORT |
| 6386 | #define IS_DSDA_DCS_TX_NOTCH_SWITCH_ENABLE 0 |
| 6387 | #else |
| 6388 | #define IS_DSDA_DCS_TX_NOTCH_SWITCH_ENABLE 0 |
| 6389 | #endif |
| 6390 | |
| 6391 | #if IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_SUPPORT |
| 6392 | #if defined(__LTE_TX_PATH_SWITCH_SUPPORT__) |
| 6393 | #define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_ENABLE 1 |
| 6394 | #else |
| 6395 | #define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_ENABLE 0 |
| 6396 | #endif |
| 6397 | #else |
| 6398 | #define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_ENABLE 0 |
| 6399 | #endif |
| 6400 | |
| 6401 | #if defined(__PS_L1_DC_ARCH__) |
| 6402 | /* to support dual-core modem architecture */ |
| 6403 | #define IS_DUAL_CORE_MODEM_SUPPORT 1 |
| 6404 | #define IS_CTIRQ3_SUPPORT 0 |
| 6405 | #else |
| 6406 | #define IS_DUAL_CORE_MODEM_SUPPORT 0 |
| 6407 | #define IS_CTIRQ3_SUPPORT 0 |
| 6408 | #endif /* defined(__PS_L1_DC_ARCH__) */ |
| 6409 | |
| 6410 | #if IS_DUAL_CORE_MODEM_SUPPORT |
| 6411 | #define IS_DUAL_CORE_MODEM_L1D_UT_DEBUG 0 |
| 6412 | #if IS_CTIRQ3_SUPPORT |
| 6413 | #define IS_TRIGER_U1_AT_CT3 0 |
| 6414 | #else |
| 6415 | #define IS_TRIGER_U1_AT_CT3 0 |
| 6416 | #endif /* IS_CTIRQ3_SUPPORT */ |
| 6417 | #define IS_SET_SBUF_AS_GLOBAL_VAR_SUPPORT 1 |
| 6418 | #else |
| 6419 | #define IS_DUAL_CORE_MODEM_L1D_UT_DEBUG 0 |
| 6420 | #define IS_TRIGER_U1_AT_CT3 0 |
| 6421 | #define IS_SET_SBUF_AS_GLOBAL_VAR_SUPPORT 0 |
| 6422 | #endif /* IS_DUAL_CORE_MODEM_SUPPORT */ |
| 6423 | |
| 6424 | #if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6425 | #define IS_OUTPUT_RF_VERSION_SUPPORT 1 |
| 6426 | #else |
| 6427 | #define IS_OUTPUT_RF_VERSION_SUPPORT 0 |
| 6428 | #endif |
| 6429 | |
| 6430 | #if defined (__ACC_NC_AFC_DB_UPDATE_SUPPORT__) |
| 6431 | #define IS_ACC_NC_AFC_DB_UPDATE_SUPPORT 1 /* Enable Accelerating NC AFC DB updating */ |
| 6432 | #else |
| 6433 | #define IS_ACC_NC_AFC_DB_UPDATE_SUPPORT 0 |
| 6434 | #endif |
| 6435 | |
| 6436 | |
| 6437 | #define IS_CSFB_WITH_SGLTE_HW_ENABLE 0 |
| 6438 | |
| 6439 | #if IS_CSFB_WITH_SGLTE_HW_ENABLE |
| 6440 | #if IS_RF_MT6165 || IS_RF_MT6166 |
| 6441 | // CSFB_WITH_SGLTE_HW can only enable on MT6165/MT6166 |
| 6442 | #else |
| 6443 | #error "This RF Chip is not support CSFB with SGLTE HW." |
| 6444 | #endif |
| 6445 | #endif |
| 6446 | |
| 6447 | #if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 /* Chipset support MML1 and DRDI */ |
| 6448 | #define IS_L1_RF_DRDI_CUSTOM_SETTING_FROM_MML1 1 |
| 6449 | #else |
| 6450 | #define IS_L1_RF_DRDI_CUSTOM_SETTING_FROM_MML1 0 |
| 6451 | #endif |
| 6452 | |
| 6453 | #if defined (__TX_POWER_OFFSET_SUPPORT__) |
| 6454 | #define IS_TX_POWER_OFFSET_SUPPORT 1 /* Enable Tx power offset */ |
| 6455 | #else |
| 6456 | #define IS_TX_POWER_OFFSET_SUPPORT 0 /* Disable Tx power offset */ |
| 6457 | #endif /*__TX_POWER_OFFSET_SUPPORT__*/ |
| 6458 | |
| 6459 | #if defined (__SAR_TX_POWER_BACKOFF_SUPPORT__) |
| 6460 | #define IS_SAR_TX_POWER_BACKOFF_SUPPORT 1 /* Enable Tx power offset for SAR test*/ |
| 6461 | #define IS_2G_DYNAMIC_SAR_TABLE_SUPPORT 1 |
| 6462 | #else |
| 6463 | #define IS_SAR_TX_POWER_BACKOFF_SUPPORT 0 /* Disable Tx power offset for SAR test*/ |
| 6464 | #define IS_2G_DYNAMIC_SAR_TABLE_SUPPORT 0 |
| 6465 | #endif /*__SAR_TX_POWER_BACKOFF_SUPPORT__*/ |
| 6466 | #if defined(__RX_POWER_OFFSET_SUPPORT__) |
| 6467 | #define IS_RX_POWER_OFFSET_SUPPORT 1 |
| 6468 | #else |
| 6469 | #define IS_RX_POWER_OFFSET_SUPPORT 0 |
| 6470 | #endif/*__RX_POWER_OFFSET_SUPPORT__*/ |
| 6471 | |
| 6472 | #if defined (__GSM_EM_TX_POWER_CONTROL_SUPPORT__) |
| 6473 | #define IS_GSM_EM_TX_POWER_CONTROL_SUPPORT 1 /* Enable EM Tx power control */ |
| 6474 | #else |
| 6475 | #define IS_GSM_EM_TX_POWER_CONTROL_SUPPORT 0 /* Disable EM Tx power control */ |
| 6476 | #endif |
| 6477 | |
| 6478 | #if IS_CHIP_MT6297_AND_LATTER_VERSION |
| 6479 | #define IS_GSM_TX_DETECTOR_SUPPORT 1 |
| 6480 | #else |
| 6481 | #define IS_GSM_TX_DETECTOR_SUPPORT 0 |
| 6482 | #endif /* defined(__GSM_TX_DETECTOR_SUPPORT__) */ |
| 6483 | |
| 6484 | #if defined (__NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__) |
| 6485 | |
| 6486 | #if defined (__EPSK_ADJUST_TPO_SUPPORT__) |
| 6487 | #define IS_EPSK_ADJUST_TPO_SUPPORT 1 /*Enable Adjust TPO feature support on EPSK*/ |
| 6488 | #else |
| 6489 | #define IS_EPSK_ADJUST_TPO_SUPPORT 0 /*Disable Adjust TPO feature support on EPSK*/ |
| 6490 | #endif//__EPSK_ADJUST_TPO_SUPPORT__ |
| 6491 | |
| 6492 | #define IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT 1 /* Enable NSFT Adjust Tx Power Offset */ |
| 6493 | #else |
| 6494 | #define IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT 0 /* Disable NSFT Adjust Tx Power Offset */ |
| 6495 | #endif /*__NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__*/ |
| 6496 | |
| 6497 | #if defined (__EM_MAX_TX_POWER_SUPPORT__) |
| 6498 | #define IS_MAX_TX_POWER_CONTROL_SUPPORT 1 /* Enable MAX Tx power control */ |
| 6499 | #else |
| 6500 | #define IS_MAX_TX_POWER_CONTROL_SUPPORT 0 /* Disable MAX Tx power control */ |
| 6501 | #endif |
| 6502 | |
| 6503 | #if defined (__GSM_INCREASE_RACH_TX_POWER_SUPPORT__) |
| 6504 | #define IS_GSM_INCREASE_RACH_TX_POWER_SUPPORT 1 /* Enable RACH Tx power control */ |
| 6505 | #else |
| 6506 | #define IS_GSM_INCREASE_RACH_TX_POWER_SUPPORT 0 /* Disable RACH Tx power control */ |
| 6507 | #endif |
| 6508 | |
| 6509 | #if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6510 | #define IS_CC_NVRAM_CUSTOM_DATA_SUPPORT 1 |
| 6511 | #else |
| 6512 | #define IS_CC_NVRAM_CUSTOM_DATA_SUPPORT 0 |
| 6513 | #endif |
| 6514 | |
| 6515 | #if IS_CHIP_TK6291 |
| 6516 | #define IS_TK6291_HW_BUG_SW_WORKAROUND_SUPPORT 1 |
| 6517 | #else |
| 6518 | #define IS_TK6291_HW_BUG_SW_WORKAROUND_SUPPORT 0 |
| 6519 | #endif |
| 6520 | |
| 6521 | #if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6522 | #define IS_MD2G_MEM_CONFIG_SUPPORT_CHIP 1 |
| 6523 | #else |
| 6524 | #define IS_MD2G_MEM_CONFIG_SUPPORT_CHIP 0 |
| 6525 | #endif |
| 6526 | |
| 6527 | #if (IS_MD2G_MEM_CONFIG_SUPPORT_CHIP) |
| 6528 | #if IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6529 | #define IS_CENTRALIZED_SW_TYPE_SETTING_SUPPORT 1 |
| 6530 | #else |
| 6531 | #define IS_CENTRALIZED_SW_TYPE_SETTING_SUPPORT 0 |
| 6532 | #endif /* IS_CHIP_MT6295 */ |
| 6533 | #else |
| 6534 | #define IS_CENTRALIZED_SW_TYPE_SETTING_SUPPORT 0 |
| 6535 | #endif /* IS_MD2G_MEM_CONFIG_SUPPORT_CHIP */ |
| 6536 | |
| 6537 | #if defined(__TAS_SUPPORT__) |
| 6538 | #if defined(__MD93__) |
| 6539 | #define IS_2G_TAS_SUPPORT 1 |
| 6540 | #define IS_2G_Gen95_UTAS_SUPPORT 0 |
| 6541 | #define IS_2G_Gen97_UTAS_SUPPORT 0 |
| 6542 | #define IS_2G_TAS_INHERIT_4G_ANT 1 |
| 6543 | #elif defined(__MD95__) /*GL1D is not involved from Gen95 onwards since GL1C is taking care of it*/ |
| 6544 | #define IS_2G_TAS_SUPPORT 0 |
| 6545 | #define IS_2G_Gen95_UTAS_SUPPORT 1 |
| 6546 | #define IS_2G_Gen97_UTAS_SUPPORT 0 |
| 6547 | #define IS_2G_TAS_INHERIT_4G_ANT 0 |
| 6548 | #elif (defined(__MD97__) || defined(__MD97P__)) |
| 6549 | #define IS_2G_TAS_SUPPORT 0 |
| 6550 | #define IS_2G_Gen95_UTAS_SUPPORT 0 |
| 6551 | #define IS_2G_Gen97_UTAS_SUPPORT 1 |
| 6552 | #define IS_2G_TAS_INHERIT_4G_ANT 0 |
| 6553 | #else |
| 6554 | #error "[ERROR] Invalid MD generation" |
| 6555 | #endif |
| 6556 | #define IS_2G_TAS_ANT_IDX_FOR_PM_WINDOW_SUPPORT 1 |
| 6557 | #else |
| 6558 | #define IS_2G_TAS_SUPPORT 0 |
| 6559 | #define IS_2G_TAS_ANT_IDX_FOR_PM_WINDOW_SUPPORT 0 |
| 6560 | #define IS_2G_TAS_INHERIT_4G_ANT 0 |
| 6561 | #define IS_2G_Gen95_UTAS_SUPPORT 0 |
| 6562 | #define IS_2G_Gen97_UTAS_SUPPORT 0 |
| 6563 | #endif |
| 6564 | |
| 6565 | #if IS_CHIP_MT6297_AND_LATTER_VERSION |
| 6566 | #define IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT 1 /*Gen97 DAT is default enable*/ |
| 6567 | #else |
| 6568 | #define IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT defined (__DYNAMIC_ANTENNA_TUNING__) |
| 6569 | #endif |
| 6570 | /*Please review those code usign this feature option*/ |
| 6571 | #define IS_L1D_USEC_TRACE_SUPPORT 1 |
| 6572 | |
| 6573 | #define IS_2G_UTAS97_DETAIL_FE_TIMING_DEBUG_TRACE_SUPPORT 0 /* Used for UTAS 97 detailed FE timing information*/ |
| 6574 | |
| 6575 | |
| 6576 | #if IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT //defined(__DYNAMIC_ANTENNA_TUNING__) |
| 6577 | #if defined(__MD93__) |
| 6578 | #define IS_2G_DAT_SUPPORT 1 |
| 6579 | #define IS_2G_Gen95_UDAT_SUPPORT 0 |
| 6580 | #define IS_2G_Gen97_UDAT_SUPPORT 0 |
| 6581 | #elif defined(__MD95__) |
| 6582 | #define IS_2G_DAT_SUPPORT 0 |
| 6583 | #define IS_2G_Gen95_UDAT_SUPPORT 1 |
| 6584 | #define IS_2G_Gen97_UDAT_SUPPORT 0 |
| 6585 | #elif (defined(__MD97__) || defined(__MD97P__)) |
| 6586 | #define IS_2G_DAT_SUPPORT 0 |
| 6587 | #define IS_2G_Gen95_UDAT_SUPPORT 0 |
| 6588 | #define IS_2G_Gen97_UDAT_SUPPORT 1 |
| 6589 | #else |
| 6590 | #error "[ERROR] Invalid MD generation" |
| 6591 | #endif |
| 6592 | #else |
| 6593 | #define IS_2G_DAT_SUPPORT 0 |
| 6594 | #define IS_2G_Gen95_UDAT_SUPPORT 0 |
| 6595 | #define IS_2G_Gen97_UDAT_SUPPORT 0 |
| 6596 | #endif |
| 6597 | #if defined(__ANT_RXPWR_OFFSET_SUPPORT__) |
| 6598 | #define IS_ANT_RXPWR_OFFSET_SUPPORT 1 |
| 6599 | #else |
| 6600 | #define IS_ANT_RXPWR_OFFSET_SUPPORT 0 |
| 6601 | #endif |
| 6602 | |
| 6603 | /* Calculate TXRX active timing , default on for Andriod N feature */ |
| 6604 | #define IS_TXRX_GET_INFO 1 |
| 6605 | |
| 6606 | #define MD97_S2U_TIME 0 |
| 6607 | #if IS_CHIP_MT6297_AND_LATTER_VERSION |
| 6608 | #define IS_MM_APC_NEW_RAMP_CONFIGURE 0 |
| 6609 | #else |
| 6610 | #define IS_MM_APC_NEW_RAMP_CONFIGURE 1 |
| 6611 | #endif |
| 6612 | |
| 6613 | /* DRDI support capability */ |
| 6614 | #if defined(__RF_DRDI_CAPABILITY_SUPPORT__) |
| 6615 | #define IS_2G_DRDI_SUPPORT 1 |
| 6616 | #else |
| 6617 | #define IS_2G_DRDI_SUPPORT 0 |
| 6618 | #endif |
| 6619 | |
| 6620 | /* 2G support PRX1 or DRX1 */ |
| 6621 | #if IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6622 | #define IS_2G_ALTERNATIVE_RX_PATH_SUPPORT 1 |
| 6623 | #else |
| 6624 | #define IS_2G_ALTERNATIVE_RX_PATH_SUPPORT 0 |
| 6625 | #endif |
| 6626 | |
| 6627 | /* 2G support PRX1 or DRX1 */ |
| 6628 | #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) && (IS_2GRXD_CHIP_MT6765_AND_LATTER_VERSION || IS_CHIP_MT6295) || IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT |
| 6629 | |
| 6630 | #define IS_2G_RXD_SUPPORT 1 |
| 6631 | #define IS_2G_RXD_ENHANCEMENT_SUPPORT 1 |
| 6632 | |
| 6633 | #define IS_GSM_RX_RXD_MODE_FIXED 0 //Force RXD mode before GL1C RAS involve |
| 6634 | |
| 6635 | #else |
| 6636 | |
| 6637 | #define IS_2G_RXD_SUPPORT 0 |
| 6638 | #define IS_2G_RXD_ENHANCEMENT_SUPPORT 0 |
| 6639 | |
| 6640 | #define IS_GSM_RX_RXD_MODE_FIXED 0 |
| 6641 | #endif |
| 6642 | |
| 6643 | #if IS_2G_RXD_SUPPORT |
| 6644 | #define IS_2G_RAS_CROSS_MODE_SUPPORT 1 |
| 6645 | #define IS_2G_RAS_DECISION_INCLUDE_DSP_POW_SUPPORT 1 |
| 6646 | #if IS_CHIP_MT6853_AND_LATTER_VERSION // Gen97, C-value enable Mouton and latter |
| 6647 | #define IS_2G_C_VALUE_SUPPORT 1 |
| 6648 | #endif |
| 6649 | #else |
| 6650 | #define IS_2G_RAS_CROSS_MODE_SUPPORT 0 |
| 6651 | #define IS_2G_RAS_DECISION_INCLUDE_DSP_POW_SUPPORT 0 |
| 6652 | #define IS_2G_C_VALUE_SUPPORT 0 |
| 6653 | #endif |
| 6654 | |
| 6655 | #if defined(__2G_RXD_BLACKLIST_SUPPORT__) |
| 6656 | #define IS_2G_RXD_BLACKLIST_SUPPORT 1 |
| 6657 | #else |
| 6658 | #define IS_2G_RXD_BLACKLIST_SUPPORT 0 |
| 6659 | #endif |
| 6660 | |
| 6661 | /* For L1C Dummy LISR removal, added debug traces */ |
| 6662 | #if (IS_CHIP_MT6292) && (defined __MTK_TARGET__) |
| 6663 | #define IS_2G_DUMMY_LISR_REMOVAL_DEBUG 1 |
| 6664 | #else |
| 6665 | #define IS_2G_DUMMY_LISR_REMOVAL_DEBUG 0 |
| 6666 | #endif |
| 6667 | |
| 6668 | #if defined(__GSM_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT__) |
| 6669 | #define IS_2G_DYNAMIC_HW_CLOCK_SUPPORT 1 //Adjust HW clock for specific ARFCNs |
| 6670 | #else |
| 6671 | #define IS_2G_DYNAMIC_HW_CLOCK_SUPPORT 0 |
| 6672 | #endif |
| 6673 | |
| 6674 | /* Support using external LNA and adjust RX gain table in L1 code flow */ |
| 6675 | #if IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M |
| 6676 | #define IS_2G_EXTERNAL_LNA_SUPPORT 1 |
| 6677 | #else |
| 6678 | #define IS_2G_EXTERNAL_LNA_SUPPORT 0 |
| 6679 | #endif |
| 6680 | |
| 6681 | #if IS_RF_MT6186M || IS_RF_MT6190T |
| 6682 | #define IS_2G_WITHOUT_MATCHING_NETWORK_SUPPORT 0 |
| 6683 | #else |
| 6684 | #define IS_2G_WITHOUT_MATCHING_NETWORK_SUPPORT 0 |
| 6685 | #endif |
| 6686 | |
| 6687 | /* Support using BYPASS and adjust RX gain table in L1 code flow */ |
| 6688 | #if IS_2G_EXTERNAL_LNA_SUPPORT |
| 6689 | #if IS_RF_MT6190T |
| 6690 | #define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 1 |
| 6691 | #define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 1 |
| 6692 | #define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 0 |
| 6693 | #elif IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M |
| 6694 | #define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 1 |
| 6695 | #define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 1 |
| 6696 | #define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 1 |
| 6697 | #elif IS_RF_MT6177L || IS_RF_MT6177M |
| 6698 | #define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 1 |
| 6699 | #define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 1 |
| 6700 | #define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 0 |
| 6701 | #else |
| 6702 | #define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 0 |
| 6703 | #define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 0 |
| 6704 | #define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 0 |
| 6705 | #endif |
| 6706 | #else |
| 6707 | #define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 0 |
| 6708 | #define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 0 |
| 6709 | #define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 0 |
| 6710 | #endif |
| 6711 | |
| 6712 | #if IS_2G_EXTERNAL_LNA_SUPPORT |
| 6713 | #define IS_2G_EXTERNAL_LNA_FSI_SYNC_SUPPORT 1 |
| 6714 | #else |
| 6715 | #define IS_2G_EXTERNAL_LNA_FSI_SYNC_SUPPORT 0 |
| 6716 | #endif |
| 6717 | #if IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6718 | #define IS_NEW_FD216_RESTART_FLOW_ENABLE 1 |
| 6719 | #define IS_SPEECH_uSIP_SUPPORT 1 |
| 6720 | #define IS_MD_TOPSM_API_USING 1 |
| 6721 | #define IS_FIXED_DSPCLK 1 |
| 6722 | #define IS_DSP_DM_4BYTE_ALIGN_CHIP 1 |
| 6723 | #else |
| 6724 | #define IS_NEW_FD216_RESTART_FLOW_ENABLE 0 |
| 6725 | #define IS_SPEECH_uSIP_SUPPORT 0 |
| 6726 | #define IS_MD_TOPSM_API_USING 0 |
| 6727 | #define IS_FIXED_DSPCLK 0 |
| 6728 | #define IS_DSP_DM_4BYTE_ALIGN_CHIP 0 |
| 6729 | #endif |
| 6730 | |
| 6731 | #if IS_CHIP_MT6295 |
| 6732 | #define IS_DYNAMICAL_NOISE_FLOOR_AND_SATURATION_SUPPORT 1 |
| 6733 | #else |
| 6734 | #define IS_DYNAMICAL_NOISE_FLOOR_AND_SATURATION_SUPPORT 0 |
| 6735 | #endif |
| 6736 | |
| 6737 | #if defined(__A54_ALGORITHM_SUPPORT__) |
| 6738 | #define IS_A54_ALGORITHM_SUPPORT 1 |
| 6739 | #else |
| 6740 | #define IS_A54_ALGORITHM_SUPPORT 0 |
| 6741 | #endif |
| 6742 | |
| 6743 | #if defined(__MMRF_RF_HAL_SEQ_GEN_SUPPORT__) |
| 6744 | #if IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M |
| 6745 | #define IS_HAL_SUPPORT 1 |
| 6746 | #else |
| 6747 | #define IS_HAL_SUPPORT 0 |
| 6748 | #endif |
| 6749 | #endif |
| 6750 | |
| 6751 | /*Some check condition for IS_2G_Gen95_UTAS_SUPPORT */ |
| 6752 | //#if IS_2G_Gen95_UTAS_SUPPORT && XXXX |
| 6753 | //#error "IS_2G_Gen95_UTAS_SUPPORT not porting for XXXX yet!!!" |
| 6754 | //#endif |
| 6755 | |
| 6756 | #if defined(__MTK_TARGET__) |
| 6757 | #if (IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT) && (!IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT) |
| 6758 | #error "(IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT) only porting for IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT !!!" |
| 6759 | #endif |
| 6760 | |
| 6761 | #if (IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT) && (!IS_2G_RXD_SUPPORT) |
| 6762 | #error "(IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT ) only porting for IS_2G_RXD_SUPPORT !!!" |
| 6763 | #endif |
| 6764 | #endif |
| 6765 | |
| 6766 | #if IS_CHIP_MT6295 |
| 6767 | #define IS_2G_TX_COARSE_DCOC_SUPPORT 1 |
| 6768 | #else |
| 6769 | #define IS_2G_TX_COARSE_DCOC_SUPPORT 0 |
| 6770 | #endif /* IS_CHIP_MT6295 */ |
| 6771 | |
| 6772 | |
| 6773 | /*===================================================================*/ |
| 6774 | /* BBTX/BBRX chip design version */ |
| 6775 | /*===================================================================*/ |
| 6776 | #define BBTXRX_VER_1 1 |
| 6777 | #define BBTXRX_VER_2 2 |
| 6778 | #define BBTXRX_VER_3 3 |
| 6779 | |
| 6780 | #if IS_CHIP_MT6583_MD2 |
| 6781 | #define BBTXRX_CHIP_DESIGN_VER BBTXRX_VER_3 |
| 6782 | #elif IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 |
| 6783 | #define BBTXRX_CHIP_DESIGN_VER BBTXRX_VER_2 |
| 6784 | #else |
| 6785 | #define BBTXRX_CHIP_DESIGN_VER BBTXRX_VER_1 |
| 6786 | #endif |
| 6787 | |
| 6788 | #define IS_BBTXRX_CHIP_DESIGN_VER_1 (BBTXRX_CHIP_DESIGN_VER == BBTXRX_VER_1) |
| 6789 | #define IS_BBTXRX_CHIP_DESIGN_VER_2 (BBTXRX_CHIP_DESIGN_VER == BBTXRX_VER_2) |
| 6790 | #define IS_BBTXRX_CHIP_DESIGN_VER_3 (BBTXRX_CHIP_DESIGN_VER == BBTXRX_VER_3) |
| 6791 | |
| 6792 | /*===================================================================*/ |
| 6793 | /* CHIP ZIMAGE setting */ |
| 6794 | /*===================================================================*/ |
| 6795 | #if IS_CHIP_MT6252 |
| 6796 | #define IS_PRIMARY_ROCODE 1 |
| 6797 | #else |
| 6798 | #define IS_PRIMARY_ROCODE 0 |
| 6799 | #endif |
| 6800 | |
| 6801 | /*===================================================================*/ |
| 6802 | /* CHIP Partial Internal RAM settings */ |
| 6803 | /*===================================================================*/ |
| 6804 | #define INTERN_NULL 0 |
| 6805 | #define INTERN_FULL 1 |
| 6806 | #define INTERN_PARTIAL 2 |
| 6807 | #define INTERN_PARTIAL_CRITICAL 3 |
| 6808 | |
| 6809 | /*===================================================================*/ |
| 6810 | /* WT co-bin feature compile option check */ |
| 6811 | /*===================================================================*/ |
| 6812 | |
| 6813 | #if L1D_WT_COBIN_ARCHITECTURE_SUPPORT |
| 6814 | #if defined(__AST2001__) || defined(__AST3001__) |
| 6815 | #error "WT Co-bin feature does not support these phase out feature!" |
| 6816 | #endif |
| 6817 | #if IS_3GRF_DETECT |
| 6818 | #error "WT Co-bin feature does not support phase out feature: IS_3GRF_DETECT !" |
| 6819 | #endif |
| 6820 | #if IS_DEFAULT_TURNOFF_3GMTCMOS |
| 6821 | #error "WT Co-bin feature does not support phase out feature: IS_DEFAULT_TURNOFF_3GMTCMOS !" |
| 6822 | #endif |
| 6823 | #if IS_GCMACHINE_V3_UMTS_SUPPORT |
| 6824 | #error "WT Co-bin feature does not support phase out feature: IS_GCMACHINE_V3_UMTS_SUPPORT !" |
| 6825 | #endif |
| 6826 | #if IS_GCMACHINE_V4_HSPA_SUPPORT |
| 6827 | #error "WT Co-bin feature does not support phase out feature: IS_GCMACHINE_V4_HSPA_SUPPORT !" |
| 6828 | #endif |
| 6829 | #if IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT |
| 6830 | #error "WT Co-bin feature does not support phase out feature: IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT !" |
| 6831 | #endif |
| 6832 | #if IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT |
| 6833 | #error "WT Co-bin feature does not support phase out feature: IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT !" |
| 6834 | #endif |
| 6835 | #if IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT |
| 6836 | #error "WT Co-bin feature does not support phase out feature: IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT !" |
| 6837 | #endif |
| 6838 | #if IS_SRCLKENA_TRIG_VRF28_SUPPORT |
| 6839 | #error "WT Co-bin feature does not support phase out feature: IS_SRCLKENA_TRIG_VRF28_SUPPORT !" |
| 6840 | #endif |
| 6841 | #if IS_AST_B2S_SUPPORT |
| 6842 | #error "WT Co-bin feature does not support phase out feature: IS_AST_B2S_SUPPORT !" |
| 6843 | #endif |
| 6844 | #if IS_TDDM_AFC_TRANSFORM_SUPPORT |
| 6845 | #error "WT Co-bin feature does not support phase out feature: IS_TDDM_AFC_TRANSFORM_SUPPORT !" |
| 6846 | #endif |
| 6847 | #if IS_CSFB_WITH_SGLTE_HW_ENABLE |
| 6848 | #error "WT Co-bin feature does not support phase out feature: IS_CSFB_WITH_SGLTE_HW_ENABLE !" |
| 6849 | #endif |
| 6850 | #endif |
| 6851 | /* ------------------------------------------------------------- */ |
| 6852 | // Global compiler option for vs1 low power feature of MT6293 |
| 6853 | /* ------------------------------------------------------------- */ |
| 6854 | #if defined(__PMIC_VS1_LOW_POWER_CTRL_SUPPORT__ ) |
| 6855 | #define IS_2G_PMIC_VS1_LOW_POWER_CTRL_SUPPORT 1 |
| 6856 | #else |
| 6857 | #define IS_2G_PMIC_VS1_LOW_POWER_CTRL_SUPPORT 0 |
| 6858 | #endif |
| 6859 | |
| 6860 | /* ------------------------------------------------------------- */ |
| 6861 | // default value |
| 6862 | /* ------------------------------------------------------------- */ |
| 6863 | #if IS_CHIP_MT6205 || IS_CHIP_MT6225 || IS_CHIP_MT6223 || IS_CHIP_MT6238_SER || IS_CHIP_MT6276 || IS_CHIP_MT6251 || IS_CHIP_MT6573 || IS_CHIP_MT6252 || IS_CHIP_MT6256 || IS_CHIP_MT6575 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6864 | #define INTERNCODE_DEFAULT INTERN_NULL |
| 6865 | #else |
| 6866 | #define INTERNCODE_DEFAULT INTERN_FULL |
| 6867 | #endif |
| 6868 | /* ------------------------------------------------------------- */ |
| 6869 | #if IS_CHIP_MT6205 || IS_CHIP_MT6225 || IS_CHIP_MT6223 || IS_CHIP_MT6238_SER || IS_CHIP_MT6276 || IS_CHIP_MT6253 || IS_CHIP_MT6251 || IS_CHIP_MT6573 || IS_CHIP_MT6256 || IS_CHIP_MT6575 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 |
| 6870 | #define INTERNDATA_DEFAULT INTERN_NULL |
| 6871 | #else |
| 6872 | #define INTERNDATA_DEFAULT INTERN_FULL |
| 6873 | #endif |
| 6874 | /* ------------------------------------------------------------- */ |
| 6875 | |
| 6876 | /* ------------------------------------------------------------- */ |
| 6877 | #define INTERNCODE_M11303 INTERNCODE_DEFAULT |
| 6878 | #define INTERNCODE_M12100 INTERNCODE_DEFAULT |
| 6879 | #define INTERNCODE_M12110 INTERNCODE_DEFAULT |
| 6880 | #define INTERNCODE_M12120 INTERNCODE_DEFAULT |
| 6881 | #define INTERNCODE_M12160 INTERNCODE_DEFAULT |
| 6882 | #define INTERNCODE_M12168 INTERNCODE_DEFAULT |
| 6883 | #define INTERNCODE_M12170 INTERNCODE_DEFAULT |
| 6884 | #define INTERNCODE_M12180 INTERNCODE_DEFAULT |
| 6885 | /* ------------------------------------------------------------- */ |
| 6886 | #define INTERNDATA_M11303 INTERNDATA_DEFAULT |
| 6887 | #define INTERNDATA_M12100 INTERNDATA_DEFAULT |
| 6888 | #define INTERNDATA_M12110 INTERNDATA_DEFAULT |
| 6889 | #define INTERNDATA_M12120 INTERNDATA_DEFAULT |
| 6890 | #define INTERNDATA_M12160 INTERNDATA_DEFAULT |
| 6891 | #define INTERNDATA_M12168 INTERNDATA_DEFAULT |
| 6892 | #define INTERNDATA_M12170 INTERNDATA_DEFAULT |
| 6893 | #define INTERNDATA_M12180 INTERNDATA_DEFAULT |
| 6894 | #define INTERNDATA_M12194 INTERNDATA_DEFAULT |
| 6895 | #define INTERNDATA_L1D_DATA INTERNDATA_DEFAULT |
| 6896 | #define INTERNDATA_L1D_INTERNAL_DATA INTERNDATA_DEFAULT |
| 6897 | /* ------------------------------------------------------------- */ |
| 6898 | #if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION |
| 6899 | #define INTERNCODE_M12167 INTERNCODE_DEFAULT |
| 6900 | #define INTERNDATA_M12167 INTERNDATA_DEFAULT |
| 6901 | #else |
| 6902 | #define INTERNCODE_M12167 INTERN_NULL |
| 6903 | #define INTERNDATA_M12167 INTERN_NULL |
| 6904 | #endif |
| 6905 | /* ------------------------------------------------------------- */ |
| 6906 | #if IS_CHIP_MT6253 || IS_CHIP_MT6236 /* MPLL FH support chips */ |
| 6907 | #define INTERNCODE_M12171 INTERNCODE_DEFAULT |
| 6908 | #define INTERNDATA_M12171 INTERNDATA_DEFAULT |
| 6909 | #else |
| 6910 | #define INTERNCODE_M12171 INTERN_NULL |
| 6911 | #define INTERNDATA_M12171 INTERN_NULL |
| 6912 | #endif |
| 6913 | /* ------------------------------------------------------------- */ |
| 6914 | |
| 6915 | #if IS_CHIP_MT6238_SER /* code: all off, data: all off */ |
| 6916 | /* ------------------------------------------------------------- */ |
| 6917 | #undef INTERNCODE_M12100 |
| 6918 | #undef INTERNCODE_M12110 |
| 6919 | #undef INTERNCODE_M12120 |
| 6920 | #undef INTERNCODE_M12160 |
| 6921 | #undef INTERNCODE_M12170 |
| 6922 | #define INTERNCODE_M12100 INTERN_FULL |
| 6923 | #if IS_GEMINI_SUPPORT |
| 6924 | #define INTERNCODE_M12110 INTERN_PARTIAL |
| 6925 | #define INTERNCODE_M12120 INTERN_PARTIAL |
| 6926 | #else |
| 6927 | #define INTERNCODE_M12110 INTERN_FULL |
| 6928 | #define INTERNCODE_M12120 INTERN_FULL |
| 6929 | #endif |
| 6930 | #define INTERNCODE_M12160 INTERN_FULL |
| 6931 | #define INTERNCODE_M12170 INTERN_FULL |
| 6932 | /* ------------------------------------------------------------- */ |
| 6933 | #undef INTERNDATA_M12100 |
| 6934 | #undef INTERNDATA_M12110 |
| 6935 | #undef INTERNDATA_M12120 |
| 6936 | #undef INTERNDATA_M12160 |
| 6937 | #undef INTERNDATA_M12170 |
| 6938 | #undef INTERNDATA_L1D_DATA |
| 6939 | #undef INTERNDATA_L1D_INTERNAL_DATA |
| 6940 | #define INTERNDATA_M12100 INTERN_FULL |
| 6941 | #define INTERNDATA_M12110 INTERN_FULL |
| 6942 | #define INTERNDATA_M12120 INTERN_FULL |
| 6943 | #define INTERNDATA_M12160 INTERN_FULL |
| 6944 | #define INTERNDATA_M12170 INTERN_FULL |
| 6945 | #define INTERNDATA_L1D_DATA INTERN_FULL |
| 6946 | #define INTERNDATA_L1D_INTERNAL_DATA INTERN_FULL |
| 6947 | |
| 6948 | #elif IS_CHIP_MT6255 || IS_CHIP_MT6250 |
| 6949 | |
| 6950 | #undef INTERNCODE_M11303 |
| 6951 | #define INTERNCODE_M11303 INTERN_PARTIAL_CRITICAL |
| 6952 | /* ------------------------------------------------------------- */ |
| 6953 | #undef INTERNDATA_M12100 |
| 6954 | #undef INTERNDATA_M12168 |
| 6955 | #undef INTERNDATA_M12170 |
| 6956 | #define INTERNDATA_M12100 INTERN_FULL |
| 6957 | #define INTERNDATA_M12168 INTERN_FULL |
| 6958 | #define INTERNDATA_M12170 INTERN_FULL |
| 6959 | /* ------------------------------------------------------------- */ |
| 6960 | #elif IS_CHIP_MT6235_SER /* code: all on , data: all on */ |
| 6961 | /* ------------------------------------------------------------- */ |
| 6962 | #if IS_GEMINI_SUPPORT |
| 6963 | #undef INTERNCODE_M12110 |
| 6964 | #undef INTERNCODE_M12120 |
| 6965 | #define INTERNCODE_M12110 INTERN_PARTIAL |
| 6966 | #define INTERNCODE_M12120 INTERN_PARTIAL |
| 6967 | #endif |
| 6968 | /* ------------------------------------------------------------- */ |
| 6969 | #elif IS_CHIP_MT6252 /* code: all off, data: all off */ |
| 6970 | /* ------------------------------------------------------------- */ |
| 6971 | #undef INTERNCODE_M11303 |
| 6972 | #undef INTERNCODE_M12110 |
| 6973 | #undef INTERNCODE_M12120 |
| 6974 | #undef INTERNCODE_M12168 |
| 6975 | #undef INTERNCODE_M12180 |
| 6976 | #define INTERNCODE_M11303 INTERN_PARTIAL_CRITICAL |
| 6977 | #define INTERNCODE_M12110 INTERN_PARTIAL_CRITICAL |
| 6978 | #define INTERNCODE_M12120 INTERN_PARTIAL_CRITICAL |
| 6979 | #define INTERNCODE_M12168 INTERN_PARTIAL_CRITICAL |
| 6980 | #define INTERNCODE_M12180 INTERN_PARTIAL_CRITICAL |
| 6981 | /* ------------------------------------------------------------- */ |
| 6982 | #elif IS_CHIP_MT6253 /* code: all on , data: all off */ |
| 6983 | /* ------------------------------------------------------------- */ |
| 6984 | #undef INTERNCODE_M11303 |
| 6985 | #undef INTERNCODE_M12110 |
| 6986 | #undef INTERNCODE_M12120 |
| 6987 | #undef INTERNCODE_M12160 |
| 6988 | #undef INTERNCODE_M12167 |
| 6989 | #undef INTERNCODE_M12168 |
| 6990 | #define INTERNCODE_M11303 INTERN_PARTIAL |
| 6991 | #define INTERNCODE_M12110 INTERN_PARTIAL |
| 6992 | #define INTERNCODE_M12120 INTERN_PARTIAL |
| 6993 | #define INTERNCODE_M12160 INTERN_PARTIAL |
| 6994 | #define INTERNCODE_M12167 INTERN_NULL |
| 6995 | #define INTERNCODE_M12168 INTERN_NULL |
| 6996 | /* ------------------------------------------------------------- */ |
| 6997 | #undef INTERNDATA_M12100 |
| 6998 | #undef INTERNDATA_M12160 |
| 6999 | #undef INTERNDATA_M12170 |
| 7000 | #undef INTERNDATA_M12171 |
| 7001 | #define INTERNDATA_M12100 INTERN_FULL |
| 7002 | #define INTERNDATA_M12160 INTERN_FULL |
| 7003 | #define INTERNDATA_M12170 INTERN_FULL |
| 7004 | #define INTERNDATA_M12171 INTERN_FULL |
| 7005 | /* ------------------------------------------------------------- */ |
| 7006 | #elif IS_CHIP_MT6223 /* code: all off, data: all off */ |
| 7007 | /* ------------------------------------------------------------- */ |
| 7008 | #undef INTERNCODE_M11303 |
| 7009 | #undef INTERNCODE_M12100 |
| 7010 | #undef INTERNCODE_M12110 |
| 7011 | #undef INTERNCODE_M12120 |
| 7012 | #undef INTERNCODE_M12160 |
| 7013 | #undef INTERNCODE_M12170 |
| 7014 | #define INTERNCODE_M11303 INTERN_PARTIAL |
| 7015 | #define INTERNCODE_M12100 INTERN_FULL |
| 7016 | #define INTERNCODE_M12110 INTERN_PARTIAL |
| 7017 | #define INTERNCODE_M12120 INTERN_PARTIAL |
| 7018 | #define INTERNCODE_M12160 INTERN_PARTIAL |
| 7019 | #define INTERNCODE_M12170 INTERN_PARTIAL |
| 7020 | /* ------------------------------------------------------------- */ |
| 7021 | #elif IS_CHIP_MT6225 /* code: all off, data: all off */ |
| 7022 | /* ------------------------------------------------------------- */ |
| 7023 | #undef INTERNCODE_M12160 |
| 7024 | #undef INTERNCODE_M12170 |
| 7025 | #define INTERNCODE_M12160 INTERN_FULL |
| 7026 | #define INTERNCODE_M12170 INTERN_FULL |
| 7027 | /* ------------------------------------------------------------- */ |
| 7028 | #undef INTERNDATA_M12160 |
| 7029 | #undef INTERNDATA_M12170 |
| 7030 | #define INTERNDATA_M12160 INTERN_FULL |
| 7031 | #define INTERNDATA_M12170 INTERN_FULL |
| 7032 | /* ------------------------------------------------------------- */ |
| 7033 | #elif IS_CHIP_MT6218 || IS_CHIP_MT6219 || IS_CHIP_MT6227 |
| 7034 | /* ------------------------------------------------------------- */ |
| 7035 | #undef INTERNCODE_M12100 |
| 7036 | #define INTERNCODE_M12100 INTERN_NULL |
| 7037 | /* ------------------------------------------------------------- */ |
| 7038 | #undef INTERNDATA_M12100 |
| 7039 | #define INTERNDATA_M12100 INTERN_NULL |
| 7040 | /* ------------------------------------------------------------- */ |
| 7041 | #elif IS_CHIP_MT6205 /* code: all off, data: all off */ |
| 7042 | /* ------------------------------------------------------------- */ |
| 7043 | #undef INTERNCODE_M12160 |
| 7044 | #undef INTERNCODE_M12170 |
| 7045 | #define INTERNCODE_M12160 INTERN_FULL |
| 7046 | #define INTERNCODE_M12170 INTERN_FULL |
| 7047 | /* ------------------------------------------------------------- */ |
| 7048 | #undef INTERNDATA_M12160 |
| 7049 | #undef INTERNDATA_M12170 |
| 7050 | #undef INTERNDATA_L1D_DATA |
| 7051 | #define INTERNDATA_M12160 INTERN_FULL |
| 7052 | #define INTERNDATA_M12170 INTERN_FULL |
| 7053 | #define INTERNDATA_L1D_DATA INTERN_FULL |
| 7054 | /* ------------------------------------------------------------- */ |
| 7055 | #endif |
| 7056 | |
| 7057 | /*===============================================================================================*/ |
| 7058 | #endif |
| 7059 | |