| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * ul1d_mmrf_interface.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * TK6291 |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * UL1D interface to Multi-Mode Multi-RAT RF Central Control |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *---------------------------------------------------------------------------- |
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| 556 | *---------------------------------------------------------------------------- |
| 557 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 558 | *============================================================================ |
| 559 | ****************************************************************************/ |
| 560 | |
| 561 | #ifndef _UL1D_MMRF_INTERFACE_H_ |
| 562 | #define _UL1D_MMRF_INTERFACE_H_ |
| 563 | |
| 564 | /*===============================================================================*/ |
| 565 | |
| 566 | #include "kal_general_types.h" |
| 567 | #include "mml1_rf_cal_def.h" |
| 568 | #include "ul1d_rf_public.h" |
| 569 | #include "mml1_rf_cal_interface.h" |
| 570 | #include "mml1_rf_interface.h" |
| 571 | #include "mml1_rf_calpocif.h" |
| 572 | #if IS_3G_UTAS_SUPPORT |
| 573 | #include "mml1_rf_ant_interface.h" |
| 574 | #endif |
| 575 | #if IS_3G_GEN97_RXDFE_RFC_API_SUPPORT |
| 576 | #include "mml1_rxdfe_api.h" |
| 577 | #endif |
| 578 | //#include "ul1d_rf_internal.h" |
| 579 | //#include "el1d_mmrf_interface.h" |
| 580 | |
| 581 | /********************************************************************************** |
| 582 | * define |
| 583 | **********************************************************************************/ |
| 584 | /* TX MIPI PA */ |
| 585 | #define UMTS_MAX_MIPI_PAON_CW_NUMBER_PER_BAND (48) //amount of 14 is used for ASM(2)/TPC(4+1) as default |
| 586 | #define UMTS_MAX_MIPI_PAOFF_CW_NUMBER_PER_BAND (20) // amount of 8 is used for TPC(4) as default |
| 587 | |
| 588 | /* RXPOC */ |
| 589 | #define UL1D_RX_IRR_DC_ROUTE_NUM_MAX 4 |
| 590 | #define UL1D_RX_IIP2_ROUTE_NUM_MAX (UL1D_RF_RX_IIP2_COMP_ROUTE_MAX) |
| 591 | |
| 592 | #if 1/*POC Re-Org Phase 1*/ |
| 593 | /** TXDFE filter coefficient and compensation data dimension*/ |
| 594 | #define UL1D_TX_DC_COMP_FC_MODE_NUM 2 |
| 595 | #define UL1D_TX_DC_COMP_PGA_SLICE_SET_NUM 8 |
| 596 | |
| 597 | #define UL1D_TX_IQ_COMP_FC_MODE_NUM 2 |
| 598 | #define UL1D_TX_IQ_COMP_PGA_SLICE_SET_NUM 8 |
| 599 | |
| 600 | #define UL1D_FREQ_DEP_COMP_FC_MODE_NUM 2 |
| 601 | #define UL1D_FREQ_DEP_COMP_PGA_SLICE_SET_NUM 8 |
| 602 | #define UL1D_FREQ_DEP_COMP_COEFF_NUM MMRFC_FILT_TAPS_NUM |
| 603 | |
| 604 | #define UL1D_ASYMM_COMP_FC_MODE_NUM 4 |
| 605 | #define UL1D_ASYMM_COMP_PGA_SLICE_SET_NUM 3 |
| 606 | #define UL1D_ASYMM_COMP_COEFF_NUM 7 |
| 607 | #endif |
| 608 | |
| 609 | #if UMTS_POC_RECAL_ENABLE |
| 610 | #define UMTS_RECAL_ITER (2) |
| 611 | #else |
| 612 | #define UMTS_RECAL_ITER (1) |
| 613 | #endif |
| 614 | |
| 615 | #define UL1D_POC_RX_DCOC_RECAL_ENABLE (0) |
| 616 | |
| 617 | #if UL1D_POC_RX_DCOC_RECAL_ENABLE |
| 618 | #define UMTS_RX_DCOC_RECAL_ITER (2) |
| 619 | #else |
| 620 | #define UMTS_RX_DCOC_RECAL_ITER (1) |
| 621 | #endif |
| 622 | |
| 623 | |
| 624 | /************************************************************************************ |
| 625 | * enum |
| 626 | ************************************************************************************/ |
| 627 | |
| 628 | typedef enum |
| 629 | { |
| 630 | BB_NO_ADJ, |
| 631 | BB_NEG_3, |
| 632 | BB_ADJ_VALUE, |
| 633 | } TX_BB_GAIN_ADJ_TYPE_T; |
| 634 | |
| 635 | typedef enum |
| 636 | { |
| 637 | FREQ_DEP_3TAPS, |
| 638 | FREQ_DEP_5TAPS, |
| 639 | FREQ_DEP_7TAPS, |
| 640 | FREQ_DEP_NA, |
| 641 | } TX_FREQ_DEP_TAPS_T; |
| 642 | |
| 643 | typedef enum |
| 644 | { |
| 645 | ASYMM_3TAPS, |
| 646 | ASYMM_5TAPS, |
| 647 | ASYMM_7TAPS, |
| 648 | ASYMM_9TAPS, |
| 649 | ASYMM_11TAPS, |
| 650 | ASYMM_NA, |
| 651 | } TX_ASYMM_TAPS_T; |
| 652 | |
| 653 | typedef enum |
| 654 | { |
| 655 | DAC_RAT_104M, |
| 656 | DAC_RAT_208M, |
| 657 | DAC_RAT_416M, |
| 658 | } TX_DAC_RATE_T; |
| 659 | |
| 660 | typedef enum |
| 661 | { |
| 662 | COS, |
| 663 | JSIN, |
| 664 | COS_PLUS_JSIN, |
| 665 | COS_MINUS_JSIN, |
| 666 | } TX_TTG_TONE_PHASE_T; |
| 667 | |
| 668 | typedef enum |
| 669 | { |
| 670 | PATH0, |
| 671 | PATH1, |
| 672 | } RX_PATH_T; |
| 673 | |
| 674 | typedef enum |
| 675 | { |
| 676 | FEC, |
| 677 | CR4, |
| 678 | } RX_SRC_SEL_T; |
| 679 | |
| 680 | typedef enum |
| 681 | { |
| 682 | ANT0, |
| 683 | ANT1, |
| 684 | } RX_ANT_T; |
| 685 | |
| 686 | typedef enum |
| 687 | { |
| 688 | FREQ_COMPLEX_BYPASS, |
| 689 | RFEQ_COMPLEX_3TAPS, |
| 690 | RFEQ_COMPLEX_5TAPS, |
| 691 | RFEQ_COMPLEX_8TAPS, |
| 692 | } RX_RFEQ_COMPLEX_TAPS_T; |
| 693 | |
| 694 | typedef enum |
| 695 | { |
| 696 | FDPM_0TAPS, |
| 697 | FDPM_2TAPS, |
| 698 | FDPM_3TAPS, |
| 699 | FDPM_4TAPS, |
| 700 | FDPM_5TAPS, |
| 701 | FDPM_6TAPS, |
| 702 | FDPM_7TAPS, |
| 703 | FDPM_8TAPS, |
| 704 | FDPM_DELAY_1TAPS, |
| 705 | FDPM_DELAY_2TAPS, |
| 706 | FDPM_DELAY_3TAPS, |
| 707 | } RX_FDPM_TAPS_T; |
| 708 | |
| 709 | typedef enum |
| 710 | { |
| 711 | RX_PATH_NONE, |
| 712 | RX_PATH_MAIN, |
| 713 | RX_PATH_DIVERSITY, |
| 714 | RX_PATH_BOTH, |
| 715 | } RF_RX_PATH_T; |
| 716 | |
| 717 | typedef enum |
| 718 | { |
| 719 | C0, |
| 720 | C1, |
| 721 | C2, |
| 722 | } RX_CARRIER_T; |
| 723 | |
| 724 | typedef enum |
| 725 | { |
| 726 | DCK, |
| 727 | IQK, |
| 728 | IIP2K, |
| 729 | IIP2K_NM, |
| 730 | } RX_CAL_MODE_T; |
| 731 | |
| 732 | typedef enum |
| 733 | { |
| 734 | BWT_SC, |
| 735 | BWT_DC, |
| 736 | BWT_3C, |
| 737 | } RX_PATH_BANDWIDTH_T; |
| 738 | |
| 739 | typedef struct |
| 740 | { |
| 741 | kal_uint16 mipi_data_start; |
| 742 | kal_uint16 mipi_data_number; |
| 743 | }UL1D_RF_CAL_MIPI_DATA_T; |
| 744 | /*===============================================================================*/ |
| 745 | /*===============================================================================*/ |
| 746 | /* RF Calibration Result Structure */ |
| 747 | /* The structure is grouped from post-processing result. Some redundent */ |
| 748 | /* items may need to be removed and excluded in shared memory or NVRAM. */ |
| 749 | /*===============================================================================*/ |
| 750 | typedef struct |
| 751 | { |
| 752 | RF_CW_T stxCw511; //STX MAIN |
| 753 | RF_CW_T stxCw529; //DCO1 |
| 754 | RF_CW_T stxCw549; //MMD2 |
| 755 | RF_CW_T stxCw582; |
| 756 | }UMTS_STX_CONFIG_BUFFER_T; |
| 757 | |
| 758 | #if defined(__MD97__) || (defined __MD97P__) |
| 759 | #else |
| 760 | typedef struct |
| 761 | { |
| 762 | kal_uint8 route_num; |
| 763 | kal_bool is_rx_tdd_band; |
| 764 | MMRFC_RX_CAL_CFG_T cfg[MMRFC_RX_IRR_COMP_ROUTE_MAX]; |
| 765 | }UL1D_RX_CAL_IRR_DC_CFG_T; |
| 766 | #endif |
| 767 | |
| 768 | typedef struct |
| 769 | { |
| 770 | MMRFC_RX_DC_RESULT_T rx_dc[MMRFC_RXDC_TIA_GAIN_STEPS][MMRFC_RXDC_PGA_GAIN_WCDMA_STEPS]; |
| 771 | } UMTS_RX_DC_HPM_RESULT_T; |
| 772 | |
| 773 | typedef struct |
| 774 | { |
| 775 | MMRFC_RX_DC_RESULT_T rx_dc[MMRFC_RXDC_TIA_GAIN_LPM_STEPS][MMRFC_RXDC_PGA_GAIN_LPM_STEPS]; |
| 776 | } UMTS_RX_DC_LPM_RESULT_T; |
| 777 | |
| 778 | |
| 779 | #if IS_URF_TRINITYE1_RFC||IS_URF_TRINITY_L||IS_URF_TRINITY_2L||IS_URF_COLUMBUS_TO_DO |
| 780 | //Trinity do not define MMRFC_UMTS_RESULT_PER_BAND_T |
| 781 | #else |
| 782 | |
| 783 | |
| 784 | typedef struct |
| 785 | { |
| 786 | /* RX IRR */ |
| 787 | MMRFC_RX_IRR_RESULT_T rx_irr_hpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM]; //4 route, 9CBW, 2ANT |
| 788 | MMRFC_RX_IRR_RESULT_T rx_irr_lpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM]; //4 route, 9CBW, 2ANT |
| 789 | |
| 790 | /* RX DC */ |
| 791 | UMTS_RX_DC_HPM_RESULT_T rx_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM]; //4 route, 2ANT |
| 792 | UMTS_RX_DC_HPM_RESULT_T rx_dig_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM]; //4 route, 2ANT Digital DC |
| 793 | UMTS_RX_DC_LPM_RESULT_T rx_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM]; //4 route, 2ANT |
| 794 | UMTS_RX_DC_LPM_RESULT_T rx_dig_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM]; //4 route, 2ANT Digital DC |
| 795 | |
| 796 | /* RX IIP2 */ |
| 797 | #if IS_URF_MT6179||IS_URF_MT6177L_RX |
| 798 | MMRFC_IIP2_RESULT_T rx_iip2[2][UL1D_RF_RX_IIP2_COMP_ROUTE_MAX]; //[0] for RXP, [1] for RXD |
| 799 | #else |
| 800 | MMRFC_IIP2_RESULT_T rx_iip2[UL1D_RF_RX_IIP2_COMP_ROUTE_MAX]; //TODO: Need to check inter-band CA case |
| 801 | #endif |
| 802 | |
| 803 | /* DET */ |
| 804 | /* Only FDIQ is dependent with sample rates, other redundent items need to be removed in NVRAM/share memory structure */ |
| 805 | kal_uint32 det_coarse_dcoc_cw807; //CW807, V_TXCDCOC1[19:0] |
| 806 | kal_uint32 det_coarse_dcoc_cw808; //CW808, V_TXCDCOC2[19:0] |
| 807 | MMRFC_DET_IQDNL_RESULT_T det_iqdnl_fwd[UL1D_DET_FE_GAIN_STEPS][UL1D_TX_CBW_NUM]; |
| 808 | MMRFC_DET_DC_RESULT_T det_dc_fwd[MMRFC_DET_GAIN_STEPS_DET_CAL]; //17 DET gain step |
| 809 | |
| 810 | MMRFC_DET_IQDNL_RESULT_T det_iqdnl_rev[UL1D_DET_FE_GAIN_STEPS][UL1D_TX_CBW_NUM]; |
| 811 | MMRFC_DET_DC_RESULT_T det_dc_rev[MMRFC_DET_GAIN_STEPS_DET_CAL]; //17 DET gain step |
| 812 | |
| 813 | /* TX LO Cal */ |
| 814 | kal_uint32 tx_lo; //CW714, {2'b00,V_TXLOCAP[6:0],V_TXLOIND,V_TXLOINBIAS[4:0],V_TXLOINBIAS[4:0]} |
| 815 | kal_uint8 tx_lo_ind; |
| 816 | kal_uint8 tx_lo_capcal_peak_cap; //CW714 |
| 817 | kal_uint8 tx_lo_in_bias_hpm; //CW714 |
| 818 | kal_uint8 tx_lo_in_bias_lpm; //CW714 |
| 819 | kal_uint32 stx_dcc_delta_nc; //CW568, V_DCC_DELTA_NC[10:0] |
| 820 | |
| 821 | /* TX RC */ |
| 822 | kal_int16 tx_rc_lpf[UL1D_TX_CBW_NUM]; |
| 823 | kal_int16 tx_rc_rcf; |
| 824 | |
| 825 | /* TX IQDC */ |
| 826 | /* TXIQ: G0, G9, G10, G12a, G14a, G12b, G14b, G21 */ |
| 827 | /* TXDC: G0, G9, G10, G12a, G14a, G12b, G14b, G21 */ |
| 828 | /* freq_dep_phase_tx is temp output for FDIQ cal */ |
| 829 | MMRFC_TX_IQDC_RESULT_T tx_iqdc_lin[UL1D_TX_PGA_SLICE_NUM+1]; |
| 830 | MMRFC_TX_IQDC_RESULT_T tx_iqdc_dpd[UL1D_TX_PGA_SLICE_NUM+1]; |
| 831 | MMRFC_TX_FD_FILT_RESULT_T tx_fdiq[UL1D_TX_CBW_NUM][UL1D_TX_PGA_SLICE_NUM+1]; |
| 832 | |
| 833 | /* TX DNL */ |
| 834 | kal_int16 tx_dnl_lin_pga_a[UL1D_TX_DNL_PGA_A_SEQ_NUM]; //20 gain diff |
| 835 | kal_int16 tx_dnl_lin_pga_b[UL1D_TX_DNL_PGA_B_SEQ_NUM]; //15 gain diff |
| 836 | kal_int16 tx_dnl_dpd_pga_a[UL1D_TX_DNL_PGA_A_SEQ_NUM]; //20 gain diff |
| 837 | kal_int16 tx_dnl_dpd_pga_b[UL1D_TX_DNL_PGA_B_SEQ_NUM]; //15 gain diff |
| 838 | |
| 839 | /* TX GA */ |
| 840 | MMRFC_TX_GA_RESULT_T tx_ga_w_ET[UL1D_TX_PGA_TYPE_NUM][UL1D_TX_CBW_NUM]; //3 PGA type, 6CBW |
| 841 | MMRFC_TX_GA_RESULT_T tx_ga_wo_ET[UL1D_TX_PGA_TYPE_NUM][UL1D_TX_CBW_NUM]; //3 PGA type, 6CBW |
| 842 | |
| 843 | /* TX PGA Phase Step */ |
| 844 | kal_int16 pga_phase_step; |
| 845 | |
| 846 | /* TX PGA Gain Step */ |
| 847 | kal_int16 pga_gain_step[UL1D_TX_PGA_GAIN_STEP_SUBBAND_NUM][UL1D_TX_PGA_GAIN_STEP_NUM]; |
| 848 | |
| 849 | /* TX PGA Cap Tuning */ |
| 850 | kal_int16 cap_tuning_pga_a; |
| 851 | kal_int16 cap_tuning_pga_b; |
| 852 | |
| 853 | |
| 854 | } MMRFC_UMTS_RESULT_PER_BAND_T; |
| 855 | |
| 856 | typedef struct |
| 857 | { |
| 858 | MMRFC_UMTS_RESULT_PER_BAND_T umts_result[MAX_SUPPORTED_BAND_INDEX]; |
| 859 | } MMRFC_UMTS_RESULT_T; |
| 860 | #endif /*IS_URF_TRINITYE1_RFC*/ |
| 861 | |
| 862 | |
| 863 | /* RX POC index and CFG table */ |
| 864 | typedef struct |
| 865 | { |
| 866 | UMTSBand band; |
| 867 | kal_uint8 route_num; |
| 868 | UMTS_Route route_idx[UL1D_RX_IRR_DC_ROUTE_NUM_MAX]; |
| 869 | }UL1D_RX_IRR_DC_CFG_INDEX_TBL_T; |
| 870 | |
| 871 | typedef struct |
| 872 | { |
| 873 | UMTSBand band; |
| 874 | kal_uint8 route_num; |
| 875 | UMTS_Route rx_route_idx[UL1D_RX_IIP2_ROUTE_NUM_MAX]; |
| 876 | UMTS_Route tx_route_idx[UL1D_RX_IIP2_ROUTE_NUM_MAX]; |
| 877 | }UL1D_RX_IIP2_CFG_INDEX_TBL_T; |
| 878 | |
| 879 | #if 1/*POC Re-Org Phase 1*/ |
| 880 | typedef struct |
| 881 | { |
| 882 | kal_int16 i_part; |
| 883 | kal_int16 q_part; |
| 884 | |
| 885 | } UL1D_TXDFE_TX_DC_COMP_T; |
| 886 | |
| 887 | typedef struct |
| 888 | { |
| 889 | UL1D_TXDFE_TX_DC_COMP_T comp_tab[UL1D_TX_DC_COMP_FC_MODE_NUM][UL1D_TX_DC_COMP_PGA_SLICE_SET_NUM]; |
| 890 | |
| 891 | } UL1D_TXDFE_TX_DC_COMP_TAB_T; |
| 892 | |
| 893 | typedef struct |
| 894 | { |
| 895 | kal_int16 gain; |
| 896 | kal_int16 phase; |
| 897 | |
| 898 | } UL1D_TXDFE_TX_IQ_COMP_T; |
| 899 | |
| 900 | typedef struct |
| 901 | { |
| 902 | UL1D_TXDFE_TX_IQ_COMP_T comp_tab[UL1D_TX_IQ_COMP_FC_MODE_NUM][UL1D_TX_IQ_COMP_PGA_SLICE_SET_NUM]; |
| 903 | |
| 904 | } UL1D_TXDFE_TX_IQ_COMP_TAB_T; |
| 905 | #endif |
| 906 | |
| 907 | #if defined(__MD97__) || (defined __MD97P__) |
| 908 | #else |
| 909 | typedef struct |
| 910 | { |
| 911 | kal_uint8 route_num; |
| 912 | kal_uint16 rx_iip2_usage_comp_idx[UL1D_RX_IIP2_ROUTE_NUM_MAX]; |
| 913 | kal_bool is_rx_tdd_band; |
| 914 | MMRFC_RX_CAL_CFG_T rx_cfg[UL1D_RX_IIP2_ROUTE_NUM_MAX]; |
| 915 | MMRFC_TX_CAL_CFG_T tx_cfg[UL1D_RX_IIP2_ROUTE_NUM_MAX]; |
| 916 | }UL1D_RX_CAL_IIP2_CFG_T; |
| 917 | #endif |
| 918 | |
| 919 | typedef struct |
| 920 | { |
| 921 | UMTS_RF_POC_RX_DC_COMP_T dc_ant0; |
| 922 | UMTS_RF_POC_RX_DC_COMP_T dc_ant1; |
| 923 | }UL1D_RX_DCOC_COMP_DATA_T; |
| 924 | |
| 925 | #if IS_URF_MT6177L_RFC || IS_URF_MT6173_RFC |
| 926 | typedef struct |
| 927 | { |
| 928 | kal_uint32 bsiDada[SEQ_3G_FDD_RFC_STX_CONFIG_BUFFER_COUNT]; |
| 929 | }URFC_STX_CONFIG_BUFFER_T; |
| 930 | |
| 931 | typedef struct |
| 932 | { |
| 933 | kal_uint32 bsiDada[SEQ_3G_FDD_RFC_TX_CONFIG_BUFFER_COUNT]; |
| 934 | }URFC_TX_CONFIG_BUFFER_T; |
| 935 | |
| 936 | typedef struct |
| 937 | { |
| 938 | kal_uint32 bsiDada[SEQ_3G_FDD_RFC_LIN_CONFIG_BUFFER_COUNT]; |
| 939 | |
| 940 | }URFC_TX_DRV_BIAS_LIN_CONFIG_BUFFER_T; |
| 941 | |
| 942 | typedef struct |
| 943 | { |
| 944 | kal_uint32 bsiDada[SEQ_3G_FDD_RFC_DPD_CONFIG_BUFFER_COUNT]; |
| 945 | }URFC_TX_DRV_BIAS_DPD_CONFIG_BUFFER_T; |
| 946 | #endif |
| 947 | |
| 948 | #if IS_3G_GEN97_RXDFE_RFC_API_SUPPORT |
| 949 | typedef struct |
| 950 | { |
| 951 | MMRF_COMMON_BAND_IDX_E band; |
| 952 | kal_uint8 ant_mask; |
| 953 | kal_uint8 srx_path; |
| 954 | kal_uint8 carrier_mask; |
| 955 | kal_uint8 carrier_cnt; |
| 956 | kal_int32 *NCO; /*10kHz, [0] for primary carrier, [1] for secondary carrier*/ |
| 957 | kal_uint32 on_ucnt; /*312MHz ucnt*/ |
| 958 | kal_bool is_lpm; |
| 959 | }UL1D_RXDFE_RFC_Window_On_Param_T; |
| 960 | |
| 961 | typedef struct |
| 962 | { |
| 963 | kal_uint8 ant_mask; |
| 964 | kal_uint8 srx_path; |
| 965 | kal_uint32 off_ucnt; /*312MHz ucnt*/ |
| 966 | }UL1D_RXDFE_RFC_Window_Off_Param_T; |
| 967 | |
| 968 | typedef struct |
| 969 | { |
| 970 | MML1_RXDFE_SW_DC_T sw_dc[MMRFC_RX_PHYSICAL_ANT_NUM]; |
| 971 | }UL1D_RXDFE_RFC_Comp_Update_DC_Param_T; |
| 972 | |
| 973 | typedef struct |
| 974 | { |
| 975 | MMRFC_RX_IRR_COMP_T rx_irr_ant[MMRFC_RX_PHYSICAL_ANT_NUM]; |
| 976 | } UL1D_RXDFE_RFC_Comp_Update_IRR_Param_T; |
| 977 | |
| 978 | typedef struct |
| 979 | { |
| 980 | MMRF_COMMON_BAND_IDX_E band; |
| 981 | kal_uint8 ant_mask; |
| 982 | kal_uint8 srx_path; |
| 983 | kal_uint8 carrier_cnt; |
| 984 | kal_bool is_lpm; |
| 985 | kal_uint32 update_ucnt; /*312MHz ucnt*/ |
| 986 | UL1D_RXDFE_RFC_Comp_Update_DC_Param_T *p_rfc_sw_dc; |
| 987 | UL1D_RXDFE_RFC_Comp_Update_IRR_Param_T *p_rfc_irr; |
| 988 | }UL1D_RXDFE_RFC_Comp_Update_Param_T; |
| 989 | #endif |
| 990 | |
| 991 | void UL1D_MMRF_PowerOnCalibration(void); |
| 992 | void UL1D_MMRF_L1CoreSHMDataInit(void); |
| 993 | void UL1D_MMRF_L1coreSHMUpdate2Local(void); |
| 994 | void UL1D_MMRF_PCoreSHMDataCacheFlush(void); |
| 995 | |
| 996 | /** Update Run-Time APIs */ |
| 997 | kal_uint32 UL1D_MMRF_UpdateRuntimeHandler( kal_uint32 nvram_lid, kal_uint32 record_idx, kal_uint8 *data, kal_uint16 nvram_size ); |
| 998 | |
| 999 | kal_uint16 UL1D_RF_Cal_Poc_NVRAM_Lid_Total_Num_InUse(void ); |
| 1000 | kal_uint16 UL1D_RF_Get_Rf_Self_Cal_Result_Size(kal_uint16 lid_index); |
| 1001 | kal_uint16 UL1D_RF_Get_Rf_Self_Cal_Result(kal_uint16 lid_index, kal_uint16 lid_size, kal_uint8 *dst); |
| 1002 | kal_uint16 UL1D_RF_Set_Rf_Self_Cal_Result(kal_uint16 lid_index, kal_uint16 lid_size, kal_uint8 *src); |
| 1003 | kal_uint16 UL1D_RF_Get_Rf_Self_Cal_String( kal_uint16 lid_index, kal_char *string_dst ); |
| 1004 | |
| 1005 | |
| 1006 | //For POC TX API |
| 1007 | //xxx_en_bit :: bit0:DPD, bit1:line mode1 without ET, bit2:line mode1 with ET,bit3:line mode2 without ET, bit4:line mode2 with ET |
| 1008 | #if 0 |
| 1009 | /* under construction !*/ |
| 1010 | /* under construction !*/ |
| 1011 | /* under construction !*/ |
| 1012 | /* under construction !*/ |
| 1013 | /* under construction !*/ |
| 1014 | /* under construction !*/ |
| 1015 | /* under construction !*/ |
| 1016 | /* under construction !*/ |
| 1017 | /* under construction !*/ |
| 1018 | /* under construction !*/ |
| 1019 | /* under construction !*/ |
| 1020 | /* under construction !*/ |
| 1021 | /* under construction !*/ |
| 1022 | /* under construction !*/ |
| 1023 | /* under construction !*/ |
| 1024 | /* under construction !*/ |
| 1025 | /* under construction !*/ |
| 1026 | /* under construction !*/ |
| 1027 | /* under construction !*/ |
| 1028 | /* under construction !*/ |
| 1029 | /* under construction !*/ |
| 1030 | #endif |
| 1031 | |
| 1032 | /** RF Route Table */ |
| 1033 | void UL1D_RF_ConstructRxConfigTable(void); |
| 1034 | void UL1D_RF_ConstructRxIrrConfigTable(void); |
| 1035 | void UL1D_RF_ConstructRxDcConfigTable(void); |
| 1036 | void UL1D_RF_ConstructRxIip2ConfigTable(void); |
| 1037 | #if defined(__MD97__) || (defined __MD97P__) |
| 1038 | #else |
| 1039 | void UL1D_RF_GetRxIrrDcConfigTable( UMTSBand band, UL1D_RX_CAL_IRR_DC_CFG_T* irr_dc_cfg, kal_uint8 is_irr_cal ); |
| 1040 | void UL1D_RF_GetRxIip2ConfigTable( UMTSBand band, UL1D_RX_CAL_IIP2_CFG_T* iip2_cfg ); |
| 1041 | #endif |
| 1042 | #if IS_URF_MT6179||IS_URF_MT6177L_RX||IS_URF_MT6173_RX |
| 1043 | void UL1D_RF_CAL_Set_TX_CW_Rx_IIP2_CAL(MMRFC_TX_CAL_CFG_T *tx_cfg, MML1_RF_BSIMM_PORT_T port_sel); |
| 1044 | void UL1D_RF_CAL_Set_TX_PGA_Gain_CW_Rx_IIP2_CAL(MMRFC_TX_CAL_CFG_T *iip2_tx_cfg_p, MML1_RF_BSIMM_PORT_T port_sel); |
| 1045 | #endif |
| 1046 | |
| 1047 | /** API to get TX DET ANT*/ |
| 1048 | void UL1D_RF_GET_TX_DET_ANT(MMRFC_XL1_BAND_NUM_E band, kal_bool is_fwd_path); |
| 1049 | #if defined(__MD97__) || (defined __MD97P__) |
| 1050 | #else |
| 1051 | kal_bool UL1D_RF_DET_Path_Query(MMRFC_XL1_BAND_NUM_E band, MMRF_DET_IO_E tx_det_io); |
| 1052 | #endif |
| 1053 | |
| 1054 | /** API for TAS*/ |
| 1055 | kal_bool UL1D_RF_TAS_Support(void); |
| 1056 | #if IS_3G_TAS_UL1_CUSTOM_SUPPORT |
| 1057 | #if IS_3G_GEN97_TAS_SUPPORT |
| 1058 | void UL1D_RF_Force_TAS(kal_bool force_tas_enable, MMRFD_CUSTOM_TAS_STATE_E tx_state, MMRFD_CUSTOM_TAS_STATE_E rx_state); |
| 1059 | #else |
| 1060 | void UL1D_RF_Force_TAS(UMTS_CUSTOM_TAS_SWITCH_E force_tas_enable, UMTS_CUSTOM_TAS_STATE_E tas_state); |
| 1061 | #endif |
| 1062 | #else |
| 1063 | void UL1D_RF_Force_TAS(kal_bool force_tas_enable, kal_uint8 tas_idx); |
| 1064 | #endif |
| 1065 | |
| 1066 | #if (defined __MD95__) |
| 1067 | kal_uint8 UL1TST_Supported_Band_Query(kal_uint8* band_info); |
| 1068 | #endif |
| 1069 | |
| 1070 | #if IS_3G_DAT_RFD_CTRL_EN |
| 1071 | void UL1D_RF_Force_DAT(kal_bool dat_feature_enable, kal_int16 scenario); |
| 1072 | kal_bool URFD_AP_Sensor_Relative_Feature_IS_Need_L1C_GAP(MMRF_AP_SENSOR_RELATIVE_OP_CODE_E OP_code, kal_int16 new_scenario); |
| 1073 | #endif |
| 1074 | |
| 1075 | #if IS_3G_GEN97_DAT_SUPPORT |
| 1076 | kal_bool UL1D_RF_DAT_Support(void); |
| 1077 | #endif |
| 1078 | |
| 1079 | /** API for BSI_W Init for MML1 normal power on flow */ |
| 1080 | void UL1D_RF_INIT_BSI_POWER_ON(void); |
| 1081 | |
| 1082 | #if 1/*POC Re-Org Phase 1*/ |
| 1083 | /** API for MMPOC Re-Org Phase 1*/ |
| 1084 | #if IS_MML1_UMTS_FDD_RAT_SUPPORT |
| 1085 | void UL1D_RFC_TXDFE_MTCMOS_CONTROL(kal_bool is_on); |
| 1086 | #if (defined __MD97__) || (defined __MD97P__) |
| 1087 | #else |
| 1088 | void UL1D_RF_TX_PARAM_COMP(RF_COMP_INDEX_E comp_idx, MMRFC_TX_RAT_CBW_CFG_E cbw_cfg, MMRFC_XL1_BAND_NUM_E band, kal_uint32 reCalIdx); |
| 1089 | void UL1D_RFC_DET_FIIQ_COMP(kal_uint32 route_idx, MMRFC_DETDFE_TIA_GAIN_IDX_E fe_gain, MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx, MMRFC_DET_FIIQ_COMP_T* p); |
| 1090 | void UL1D_RFC_DET_DC_COMP(kal_uint32 route_idx, kal_uint32 det_gain_step, MMRFC_DET_DC_COMP_T* p); |
| 1091 | void UL1D_RFC_DET_FDPCB_COMP(kal_uint32 route_idx, MMRFC_DETDFE_TIA_GAIN_IDX_E fe_gain, MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx, MMRFC_DET_EQLPF_CFG_T* p); |
| 1092 | void UL1D_RF_GetDetBwConfig(MMRFC_DET_CAL_ITEM_CFG_E detk_item, MMRFC_TX_RAT_CBW_CFG_E* start_cbw, MMRFC_TX_RAT_CBW_CFG_E* end_cbw, kal_uint8* tone_num); |
| 1093 | void UL1D_RF_GetTxBwConfig(MMRFC_TX_CAL_ITEM_CFG_E txk_item, MMRFC_TX_RAT_CBW_CFG_E* start_cbw, MMRFC_TX_RAT_CBW_CFG_E* end_cbw); |
| 1094 | kal_uint32 UL1D_RF_DATA_BUFFER_LENGTH_RETURN(MMPOC_BUFFER_IDX_E buf_type); |
| 1095 | kal_uint32* UL1D_RF_DATA_BUFFER_PTR_RETURN(MMPOC_BUFFER_IDX_E buf_type); |
| 1096 | kal_uint32 UL1D_RF_DATA_BUFFER_MIPI_LENGTH_RETURN(kal_bool is_mipi_on, kal_uint8 curr_band_idx); |
| 1097 | MML1_RF_BSIMM_PORT_T UL1D_RF_BUF_DATA_PORT_TABLE_RETURN(MMPOC_BUFFER_IDX_E bufId); |
| 1098 | #endif |
| 1099 | #endif |
| 1100 | |
| 1101 | #endif/*POC Re-Org Phase 1*/ |
| 1102 | |
| 1103 | #if 1/*POC Re-Org Phase 2*/ |
| 1104 | |
| 1105 | /*TX*/ |
| 1106 | #if (defined __MD97__) || (defined __MD97P__) |
| 1107 | #else |
| 1108 | void UL1D_RF_MMPOC_GetTxCfg(MMRFC_XL1_BAND_NUM_E band, MMRFC_TX_ROUTE_CFG_T* tx_cfg); |
| 1109 | void UL1D_RFC_GetCalibrationResults_RX_DC(MMRFC_POWER_MODE_E mode,kal_uint16 dc_comp_route_idx,RX_TIA_GAIN_E tia_gain_idx,RXIF_GAIN_E if_gain_idx,UMTS_RF_POC_RX_DC_COMP_T* rf_dc,MMRFC_XL1_BAND_NUM_E band); |
| 1110 | void UL1D_RFC_GetCalibrationResults_RX_Dig_DC(MMRFC_POWER_MODE_E mode,kal_uint16 dc_comp_route_idx,RX_TIA_GAIN_E tia_gain_idx,RXIF_GAIN_E if_gain_idx,UMTS_RF_POC_RX_DC_COMP_T* rf_dig_dc, MMRFC_XL1_BAND_NUM_E band); |
| 1111 | void UL1D_RFC_Get_Rx_IRR_Comp_Data( kal_uint16 rx_irr_comp_idx, MMRFC_RXIRR_CAL_MODE_E power_mode,kal_uint8 rx_bw_idx,UMTS_RF_POC_RX_IRR_COMP_T* rf_rx_irr_comp_p,MMRFC_XL1_BAND_NUM_E band); |
| 1112 | void UL1D_RFC_RF_RXDFE_Comp_Imm(RF_COMP_INDEX_E comp_idx, MMRFC_PATH_BITMAP_E path_sel,MML1_RF_BSIMM_PORT_T rfic,MMRFC_RX_GAIN_T rx_gain_info,kal_uint32 rx_rf_route_idx,MMRFC_XL1_BAND_NUM_E band,MMRFC_RX_CAL_TYPE_E rx_cal_item,kal_uint8 re_cal_indx); |
| 1113 | void UL1D_RFC_RXIRR_Gain_Config(MMRFC_RXIRR_CAL_MODE_E irr_mode_idx, kal_uint32 rx_gain_idx, RXIF_GAIN_E* pga_gain_p, RX_LNA_GAIN_E* lna_gain_p, RX_TIA_GAIN_E* tia_gain_p); |
| 1114 | /*RX*/ |
| 1115 | void UL1D_RF_CAL_Set_Tunnel_Path_Ctrl_CW(MMRFC_RX_CW_PARAM_T* rx_cw_param, MMRFC_RXT_PATH_CTRL_BUFFER_T* buffer); |
| 1116 | void UL1D_RFC_Get_Rx_IRR_Recal_Comp_Data( kal_uint16 rx_irr_comp_idx, MMRFC_RXIRR_CAL_MODE_E power_mode,kal_uint8 rx_bw_idx,UMTS_RF_POC_RX_IRR_COMP_T* rf_rx_irr_comp_p,MMRFC_XL1_BAND_NUM_E band,kal_uint8 re_cal_indx); |
| 1117 | void UL1D_RFC_GetCalibrationResults_RX_DC_Recal(MMRFC_POWER_MODE_E mode,kal_uint16 dc_comp_route_idx,RX_TIA_GAIN_E tia_gain_idx,RXIF_GAIN_E if_gain_idx,UMTS_RF_POC_RX_DC_COMP_T* rf_dc,MMRFC_XL1_BAND_NUM_E band,kal_uint8 re_cal_indx); |
| 1118 | void UL1D_RF_CAL_Set_Rx_Path_Ctrl_CW(MMRFC_RX_CW_PARAM_T* rx_cw_param, MMRFC_RX_CAL_CFG_T* rx_cfg); |
| 1119 | void UL1D_RF_CAL_Set_Rx_Mixer_Gate_Bias_CW(MMRFC_RX_CW_PARAM_T* rx_cw_param, MMRFC_RX_CAL_CFG_T* rx_cfg); |
| 1120 | void UL1D_RF_CAL_Set_Rx_LO_Ctrl_CW(MMRFC_RX_CW_PARAM_T* rx_cw_param, MMRFC_RX_CAL_CFG_T* rx_cfg); |
| 1121 | void UL1D_RF_CAL_Set_Srx_Config_CW(MMRFC_RX_CW_PARAM_T* rx_cw_param, MMRFC_RX_CAL_CFG_T* rx_cfg); |
| 1122 | |
| 1123 | |
| 1124 | #if IS_URF_MT6177L_RFC||IS_URF_MT6173_RFC |
| 1125 | void UL1D_RFC_STX_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, |
| 1126 | kal_uint8* length, |
| 1127 | URFC_STX_CONFIG_BUFFER_T* buffer); |
| 1128 | void UL1D_RFC_TX_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, |
| 1129 | kal_uint8* length, |
| 1130 | URFC_TX_CONFIG_BUFFER_T* buffer); |
| 1131 | void UL1D_RFC_LIN_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, |
| 1132 | kal_uint8* length, |
| 1133 | URFC_TX_DRV_BIAS_LIN_CONFIG_BUFFER_T* buffer); |
| 1134 | void UL1D_RFC_DPD_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, |
| 1135 | kal_uint8* length, |
| 1136 | URFC_TX_DRV_BIAS_DPD_CONFIG_BUFFER_T* buffer); |
| 1137 | #else |
| 1138 | void UL1D_RFC_STX_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, |
| 1139 | kal_uint8* length, |
| 1140 | MMRFC_STX_CONFIG_BUFFER_T* buffer); |
| 1141 | void UL1D_RFC_TX_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, |
| 1142 | kal_uint8* length, |
| 1143 | MMRFC_TX_CONFIG_BUFFER_T* buffer); |
| 1144 | void UL1D_RFC_LIN_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, |
| 1145 | kal_uint8* length, |
| 1146 | MMRFC_TX_DRV_BIAS_LIN_CONFIG_BUFFER_T* buffer); |
| 1147 | void UL1D_RFC_DPD_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, |
| 1148 | kal_uint8* length, |
| 1149 | MMRFC_TX_DRV_BIAS_DPD_CONFIG_BUFFER_T* buffer); |
| 1150 | #endif |
| 1151 | void UL1D_MMRF_RFCAL_TX_PA_ON_LOWGAIN_CONFIG_BUFFER_2(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, |
| 1152 | kal_uint8* length, |
| 1153 | MMRFC_TXPA_ON_LOWGAIN_BUFFER_T* buffer, |
| 1154 | MML1_RF_BSIMM_PORT_T* port_sel); |
| 1155 | |
| 1156 | void UL1D_MMRF_RFCAL_TX_PA_OFF_CONFIG_BUFFER_2(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, |
| 1157 | kal_uint8* length, |
| 1158 | MMRFC_TXPA_OFF_BUFFER_T* buffer, |
| 1159 | MML1_RF_BSIMM_PORT_T* port_sel); |
| 1160 | |
| 1161 | void UL1D_MMRF_RFCAL_TX_PA_ETM_CONFIG_BUFFER(MMRFC_XL1_BAND_SUPPORT_CAPABILITY_T* band_cap_p, |
| 1162 | kal_uint32 pa_lvl, |
| 1163 | kal_uint16 ul_freq, |
| 1164 | kal_bool etm_on, |
| 1165 | kal_uint8* length, |
| 1166 | MMRFC_TXPA_ETM_CONFIG_BUFFER_T* buffer); |
| 1167 | |
| 1168 | void UL1D_RFC_RXIRR_RESULT_WRITE_BACK(MMRFC_RXIRR_CAL_MODE_E irr_mode_idx, |
| 1169 | kal_uint8 irr_route_idx , |
| 1170 | MMRFC_XL1_BAND_NUM_E band, |
| 1171 | kal_uint8 cbw_idx, |
| 1172 | kal_uint8 ant_idx, |
| 1173 | MMRFC_RX_IRR_RESULT_T* rx_irr_data, |
| 1174 | kal_bool internal_ms_elapsed_time_check_flag); |
| 1175 | |
| 1176 | void UL1D_RF_CAL_TXCAP_RESULT_WRITE_BACK( |
| 1177 | MMRFC_XL1_BAND_NUM_E band, |
| 1178 | kal_uint32 subband_idx, |
| 1179 | kal_uint8 pga_ab, |
| 1180 | kal_bool is_pre_cap_tuning, |
| 1181 | kal_uint8 CAP_OPT_A, |
| 1182 | kal_uint8 CAP_OPT_B, |
| 1183 | kal_bool internal_ms_elapsed_time_check_flag); |
| 1184 | |
| 1185 | void UL1D_RF_TX_PGA_PHASE_STEP_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band, kal_int16 result); |
| 1186 | void UL1D_RF_CAL_TXDC_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band, |
| 1187 | kal_uint32 pwr_mode, |
| 1188 | kal_uint32 tx_pga_slice, |
| 1189 | MMRFC_TX_IQDC_RESULT_T* tx_iqdc_calgo_result, |
| 1190 | kal_uint32 recal, |
| 1191 | kal_bool internal_ms_elapsed_time_check_flag); |
| 1192 | void UL1D_RF_CAL_TXFIIQ_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band, |
| 1193 | kal_uint32 pwr_mode, |
| 1194 | kal_uint32 tx_pga_slice, |
| 1195 | MMRFC_TX_IQDC_RESULT_T* tx_iqdc_calgo_result, |
| 1196 | kal_uint32 recal, |
| 1197 | kal_bool internal_ms_elapsed_time_check_flag); |
| 1198 | void UL1D_RF_CAL_TXRC_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band, |
| 1199 | MMRFC_LPF_RCF_CAL_TYPE_E lpf_rcf_select, |
| 1200 | kal_int16 tx_rc_calgo_result, |
| 1201 | kal_bool internal_ms_elapsed_time_check_flag); |
| 1202 | #endif |
| 1203 | #endif/*POC ReOrg Phase 2*/ |
| 1204 | |
| 1205 | #if (defined __MD97__) || (defined __MD97P__) |
| 1206 | #else |
| 1207 | kal_uint8 UL1D_RF_CAL_RSEL_RCF(MMRFC_XL1_BAND_NUM_E band); |
| 1208 | kal_uint8 UL1D_RF_CAL_RSEL_LPF(MMRFC_XL1_BAND_NUM_E band); |
| 1209 | |
| 1210 | void UL1D_RF_RXIRR_Gain_Config(MMRFC_RXIRR_CAL_MODE_E irr_mode_idx, kal_uint32 rx_bw_idx, RXIF_GAIN_E* pga_gain_p, RX_LNA_GAIN_E* lna_gain_p, RX_TIA_GAIN_E* tia_gain_p); |
| 1211 | void UL1D_RF_POC_RxGainCW(MMRFC_RX_CW_PARAM_T* rx_cw_param, MMRFC_RXIRR_CAL_MODE_E power_mode_idx, kal_uint32 rx_gain_idx, |
| 1212 | MMRFC_PATH_BITMAP_E path_sel, MMRFC_RX_GAIN_CW_BUFFER_T* buffer); |
| 1213 | void UL1D_RF_RXDC_Setting_Config(kal_uint32** rx_hpm_gain_idx_by_rat, kal_uint32** rx_lpm_gain_idx_by_rat, MMRFC_POWER_MODE_E** dc_mode_idx_cal_end); |
| 1214 | |
| 1215 | void UL1D_RF_DETCDCOC_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band, |
| 1216 | kal_uint32 det_coarse_dcoc_cw807, |
| 1217 | kal_uint32 det_coarse_dcoc_cw808); |
| 1218 | |
| 1219 | void UL1D_RF_TXLO_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band, |
| 1220 | kal_uint8 ind_sw, |
| 1221 | kal_uint8 capcal_peak_cap, |
| 1222 | kal_uint8 in_bias_lpm, |
| 1223 | kal_uint8 in_bias_hpm); |
| 1224 | |
| 1225 | void UL1D_RF_DETDC_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band, |
| 1226 | kal_uint8 gain_idx, |
| 1227 | kal_uint32 recal, |
| 1228 | MMRFC_DET_DC_RESULT_T* tx_det_dc_calgo_result, |
| 1229 | kal_bool internal_ms_elapsed_time_check_flag); |
| 1230 | |
| 1231 | void UL1D_RF_DETFDPCB_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band, |
| 1232 | MMRFC_DET_TIA_COMP_INDEX_E fe_gain_idx, |
| 1233 | MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx, |
| 1234 | kal_uint32 recal, |
| 1235 | MMRFC_DET_EQLPF_CFG_T* tx_det_pcb_calgo_result, |
| 1236 | kal_bool internal_ms_elapsed_time_check_flag); |
| 1237 | |
| 1238 | void UL1D_RF_DETIQDNL_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band, |
| 1239 | MMRFC_DET_TIA_COMP_INDEX_E fe_gain_idx, |
| 1240 | MMRFC_DET_G_IDX gain_idx, |
| 1241 | MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx, |
| 1242 | kal_uint32 recal, |
| 1243 | MMRFC_DET_IQDNL_RESULT_T* tx_det_iqdnl_calgo_result, |
| 1244 | kal_bool internal_ms_elapsed_time_check_flag); |
| 1245 | |
| 1246 | void UL1D_RF_TXDNL_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band, |
| 1247 | kal_uint32 tx_gain_idx, |
| 1248 | kal_int32 tx_dnl_calgo_result0, |
| 1249 | kal_int32 tx_dnl_calgo_result1, |
| 1250 | kal_bool internal_ms_elapsed_time_check_flag); |
| 1251 | |
| 1252 | void UL1D_RFC_RXDC_RESULT_WRITE_BACK(MMRFC_POWER_MODE_E dc_mode_idx, |
| 1253 | MMRFC_XL1_BAND_NUM_E band, |
| 1254 | kal_uint8 tia_gain_idx, |
| 1255 | kal_uint8 if_gain_idx, |
| 1256 | kal_uint8 route_idx, |
| 1257 | kal_uint8 ant_idx, |
| 1258 | MMRFC_RX_DC_RESULT_T* rf_dc, |
| 1259 | MMRFC_RX_DC_RESULT_T* dig_dc, |
| 1260 | kal_bool internal_ms_elapsed_time_check_flag); |
| 1261 | |
| 1262 | void UL1D_RFC_RXIIP2_RESULT_WRITE_BACK(MMRFC_XL1_BAND_NUM_E band, |
| 1263 | kal_uint16 iip2_route_idx, |
| 1264 | MMRFC_IIP2_RESULT_T* rxp_iip2, |
| 1265 | MMRFC_IIP2_RESULT_T* rxd_iip2, |
| 1266 | kal_bool internal_ms_elapsed_time_check_flag); |
| 1267 | |
| 1268 | void UL1D_RFC_TX_DNL_SET_DEFAULT(MMRFC_XL1_BAND_NUM_E band); |
| 1269 | #endif |
| 1270 | //Gen97 |
| 1271 | #if IS_3G_GEN97_RXDFE_RFC_API_SUPPORT |
| 1272 | void UL1D_RXDFE_RFC_Window_On(UL1D_RXDFE_RFC_Window_On_Param_T *p_win_on_param); |
| 1273 | void UL1D_RXDFE_RFC_Window_Off(UL1D_RXDFE_RFC_Window_Off_Param_T *p_win_off_param); |
| 1274 | void UL1D_RXDFE_RFC_Comp_Update(UL1D_RXDFE_RFC_Comp_Update_Param_T *p_comp_update_param); |
| 1275 | extern kal_uint8 UL1D_RXDFE_SRX_IDX_TO_DFE_PATH(kal_uint8 srx_idx); |
| 1276 | #endif |
| 1277 | //Gen93/95 |
| 1278 | void UL1D_RFC_RXDFE_Win_On_Ctrl(MMRFC_RX_CAL_TYPE_E rx_cal_type, MMRFC_XL1_BAND_NUM_E band, MMRFC_PATH_BITMAP_E path_sel); |
| 1279 | void UL1D_RFC_RXDFE_Meas_Trigger(MMRFC_RX_CAL_TYPE_E rx_cal_type, kal_uint32 meas_atime, MMRFC_PATH_BITMAP_E path_sel); |
| 1280 | void UL1D_RFC_RXDFE_Win_Off_Ctrl(MMRFC_RX_CAL_TYPE_E rx_cal_type, MMRFC_PATH_BITMAP_E path_sel); |
| 1281 | void UL1D_RXDFE_Comp_ActBuff_Rxk(MMRFC_RX_CAL_TYPE_E calType, kal_bool is_hpm, kal_uint32 rx_bw_idx, UMTS_RF_POC_RX_IRR_COMP_T* irr_comp, UMTS_RF_POC_RX_DC_COMP_T* dc_comp); |
| 1282 | |
| 1283 | void ul1d_rf_cal_calculate_det_gain(UMTS_RF_POC_DET_COMP_DATA_T* p_det_shm); |
| 1284 | |
| 1285 | #if IS_URF_TRINITYE1_RFC||IS_URF_TRINITY_2L |
| 1286 | void UL1D_RFC_Get_RxrouteConfigTable_PerBand(MMRFC_XL1_BAND_NUM_E band, MMRFC_RX_CAL_ROUTE_PER_BAND_FROM_RXROUTE_CFG_T* irr_dc_cfg); |
| 1287 | |
| 1288 | void UL1D_RFC_Get_RxT2RConfigTable_PerBand( MMRFC_XL1_BAND_NUM_E band, MMRFC_RX_CAL_ROUTE_PER_BAND_FROM_T2R_CFG_T* iip2_cfg ); |
| 1289 | |
| 1290 | void UL1D_RFC_Get_TxConfigTable_PerBand( MMRFC_XL1_BAND_NUM_E mmrfc_band, MMRFC_TX_CAL_ROUTE_PER_BAND_CFG_T *tx_route_cfg); |
| 1291 | |
| 1292 | void UL1D_RFC_RX_DC_RESULT_HANDLING(MMRFC_POWER_MODE_E dc_mode_idx, |
| 1293 | RX_TIA_GAIN_E tia_gain_idx, |
| 1294 | RXIF_GAIN_E if_gain_idx, |
| 1295 | kal_uint16 dc_route_idx, |
| 1296 | kal_uint8 ant_idx, |
| 1297 | MMRFC_RX_DC_RESULT_T* rf_dc, |
| 1298 | MMRFC_RX_DC_RESULT_T* dig_dc, |
| 1299 | kal_uint8 re_cal_index, |
| 1300 | kal_bool is_write_back); |
| 1301 | |
| 1302 | void UL1D_RFC_RX_IRR_RESULT_HANDLING(MMRFC_RXIRR_CAL_MODE_E irr_mode_idx, |
| 1303 | kal_uint16 irr_route_idx, |
| 1304 | MMRFC_RX_RAT_CBW_CFG_E rx_cbw, |
| 1305 | kal_uint8 ant_idx, |
| 1306 | MMRFC_RX_IRR_RESULT_T* rx_irr_data, |
| 1307 | kal_uint8 re_cal_index, |
| 1308 | kal_bool is_write_back); |
| 1309 | |
| 1310 | void UL1D_RFC_RX_IIP2_RESULT_HANDLING(kal_uint16 iip2_route_idx, |
| 1311 | MMRFC_IIP2_RESULT_T* rxp_iip2, |
| 1312 | MMRFC_IIP2_RESULT_T* rxd_iip2, |
| 1313 | kal_bool is_write_back); |
| 1314 | |
| 1315 | void UL1D_RFC_TX_CAP_RESULT_HANDLING(kal_uint32 route_idx, |
| 1316 | MMRFC_XL1_BAND_NUM_E band, |
| 1317 | kal_bool is_pre_cap_tuning, |
| 1318 | kal_uint32 *CAP_OPT_A, |
| 1319 | kal_bool is_write_back); |
| 1320 | |
| 1321 | |
| 1322 | |
| 1323 | void UL1D_RFC_TX_DNL_RESULT_HANDLING(kal_bool is_tx_dnl_valid, |
| 1324 | kal_uint32 route_idx, |
| 1325 | kal_int16 *tx_dnl_calgo_result, |
| 1326 | kal_bool is_write_back); |
| 1327 | |
| 1328 | |
| 1329 | |
| 1330 | void UL1D_RFC_TX_FDIQ_RESULT_HANDLING(kal_uint32 route_idx, |
| 1331 | MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx, |
| 1332 | MMRFC_TX_ABB_SLICE_E tx_pga_slice, |
| 1333 | kal_uint32 recal, |
| 1334 | MMRFC_TX_FD_FILT_RESULT_T *tx_fdiq_calgo_result, |
| 1335 | kal_bool is_write_back); |
| 1336 | |
| 1337 | |
| 1338 | void UL1D_RFC_TX_FIIQDC_RESULT_HANDLING(kal_uint32 route_idx, |
| 1339 | MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx, |
| 1340 | MMRFC_TX_ABB_SLICE_E tx_pga_slice, |
| 1341 | kal_uint32 recal, |
| 1342 | MMRFC_TX_IQDC_RESULT_T *tx_iqdc_calgo_result, |
| 1343 | kal_bool is_write_back); |
| 1344 | |
| 1345 | void UL1D_RFC_TX_RCF_RESULT_HANDLING(kal_uint32 route_idx, |
| 1346 | kal_int16 *rsel_val, |
| 1347 | kal_int16 *csel_4a_val, |
| 1348 | kal_int16 *csel_1b_val, |
| 1349 | kal_int16 *csel_2a_val, |
| 1350 | kal_bool is_write_back); |
| 1351 | |
| 1352 | |
| 1353 | void UL1D_RFC_TX_LPF_RESULT_HANDLING(kal_uint32 route_idx, |
| 1354 | kal_int16 *rsel_val, |
| 1355 | kal_int16 *csel_val1, |
| 1356 | kal_int16 *csel_val2, |
| 1357 | kal_bool is_write_back); |
| 1358 | |
| 1359 | void UL1D_RFC_TX_CDCOC_RESULT_HANDLING(kal_uint32 route_idx, |
| 1360 | MMRFC_TX_ABB_SLICE_E tx_pga_slice, |
| 1361 | kal_int32 *tx_coarsedc_i, |
| 1362 | kal_int32 *tx_coarsedc_q, |
| 1363 | kal_uint32 recal, |
| 1364 | kal_bool is_write_back); |
| 1365 | |
| 1366 | |
| 1367 | void UL1D_RFC_TX_MOD_RESULT_HANDLING(kal_uint32 route_idx, |
| 1368 | kal_uint32 rfc_rt_idx, |
| 1369 | MMRFC_XL1_BAND_NUM_E band, |
| 1370 | kal_uint32 subband_idx, |
| 1371 | kal_uint32 *tx_drv_ctunemod, |
| 1372 | kal_bool is_write_back); |
| 1373 | |
| 1374 | #if IS_URF_TRINITY_L||IS_URF_TRINITY_2L |
| 1375 | void UL1D_RFC_TX_PGA_BIAS_RESULT_HANDLING(kal_uint32 route_idx, |
| 1376 | MMRFC_POC_PGA_BIAS_T *tx_pga_bias_data, |
| 1377 | kal_bool is_write_back); |
| 1378 | #endif |
| 1379 | |
| 1380 | void UL1D_RFC_MRX_CDCOC_RESULT_HANDLING(kal_uint32 route_idx, |
| 1381 | MMRFC_DET_G_IDX det_gain_idx, |
| 1382 | kal_uint32 recal, |
| 1383 | MMRFC_POC_MRX_COARSE_DC_T *det_coarse_dc_data, |
| 1384 | kal_bool is_write_back |
| 1385 | #if IS_MRX_DC_LOOP_ID_SUPPORT |
| 1386 | ,MMRFC_MRX_LOOP_ID_E loop_id |
| 1387 | #endif |
| 1388 | ); |
| 1389 | |
| 1390 | |
| 1391 | void UL1D_RFC_MRX_DC_RESULT_HANDLING(kal_uint32 route_idx, |
| 1392 | MMRFC_DET_G_IDX gain_idx, |
| 1393 | kal_uint32 recal, |
| 1394 | MMRFC_DET_DC_RESULT_T* tx_det_dc_calgo_result, |
| 1395 | kal_bool is_write_back |
| 1396 | #if IS_MRX_DC_LOOP_ID_SUPPORT |
| 1397 | ,MMRFC_MRX_LOOP_ID_E loop_id |
| 1398 | #endif |
| 1399 | ); |
| 1400 | |
| 1401 | |
| 1402 | void UL1D_RFC_MRX_FIIQ_RESULT_HANDLING(kal_uint32 route_idx, |
| 1403 | MMRFC_DET_G_IDX gain_idx, |
| 1404 | kal_uint32 recal, |
| 1405 | MMRFC_DET_IQAD_RESULT_T* tx_det_iqdnl_calgo_result, |
| 1406 | kal_bool is_write_back); |
| 1407 | |
| 1408 | |
| 1409 | void UL1D_RFC_MRX_FDPCB_RESULT_HANDLING(kal_uint32 route_idx, |
| 1410 | MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx, |
| 1411 | kal_uint32 recal, |
| 1412 | MMRFC_DET_EQLPF_CFG_T* tx_det_pcb_calgo_result, |
| 1413 | kal_bool is_write_back); |
| 1414 | |
| 1415 | void UL1D_RFC_MRX_FDPCB_RESULT_HANDLING(kal_uint32 route_idx, |
| 1416 | MMRFC_TX_RAT_CBW_CFG_E cbw_case_idx, |
| 1417 | kal_uint32 recal, |
| 1418 | MMRFC_DET_EQLPF_CFG_T* tx_det_pcb_calgo_result, |
| 1419 | kal_bool is_write_back); |
| 1420 | |
| 1421 | void UL1D_RFC_MRX_PGA_TZA_RESULT_HANDLING(kal_uint32 route_idx, |
| 1422 | MMRFC_MRX_PGA_TZA_BW_E bw_idx, |
| 1423 | kal_int16 *mrx_ctune_pga, |
| 1424 | kal_int16 *mrx_ctune_tza, |
| 1425 | kal_bool is_write_back); |
| 1426 | |
| 1427 | kal_bool UL1D_RFC_Query_RXDFE_RXIQ_Swap(MMRFC_PATH_BITMAP_E path_sel, MMRFC_RF_RXPD_SEL_E ant_sel); |
| 1428 | |
| 1429 | #if MMRFC_DEBUG_TRACE_RESULT_HANDLE |
| 1430 | |
| 1431 | void UL1D_RFC_VERIFICATION_CRITERION_TX_DNL(kal_uint32 route_idx, |
| 1432 | kal_uint32 i, |
| 1433 | kal_int32 check_criterion, |
| 1434 | kal_int16 dnl_cal, |
| 1435 | kal_int16* dnl_default, |
| 1436 | kal_bool* is_pass); |
| 1437 | |
| 1438 | void UL1D_RFC_VERIFICATION_CRITERION_TX_RCF(kal_int16 csel_4a_val, |
| 1439 | kal_uint32 route_idx, |
| 1440 | kal_uint32* criterion_upper, |
| 1441 | kal_uint32* criterion_lower, |
| 1442 | kal_int16* nominal_value, |
| 1443 | kal_bool* is_pass); |
| 1444 | |
| 1445 | void UL1D_RFC_VERIFICATION_CRITERION_TX_LPF(kal_uint32 route_idx, |
| 1446 | kal_int16* csel_val2, |
| 1447 | kal_int16* nominal_value, |
| 1448 | kal_uint32* criterion_upper, |
| 1449 | kal_uint32* criterion_lower, |
| 1450 | kal_bool* is_pass); |
| 1451 | |
| 1452 | |
| 1453 | void UL1D_RFC_GET_DEFAULT_TX_RCF(kal_uint32 route_idx, |
| 1454 | kal_int16* nominal_value); |
| 1455 | |
| 1456 | void UL1D_RFC_GET_DEFAULT_TX_LPF(kal_uint32 route_idx, |
| 1457 | kal_int16* nominal_value); |
| 1458 | |
| 1459 | #if IS_URF_TRINITY_L||IS_URF_TRINITY_2L |
| 1460 | void UL1D_RFC_GET_DEFAULT_TX_PGA_BIAS(kal_uint32 route_idx, |
| 1461 | MMRFC_POC_PGA_BIAS_T* p_nominal_val); |
| 1462 | #endif |
| 1463 | |
| 1464 | #endif//MMRFC_DEBUG_TRACE_RESULT_HANDLE |
| 1465 | |
| 1466 | #endif//IS_URF_TRINITYE1_RFC |
| 1467 | |
| 1468 | //WTPC part for NVRAM run time update |
| 1469 | extern void UL1D_HWTPC_NVRAM_init(void); |
| 1470 | |
| 1471 | extern void UL1D_RFC_RxDcocCW(MMRFC_PATH_BITMAP_E path_sel , UMTS_RF_POC_RX_DC_COMP_T* dcoc_comp, MML1_RF_BSIMM_PORT_T port_sel); |
| 1472 | |
| 1473 | extern void UL1D_RF_ContructRxConfigTable(); |
| 1474 | |
| 1475 | /************************************************************************************ |
| 1476 | * Global Variables extern (Interface) |
| 1477 | ************************************************************************************/ |
| 1478 | extern kal_uint32* wrfcalPocBufferTable [/*MMPOC_BUFFER_TYPE_NUM_OF*/]; |
| 1479 | extern kal_uint32 wrfcalPocBufferSizeTable [/*MMPOC_BUFFER_TYPE_NUM_OF*/]; |
| 1480 | extern MML1_RF_BSIMM_PORT_T wrfcalPocBufferDataPortSelTable [/*MMPOC_BUFFER_TYPE_NUM_OF*/]; |
| 1481 | extern MML1_MIPI_REG_RW_T wrfcalPocBufferDataMipiCwTypeTable[/*MMPOC_BUFFER_TYPE_NUM_OF*/]; |
| 1482 | extern UL1D_RF_CAL_MIPI_DATA_T UMTS_MIPI_PA_ON_DATA [/*MMPOC_BUFFER_TYPE_NUM_OF*/]; |
| 1483 | extern UL1D_RF_CAL_MIPI_DATA_T UMTS_MIPI_PA_OFF_DATA [/*MMPOC_BUFFER_TYPE_NUM_OF*/]; |
| 1484 | |
| 1485 | #if UMTS_POC_RECAL_ENABLE |
| 1486 | extern UMTS_RECAL_DEBUG_T umts_result_rek[UMTS_RECAL_ITER]; |
| 1487 | extern UMTS_RECAL_TXDET_INFO_T txdetRecalInfo; |
| 1488 | #endif |
| 1489 | |
| 1490 | |
| 1491 | #if IS_3G_TAS_TST_SUPPORT |
| 1492 | kal_uint16 UL1D_IsQueryingTasStateInfoSupported( void ); |
| 1493 | #if IS_3G_UTAS_SUPPORT |
| 1494 | kal_uint16 UL1D_GetTasStateConfigBandList( kal_uint16* band_list ); |
| 1495 | void UL1D_GetTasStateConfigByBand(kal_uint16 band, kal_uint16* cal_default_state, kal_uint16* toggled_state_num, kal_uint16* toggled_state_list ); |
| 1496 | #else |
| 1497 | kal_uint16 UL1D_QueryTasVersion( void ); |
| 1498 | kal_uint16 UL1D_GetTasStateConfigBandNum( void ); |
| 1499 | void UL1D_GetTasStateConfig(kal_uint16 buf_length, kal_uint16* band_list, kal_uint16* state_limit, kal_uint16* tas_state ); |
| 1500 | #endif |
| 1501 | #endif |
| 1502 | |
| 1503 | #if IS_3G_UTAS_SUPPORT |
| 1504 | #if IS_3G_GEN97_TAS_SUPPORT |
| 1505 | void UL1D_Get_META_Default_TAS_State(MMRF_COMMON_BAND_IDX_E band, MML1_COMMON_CAL_ANT_STATE_INFO_T* cal_default_state_pair); |
| 1506 | kal_uint16 UL1D_Supported_Band_Query(MMRF_COMMON_BAND_IDX_E* band_list); |
| 1507 | #else |
| 1508 | kal_uint16 UL1D_Get_Ant_FE_Layout_Group(kal_uint16 band); |
| 1509 | MMRFD_CUSTOM_TAS_STATE_E UL1D_Get_META_Default_TAS_State(kal_uint16 band); |
| 1510 | #endif |
| 1511 | #endif |
| 1512 | |
| 1513 | #if ((defined __MD93__) || (defined __MD95__)) |
| 1514 | #else |
| 1515 | void UL1D_TXDFE_Serdes_Assert(void); |
| 1516 | #endif |
| 1517 | |
| 1518 | #endif /* End of #ifndef _UL1D_MMRF_INTERFACE_H_ */ |
| 1519 | |