| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | #ifndef __SVC_DSP_DEBUG_CONTROL_H__ |
| 2 | #define __SVC_DSP_DEBUG_CONTROL_H__ |
| 3 | |
| 4 | #include "drv_comm.h" |
| 5 | #include "reg_base.h" |
| 6 | |
| 7 | /******************************************************************************* |
| 8 | * SCQ DBG APB CR Definition |
| 9 | *******************************************************************************/ |
| 10 | #if defined(__MD93__) || defined(__MD95__) |
| 11 | #define SCQ0_APB_BASE (BASE_MADDR_MDPERI_MD_DBGSYS2 + 0xC000) |
| 12 | #define SCQ1_APB_BASE (BASE_MADDR_MDPERI_MD_DBGSYS2 + 0xD000) |
| 13 | #elif defined(__MD97__) || defined(__MD97P__) |
| 14 | #define SCQ0_APB_BASE (BASE_MADDR_VDSP_1_MD32SCQ) |
| 15 | #define SCQ1_APB_BASE (BASE_MADDR_VDSP_2_MD32SCQ) |
| 16 | #define SCQ2_APB_BASE (BASE_MADDR_VDSP_3_MD32SCQ) |
| 17 | #define SCQ3_APB_BASE (BASE_MADDR_VDSP_4_MD32SCQ) |
| 18 | #else |
| 19 | #error "Unsupported project!!" |
| 20 | #endif |
| 21 | |
| 22 | /******************************************************************************* |
| 23 | * MACRO Definition |
| 24 | *******************************************************************************/ |
| 25 | #define SCQ_APB_DBG_EN_OFFSET 0x0 |
| 26 | #define SCQ_APB_MODE_SEL_OFFSET 0x4 |
| 27 | #define SCQ_APB_DBG_INST_OFFSET 0x10 |
| 28 | #define SCQ_APB_DBG_EXECUTE_OFFSET 0x14 |
| 29 | |
| 30 | #if defined(__MD93__) || defined(__MD95__) |
| 31 | #define SCQ_APB_DBG_STATUS_OFFSET 0x20 |
| 32 | #elif defined (__MD97__) || defined(__MD97P__) |
| 33 | #define SCQ_APB_DBG_STATUS_OFFSET 0x24 |
| 34 | #else |
| 35 | #error "Unsupported project!!" |
| 36 | #endif |
| 37 | |
| 38 | #define SCQ_APB_DBG_ATTACH_INST 0x900 |
| 39 | #define SCQ_APB_DBG_REQ_INST 0x811 |
| 40 | #define SCQ_APB_DBG_STATUS_INST 0x803 |
| 41 | #define SCQ_APB_DBG_RESUME_INST 0x812 |
| 42 | |
| 43 | #if defined(__SCQ16_SUPPORT_CTI_RESTART__) |
| 44 | /* TODO: Add code for 97 CTI restart when HW ready */ |
| 45 | #endif |
| 46 | |
| 47 | #endif |