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192.168.1.100 / T800_MD / c592bc760e2308f0a66c1f96be789d29bd1a76d4 / . / mcu / custom / service / nvram / cl1_nvram_def.c
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * cl1_nvram_def.c
41 *
42 * Project:
43 * --------
44 * MAUI
45 *
46 * Description:
47 * ------------
48 * This file is intends for NVRAM security customization.
49 *
50 * Author:
51 * -------
52 *
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
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234 *------------------------------------------------------------------------------
235 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
236 *============================================================================
237 ****************************************************************************/
238
239#ifndef NVRAM_NOT_PRESENT
240#if defined (__C2K_RAT__) || defined(__CL1_TASK_ENABLE__)
241
242#include "kal_general_types.h"
243#ifdef NVRAM_AUTO_GEN
244#include "nvram_auto_gen.h"
245#endif
246
247#include "nvram_enums.h"
248#include "nvram_defs.h"
249
250/*
251 * User Headers & Default value
252 */
253#include "cl1_nvram_def.h"
254#include "cl1_nvram_editor.h"
255extern void nvram_get_cl1_default_value_to_write(nvram_lid_enum lid, kal_uint8 *buffer, kal_uint16 buffer_size);
256extern void nvram_get_cl1_poc_default_value_to_write(nvram_lid_enum lid, kal_uint8 *buffer, kal_uint16 buffer_size);
257
258#define CL1_L1D_ACC_PWR_OFFSET_BAND_0 0
259#define CL1_L1D_ACC_PWR_OFFSET_BAND_1 0
260#define CL1_L1D_ACC_PWR_OFFSET_BAND_10 0
261#define CL1_L1D_MAX_PWR_BACKOFF_BAND_0 0
262#define CL1_L1D_MAX_PWR_BACKOFF_BAND_1 0
263#define CL1_L1D_MAX_PWR_BACKOFF_BAND_10 0
264extern void nvram_get_cl1_1xrtt_dpd_am_pm_default_value_to_write(nvram_lid_enum lid, kal_uint8 *buffer, kal_uint16 buffer_size);
265extern void nvram_get_cl1_evdo_dpd_am_pm_default_value_to_write(nvram_lid_enum lid, kal_uint8 *buffer, kal_uint16 buffer_size);
266
267const CL1_L1D_TX_POWER_OFFSET_T cl1TxPwrOffset =
268{
269 {CL1_L1D_ACC_PWR_OFFSET_BAND_0,CL1_L1D_ACC_PWR_OFFSET_BAND_1,0,0,0,0,0,0,0,0,CL1_L1D_ACC_PWR_OFFSET_BAND_10,0,0,0,0,0,0,0,0,0,0}, /*accTxPwrOffset*/
270 {CL1_L1D_MAX_PWR_BACKOFF_BAND_0,CL1_L1D_MAX_PWR_BACKOFF_BAND_1,0,0,0,0,0,0,0,0,CL1_L1D_MAX_PWR_BACKOFF_BAND_10,0,0,0,0,0,0,0,0,0,0} /*maxPwrbackoff*/
271};
272
273// LID Declaration
274#if defined(__MD93__) || defined(__MD95__)
275ltable_entry_struct logical_data_item_table_cl1[] =
276{
277 {
278 NVRAM_EF_CL1_CUST_PARAM_LID,
279 NVRAM_EF_CL1_CUST_PARAM_TOTAL,
280 NVRAM_EF_CL1_CUST_PARAM_SIZE,
281 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
282 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
283 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
284 "CL00",
285 VER(NVRAM_EF_CL1_CUST_PARAM_LID)
286 },
287
288 {
289 NVRAM_EF_CL1_CUST_BPI_CFG_LID,
290 NVRAM_EF_CL1_CUST_BPI_CFG_TOTAL,
291 NVRAM_EF_CL1_CUST_BPI_CFG_SIZE,
292 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
293 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
294 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
295 "CL01",
296 VER(NVRAM_EF_CL1_CUST_BPI_CFG_LID)
297 },
298
299 {
300 NVRAM_EF_CL1_MIPI_PARAM_LID,
301 NVRAM_EF_CL1_MIPI_PARAM_TOTAL,
302 NVRAM_EF_CL1_MIPI_PARAM_SIZE,
303 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
304 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
305 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
306 "CL02",
307 VER(NVRAM_EF_CL1_MIPI_PARAM_LID)
308 },
309
310 {
311 NVRAM_EF_CL1_MIPI_RX_EVENT_LID,
312 NVRAM_EF_CL1_MIPI_RX_EVENT_TOTAL,
313 NVRAM_EF_CL1_MIPI_RX_EVENT_SIZE,
314 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
315 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
316 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
317 "CL03",
318 VER(NVRAM_EF_CL1_MIPI_RX_EVENT_LID)
319 },
320
321 {
322 NVRAM_EF_CL1_MIPI_RX_DATA_LID,
323 NVRAM_EF_CL1_MIPI_RX_DATA_TOTAL,
324 NVRAM_EF_CL1_MIPI_RX_DATA_SIZE,
325 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
326 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
327 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
328 "CL04",
329 VER(NVRAM_EF_CL1_MIPI_RX_DATA_LID)
330 },
331
332 {
333 NVRAM_EF_CL1_MIPI_TX_EVENT_LID,
334 NVRAM_EF_CL1_MIPI_TX_EVENT_TOTAL,
335 NVRAM_EF_CL1_MIPI_TX_EVENT_SIZE,
336 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
337 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
338 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
339 "CL05",
340 VER(NVRAM_EF_CL1_MIPI_TX_EVENT_LID)
341 },
342
343 {
344 NVRAM_EF_CL1_MIPI_TX_DATA_LID,
345 NVRAM_EF_CL1_MIPI_TX_DATA_TOTAL,
346 NVRAM_EF_CL1_MIPI_TX_DATA_SIZE,
347 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
348 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
349 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
350 "CL06",
351 VER(NVRAM_EF_CL1_MIPI_TX_DATA_LID)
352 },
353
354 {
355 NVRAM_EF_CL1_MIPI_TPC_EVENT_LID,
356 NVRAM_EF_CL1_MIPI_TPC_EVENT_TOTAL,
357 NVRAM_EF_CL1_MIPI_TPC_EVENT_SIZE,
358 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
359 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
360 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
361 "CL07",
362 VER(NVRAM_EF_CL1_MIPI_TPC_EVENT_LID)
363 },
364
365 {
366 NVRAM_EF_CL1_MIPI_TPC_DATA_LID,
367 NVRAM_EF_CL1_MIPI_TPC_DATA_TOTAL,
368 NVRAM_EF_CL1_MIPI_TPC_DATA_SIZE,
369 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
370 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
371 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
372 "CL08",
373 VER(NVRAM_EF_CL1_MIPI_TPC_DATA_LID)
374 },
375
376 {
377 NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_1XRTT_LID,
378 NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_1XRTT_TOTAL,
379 NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_1XRTT_SIZE,
380 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
381 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
382 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
383 "CL09",
384 VER(NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_1XRTT_LID)
385 },
386
387 {
388 NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_EVDO_LID,
389 NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_EVDO_TOTAL,
390 NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_EVDO_SIZE,
391 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
392 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
393 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
394 "CL0A",
395 VER(NVRAM_EF_CL1_MIPI_PA_SECTION_DATA_EVDO_LID)
396 },
397
398 {
399 NVRAM_EF_CL1_MIPI_ETM_TX_EVENT_LID,
400 NVRAM_EF_CL1_MIPI_ETM_TX_EVENT_TOTAL,
401 NVRAM_EF_CL1_MIPI_ETM_TX_EVENT_SIZE,
402 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
403 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
404 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
405 "CL0B",
406 VER(NVRAM_EF_CL1_MIPI_ETM_TX_EVENT_LID)
407 },
408
409 {
410 NVRAM_EF_CL1_MIPI_ETM_TX_DATA_LID,
411 NVRAM_EF_CL1_MIPI_ETM_TX_DATA_TOTAL,
412 NVRAM_EF_CL1_MIPI_ETM_TX_DATA_SIZE,
413 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
414 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
415 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
416 "CL0C",
417 VER(NVRAM_EF_CL1_MIPI_ETM_TX_DATA_LID)
418 },
419
420 {
421 NVRAM_EF_CL1_MIPI_ETM_TPC_EVENT_LID,
422 NVRAM_EF_CL1_MIPI_ETM_TPC_EVENT_TOTAL,
423 NVRAM_EF_CL1_MIPI_ETM_TPC_EVENT_SIZE,
424 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
425 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
426 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
427 "CL0D",
428 VER(NVRAM_EF_CL1_MIPI_ETM_TPC_EVENT_LID)
429 },
430
431 {
432 NVRAM_EF_CL1_MIPI_ETM_TPC_DATA_LID,
433 NVRAM_EF_CL1_MIPI_ETM_TPC_DATA_TOTAL,
434 NVRAM_EF_CL1_MIPI_ETM_TPC_DATA_SIZE,
435 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
436 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
437 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
438 "CL0E",
439 VER(NVRAM_EF_CL1_MIPI_ETM_TPC_DATA_LID)
440 },
441
442 {
443 NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_1XRTT_LID,
444 NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_1XRTT_TOTAL,
445 NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_1XRTT_SIZE,
446 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
447 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
448 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
449 "CL0F",
450 VER(NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_1XRTT_LID)
451 },
452
453 {
454 NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_EVDO_LID,
455 NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_EVDO_TOTAL,
456 NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_EVDO_SIZE,
457 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
458 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
459 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
460 "CL0G",
461 VER(NVRAM_EF_CL1_MIPI_ETM_PA_SECTION_DATA_EVDO_LID)
462 },
463
464 {
465 NVRAM_EF_CL1_CUST_TAS_FEATURE_LID,
466 NVRAM_EF_CL1_CUST_TAS_FEATURE_TOTAL,
467 NVRAM_EF_CL1_CUST_TAS_FEATURE_SIZE,
468 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
469 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
470 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
471 "CL0H",
472 VER(NVRAM_EF_CL1_CUST_TAS_FEATURE_LID)
473 },
474#ifdef __MD93__
475 {
476 NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_LID,
477 NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_TOTAL,
478 NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_SIZE,
479 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
480 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
481 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
482 "CL0I",
483 VER(NVRAM_EF_CL1_CUST_TAS_FE_ROUTE_DATABASE_LID)
484 },
485
486 {
487 NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_LID,
488 NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_TOTAL,
489 NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_SIZE,
490 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
491 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
492 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
493 "CL0J",
494 VER(NVRAM_EF_CL1_CUST_TAS_FE_CAT_A_LID)
495 },
496
497 {
498 NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_LID,
499 NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_TOTAL,
500 NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_SIZE,
501 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
502 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
503 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
504 "CL0K",
505 VER(NVRAM_EF_CL1_CUST_TAS_FE_CAT_B_LID)
506 },
507
508 {
509 NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_LID,
510 NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_TOTAL,
511 NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_SIZE,
512 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
513 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
514 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
515 "CL0L",
516 VER(NVRAM_EF_CL1_CUST_TAS_FE_CAT_C_LID)
517 },
518
519 {
520 NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_LID,
521 NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_TOTAL,
522 NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_SIZE,
523 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
524 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
525 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
526 "CL0M",
527 VER(NVRAM_EF_CL1_CUST_TUNER_FE_ROUTE_TABLE_LID)
528 },
529
530 {
531 NVRAM_EF_CL1_CUST_TUNER_LID,
532 NVRAM_EF_CL1_CUST_TUNER_TOTAL,
533 NVRAM_EF_CL1_CUST_TUNER_SIZE,
534 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
535 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
536 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
537 "CL0N",
538 VER(NVRAM_EF_CL1_CUST_TUNER_LID)
539 },
540
541 {
542 NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_LID,
543 NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_TOTAL,
544 NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_SIZE,
545 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
546 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
547 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
548 "CL0O",
549 VER(NVRAM_EF_CL1_CUST_TUNER_ROUTE_EVENT_LID)
550 },
551
552 {
553 NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_LID,
554 NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_TOTAL,
555 NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_SIZE,
556 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
557 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
558 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
559 "CL0P",
560 VER(NVRAM_EF_CL1_CUST_TUNER_ROUTE_DATA_LID)
561 },
562
563 {
564 NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_LID,
565 NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_TOTAL,
566 NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_SIZE,
567 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
568 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
569 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
570 "CL0Q",
571 VER(NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_A_LID)
572 },
573
574 {
575 NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_LID,
576 NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_TOTAL,
577 NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_SIZE,
578 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
579 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
580 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
581 "CL0R",
582 VER(NVRAM_EF_CL1_CUST_TAS_DATA_CAT_A_LID)
583 },
584
585 {
586 NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_LID,
587 NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_TOTAL,
588 NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_SIZE,
589 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
590 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
591 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
592 "CL0S",
593 VER(NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_B_LID)
594 },
595
596 {
597 NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_LID,
598 NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_TOTAL,
599 NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_SIZE,
600 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
601 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
602 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
603 "CL0T",
604 VER(NVRAM_EF_CL1_CUST_TAS_DATA_CAT_B_LID)
605 },
606
607 {
608 NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_LID,
609 NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_TOTAL,
610 NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_SIZE,
611 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
612 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
613 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
614 "CL0U",
615 VER(NVRAM_EF_CL1_CUST_TAS_EVENT_CAT_C_LID)
616 },
617
618 {
619 NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_LID,
620 NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_TOTAL,
621 NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_SIZE,
622 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
623 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
624 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
625 "CL0V",
626 VER(NVRAM_EF_CL1_CUST_TAS_DATA_CAT_C_LID)
627 },
628 #endif
629 {
630 NVRAM_EF_CL1_CUST_ELNA_CFG_LID,
631 NVRAM_EF_CL1_CUST_ELNA_CFG_TOTAL,
632 NVRAM_EF_CL1_CUST_ELNA_CFG_SIZE,
633 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
634 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
635 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
636 "CL0X",
637 VER(NVRAM_EF_CL1_CUST_ELNA_CFG_LID)
638 },
639
640 {
641 NVRAM_EF_CL1_TX_POWER_BACK_OFF_LID,
642 NVRAM_EF_CL1_TX_POWER_BACK_OFF_TOTAL,
643 NVRAM_EF_CL1_TX_POWER_BACK_OFF_SIZE,
644 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
645 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
646 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
647 "CL10",
648 VER(NVRAM_EF_CL1_TX_POWER_BACK_OFF_LID)
649 },
650#if defined(__TX_POWER_OFFSET_SUPPORT__)
651 {
652 NVRAM_EF_CL1_TX_POWER_OFFSET_LID,
653 NVRAM_EF_CL1_TX_POWER_OFFSET_TOTAL,
654 NVRAM_EF_CL1_TX_POWER_OFFSET_SIZE,
655 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
656 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
657 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
658 "CL11",
659 VER(NVRAM_EF_CL1_TX_POWER_OFFSET_LID)
660 },
661#endif
662 {
663 NVRAM_EF_CL1_TAS_TST_CONFIG_LID,
664 NVRAM_EF_CL1_TAS_TST_CFG_TOTAL,
665 NVRAM_EF_CL1_TAS_TST_CONFIG_SZIE,
666 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
667 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
668 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
669 "CL12",
670 VER(NVRAM_EF_CL1_TAS_TST_CONFIG_LID)
671 },
672#if IS_C2K_DAT_RFD_CTRL_EN
673 {
674 NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_LID,
675 NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_TOTAL,
676 NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_SIZE,
677 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
678 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
679 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
680 "CL13",
681 VER(NVRAM_EF_CL1_DAT_FE_ROUTE_DATABASE_LID)
682 },
683 {
684 NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_LID,
685 NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_TOTAL,
686 NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_SIZE,
687 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
688 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
689 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
690 "CL14",
691 VER(NVRAM_EF_CL1_DAT_FE_CAT_A_DATABASE_LID)
692 },
693 {
694 NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_LID,
695 NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_TOTAL,
696 NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_SIZE,
697 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
698 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
699 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
700 "CL15",
701 VER(NVRAM_EF_CL1_DAT_FE_CAT_B_DATABASE_LID)
702 },
703 {
704 NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_LID,
705 NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_TOTAL,
706 NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_SIZE,
707 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
708 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
709 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
710 "CL16",
711 VER(NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_A_LID)
712 },
713 {
714 NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_LID,
715 NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_TOTAL,
716 NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_SIZE,
717 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
718 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
719 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
720 "CL17",
721 VER(NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_A_LID)
722 },
723 {
724 NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_LID,
725 NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_TOTAL,
726 NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_SIZE,
727 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
728 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
729 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
730 "CL18",
731 VER(NVRAM_EF_CL1_DAT_MIPI_EVENT_CAT_B_LID)
732 },
733 {
734 NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_LID,
735 NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_TOTAL,
736 NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_SIZE,
737 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
738 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
739 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
740 "CL19",
741 VER(NVRAM_EF_CL1_DAT_MIPI_DATA_CAT_B_LID)
742 },
743#endif
744#if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__)
745 {
746 NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_LID,
747 NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_TOTAL,
748 NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_SIZE,
749 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
750 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
751 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
752 "CL1A",
753 VER(NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_LID)
754 },
755#endif
756 {
757 NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_LID,
758 NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_TOTAL,
759 NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_SIZE,
760 NVRAM_NORMAL(&cl1TxPwrOffset),
761 NVRAM_CATEGORY_USER,
762 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
763 "CL1F",
764 VER(NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_LID)
765 },
766 {
767 NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_1XRTT_LID,
768 NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_1XRTT_TOTAL,
769 NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_1XRTT_SIZE,
770 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
771 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
772 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
773 "CL1B",
774 VER(NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_1XRTT_LID)
775 },
776
777 {
778 NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_EVDO_LID,
779 NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_EVDO_TOTAL,
780 NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_EVDO_SIZE,
781 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
782 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
783 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
784 "CL1C",
785 VER(NVRAM_EF_CL1_MIPI_PA_SECTION_DPD_DATA_EVDO_LID)
786 },
787 {
788 NVRAM_EF_CL1_DPD_COMMON_CTRL_LID,
789 NVRAM_EF_CL1_DPD_COMMON_CTRL_TOTAL,
790 NVRAM_EF_CL1_DPD_COMMON_CTRL_SIZE,
791 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
792 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
793 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT,
794 "CL1D",
795 VER(NVRAM_EF_CL1_DPD_COMMON_CTRL_LID)
796 },
797 {
798 NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_LID,
799 NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_TOTAL,
800 NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_SIZE,
801 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
802 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
803 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
804 "CL1E",
805 VER(NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_LID)
806 },
807#ifdef __MD95__
808 {
809 NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_LID,
810 NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_TOTAL,
811 NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_SIZE,
812 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
813 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
814 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
815 "CL1G",
816 VER(NVRAM_EF_CL1_CUST_ANT_FE_ROUTE_DATABASE_LID)
817 },
818 {
819 NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_LID,
820 NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_TOTAL,
821 NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_SIZE,
822 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
823 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
824 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
825 "CL1H",
826 VER(NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_LID)
827 },
828#endif
829#if IS_C2K_UDAT_SUPPORT
830 {
831 NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_LID,
832 NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_TOTAL,
833 NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_SIZE,
834 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
835 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
836 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
837 "CL1J",
838 VER(NVRAM_EF_CL1_CUST_DAT_ANT_TUNER_ROUTE_DATABASE_LID)
839 },
840#endif
841
842 NVRAM_LTABLE_END
843};
844#endif
845
846#if (defined(__MD97__) || defined(__MD97P__))
847ltable_entry_struct logical_data_item_table_cl1[] =
848{
849 {
850 NVRAM_EF_CL1_CUST_PARAM_LID,
851 NVRAM_EF_CL1_CUST_PARAM_TOTAL,
852 NVRAM_EF_CL1_CUST_PARAM_SIZE,
853 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
854 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
855 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MCF_OTA,
856 "CL00",
857 VER(NVRAM_EF_CL1_CUST_PARAM_LID)
858 },
859 {
860 NVRAM_EF_CL1_TX_POWER_BACK_OFF_LID,
861 NVRAM_EF_CL1_TX_POWER_BACK_OFF_TOTAL,
862 NVRAM_EF_CL1_TX_POWER_BACK_OFF_SIZE,
863 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
864 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
865 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT | NVRAM_ATTR_MCF_OTA,
866 "CL10",
867 VER(NVRAM_EF_CL1_TX_POWER_BACK_OFF_LID)
868 },
869#if defined(__TX_POWER_OFFSET_SUPPORT__)
870 {
871 NVRAM_EF_CL1_TX_POWER_OFFSET_LID,
872 NVRAM_EF_CL1_TX_POWER_OFFSET_TOTAL,
873 NVRAM_EF_CL1_TX_POWER_OFFSET_SIZE,
874 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
875 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
876 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT | NVRAM_ATTR_MCF_OTA,
877 "CL11",
878 VER(NVRAM_EF_CL1_TX_POWER_OFFSET_LID)
879 },
880#endif
881#if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__)
882 {
883 NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_LID,
884 NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_TOTAL,
885 NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_SIZE,
886 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
887 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
888 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT | NVRAM_ATTR_MCF_OTA,
889 "CL1A",
890 VER(NVRAM_EF_CL1_SAR_TX_POWER_OFFSET_LID)
891 },
892#endif
893 {
894 NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_LID,
895 NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_TOTAL,
896 NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_SIZE,
897 NVRAM_NORMAL(&cl1TxPwrOffset),
898 NVRAM_CATEGORY_USER,
899 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MCF_OTA,
900 "CL1F",
901 VER(NVRAM_EF_CL1_L1D_TX_POWER_OFFSET_LID)
902 },
903
904 {
905 NVRAM_EF_CL1_DPD_COMMON_CTRL_LID,
906 NVRAM_EF_CL1_DPD_COMMON_CTRL_TOTAL,
907 NVRAM_EF_CL1_DPD_COMMON_CTRL_SIZE,
908 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
909 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
910 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MULTI_DEFAULT | NVRAM_ATTR_MCF_OTA,
911 "CL1D",
912 VER(NVRAM_EF_CL1_DPD_COMMON_CTRL_LID)
913 },
914 {
915 NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_LID,
916 NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_TOTAL,
917 NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_SIZE,
918 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
919 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
920 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MCF_OTA,
921 "CL1E",
922 VER(NVRAM_EF_CL1_PCFE_DPD_OTFC_CUSTOM_PARA_LID)
923 },
924#if _C2K_UTAS_SUPPORT_97
925 {
926 NVRAM_EF_CL1_CUST_TAS_FEATURE_LID,
927 NVRAM_EF_CL1_CUST_TAS_FEATURE_TOTAL,
928 NVRAM_EF_CL1_CUST_TAS_FEATURE_SIZE,
929 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
930 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
931 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MCF_OTA,
932 "CL0H",
933 VER(NVRAM_EF_CL1_CUST_TAS_FEATURE_LID)
934 },
935
936 {
937 NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_LID,
938 NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_TOTAL,
939 NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_SIZE,
940 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
941 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
942 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MCF_OTA,
943 "CL1H",
944 VER(NVRAM_EF_CL1_CUST_UTAS_ALGORITHM_PARAMETER_LID)
945 },
946#endif
947
948#if IS_C2K_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
949 {
950 NVRAM_EF_CL1_CUST_RF_HOPPING_LID,
951 NVRAM_EF_CL1_CUST_RF_HOPPING_DATABASE_TOTAL,
952 NVRAM_EF_CL1_CUST_RF_HOPPING_DATABASE_SIZE,
953 NVRAM_DEFAULT_FUNC(nvram_get_cl1_default_value_to_write),
954 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
955 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT | NVRAM_ATTR_MCF_OTA,
956 "CL1K",
957 VER(NVRAM_EF_CL1_CUST_RF_HOPPING_LID)
958 },
959#endif
960
961 NVRAM_LTABLE_END
962};
963#endif
964
965#else /* (__C2K_RAT__) || (__CL1_TASK_ENABLE__) */
966
967#include "nvram_enums.h"
968#include "nvram_defs.h"
969
970ltable_entry_struct logical_data_item_table_cl1[] =
971{
972 NVRAM_LTABLE_END
973};
974#endif /* (__C2K_RAT__) || (__CL1_TASK_ENABLE__) */
975
976#endif /* NVRAM_NOT_PRESENT */