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192.168.1.100 / T800_MD / e372c32e037a8a05d47715a834fa5b827c6540d1 / . / mcu / custom / service / nvram / nrrc_nvram_def.c
blob: c7451195fc7eb19483cf05bbdfbddb56d7c7dcc6 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
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34*****************************************************************************/
35#ifndef NVRAM_NOT_PRESENT
36
37#ifdef __NR_RAT__
38#include "kal_general_types.h"
39#ifdef NVRAM_AUTO_GEN
40#include "nvram_auto_gen.h"
41#endif /* NVRAM_AUTO_GEN */
42
43#include "nvram_enums.h"
44#include "nvram_defs.h"
45
46// LID Group Definition
47#include "nrrc_nvram_def.h"
48#include "nrrc_nvram_editor.h"
49
50/********************************************
51 * MACROS *
52 ********************************************/
53
54
55/********************************************
56 * TYPE DEFINITIONS & ENUMS *
57 ********************************************/
58
59
60/********************************************
61 * VARIABLES *
62 ********************************************/
63
64// Default Values
65
66nvram_ef_nr_cap_struct const NVRAM_EF_NR_CAP_DEFAULT[] =
67{
68 {
69 0xF0, //nea_support
70 0xF0, //nia_support
71 0x00, //nras_power_class
72#ifdef __ENDC__
73 0x01 //endc_support
74#else
75 0x00 //endc_support
76#endif
77 }
78};
79
80nvram_ef_ue_nr_cap_struct const NVRAM_EF_UE_NR_CAP_DEFAULT[] =
81{
82 {
83 { //mrdc_cap
84 { //general_params
85#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
86 { //common
87 0x01, //split_srb_with_one_ul_path
88 0x01, //split_drb_with_ul_both_mcg_scg
89 0x01, //srb3
90 },
91 { //fdd
92 0x00 //v2x_eutra
93 },
94 { //tdd
95 0x00 //v2x_eutra
96 }
97#else /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
98 { //fdd
99 0x01, //split_srb_with_one_ul_path
100 0x01, //split_drb_with_ul_both_mcg_scg
101 0x01, //srb3
102 0x00 //v2x_eutra_v1530
103 },
104 { //tdd
105 0x01, //split_srb_with_one_ul_path
106 0x01, //split_drb_with_ul_both_mcg_scg
107 0x01, //srb3
108 0x00 //v2x_eutra_v1530
109 }
110#endif /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
111 },
112 { //pdcp_params
113 0x01, //pdcp_duplication_split_srb
114 0x01 //pdcp_duplication_split_drb
115 }
116 },
117 { // nr_cap
118 { //pdcp_params
119 { //rohc_profiles
120 0x01, //profile_0x0001
121 0x01, //profile_0x0002
122 0x00, //profile_0x0003
123 0x01, //profile_0x0004
124 0x00, //profile_0x0006
125 0x00, //profile_0x0101
126 0x00, //profile_0x0102
127 0x00, //profile_0x0103
128 0x00 //profile_0x0104
129 },
130 16, //max_number_rohc_context_sessions
131 0x00, //uplink_only_rohc_profiles
132 0x00, //continue_rohc_context
133 0x01, //out_of_order_delivery
134 0x01, //short_sn
135 0x01, //pdcp_duplication_srb
136 0x01 //pdcp_duplication_mcg_or_scg_drb
137 },
138 { //rlc_params
139 0x01, //am_with_short_sn
140 0x01, //um_with_short_sn
141 0x01 //um_with_long_sn
142 },
143 { //mac_params
144 { //common
145 0x00, //lcp_restriction
146 0x00, //lch_to_scell_restriction
147 0x00, //recommended_bit_rate
148 0x00 //recommended_bit_rate_query
149 },
150 { //fdd
151 0x00, //skip_uplink_tx_dynamic
152 0x01, //logical_channel_sr_delay_timer
153 0x01, //long_drx_cycle
154 0x01, //short_drx_cycle
155 0x00, //multiple_sr_configurations
156 0x00 //multiple_configured_grants
157 },
158 { //tdd
159 0x00, //skip_uplink_tx_dynamic
160 0x01, //logical_channel_sr_delay_timer
161 0x01, //long_drx_cycle
162 0x01, //short_drx_cycle
163 0x00, //multiple_sr_configurations
164 0x00 //multiple_configured_grant_configurations
165 }
166 },
167 { //meas_params
168 { //common
169 0x01, //handover_fdd_tdd
170 0x01, //eutra_cgi_reporting
171 0x01 //nr_cgi_reporting
172#if (CUR_MD_SPEC >= MD_SPEC_2019MAR)
173 ,0x01 //nr_cgi_reporting_endc
174#endif /* (CUR_MD_SPEC >= MD_SPEC_2019MAR) */
175 },
176 { //fdd
177 0x01, //handover_inter_f
178#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
179 0x01, //handover_lte_epc
180 0x00 //handover_lte_5gc
181#else /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
182 0x01, //handover_lte
183 0x00 //handover_elte
184#endif /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
185 },
186 { //tdd
187 0x01, //handover_inter_f
188#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
189 0x01, //handover_lte_epc
190 0x00 //handover_lte_5gc
191#else /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
192 0x01, //handover_lte
193 0x00 //handover_elte
194#endif /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
195 },
196 { //fr1
197 0x01, //handover_inter_f
198#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
199 0x01, //handover_lte_epc
200 0x00 //handover_lte_5gc
201#else /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
202 0x01, //handover_lte
203 0x00 //handover_elte
204#endif /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
205 },
206 { //fr2
207 0x01, //handover_inter_f
208#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
209 0x01, //handover_lte_epc
210 0x00 //handover_lte_5gc
211#else /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
212 0x01, //handover_lte
213 0x00 //handover_elte
214#endif /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
215 }
216 },
217 { //ue_nr_capability_v1530
218 { //inter_rat_params
219 { // eutra
220 { //common
221 0x01, //mfbi_eutra
222 0x01, //multi_ns_pmax_eutra
223#ifdef __RS_SINR_MEAS_CAP__
224 0x01 //rs_sinr_meas_eutra
225#else /* __RS_SINR_MEAS_CAP__ */
226 0x00 //rs_sinr_meas_eutra
227#endif /* __RS_SINR_MEAS_CAP__ */
228 },
229 { //fdd
230 0x01 //rsrq_meas_wideband_eutra
231 },
232 { //tdd
233 0x01 //rsrq_meas_wideband_eutra
234 }
235 }
236 },
237 0x01, //inactive_state
238 },
239 { //ue_nr_capability_v1540
rjw2b1408e2022-12-19 11:19:29 +0800[diff] [blame]240 { //sdap_params, the IE is changed to SBP configuration. To be removed.
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]241 0x01 //as_reflective_qos
242 },
243 { //ims_params
244 { //common
245 0x00 //voice_over_eutra_5gc
246 }
247 },
248 }
249#if (CUR_MD_SPEC >= MD_SPEC_2019MAR)
250 ,
251 { //ue_nr_capability_v1550
252 0x00 //reduced_cp_latency
253 }
254#endif /* (CUR_MD_SPEC >= MD_SPEC_2019MAR) */
255 },
256 0x00 // background_search_status_in_test_mode
257 }
258};
259
260nvram_ef_nrrc_common_config_struct const NVRAM_EF_NRRC_COMMON_CONFIG_DEFAULT[] =
261{
262 {
263 { //smart_idle
264 0x3C, //inactivity_timer_length
265 0x12C, //inactivity_timer_length_drx
266 0x00, //fake_a2_report_sending_allowed
267 0x3E8 //mru_oos_detection_timer_length
268 },
269 { //plmn_band_info
270 { // plmn_band_list
271 { // Record 1
272 {0x04, 0x06, 0x00, 0x00, 0x00, 0x0f}, // CMCC
273 { 3, 39, 40, 0, 0, 0, 0, 0, 0, 0}, // LTE bands
274 {41, 78, 79, 0, 0, 0, 0, 0, 0, 0} // NR bands
275 },
276 { // Record 2
277 {0x04, 0x06, 0x00, 0x00, 0x03, 0x0f}, // CT
278 { 1, 3, 5, 8, 39, 40, 0, 0, 0, 0}, // LTE bands
279 { 1, 3, 5, 41, 78, 79, 0, 0, 0, 0} // NR bands
280 },
281 { // Record 3
282 {0x04, 0x06, 0x00, 0x00, 0x01, 0x0f}, // CU
283 { 1, 3, 5, 8, 39, 40, 0, 0, 0, 0}, // LTE bands
284 { 1, 3, 8, 41, 78, 0, 0, 0, 0, 0} // NR bands
285 },
286 { // Record 4
287 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // unused
288 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // LTE bands
289 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} // NR bands
290 },
291 { // Record 5
292 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // unused
293 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // LTE bands
294 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} // NR bands
295 }
296 }
297 },
298 { //performance
299 { //est_th
300 0x0005, //srxlev
301 0x0003 //squal
302 }
303 },
304 {//meas_nl1mob_performance
305 { //l4c_cus_bar_th
306 0xFE28, //rsrp_th = -472 qdbm (-118dbm)
307 0xFFD0 //rsrq_th = -48 qdb
308 },
309 { //cus_qrxlevmin_adj
310 0x00, //qrxlevmin_relax, defult 0 to NOT relax rxlevemin
311 0xFFF1, //rsrq_th = -15 db
312 0xFFC7, //qrxlevmin_good = -57 (sib1 ie value; -114dbm = -456qdbm)
313 0xFFCC //qrxlevmin_bad = -52 (sib1 ie value; -104dbm = -416qdbm)
314 },
315 { //A3A4A5_ignore_th
316 0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM, 0x20: A3 enable, 0x40: A4 enable, 0x80: A5 enable
317 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
318 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
319 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
320 0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
321 0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
322 0x8000 //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
323 },
324 { //A3A4A5_force_th
325 0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM, 0x20: A3 enable, 0x40: A4 enable, 0x80: A5 enable
326 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
327 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
328 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
329 0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
330 0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
331 0x8000 //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
332 },
333 { //lte_B1_B2_ignore_th
334 0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM, 0x40: B1 enable, 0x80: B2 enable
335 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
336 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
337 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
338 0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
339 0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
340 0x8000 //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
341 },
342 { //lte_B1_B2_ignore_th_serv_per_band_list
343 {
344 {
345 //per_band_threshold[0]
346 0x0000, //band, range: 1~65535, disable: 0x0000
347 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
348 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
349 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
350 },
351 {
352 //per_band_threshold[1]
353 0x0000, //band, range: 1~65535, disable: 0x0000
354 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
355 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
356 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
357 },
358 {
359 //per_band_threshold[2]
360 0x0000, //band, range: 1~65535, disable: 0x0000
361 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
362 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
363 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
364 },
365 {
366 //per_band_threshold[3]
367 0x0000, //band, range: 1~65535, disable: 0x0000
368 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
369 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
370 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
371 },
372 {
373 //per_band_threshold[4]
374 0x0000, //band, range: 1~65535, disable: 0x0000
375 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
376 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
377 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
378 },
379 {
380 //per_band_threshold[5]
381 0x0000, //band, range: 1~65535, disable: 0x0000
382 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
383 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
384 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
385 },
386 {
387 //per_band_threshold[6]
388 0x0000, //band, range: 1~65535, disable: 0x0000
389 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
390 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
391 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
392 },
393 {
394 //per_band_threshold[7]
395 0x0000, //band, range: 1~65535, disable: 0x0000
396 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
397 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
398 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
399 },
400 {
401 //per_band_threshold[8]
402 0x0000, //band, range: 1~65535, disable: 0x0000
403 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
404 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
405 0x8000 //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
406 }
407 }
408 },
409 { //lte_B1_B2_force_th
410 0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM, 0x40: B1 enable, 0x80: B2 enable
411 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
412 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
413 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
414 0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
415 0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
416 0x8000 //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
417 },
rjw2b1408e2022-12-19 11:19:29 +0800[diff] [blame]418 { //lte_B1_B2_force_th_vonr
419 0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM, 0x40: B1 enable, 0x80: B2 enable
420 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
421 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
422 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
423 0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
424 0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
425 0x8000 //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
426 },
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]427 { //lte_B1_B2_force_th_serv_per_band_list
428 {
429 {
430 //per_band_threshold[0]
431 0x0000, //band, range: 1~65535, disable: 0x0000
432 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
433 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
434 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
435 },
436 {
437 //per_band_threshold[1]
438 0x0000, //band, range: 1~65535, disable: 0x0000
439 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
440 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
441 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
442 },
443 {
444 //per_band_threshold[2]
445 0x0000, //band, range: 1~65535, disable: 0x0000
446 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
447 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
448 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
449 },
450 {
451 //per_band_threshold[3]
452 0x0000, //band, range: 1~65535, disable: 0x0000
453 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
454 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
455 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
456 },
457 {
458 //per_band_threshold[4]
459 0x0000, //band, range: 1~65535, disable: 0x0000
460 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
461 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
462 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
463 },
464 {
465 //per_band_threshold[5]
466 0x0000, //band, range: 1~65535, disable: 0x0000
467 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
468 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
469 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
470 },
471 {
472 //per_band_threshold[6]
473 0x0000, //band, range: 1~65535, disable: 0x0000
474 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
475 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
476 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
477 },
478 {
479 //per_band_threshold[7]
480 0x0000, //band, range: 1~65535, disable: 0x0000
481 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
482 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
483 0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
484 },
485 {
486 //per_band_threshold[8]
487 0x0000, //band, range: 1~65535, disable: 0x0000
488 0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
489 0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
490 0x8000 //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
491 }
492 }
493 },
494 { //nr_to_lte_resel_ignore_th
495 0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM
496 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
497 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
498 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
499 0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
500 0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
501 0x8000 //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
502 },
503 { //nr_to_lte_resel_force_th
504 0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM
505 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
506 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
507 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
508 0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
509 0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
510 0x8000 //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
511 },
512 0x0000, // custom_enh_ind_update_period, unit: s , range: 3~65535, 0x0000: disable update
513 { //ping_pong_parameter
514 0xFF, //ctrl_bmp, 0x01: enable pingpong_bar, 0x02: disable on test SIM
515 0x12c, //ping-pong cell bar time(300s), range: 60~600, disable: 0x8000
516 0x14, //ping-pong cell monitor period(20s), range: 10~30 , disable: 0x8000
517 0x02, //ping-pong hit count threshold, range: 2~5 , disable: 0x80
518 },
rjw2b1408e2022-12-19 11:19:29 +0800[diff] [blame]519 { //nr_irat_ping_pong_parameter
520 0xFF, //ctrl_bmp, 0x01: enable nr irat pingpong_bar, 0x02: disable on test SIM
521 0x12c, //irat ping-pong cell bar time(300s), range: 60~600, disable: 0x8000
522 0x3C, //irat ping-pong cell monitor period(60s), range: 30~180, disable: 0x8000
523 0x02, //irat ping-pong hit count threshold, range: 2~5 , disable: 0x80
524 },
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]525 { //a2_adjust_th
526 0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable good_a2_rsrp_th, 0x04: enable bad_a2_rsrp_th, 0x08: disable on test SIM
527 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
528 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
529 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
530 0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
531 0x8000 //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
532 },
rjw2b1408e2022-12-19 11:19:29 +0800[diff] [blame]533 { //a2_adjust_th_vonr
534 0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable good_a2_rsrp_th, 0x04: enable bad_a2_rsrp_th, 0x08: disable on test SIM
535 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
536 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
537 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
538 0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
539 0x8000 //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
540 },
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]541 { //a2_adjust_th_per_band_list
542 {
543 {
544 //per_band_threshold[0]
545 0x0000, //band, range: 1~65535, disable: 0x0000
546 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
547 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
548 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
549 0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
550 0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
551 },
552 {
553 //per_band_threshold[1]
554 0x0000, //band, range: 1~65535, disable: 0x0000
555 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
556 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
557 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
558 0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
559 0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
560 },
561 {
562 //per_band_threshold[2]
563 0x0000, //band, range: 1~65535, disable: 0x0000
564 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
565 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
566 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
567 0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
568 0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
569 },
570 {
571 //per_band_threshold[3]
572 0x0000, //band, range: 1~65535, disable: 0x0000
573 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
574 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
575 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
576 0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
577 0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
578 },
579 {
580 //per_band_threshold[4]
581 0x0000, //band, range: 1~65535, disable: 0x0000
582 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
583 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
584 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
585 0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
586 0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
587 },
588 {
589 //per_band_threshold[5]
590 0x0000, //band, range: 1~65535, disable: 0x0000
591 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
592 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
593 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
594 0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
595 0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
596 },
597 {
598 //per_band_threshold[6]
599 0x0000, //band, range: 1~65535, disable: 0x0000
600 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
601 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
602 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
603 0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
604 0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
605 },
606 {
607 //per_band_threshold[7]
608 0x0000, //band, range: 1~65535, disable: 0x0000
609 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
610 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
611 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
612 0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
613 0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
614 },
615 {
616 //per_band_threshold[8]
617 0x0000, //band, range: 1~65535, disable: 0x0000
618 0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
619 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
620 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
621 0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
622 0x8000 //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
623 }
624 }
625 },
626 { //cus_poor_sinr_th
627 0xFFD8, //sinr_th = -40 qdb
628 0x3C, //timer_th = 60 seconds
629 0x08 //sinr_hys = 8 qdb
630 },
631 { //A3A4A5_prefer_cell
632 0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable th_for_offset, 0x04: enable th_for_ignore_rpt, 0x08: disable on test SIM, 0x20: A3 enable, 0x40: A4 enable, 0x80: A5 enable
633 0xFF, //rpt_rsrp_offset, unit: qdBm, range: 0~40, disable: 0xFF
634 0x8000, //rsrp_th_for_offset, unit: qdBm, range: -640~-120, disable: 0x8000
635 0x8000, //rsrq_th_for_offset, unit: qdB , range: -180~80, disable: 0x8000
636 0x8000, //sinr_th_for_offset, unit: qdB , range: -100~160, disable: 0x8000
637 0x8000, //rsrp_th_for_ignore_rpt, unit: qdBm, range: -640~-120, disable: 0x8000
638 0x8000, //rsrq_th_for_ignore_rpt, unit: qdB , range: -180~80, disable: 0x8000
639 0x8000 //sinr_th_for_ignore_rpt, unit: qdB , range: -100~160, disable: 0x8000
rjw8e44aab2022-11-30 16:42:16 +0800[diff] [blame]640 },
641 { //postpone_a2_for_b1b2
642 0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable a2_rsrp_th, 0x04: enable a2_rsrq_th, 0x08: disable on test SIM
643 0x4B0, //timer_postpone_a2, unit: ms, default: 1200ms, disable: 0
644 0xFE20, //srv_rsrp_th, unit: qdBm, range: -640~-120, default: -480, disable: 0x8000
645 0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
646 0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
rjw2b1408e2022-12-19 11:19:29 +0800[diff] [blame]647 },
648 { //nr_lte_prefer_rat_rsrp_th
649 0xFF, //ctrl_bmp, 0x01: enable nr_lte_prefer_rat_rsrp_th, 0x02: disable on test SIM
650 0x8000, //nr_good_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
651 0x8000, //nr_bad_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
652 0x8000, //lte_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
653 },
654 0xFE34 //game_nbr_bad_rsrp_th, unit: qdBm, range: -640~-120, default: -460, disable: 0x8000
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]655 },
656 { //scg_bar_info
657 0x05, //scg_bar_th
658 0x1e, //scg_bar_time (30second)
659 0x0a //bad_cell_watch_period (10 second)
660 },
661 { //ampr_mcc_list
662 {0x03, 0x01, 0x00, 0xff, 0xff, 0xff}, // plmnid0: 310 xxx
663 {0x03, 0x01, 0x01, 0xff, 0xff, 0xff}, // plmnid1: 311 xxx
664 {0x03, 0x01, 0x02, 0xff, 0xff, 0xff}, // plmnid2: 312 xxx
665 {0x03, 0x01, 0x03, 0xff, 0xff, 0xff}, // plmnid3: 313 xxx
666 {0x03, 0x01, 0x04, 0xff, 0xff, 0xff}, // plmnid4: 314 xxx
667 {0x03, 0x01, 0x05, 0xff, 0xff, 0xff}, // plmnid5: 315 xxx
668 {0x03, 0x01, 0x06, 0xff, 0xff, 0xff}, // plmnid6: 316 xxx
669 {0x03, 0x03, 0x00, 0xff, 0xff, 0xff}, // plmnid7: 330 xxx
670 {0x03, 0x07, 0x06, 0xff, 0xff, 0xff}, // plmnid8: 376 xxx
671 {0x05, 0x04, 0x04, 0xff, 0xff, 0xff}, // plmnid9: 544 xxx
672 {0x03, 0x00, 0x02, 0xff, 0xff, 0xff}, // plmnid10: 302 xxx
673 {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} // plmnid11: xxx xxx
674 },
675 { //Connection establishment failure control parameters.
676 0x04, // Failure count (4)
677 0x1E, // Offset validity (30)
678 0xFF // Offset (infinity)
679 },
680 { //abnormal scenario recovery parameters
681 0x03, // offset counter(3)
682 0x96, // offset bar counter duration(150)
683 0x12c, // offset bar_time(300)
rjw2b1408e2022-12-19 11:19:29 +0800[diff] [blame]684 0x258, // offset monitor duration(600)
685 0x02, // nw_reject_with_long_wait_time_counter (2)
686 0x3C, // nw_reject_with_long_wait_time_monitoring_time (60)
687 0x12c, // nw_reject_with_long_wait_time_bar_time (300)
688 0x10 // nw_reject_with_long_wait_time_threshold (16)
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]689 },
690 { //nrrc_idle_param
691 0x12c, // nr_tacless_bar_cell_timer (default: 300 seconds)
692 { //nrrc_idle_custom_redir_param_info
693 0x0, // offset_penalty (dB)
694 0x0 // offset_time (s)
695 }
696 },
697 { //nrrc_si_param
698 {
699 0x0, // q_rx_lv_min.is_valid
700 0x0, // q_rx_lv_min.custom_val
701 0x0, // q_rx_lv_min.threshold_high
702 0x0 // q_rx_lv_min.threshold_low
703 },
704 {
705 0x0, // q_qual_lv_min.is_valid
706 0x0, // q_qual_lv_min.custom_val
707 0x0, // q_qual_lv_min.threshold_high
708 0x0 // q_qual_lv_min.threshold_low
709 }
710 },
711 {//hst_cell_param
712 0xFE48, //rsrp_th = -440 qdbm
713 0xFFD8, //rsrq_th = -40 qdb
714 0xFFEC //sinr_th = -20 qdb
715 }
716 }
717};
718
719#ifdef __NVM_GLOBAL_CABC__
720/* Record num from 0 to 200 */
721nvram_nr_band_support_plmn_struct const NR_BAND_SUPPORT_PLMN_DEFAULT[] =
722{
723 { // Record 0
724 // enable n3, n28, n41, n77 and n78 for KDDI
725 {0x04, 0x04, 0x00, 0x05, 0x00, 0x0f}, // plmn_id
726 // band_support_for_sa
727 {0x04, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
728 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
729 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
730 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
731 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
732 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
733 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
734 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
735 // band_support_for_endc
736 {0x04, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
737 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
738 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
739 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
740 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
741 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
742 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
743 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
744 },
745 { // Record 1
746 // enable n3, n28, n41, n77 and n78 for KDDI
747 {0x04, 0x04, 0x00, 0x05, 0x01, 0x0f}, // plmn_id
748 // band_support_for_sa
749 {0x04, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
750 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
751 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
752 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
753 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
754 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
755 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
756 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
757 // band_support_for_endc
758 {0x04, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
759 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
760 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
761 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
762 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
763 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
764 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
765 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
766 },
767 { // Record 2
768 // enable n3, n28, n41, n77 and n78 for KDDI
769 {0x04, 0x04, 0x00, 0x05, 0x04, 0x0f}, // plmn_id
770 // band_support_for_sa
771 {0x04, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
772 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
773 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
774 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
775 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
776 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
777 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
778 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
779 // band_support_for_endc
780 {0x04, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
781 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
782 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
783 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
784 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
785 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
786 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
787 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
yu.donge372c322023-08-30 20:25:04 -0700[diff] [blame^]788 },
789 { // Record 3
790 // Softbank has only following bands. NR: n3, n28, n77
791 {0x04, 0x04, 0x00, 0x00, 0x00, 0x0f}, // plmn_id
792 // band_support_for_sa
793 {0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
794 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
795 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
796 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
797 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
798 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
799 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
800 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
801 // band_support_for_endc
802 {0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
803 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
804 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
805 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
806 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
807 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
808 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
809 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
810 },
811 { // Record 4
812 // Softbank has only following bands. NR: n3, n28, n77
813 {0x04, 0x04, 0x00, 0x02, 0x00, 0x0f}, // plmn_id
814 // band_support_for_sa
815 {0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
816 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
817 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
818 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
819 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
820 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
821 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
822 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
823 // band_support_for_endc
824 {0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
825 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
826 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
827 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
828 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
829 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
830 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
831 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
832 },
833 { // Record 5
834 // Softbank has only following bands. NR: n3, n28, n77
835 {0x04, 0x04, 0x01, 0x09, 0x00, 0x0f}, // plmn_id
836 // band_support_for_sa
837 {0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
838 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
839 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
840 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
841 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
842 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
843 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
844 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
845 // band_support_for_endc
846 {0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
847 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
848 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
849 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
850 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
851 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
852 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
853 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
854 },
855 { // Record 6
856 // enable n78, n79, and n257 for SA under DoCoMo
857 {0x04, 0x04, 0x00, 0x01, 0x00, 0x0f}, // plmn_id
858 // band_support_for_sa
859 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
860 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
861 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
862 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
863 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
864 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
865 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
866 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
867 // band_support_for_endc (ENDC BC is not restricted)
868 {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
869 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
870 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
871 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
872 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
873 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
874 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
875 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]876 }
877};
878
879void nvram_get_nrrc_default_value_to_write(nvram_lid_enum lid, kal_uint8 *buffer, kal_uint16 buffer_size)
880{
881 nvram_ef_nrrc_band_support_plmn_struct *p_nrrc_band_support_plmn = NULL;
882 nvram_nr_band_support_plmn_struct *p_nvram_nr_band_support_plmn = NULL;
883 const nvram_nr_band_support_plmn_struct *p_default_nr_band_support_plmn = NULL;
884 kal_uint16 plmn_index = 0;
885 kal_uint16 band_index = 0;
886 buffer_size = buffer_size;
887
888 switch (lid)
889 {
890 case NVRAM_EF_NRRC_BAND_SUPPORT_PLMN_LID:
891 p_nrrc_band_support_plmn = (nvram_ef_nrrc_band_support_plmn_struct *)buffer;
892 p_nrrc_band_support_plmn->feature_switch = KAL_TRUE;
893
894 p_nrrc_band_support_plmn->num_of_plmn =
895 sizeof(NR_BAND_SUPPORT_PLMN_DEFAULT)/sizeof(nvram_nr_band_support_plmn_struct);
896
897 for (plmn_index = 0;
898 (plmn_index < p_nrrc_band_support_plmn->num_of_plmn) && (plmn_index < NVRAM_MAX_NR_BAND_SUPPORT_PLMN_NUM);
899 plmn_index++)
900 {
901 p_nvram_nr_band_support_plmn = &(p_nrrc_band_support_plmn->band_support_plmn[plmn_index]);
902 p_default_nr_band_support_plmn = &(NR_BAND_SUPPORT_PLMN_DEFAULT[plmn_index]);
903
904 p_nvram_nr_band_support_plmn->plmn_id.mcc1 = p_default_nr_band_support_plmn->plmn_id.mcc1;
905 p_nvram_nr_band_support_plmn->plmn_id.mcc2 = p_default_nr_band_support_plmn->plmn_id.mcc2;
906 p_nvram_nr_band_support_plmn->plmn_id.mcc3 = p_default_nr_band_support_plmn->plmn_id.mcc3;
907 p_nvram_nr_band_support_plmn->plmn_id.mnc1 = p_default_nr_band_support_plmn->plmn_id.mnc1;
908 p_nvram_nr_band_support_plmn->plmn_id.mnc2 = p_default_nr_band_support_plmn->plmn_id.mnc2;
909 p_nvram_nr_band_support_plmn->plmn_id.mnc3 = p_default_nr_band_support_plmn->plmn_id.mnc3;
910
911 for (band_index = 0; band_index < NVRAM_MAX_BYTE_NR_BAND_BITMASK; band_index++)
912 {
913 p_nvram_nr_band_support_plmn->band_support_for_sa[band_index] =
914 p_default_nr_band_support_plmn->band_support_for_sa[band_index];
915 p_nvram_nr_band_support_plmn->band_support_for_endc[band_index] =
916 p_default_nr_band_support_plmn->band_support_for_endc[band_index];
917 }
918 }
919 break;
920 default:
921 break;
922 }
923}
924#endif /* __NVM_GLOBAL_CABC__ */
925
926nvram_ef_nrrc_custom_endc_comb_list_struct const NVRAM_EF_NRRC_CUSTOM_ENDC_COMB_LIST_DEFAULT[] =
927{
928 {
929 "", /* ENDC: white_list */
930 "", /* ENDC: black_list */
931 "", /* SA: white_list */
932 "" /* SA: black_list */
933 }
934};
935
936nvram_ef_nrrc_nr_feature_ctrl_struct const NVRAM_EF_NRRC_NR_FEATURE_CTRL_DEFAULT[] =
937{
938 {
939 {
940 /* Byte 0 : bit [7..0]
941 * bit 0: AT CMD control CDRX. 1 = enable, 0 = disable. (default: 1)
942 * bit 1: Undefined
943 * bit 2: Undefined
944 * bit 3: Undefined
945 * bit 4: Undefined
946 * bit 5: Undefined
947 * bit 6: Undefined
948 * bit 7: Undefined
949 */
950 0x01,
951 /* Byte 1 : bit [7..0]
952 * bit 0: Undefined
953 * bit 1: Undefined
954 * bit 2: Undefined
955 * bit 3: Undefined
956 * bit 4: Undefined
957 * bit 5: Undefined
958 * bit 6: Undefined
959 * bit 7: Reserved
960 */
961 0x00
962 }
963 }
964};
965
yu.donge372c322023-08-30 20:25:04 -0700[diff] [blame^]966static nvram_ef_nrrc_stored_operator_band_priority_struct const NVRAM_EF_NRRC_STORED_OPERATOR_BAND_PRIORITY_DEFAULT[] =
967{
968 /*operator_num*/
969 0x00,
970#if 0
971/* under construction !*/
972/* under construction !*/
973/* under construction !*/
974/* under construction !*/
975/* under construction !*/
976/* under construction !*/
977/* under construction !*/
978/* under construction !*/
979/* under construction !*/
980/* under construction !*/
981/* under construction !*/
982/* under construction !*/
983/* under construction !*/
984/* under construction !*/
985/* under construction !*/
986/* under construction !*/
987/* under construction !*/
988/* under construction !*/
989/* under construction !*/
990/* under construction !*/
991/* under construction !*/
992/* under construction !*/
993/* under construction !*/
994/* under construction !*/
995/* under construction !*/
996/* under construction !*/
997/* under construction !*/
998/* under construction !*/
999/* under construction !*/
1000/* under construction !*/
1001/* under construction !*/
1002/* under construction !*/
1003/* under construction !*/
1004/* under construction !*/
1005/* under construction !*/
1006/* under construction !*/
1007/* under construction !*/
1008/* under construction !*/
1009/* under construction !*/
1010/* under construction !*/
1011/* under construction !*/
1012/* under construction !*/
1013/* under construction !*/
1014/* under construction !*/
1015/* under construction !*/
1016/* under construction !*/
1017/* under construction !*/
1018/* under construction !*/
1019/* under construction !*/
1020/* under construction !*/
1021/* under construction !*/
1022/* under construction !*/
1023/* under construction !*/
1024/* under construction !*/
1025/* under construction !*/
1026/* under construction !*/
1027/* under construction !*/
1028/* under construction !*/
1029/* under construction !*/
1030/* under construction !*/
1031/* under construction !*/
1032/* under construction !*/
1033/* under construction !*/
1034/* under construction !*/
1035/* under construction !*/
1036/* under construction !*/
1037/* under construction !*/
1038/* under construction !*/
1039/* under construction !*/
1040/* under construction !*/
1041/* under construction !*/
1042/* under construction !*/
1043/* under construction !*/
1044/* under construction !*/
1045/* under construction !*/
1046/* under construction !*/
1047/* under construction !*/
1048/* under construction !*/
1049/* under construction !*/
1050/* under construction !*/
1051/* under construction !*/
1052/* under construction !*/
1053/* under construction !*/
1054/* under construction !*/
1055/* under construction !*/
1056/* under construction !*/
1057/* under construction !*/
1058/* under construction !*/
1059/* under construction !*/
1060/* under construction !*/
1061/* under construction !*/
1062/* under construction !*/
1063/* under construction !*/
1064/* under construction !*/
1065/* under construction !*/
1066/* under construction !*/
1067/* under construction !*/
1068/* under construction !*/
1069/* under construction !*/
1070/* under construction !*/
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4713/* under construction !*/
4714/* under construction !*/
4715/* under construction !*/
4716/* under construction !*/
4717/* under construction !*/
4718/* under construction !*/
4719/* under construction !*/
4720/* under construction !*/
4721/* under construction !*/
4722/* under construction !*/
4723/* under construction !*/
4724/* under construction !*/
4725/* under construction !*/
4726/* under construction !*/
4727/* under construction !*/
4728/* under construction !*/
4729/* under construction !*/
4730/* under construction !*/
4731/* under construction !*/
4732/* under construction !*/
4733/* under construction !*/
4734/* under construction !*/
4735/* under construction !*/
4736/* under construction !*/
4737/* under construction !*/
4738/* under construction !*/
4739/* under construction !*/
4740/* under construction !*/
4741/* under construction !*/
4742/* under construction !*/
4743/* under construction !*/
4744/* under construction !*/
4745/* under construction !*/
4746/* under construction !*/
4747/* under construction !*/
4748/* under construction !*/
4749/* under construction !*/
4750/* under construction !*/
4751/* under construction !*/
4752/* under construction !*/
4753/* under construction !*/
4754/* under construction !*/
4755/* under construction !*/
4756/* under construction !*/
4757/* under construction !*/
4758/* under construction !*/
4759/* under construction !*/
4760/* under construction !*/
4761/* under construction !*/
4762/* under construction !*/
4763/* under construction !*/
4764/* under construction !*/
4765/* under construction !*/
4766/* under construction !*/
4767/* under construction !*/
4768/* under construction !*/
4769/* under construction !*/
4770/* under construction !*/
4771/* under construction !*/
4772/* under construction !*/
4773/* under construction !*/
4774/* under construction !*/
4775/* under construction !*/
4776/* under construction !*/
4777/* under construction !*/
4778/* under construction !*/
4779/* under construction !*/
4780/* under construction !*/
4781/* under construction !*/
4782/* under construction !*/
4783/* under construction !*/
4784/* under construction !*/
4785/* under construction !*/
4786/* under construction !*/
4787/* under construction !*/
4788/* under construction !*/
4789/* under construction !*/
4790/* under construction !*/
4791/* under construction !*/
4792/* under construction !*/
4793/* under construction !*/
4794/* under construction !*/
4795/* under construction !*/
4796/* under construction !*/
4797/* under construction !*/
4798/* under construction !*/
4799/* under construction !*/
4800/* under construction !*/
4801/* under construction !*/
4802/* under construction !*/
4803/* under construction !*/
4804/* under construction !*/
4805/* under construction !*/
4806/* under construction !*/
4807/* under construction !*/
4808/* under construction !*/
4809/* under construction !*/
4810/* under construction !*/
4811/* under construction !*/
4812/* under construction !*/
4813/* under construction !*/
4814/* under construction !*/
4815/* under construction !*/
4816/* under construction !*/
4817/* under construction !*/
4818/* under construction !*/
4819/* under construction !*/
4820/* under construction !*/
4821/* under construction !*/
4822/* under construction !*/
4823/* under construction !*/
4824/* under construction !*/
4825/* under construction !*/
4826/* under construction !*/
4827/* under construction !*/
4828/* under construction !*/
4829/* under construction !*/
4830/* under construction !*/
4831/* under construction !*/
4832/* under construction !*/
4833/* under construction !*/
4834/* under construction !*/
4835/* under construction !*/
4836/* under construction !*/
4837/* under construction !*/
4838#endif
4839};
4840
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]4841
4842// LID Declaration
4843ltable_entry_struct logical_data_item_table_nrrc[] =
4844{
4845 {
4846 NVRAM_EF_UE_NR_CAP_LID,
4847 NVRAM_EF_UE_NR_CAP_TOTAL,
4848 NVRAM_EF_UE_NR_CAP_SIZE,
4849 NVRAM_NORMAL(NVRAM_EF_UE_NR_CAP_DEFAULT),
4850 NVRAM_CATEGORY_USER,
4851 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_MCF_OTA_BY_OP,
4852 "NR01", // The first two characters of LID filename defined in nvram_enums.h
4853 VER(NVRAM_EF_UE_NR_CAP_LID)
4854 },
4855 {
4856 NVRAM_EF_NR_CAP_LID,
4857 NVRAM_EF_NR_CAP_TOTAL,
4858 NVRAM_EF_NR_CAP_SIZE,
4859 NVRAM_NORMAL(NVRAM_EF_NR_CAP_DEFAULT),
4860 NVRAM_CATEGORY_USER,
4861 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_MCF_OTA_BY_OP,
4862 "NR02", // The first two characters of LID filename defined in nvram_enums.h
4863 VER(NVRAM_EF_NR_CAP_LID)
4864 },
4865 {
4866 NVRAM_EF_NR_STORED_INFO_LID,
4867 NVRAM_EF_NR_STORED_INFO_TOTAL,
4868 NVRAM_EF_NR_STORED_INFO_SIZE,
4869 NVRAM_NORMAL(NVRAM_EF_ZERO_DEFAULT),
4870 NVRAM_CATEGORY_USER,
4871 NVRAM_ATTR_OTA_RESET,
4872 "NR03", // The first two characters of LID filename defined in nvram_enums.h
4873 VER(NVRAM_EF_NR_STORED_INFO_LID)
4874 },
4875 {
4876 NVRAM_EF_NRRC_COMMON_CONFIG_LID,
4877 NVRAM_EF_NRRC_COMMON_CONFIG_TOTAL,
4878 NVRAM_EF_NRRC_COMMON_CONFIG_SIZE,
4879 NVRAM_NORMAL(NVRAM_EF_NRRC_COMMON_CONFIG_DEFAULT),
4880 NVRAM_CATEGORY_USER,
4881 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_MCF_OTA_BY_OP,
4882 "NR04", // The first two characters of LID filename defined in nvram_enums.h
4883 VER(NVRAM_EF_NRRC_COMMON_CONFIG_LID)
4884 },
4885#ifdef __NVM_GLOBAL_CABC__
4886 {
4887 NVRAM_EF_NRRC_BAND_SUPPORT_PLMN_LID,
4888 NVRAM_EF_NRRC_BAND_SUPPORT_PLMN_TOTAL,
4889 NVRAM_EF_NRRC_BAND_SUPPORT_PLMN_SIZE,
4890 NVRAM_DEFAULT_FUNC(nvram_get_nrrc_default_value_to_write),
4891 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
4892 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_MCF_OTA_BY_OP,
4893 "NR08", // The first two characters of LID filename defined in nvram_enums.h
4894 VER(NVRAM_EF_NRRC_BAND_SUPPORT_PLMN_LID)
4895 },
4896#endif /* __NVM_GLOBAL_CABC__ */
4897 {
4898 NVRAM_EF_NRRC_CUSTOM_ENDC_COMB_LIST_LID,
4899 NVRAM_EF_NRRC_CUSTOM_ENDC_COMB_LIST_TOTAL,
4900 NVRAM_EF_NRRC_CUSTOM_ENDC_COMB_LIST_SIZE,
4901 NVRAM_NORMAL(NVRAM_EF_NRRC_CUSTOM_ENDC_COMB_LIST_DEFAULT),
4902 NVRAM_CATEGORY_USER,
4903 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_MCF_OTA_BY_OP,
4904 "NR06", // The first two characters of LID filename defined in nvram_enums.h
4905 VER(NVRAM_EF_NRRC_CUSTOM_ENDC_COMB_LIST_LID)
4906 },
4907 {
4908 NVRAM_EF_NRRC_NR_FEATURE_CTRL_LID,
4909 NVRAM_EF_NRRC_NR_FEATURE_CTRL_TOTAL,
4910 NVRAM_EF_NRRC_NR_FEATURE_CTRL_SIZE,
4911 NVRAM_NORMAL(NVRAM_EF_NRRC_NR_FEATURE_CTRL_DEFAULT),
4912 NVRAM_CATEGORY_USER,
4913 NVRAM_ATTR_AVERAGE,
4914 "NR09", // The first two characters of LID filename defined in nvram_enums.h
4915 VER(NVRAM_EF_NRRC_NR_FEATURE_CTRL_LID)
4916 },
yu.donge372c322023-08-30 20:25:04 -0700[diff] [blame^]4917 {
4918 NVRAM_EF_NRRC_STORED_OPERATOR_BAND_PRIORITY_LID,
4919 NVRAM_EF_NRRC_STORED_OPERATOR_BAND_PRIORITY_TOTAL,
4920 NVRAM_EF_NRRC_STORED_OPERATOR_BAND_PRIORITY_SIZE,
4921 NVRAM_NORMAL(NVRAM_EF_NRRC_STORED_OPERATOR_BAND_PRIORITY_DEFAULT),
4922 NVRAM_CATEGORY_USER,
4923 NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_MCF_OTA_BY_OP,
4924 "NR12", // The first two characters of LID filename defined in nvram_enums.h
4925 VER(NVRAM_EF_NRRC_STORED_OPERATOR_BAND_PRIORITY_LID)
4926 },
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]4927 NVRAM_LTABLE_END
4928};
4929
4930/********************************************
4931 * FUNCTION DECLARATIONS *
4932 ********************************************/
4933
4934
4935/********************************************
4936 * FUNCTION DEFINITIONS *
4937 ********************************************/
4938
4939#endif /* __NR_RAT__ */
4940
4941#endif /* NVRAM_NOT_PRESENT */